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(MINI-LFR) 0.1.48...
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r511:86256eafc431 (MINI-LFR) WFP_MS-0-1-48 JC
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1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
21 -------------------------------------------------------------------------------
22 LIBRARY IEEE;
22 LIBRARY IEEE;
23 USE IEEE.numeric_std.ALL;
23 USE IEEE.numeric_std.ALL;
24 USE IEEE.std_logic_1164.ALL;
24 USE IEEE.std_logic_1164.ALL;
25 LIBRARY grlib;
25 LIBRARY grlib;
26 USE grlib.amba.ALL;
26 USE grlib.amba.ALL;
27 USE grlib.stdlib.ALL;
27 USE grlib.stdlib.ALL;
28 LIBRARY techmap;
28 LIBRARY techmap;
29 USE techmap.gencomp.ALL;
29 USE techmap.gencomp.ALL;
30 LIBRARY gaisler;
30 LIBRARY gaisler;
31 USE gaisler.memctrl.ALL;
31 USE gaisler.memctrl.ALL;
32 USE gaisler.leon3.ALL;
32 USE gaisler.leon3.ALL;
33 USE gaisler.uart.ALL;
33 USE gaisler.uart.ALL;
34 USE gaisler.misc.ALL;
34 USE gaisler.misc.ALL;
35 USE gaisler.spacewire.ALL;
35 USE gaisler.spacewire.ALL;
36 LIBRARY esa;
36 LIBRARY esa;
37 USE esa.memoryctrl.ALL;
37 USE esa.memoryctrl.ALL;
38 LIBRARY lpp;
38 LIBRARY lpp;
39 USE lpp.lpp_memory.ALL;
39 USE lpp.lpp_memory.ALL;
40 USE lpp.lpp_ad_conv.ALL;
40 USE lpp.lpp_ad_conv.ALL;
41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
43 USE lpp.iir_filter.ALL;
43 USE lpp.iir_filter.ALL;
44 USE lpp.general_purpose.ALL;
44 USE lpp.general_purpose.ALL;
45 USE lpp.lpp_lfr_time_management.ALL;
45 USE lpp.lpp_lfr_time_management.ALL;
46 USE lpp.lpp_leon3_soc_pkg.ALL;
46 USE lpp.lpp_leon3_soc_pkg.ALL;
47
47
48 ENTITY MINI_LFR_top IS
48 ENTITY MINI_LFR_top IS
49
49
50 PORT (
50 PORT (
51 clk_50 : IN STD_LOGIC;
51 clk_50 : IN STD_LOGIC;
52 clk_49 : IN STD_LOGIC;
52 clk_49 : IN STD_LOGIC;
53 reset : IN STD_LOGIC;
53 reset : IN STD_LOGIC;
54 --BPs
54 --BPs
55 BP0 : IN STD_LOGIC;
55 BP0 : IN STD_LOGIC;
56 BP1 : IN STD_LOGIC;
56 BP1 : IN STD_LOGIC;
57 --LEDs
57 --LEDs
58 LED0 : OUT STD_LOGIC;
58 LED0 : OUT STD_LOGIC;
59 LED1 : OUT STD_LOGIC;
59 LED1 : OUT STD_LOGIC;
60 LED2 : OUT STD_LOGIC;
60 LED2 : OUT STD_LOGIC;
61 --UARTs
61 --UARTs
62 TXD1 : IN STD_LOGIC;
62 TXD1 : IN STD_LOGIC;
63 RXD1 : OUT STD_LOGIC;
63 RXD1 : OUT STD_LOGIC;
64 nCTS1 : OUT STD_LOGIC;
64 nCTS1 : OUT STD_LOGIC;
65 nRTS1 : IN STD_LOGIC;
65 nRTS1 : IN STD_LOGIC;
66
66
67 TXD2 : IN STD_LOGIC;
67 TXD2 : IN STD_LOGIC;
68 RXD2 : OUT STD_LOGIC;
68 RXD2 : OUT STD_LOGIC;
69 nCTS2 : OUT STD_LOGIC;
69 nCTS2 : OUT STD_LOGIC;
70 nDTR2 : IN STD_LOGIC;
70 nDTR2 : IN STD_LOGIC;
71 nRTS2 : IN STD_LOGIC;
71 nRTS2 : IN STD_LOGIC;
72 nDCD2 : OUT STD_LOGIC;
72 nDCD2 : OUT STD_LOGIC;
73
73
74 --EXT CONNECTOR
74 --EXT CONNECTOR
75 IO0 : INOUT STD_LOGIC;
75 IO0 : INOUT STD_LOGIC;
76 IO1 : INOUT STD_LOGIC;
76 IO1 : INOUT STD_LOGIC;
77 IO2 : INOUT STD_LOGIC;
77 IO2 : INOUT STD_LOGIC;
78 IO3 : INOUT STD_LOGIC;
78 IO3 : INOUT STD_LOGIC;
79 IO4 : INOUT STD_LOGIC;
79 IO4 : INOUT STD_LOGIC;
80 IO5 : INOUT STD_LOGIC;
80 IO5 : INOUT STD_LOGIC;
81 IO6 : INOUT STD_LOGIC;
81 IO6 : INOUT STD_LOGIC;
82 IO7 : INOUT STD_LOGIC;
82 IO7 : INOUT STD_LOGIC;
83 IO8 : INOUT STD_LOGIC;
83 IO8 : INOUT STD_LOGIC;
84 IO9 : INOUT STD_LOGIC;
84 IO9 : INOUT STD_LOGIC;
85 IO10 : INOUT STD_LOGIC;
85 IO10 : INOUT STD_LOGIC;
86 IO11 : INOUT STD_LOGIC;
86 IO11 : INOUT STD_LOGIC;
87
87
88 --SPACE WIRE
88 --SPACE WIRE
89 SPW_EN : OUT STD_LOGIC; -- 0 => off
89 SPW_EN : OUT STD_LOGIC; -- 0 => off
90 SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK
90 SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK
91 SPW_NOM_SIN : IN STD_LOGIC;
91 SPW_NOM_SIN : IN STD_LOGIC;
92 SPW_NOM_DOUT : OUT STD_LOGIC;
92 SPW_NOM_DOUT : OUT STD_LOGIC;
93 SPW_NOM_SOUT : OUT STD_LOGIC;
93 SPW_NOM_SOUT : OUT STD_LOGIC;
94 SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK
94 SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK
95 SPW_RED_SIN : IN STD_LOGIC;
95 SPW_RED_SIN : IN STD_LOGIC;
96 SPW_RED_DOUT : OUT STD_LOGIC;
96 SPW_RED_DOUT : OUT STD_LOGIC;
97 SPW_RED_SOUT : OUT STD_LOGIC;
97 SPW_RED_SOUT : OUT STD_LOGIC;
98 -- MINI LFR ADC INPUTS
98 -- MINI LFR ADC INPUTS
99 ADC_nCS : OUT STD_LOGIC;
99 ADC_nCS : OUT STD_LOGIC;
100 ADC_CLK : OUT STD_LOGIC;
100 ADC_CLK : OUT STD_LOGIC;
101 ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
101 ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
102
102
103 -- SRAM
103 -- SRAM
104 SRAM_nWE : OUT STD_LOGIC;
104 SRAM_nWE : OUT STD_LOGIC;
105 SRAM_CE : OUT STD_LOGIC;
105 SRAM_CE : OUT STD_LOGIC;
106 SRAM_nOE : OUT STD_LOGIC;
106 SRAM_nOE : OUT STD_LOGIC;
107 SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
107 SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
108 SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
108 SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
109 SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0)
109 SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0)
110 );
110 );
111
111
112 END MINI_LFR_top;
112 END MINI_LFR_top;
113
113
114
114
115 ARCHITECTURE beh OF MINI_LFR_top IS
115 ARCHITECTURE beh OF MINI_LFR_top IS
116 SIGNAL clk_50_s : STD_LOGIC := '0';
116 SIGNAL clk_50_s : STD_LOGIC := '0';
117 SIGNAL clk_25 : STD_LOGIC := '0';
117 SIGNAL clk_25 : STD_LOGIC := '0';
118 SIGNAL clk_24 : STD_LOGIC := '0';
118 SIGNAL clk_24 : STD_LOGIC := '0';
119 -----------------------------------------------------------------------------
119 -----------------------------------------------------------------------------
120 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
120 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
121 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
121 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
122 --
122 --
123 SIGNAL errorn : STD_LOGIC;
123 SIGNAL errorn : STD_LOGIC;
124 -- UART AHB ---------------------------------------------------------------
124 -- UART AHB ---------------------------------------------------------------
125 -- SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data
125 -- SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data
126 -- SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data
126 -- SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data
127
127
128 -- UART APB ---------------------------------------------------------------
128 -- UART APB ---------------------------------------------------------------
129 -- SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data
129 -- SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data
130 -- SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data
130 -- SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data
131 --
131 --
132 SIGNAL I00_s : STD_LOGIC;
132 SIGNAL I00_s : STD_LOGIC;
133
133
134 -- CONSTANTS
134 -- CONSTANTS
135 CONSTANT CFG_PADTECH : INTEGER := inferred;
135 CONSTANT CFG_PADTECH : INTEGER := inferred;
136 --
136 --
137 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
137 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
138 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
138 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
139 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
139 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
140
140
141 SIGNAL apbi_ext : apb_slv_in_type;
141 SIGNAL apbi_ext : apb_slv_in_type;
142 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5); -- := (OTHERS => apb_none);
142 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5); -- := (OTHERS => apb_none);
143 SIGNAL ahbi_s_ext : ahb_slv_in_type;
143 SIGNAL ahbi_s_ext : ahb_slv_in_type;
144 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3); -- := (OTHERS => ahbs_none);
144 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3); -- := (OTHERS => ahbs_none);
145 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
145 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
146 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1); -- := (OTHERS => ahbm_none);
146 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1); -- := (OTHERS => ahbm_none);
147
147
148 -- Spacewire signals
148 -- Spacewire signals
149 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
149 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
150 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
150 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
151 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
151 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
152 SIGNAL spw_rxtxclk : STD_ULOGIC;
152 SIGNAL spw_rxtxclk : STD_ULOGIC;
153 SIGNAL spw_rxclkn : STD_ULOGIC;
153 SIGNAL spw_rxclkn : STD_ULOGIC;
154 SIGNAL spw_clk : STD_LOGIC;
154 SIGNAL spw_clk : STD_LOGIC;
155 SIGNAL swni : grspw_in_type;
155 SIGNAL swni : grspw_in_type;
156 SIGNAL swno : grspw_out_type;
156 SIGNAL swno : grspw_out_type;
157 -- SIGNAL clkmn : STD_ULOGIC;
157 -- SIGNAL clkmn : STD_ULOGIC;
158 -- SIGNAL txclk : STD_ULOGIC;
158 -- SIGNAL txclk : STD_ULOGIC;
159
159
160 --GPIO
160 --GPIO
161 SIGNAL gpioi : gpio_in_type;
161 SIGNAL gpioi : gpio_in_type;
162 SIGNAL gpioo : gpio_out_type;
162 SIGNAL gpioo : gpio_out_type;
163
163
164 -- AD Converter ADS7886
164 -- AD Converter ADS7886
165 SIGNAL sample : Samples14v(7 DOWNTO 0);
165 SIGNAL sample : Samples14v(7 DOWNTO 0);
166 SIGNAL sample_s : Samples(7 DOWNTO 0);
166 SIGNAL sample_s : Samples(7 DOWNTO 0);
167 SIGNAL sample_val : STD_LOGIC;
167 SIGNAL sample_val : STD_LOGIC;
168 SIGNAL ADC_nCS_sig : STD_LOGIC;
168 SIGNAL ADC_nCS_sig : STD_LOGIC;
169 SIGNAL ADC_CLK_sig : STD_LOGIC;
169 SIGNAL ADC_CLK_sig : STD_LOGIC;
170 SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
170 SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
171
171
172 SIGNAL bias_fail_sw_sig : STD_LOGIC;
172 SIGNAL bias_fail_sw_sig : STD_LOGIC;
173
173
174 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
174 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
175 SIGNAL observation_vector_0 : STD_LOGIC_VECTOR(11 DOWNTO 0);
175 SIGNAL observation_vector_0 : STD_LOGIC_VECTOR(11 DOWNTO 0);
176 SIGNAL observation_vector_1 : STD_LOGIC_VECTOR(11 DOWNTO 0);
176 SIGNAL observation_vector_1 : STD_LOGIC_VECTOR(11 DOWNTO 0);
177 -----------------------------------------------------------------------------
177 -----------------------------------------------------------------------------
178
178
179 SIGNAL LFR_soft_rstn : STD_LOGIC;
179 SIGNAL LFR_soft_rstn : STD_LOGIC;
180 SIGNAL LFR_rstn : STD_LOGIC;
180 SIGNAL LFR_rstn : STD_LOGIC;
181
181
182
182
183 SIGNAL rstn_25 : STD_LOGIC;
183 SIGNAL rstn_25 : STD_LOGIC;
184 SIGNAL rstn_25_d1 : STD_LOGIC;
184 SIGNAL rstn_25_d1 : STD_LOGIC;
185 SIGNAL rstn_25_d2 : STD_LOGIC;
185 SIGNAL rstn_25_d2 : STD_LOGIC;
186 SIGNAL rstn_25_d3 : STD_LOGIC;
186 SIGNAL rstn_25_d3 : STD_LOGIC;
187
187
188 SIGNAL rstn_50 : STD_LOGIC;
188 SIGNAL rstn_50 : STD_LOGIC;
189 SIGNAL rstn_50_d1 : STD_LOGIC;
189 SIGNAL rstn_50_d1 : STD_LOGIC;
190 SIGNAL rstn_50_d2 : STD_LOGIC;
190 SIGNAL rstn_50_d2 : STD_LOGIC;
191 SIGNAL rstn_50_d3 : STD_LOGIC;
191 SIGNAL rstn_50_d3 : STD_LOGIC;
192
192
193 SIGNAL lfr_debug_vector : STD_LOGIC_VECTOR(11 DOWNTO 0);
193 SIGNAL lfr_debug_vector : STD_LOGIC_VECTOR(11 DOWNTO 0);
194 SIGNAL lfr_debug_vector_ms : STD_LOGIC_VECTOR(11 DOWNTO 0);
194 SIGNAL lfr_debug_vector_ms : STD_LOGIC_VECTOR(11 DOWNTO 0);
195
195
196 --
196 --
197 SIGNAL SRAM_CE_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
197 SIGNAL SRAM_CE_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
198
199 --
200 SIGNAL sample_hk : STD_LOGIC_VECTOR(15 DOWNTO 0);
201 SIGNAL HK_SEL : STD_LOGIC_VECTOR( 1 DOWNTO 0);
202
198
203 BEGIN -- beh
199 BEGIN -- beh
204
200
205 -----------------------------------------------------------------------------
201 -----------------------------------------------------------------------------
206 -- CLK
202 -- CLK
207 -----------------------------------------------------------------------------
203 -----------------------------------------------------------------------------
208
204
209 --PROCESS(clk_50)
205 --PROCESS(clk_50)
210 --BEGIN
206 --BEGIN
211 -- IF clk_50'EVENT AND clk_50 = '1' THEN
207 -- IF clk_50'EVENT AND clk_50 = '1' THEN
212 -- clk_50_s <= NOT clk_50_s;
208 -- clk_50_s <= NOT clk_50_s;
213 -- END IF;
209 -- END IF;
214 --END PROCESS;
210 --END PROCESS;
215
211
216 --PROCESS(clk_50_s)
212 --PROCESS(clk_50_s)
217 --BEGIN
213 --BEGIN
218 -- IF clk_50_s'EVENT AND clk_50_s = '1' THEN
214 -- IF clk_50_s'EVENT AND clk_50_s = '1' THEN
219 -- clk_25 <= NOT clk_25;
215 -- clk_25 <= NOT clk_25;
220 -- END IF;
216 -- END IF;
221 --END PROCESS;
217 --END PROCESS;
222
218
223 --PROCESS(clk_49)
219 --PROCESS(clk_49)
224 --BEGIN
220 --BEGIN
225 -- IF clk_49'EVENT AND clk_49 = '1' THEN
221 -- IF clk_49'EVENT AND clk_49 = '1' THEN
226 -- clk_24 <= NOT clk_24;
222 -- clk_24 <= NOT clk_24;
227 -- END IF;
223 -- END IF;
228 --END PROCESS;
224 --END PROCESS;
229
225
230 --PROCESS(clk_25)
226 --PROCESS(clk_25)
231 --BEGIN
227 --BEGIN
232 -- IF clk_25'EVENT AND clk_25 = '1' THEN
228 -- IF clk_25'EVENT AND clk_25 = '1' THEN
233 -- rstn_25 <= reset;
229 -- rstn_25 <= reset;
234 -- END IF;
230 -- END IF;
235 --END PROCESS;
231 --END PROCESS;
236
232
237 PROCESS (clk_50, reset)
233 PROCESS (clk_50, reset)
238 BEGIN -- PROCESS
234 BEGIN -- PROCESS
239 IF reset = '0' THEN -- asynchronous reset (active low)
235 IF reset = '0' THEN -- asynchronous reset (active low)
240 clk_50_s <= '0';
236 clk_50_s <= '0';
241 rstn_50 <= '0';
237 rstn_50 <= '0';
242 rstn_50_d1 <= '0';
238 rstn_50_d1 <= '0';
243 rstn_50_d2 <= '0';
239 rstn_50_d2 <= '0';
244 rstn_50_d3 <= '0';
240 rstn_50_d3 <= '0';
245
241
246 ELSIF clk_50'EVENT AND clk_50 = '1' THEN -- rising clock edge
242 ELSIF clk_50'EVENT AND clk_50 = '1' THEN -- rising clock edge
247 clk_50_s <= NOT clk_50_s;
243 clk_50_s <= NOT clk_50_s;
248 rstn_50_d1 <= '1';
244 rstn_50_d1 <= '1';
249 rstn_50_d2 <= rstn_50_d1;
245 rstn_50_d2 <= rstn_50_d1;
250 rstn_50_d3 <= rstn_50_d2;
246 rstn_50_d3 <= rstn_50_d2;
251 rstn_50 <= rstn_50_d3;
247 rstn_50 <= rstn_50_d3;
252 END IF;
248 END IF;
253 END PROCESS;
249 END PROCESS;
254
250
255 PROCESS (clk_50_s, rstn_50)
251 PROCESS (clk_50_s, rstn_50)
256 BEGIN -- PROCESS
252 BEGIN -- PROCESS
257 IF rstn_50 = '0' THEN -- asynchronous reset (active low)
253 IF rstn_50 = '0' THEN -- asynchronous reset (active low)
258 clk_25 <= '0';
254 clk_25 <= '0';
259 rstn_25 <= '0';
255 rstn_25 <= '0';
260 rstn_25_d1 <= '0';
256 rstn_25_d1 <= '0';
261 rstn_25_d2 <= '0';
257 rstn_25_d2 <= '0';
262 rstn_25_d3 <= '0';
258 rstn_25_d3 <= '0';
263 ELSIF clk_50_s'EVENT AND clk_50_s = '1' THEN -- rising clock edge
259 ELSIF clk_50_s'EVENT AND clk_50_s = '1' THEN -- rising clock edge
264 clk_25 <= NOT clk_25;
260 clk_25 <= NOT clk_25;
265 rstn_25_d1 <= '1';
261 rstn_25_d1 <= '1';
266 rstn_25_d2 <= rstn_25_d1;
262 rstn_25_d2 <= rstn_25_d1;
267 rstn_25_d3 <= rstn_25_d2;
263 rstn_25_d3 <= rstn_25_d2;
268 rstn_25 <= rstn_25_d3;
264 rstn_25 <= rstn_25_d3;
269 END IF;
265 END IF;
270 END PROCESS;
266 END PROCESS;
271
267
272 PROCESS (clk_49, reset)
268 PROCESS (clk_49, reset)
273 BEGIN -- PROCESS
269 BEGIN -- PROCESS
274 IF reset = '0' THEN -- asynchronous reset (active low)
270 IF reset = '0' THEN -- asynchronous reset (active low)
275 clk_24 <= '0';
271 clk_24 <= '0';
276 ELSIF clk_49'EVENT AND clk_49 = '1' THEN -- rising clock edge
272 ELSIF clk_49'EVENT AND clk_49 = '1' THEN -- rising clock edge
277 clk_24 <= NOT clk_24;
273 clk_24 <= NOT clk_24;
278 END IF;
274 END IF;
279 END PROCESS;
275 END PROCESS;
280
276
281 -----------------------------------------------------------------------------
277 -----------------------------------------------------------------------------
282
278
283 PROCESS (clk_25, rstn_25)
279 PROCESS (clk_25, rstn_25)
284 BEGIN -- PROCESS
280 BEGIN -- PROCESS
285 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
281 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
286 LED0 <= '0';
282 LED0 <= '0';
287 LED1 <= '0';
283 LED1 <= '0';
288 LED2 <= '0';
284 LED2 <= '0';
289 --IO1 <= '0';
285 --IO1 <= '0';
290 --IO2 <= '1';
286 --IO2 <= '1';
291 --IO3 <= '0';
287 --IO3 <= '0';
292 --IO4 <= '0';
288 --IO4 <= '0';
293 --IO5 <= '0';
289 --IO5 <= '0';
294 --IO6 <= '0';
290 --IO6 <= '0';
295 --IO7 <= '0';
291 --IO7 <= '0';
296 --IO8 <= '0';
292 --IO8 <= '0';
297 --IO9 <= '0';
293 --IO9 <= '0';
298 --IO10 <= '0';
294 --IO10 <= '0';
299 --IO11 <= '0';
295 --IO11 <= '0';
300 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
296 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
301 LED0 <= '0';
297 LED0 <= '0';
302 LED1 <= '1';
298 LED1 <= '1';
303 LED2 <= BP0 OR BP1 OR nDTR2 OR nRTS2 OR nRTS1;
299 LED2 <= BP0 OR BP1 OR nDTR2 OR nRTS2 OR nRTS1;
304 --IO1 <= '1';
300 --IO1 <= '1';
305 --IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN;
301 --IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN;
306 --IO3 <= ADC_SDO(0);
302 --IO3 <= ADC_SDO(0);
307 --IO4 <= ADC_SDO(1);
303 --IO4 <= ADC_SDO(1);
308 --IO5 <= ADC_SDO(2);
304 --IO5 <= ADC_SDO(2);
309 --IO6 <= ADC_SDO(3);
305 --IO6 <= ADC_SDO(3);
310 --IO7 <= ADC_SDO(4);
306 --IO7 <= ADC_SDO(4);
311 --IO8 <= ADC_SDO(5);
307 --IO8 <= ADC_SDO(5);
312 --IO9 <= ADC_SDO(6);
308 --IO9 <= ADC_SDO(6);
313 --IO10 <= ADC_SDO(7);
309 --IO10 <= ADC_SDO(7);
314 --IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1;
310 --IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1;
315 END IF;
311 END IF;
316 END PROCESS;
312 END PROCESS;
317
313
318 PROCESS (clk_24, rstn_25)
314 PROCESS (clk_24, rstn_25)
319 BEGIN -- PROCESS
315 BEGIN -- PROCESS
320 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
316 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
321 I00_s <= '0';
317 I00_s <= '0';
322 ELSIF clk_24'EVENT AND clk_24 = '1' THEN -- rising clock edge
318 ELSIF clk_24'EVENT AND clk_24 = '1' THEN -- rising clock edge
323 I00_s <= NOT I00_s;
319 I00_s <= NOT I00_s;
324 END IF;
320 END IF;
325 END PROCESS;
321 END PROCESS;
326 -- IO0 <= I00_s;
322 -- IO0 <= I00_s;
327
323
328 --UARTs
324 --UARTs
329 nCTS1 <= '1';
325 nCTS1 <= '1';
330 nCTS2 <= '1';
326 nCTS2 <= '1';
331 nDCD2 <= '1';
327 nDCD2 <= '1';
332
328
333 --EXT CONNECTOR
329 --EXT CONNECTOR
334
330
335 --SPACE WIRE
331 --SPACE WIRE
336
332
337 leon3_soc_1 : leon3_soc
333 leon3_soc_1 : leon3_soc
338 GENERIC MAP (
334 GENERIC MAP (
339 fabtech => apa3e,
335 fabtech => apa3e,
340 memtech => apa3e,
336 memtech => apa3e,
341 padtech => inferred,
337 padtech => inferred,
342 clktech => inferred,
338 clktech => inferred,
343 disas => 0,
339 disas => 0,
344 dbguart => 0,
340 dbguart => 0,
345 pclow => 2,
341 pclow => 2,
346 clk_freq => 25000,
342 clk_freq => 25000,
347 NB_CPU => 1,
343 NB_CPU => 1,
348 ENABLE_FPU => 1,
344 ENABLE_FPU => 1,
349 FPU_NETLIST => 0,
345 FPU_NETLIST => 0,
350 ENABLE_DSU => 1,
346 ENABLE_DSU => 1,
351 ENABLE_AHB_UART => 1,
347 ENABLE_AHB_UART => 1,
352 ENABLE_APB_UART => 1,
348 ENABLE_APB_UART => 1,
353 ENABLE_IRQMP => 1,
349 ENABLE_IRQMP => 1,
354 ENABLE_GPT => 1,
350 ENABLE_GPT => 1,
355 NB_AHB_MASTER => NB_AHB_MASTER,
351 NB_AHB_MASTER => NB_AHB_MASTER,
356 NB_AHB_SLAVE => NB_AHB_SLAVE,
352 NB_AHB_SLAVE => NB_AHB_SLAVE,
357 NB_APB_SLAVE => NB_APB_SLAVE,
353 NB_APB_SLAVE => NB_APB_SLAVE,
358 ADDRESS_SIZE => 20,
354 ADDRESS_SIZE => 20,
359 USES_IAP_MEMCTRLR => 0)
355 USES_IAP_MEMCTRLR => 0)
360 PORT MAP (
356 PORT MAP (
361 clk => clk_25,
357 clk => clk_25,
362 reset => rstn_25,
358 reset => rstn_25,
363 errorn => errorn,
359 errorn => errorn,
364 ahbrxd => TXD1,
360 ahbrxd => TXD1,
365 ahbtxd => RXD1,
361 ahbtxd => RXD1,
366 urxd1 => TXD2,
362 urxd1 => TXD2,
367 utxd1 => RXD2,
363 utxd1 => RXD2,
368 address => SRAM_A,
364 address => SRAM_A,
369 data => SRAM_DQ,
365 data => SRAM_DQ,
370 nSRAM_BE0 => SRAM_nBE(0),
366 nSRAM_BE0 => SRAM_nBE(0),
371 nSRAM_BE1 => SRAM_nBE(1),
367 nSRAM_BE1 => SRAM_nBE(1),
372 nSRAM_BE2 => SRAM_nBE(2),
368 nSRAM_BE2 => SRAM_nBE(2),
373 nSRAM_BE3 => SRAM_nBE(3),
369 nSRAM_BE3 => SRAM_nBE(3),
374 nSRAM_WE => SRAM_nWE,
370 nSRAM_WE => SRAM_nWE,
375 nSRAM_CE => SRAM_CE_s,
371 nSRAM_CE => SRAM_CE_s,
376 nSRAM_OE => SRAM_nOE,
372 nSRAM_OE => SRAM_nOE,
377 nSRAM_READY => '0',
373 nSRAM_READY => '0',
378 SRAM_MBE => OPEN,
374 SRAM_MBE => OPEN,
379 apbi_ext => apbi_ext,
375 apbi_ext => apbi_ext,
380 apbo_ext => apbo_ext,
376 apbo_ext => apbo_ext,
381 ahbi_s_ext => ahbi_s_ext,
377 ahbi_s_ext => ahbi_s_ext,
382 ahbo_s_ext => ahbo_s_ext,
378 ahbo_s_ext => ahbo_s_ext,
383 ahbi_m_ext => ahbi_m_ext,
379 ahbi_m_ext => ahbi_m_ext,
384 ahbo_m_ext => ahbo_m_ext);
380 ahbo_m_ext => ahbo_m_ext);
385
381
386 SRAM_CE <= SRAM_CE_s(0);
382 SRAM_CE <= SRAM_CE_s(0);
387 -------------------------------------------------------------------------------
383 -------------------------------------------------------------------------------
388 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
384 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
389 -------------------------------------------------------------------------------
385 -------------------------------------------------------------------------------
390 apb_lfr_time_management_1 : apb_lfr_time_management
386 apb_lfr_time_management_1 : apb_lfr_time_management
391 GENERIC MAP (
387 GENERIC MAP (
392 pindex => 6,
388 pindex => 6,
393 paddr => 6,
389 paddr => 6,
394 pmask => 16#fff#,
390 pmask => 16#fff#,
395 FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
391 FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
396 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
392 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
397 PORT MAP (
393 PORT MAP (
398 clk25MHz => clk_25,
394 clk25MHz => clk_25,
399 clk24_576MHz => clk_24, -- 49.152MHz/2
395 clk24_576MHz => clk_24, -- 49.152MHz/2
400 resetn => rstn_25,
396 resetn => rstn_25,
401 grspw_tick => swno.tickout,
397 grspw_tick => swno.tickout,
402 apbi => apbi_ext,
398 apbi => apbi_ext,
403 apbo => apbo_ext(6),
399 apbo => apbo_ext(6),
404 coarse_time => coarse_time,
400 coarse_time => coarse_time,
405 fine_time => fine_time,
401 fine_time => fine_time,
406 LFR_soft_rstn => LFR_soft_rstn
402 LFR_soft_rstn => LFR_soft_rstn
407 );
403 );
408
404
409 -----------------------------------------------------------------------
405 -----------------------------------------------------------------------
410 --- SpaceWire --------------------------------------------------------
406 --- SpaceWire --------------------------------------------------------
411 -----------------------------------------------------------------------
407 -----------------------------------------------------------------------
412
408
413 SPW_EN <= '1';
409 SPW_EN <= '1';
414
410
415 spw_clk <= clk_50_s;
411 spw_clk <= clk_50_s;
416 spw_rxtxclk <= spw_clk;
412 spw_rxtxclk <= spw_clk;
417 spw_rxclkn <= NOT spw_rxtxclk;
413 spw_rxclkn <= NOT spw_rxtxclk;
418
414
419 -- PADS for SPW1
415 -- PADS for SPW1
420 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
416 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
421 PORT MAP (SPW_NOM_DIN, dtmp(0));
417 PORT MAP (SPW_NOM_DIN, dtmp(0));
422 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
418 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
423 PORT MAP (SPW_NOM_SIN, stmp(0));
419 PORT MAP (SPW_NOM_SIN, stmp(0));
424 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
420 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
425 PORT MAP (SPW_NOM_DOUT, swno.d(0));
421 PORT MAP (SPW_NOM_DOUT, swno.d(0));
426 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
422 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
427 PORT MAP (SPW_NOM_SOUT, swno.s(0));
423 PORT MAP (SPW_NOM_SOUT, swno.s(0));
428 -- PADS FOR SPW2
424 -- PADS FOR SPW2
429 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
425 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
430 PORT MAP (SPW_RED_SIN, dtmp(1));
426 PORT MAP (SPW_RED_SIN, dtmp(1));
431 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
427 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
432 PORT MAP (SPW_RED_DIN, stmp(1));
428 PORT MAP (SPW_RED_DIN, stmp(1));
433 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
429 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
434 PORT MAP (SPW_RED_DOUT, swno.d(1));
430 PORT MAP (SPW_RED_DOUT, swno.d(1));
435 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
431 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
436 PORT MAP (SPW_RED_SOUT, swno.s(1));
432 PORT MAP (SPW_RED_SOUT, swno.s(1));
437
433
438 -- GRSPW PHY
434 -- GRSPW PHY
439 --spw1_input: if CFG_SPW_GRSPW = 1 generate
435 --spw1_input: if CFG_SPW_GRSPW = 1 generate
440 spw_inputloop : FOR j IN 0 TO 1 GENERATE
436 spw_inputloop : FOR j IN 0 TO 1 GENERATE
441 spw_phy0 : grspw_phy
437 spw_phy0 : grspw_phy
442 GENERIC MAP(
438 GENERIC MAP(
443 tech => apa3e,
439 tech => apa3e,
444 rxclkbuftype => 1,
440 rxclkbuftype => 1,
445 scantest => 0)
441 scantest => 0)
446 PORT MAP(
442 PORT MAP(
447 rxrst => swno.rxrst,
443 rxrst => swno.rxrst,
448 di => dtmp(j),
444 di => dtmp(j),
449 si => stmp(j),
445 si => stmp(j),
450 rxclko => spw_rxclk(j),
446 rxclko => spw_rxclk(j),
451 do => swni.d(j),
447 do => swni.d(j),
452 ndo => swni.nd(j*5+4 DOWNTO j*5),
448 ndo => swni.nd(j*5+4 DOWNTO j*5),
453 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
449 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
454 END GENERATE spw_inputloop;
450 END GENERATE spw_inputloop;
455
451
456 swni.rmapnodeaddr <= (OTHERS => '0');
452 swni.rmapnodeaddr <= (OTHERS => '0');
457
453
458 -- SPW core
454 -- SPW core
459 sw0 : grspwm GENERIC MAP(
455 sw0 : grspwm GENERIC MAP(
460 tech => apa3e,
456 tech => apa3e,
461 hindex => 1,
457 hindex => 1,
462 pindex => 5,
458 pindex => 5,
463 paddr => 5,
459 paddr => 5,
464 pirq => 11,
460 pirq => 11,
465 sysfreq => 25000, -- CPU_FREQ
461 sysfreq => 25000, -- CPU_FREQ
466 rmap => 1,
462 rmap => 1,
467 rmapcrc => 1,
463 rmapcrc => 1,
468 fifosize1 => 16,
464 fifosize1 => 16,
469 fifosize2 => 16,
465 fifosize2 => 16,
470 rxclkbuftype => 1,
466 rxclkbuftype => 1,
471 rxunaligned => 0,
467 rxunaligned => 0,
472 rmapbufs => 4,
468 rmapbufs => 4,
473 ft => 0,
469 ft => 0,
474 netlist => 0,
470 netlist => 0,
475 ports => 2,
471 ports => 2,
476 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
472 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
477 memtech => apa3e,
473 memtech => apa3e,
478 destkey => 2,
474 destkey => 2,
479 spwcore => 1
475 spwcore => 1
480 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
476 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
481 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
477 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
482 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
478 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
483 )
479 )
484 PORT MAP(rstn_25, clk_25, spw_rxclk(0),
480 PORT MAP(rstn_25, clk_25, spw_rxclk(0),
485 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
481 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
486 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
482 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
487 swni, swno);
483 swni, swno);
488
484
489 swni.tickin <= '0';
485 swni.tickin <= '0';
490 swni.rmapen <= '1';
486 swni.rmapen <= '1';
491 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
487 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
492 swni.tickinraw <= '0';
488 swni.tickinraw <= '0';
493 swni.timein <= (OTHERS => '0');
489 swni.timein <= (OTHERS => '0');
494 swni.dcrstval <= (OTHERS => '0');
490 swni.dcrstval <= (OTHERS => '0');
495 swni.timerrstval <= (OTHERS => '0');
491 swni.timerrstval <= (OTHERS => '0');
496
492
497 -------------------------------------------------------------------------------
493 -------------------------------------------------------------------------------
498 -- LFR ------------------------------------------------------------------------
494 -- LFR ------------------------------------------------------------------------
499 -------------------------------------------------------------------------------
495 -------------------------------------------------------------------------------
500
496
501
497
502 LFR_rstn <= LFR_soft_rstn AND rstn_25;
498 LFR_rstn <= LFR_soft_rstn AND rstn_25;
503 --LFR_rstn <= rstn_25;
499 --LFR_rstn <= rstn_25;
504
500
505 lpp_lfr_1 : lpp_lfr
501 lpp_lfr_1 : lpp_lfr
506 GENERIC MAP (
502 GENERIC MAP (
507 Mem_use => use_RAM,
503 Mem_use => use_RAM,
508 nb_data_by_buffer_size => 32,
504 nb_data_by_buffer_size => 32,
509 nb_snapshot_param_size => 32,
505 nb_snapshot_param_size => 32,
510 delta_vector_size => 32,
506 delta_vector_size => 32,
511 delta_vector_size_f0_2 => 7, -- log2(96)
507 delta_vector_size_f0_2 => 7, -- log2(96)
512 pindex => 15,
508 pindex => 15,
513 paddr => 15,
509 paddr => 15,
514 pmask => 16#fff#,
510 pmask => 16#fff#,
515 pirq_ms => 6,
511 pirq_ms => 6,
516 pirq_wfp => 14,
512 pirq_wfp => 14,
517 hindex => 2,
513 hindex => 2,
518 top_lfr_version => X"00012E") -- aa.bb.cc version
514 top_lfr_version => X"000130") -- aa.bb.cc version
519 PORT MAP (
515 PORT MAP (
520 clk => clk_25,
516 clk => clk_25,
521 rstn => LFR_rstn,
517 rstn => LFR_rstn,
522 sample_B => sample_s(2 DOWNTO 0),
518 sample_B => sample_s(2 DOWNTO 0),
523 sample_E => sample_s(7 DOWNTO 3),
519 sample_E => sample_s(7 DOWNTO 3),
524 sample_val => sample_val,
520 sample_val => sample_val,
525 apbi => apbi_ext,
521 apbi => apbi_ext,
526 apbo => apbo_ext(15),
522 apbo => apbo_ext(15),
527 ahbi => ahbi_m_ext,
523 ahbi => ahbi_m_ext,
528 ahbo => ahbo_m_ext(2),
524 ahbo => ahbo_m_ext(2),
529 coarse_time => coarse_time,
525 coarse_time => coarse_time,
530 fine_time => fine_time,
526 fine_time => fine_time,
531 data_shaping_BW => bias_fail_sw_sig,
527 data_shaping_BW => bias_fail_sw_sig,
532 debug_vector => lfr_debug_vector,
528 debug_vector => lfr_debug_vector,
533 debug_vector_ms => lfr_debug_vector_ms
529 debug_vector_ms => lfr_debug_vector_ms
534 );
530 );
535
531
536 observation_reg(11 DOWNTO 0) <= lfr_debug_vector;
532 observation_reg(11 DOWNTO 0) <= lfr_debug_vector;
537 observation_reg(31 DOWNTO 12) <= (OTHERS => '0');
533 observation_reg(31 DOWNTO 12) <= (OTHERS => '0');
538 observation_vector_0(11 DOWNTO 0) <= lfr_debug_vector;
534 observation_vector_0(11 DOWNTO 0) <= lfr_debug_vector;
539 observation_vector_1(11 DOWNTO 0) <= lfr_debug_vector;
535 observation_vector_1(11 DOWNTO 0) <= lfr_debug_vector;
540 IO0 <= rstn_25;
536 IO0 <= rstn_25;
541 IO1 <= lfr_debug_vector_ms(0); -- LFR MS FFT data_valid
537 IO1 <= lfr_debug_vector_ms(0); -- LFR MS FFT data_valid
542 IO2 <= lfr_debug_vector_ms(0); -- LFR MS FFT ready
538 IO2 <= lfr_debug_vector_ms(0); -- LFR MS FFT ready
543 IO3 <= lfr_debug_vector(0); -- LFR APBREG error_buffer_full
539 IO3 <= lfr_debug_vector(0); -- LFR APBREG error_buffer_full
544 IO4 <= lfr_debug_vector(1); -- LFR APBREG reg_sp.status_error_buffer_full
540 IO4 <= lfr_debug_vector(1); -- LFR APBREG reg_sp.status_error_buffer_full
545 IO5 <= lfr_debug_vector(8); -- LFR APBREG ready_matrix_f2
541 IO5 <= lfr_debug_vector(8); -- LFR APBREG ready_matrix_f2
546 IO6 <= lfr_debug_vector(9); -- LFR APBREG reg0_ready_matrix_f2
542 IO6 <= lfr_debug_vector(9); -- LFR APBREG reg0_ready_matrix_f2
547 IO7 <= lfr_debug_vector(10); -- LFR APBREG reg0_ready_matrix_f2
543 IO7 <= lfr_debug_vector(10); -- LFR APBREG reg0_ready_matrix_f2
548
544
549 all_sample : FOR I IN 7 DOWNTO 0 GENERATE
545 all_sample : FOR I IN 7 DOWNTO 0 GENERATE
550 sample_s(I) <= sample(I)(11 DOWNTO 0) & '0' & '0' & '0' & '0';
546 sample_s(I) <= sample(I)(11 DOWNTO 0) & '0' & '0' & '0' & '0';
551 END GENERATE all_sample;
547 END GENERATE all_sample;
552
548
553 top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2
549 top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2
554 GENERIC MAP(
550 GENERIC MAP(
555 ChannelCount => 8,
551 ChannelCount => 8,
556 SampleNbBits => 14,
552 SampleNbBits => 14,
557 ncycle_cnv_high => 40, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 /2 = 31.5
553 ncycle_cnv_high => 40, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 /2 = 31.5
558 ncycle_cnv => 249) -- 49 152 000 / 98304 /2
554 ncycle_cnv => 249) -- 49 152 000 / 98304 /2
559 PORT MAP (
555 PORT MAP (
560 -- CONV
556 -- CONV
561 cnv_clk => clk_24,
557 cnv_clk => clk_24,
562 cnv_rstn => rstn_25,
558 cnv_rstn => rstn_25,
563 cnv => ADC_nCS_sig,
559 cnv => ADC_nCS_sig,
564 -- DATA
560 -- DATA
565 clk => clk_25,
561 clk => clk_25,
566 rstn => rstn_25,
562 rstn => rstn_25,
567 sck => ADC_CLK_sig,
563 sck => ADC_CLK_sig,
568 sdo => ADC_SDO_sig,
564 sdo => ADC_SDO_sig,
569 -- SAMPLE
565 -- SAMPLE
570 sample => sample,
566 sample => sample,
571 sample_val => sample_val);
567 sample_val => sample_val);
572
568
573 --IO10 <= ADC_SDO_sig(5);
569 --IO10 <= ADC_SDO_sig(5);
574 --IO9 <= ADC_SDO_sig(4);
570 --IO9 <= ADC_SDO_sig(4);
575 --IO8 <= ADC_SDO_sig(3);
571 --IO8 <= ADC_SDO_sig(3);
576
572
577 ADC_nCS <= ADC_nCS_sig;
573 ADC_nCS <= ADC_nCS_sig;
578 ADC_CLK <= ADC_CLK_sig;
574 ADC_CLK <= ADC_CLK_sig;
579 ADC_SDO_sig <= ADC_SDO;
575 ADC_SDO_sig <= ADC_SDO;
580
576
581 lpp_lfr_hk_1: lpp_lfr_hk
582 GENERIC MAP (
583 pindex => 7,
584 paddr => 7,
585 pmask => 16#fff#)
586 PORT MAP (
587 clk => clk_25,
588 rstn => rstn_25,
589
590 apbi => apbi_ext,
591 apbo => apbo_ext(7),
592
593 sample_val => sample_val,
594 sample => sample_hk,
595 HK_SEL => HK_SEL);
596
597 sample_hk <= "0001000100010001" WHEN HK_SEL = "00" ELSE
598 "0010001000100010" WHEN HK_SEL = "10" ELSE
599 "0100010001000100" WHEN HK_SEL = "10" ELSE
600 (OTHERS => '0');
601
602
603 ----------------------------------------------------------------------
577 ----------------------------------------------------------------------
604 --- GPIO -----------------------------------------------------------
578 --- GPIO -----------------------------------------------------------
605 ----------------------------------------------------------------------
579 ----------------------------------------------------------------------
606
580
607 grgpio0 : grgpio
581 grgpio0 : grgpio
608 GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8)
582 GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8)
609 PORT MAP(rstn_25, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo);
583 PORT MAP(rstn_25, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo);
610
584
611 gpioi.sig_en <= (OTHERS => '0');
585 gpioi.sig_en <= (OTHERS => '0');
612 gpioi.sig_in <= (OTHERS => '0');
586 gpioi.sig_in <= (OTHERS => '0');
613 gpioi.din <= (OTHERS => '0');
587 gpioi.din <= (OTHERS => '0');
614 --pio_pad_0 : iopad
588 --pio_pad_0 : iopad
615 -- GENERIC MAP (tech => CFG_PADTECH)
589 -- GENERIC MAP (tech => CFG_PADTECH)
616 -- PORT MAP (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0));
590 -- PORT MAP (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0));
617 --pio_pad_1 : iopad
591 --pio_pad_1 : iopad
618 -- GENERIC MAP (tech => CFG_PADTECH)
592 -- GENERIC MAP (tech => CFG_PADTECH)
619 -- PORT MAP (IO1, gpioo.dout(1), gpioo.oen(1), gpioi.din(1));
593 -- PORT MAP (IO1, gpioo.dout(1), gpioo.oen(1), gpioi.din(1));
620 --pio_pad_2 : iopad
594 --pio_pad_2 : iopad
621 -- GENERIC MAP (tech => CFG_PADTECH)
595 -- GENERIC MAP (tech => CFG_PADTECH)
622 -- PORT MAP (IO2, gpioo.dout(2), gpioo.oen(2), gpioi.din(2));
596 -- PORT MAP (IO2, gpioo.dout(2), gpioo.oen(2), gpioi.din(2));
623 --pio_pad_3 : iopad
597 --pio_pad_3 : iopad
624 -- GENERIC MAP (tech => CFG_PADTECH)
598 -- GENERIC MAP (tech => CFG_PADTECH)
625 -- PORT MAP (IO3, gpioo.dout(3), gpioo.oen(3), gpioi.din(3));
599 -- PORT MAP (IO3, gpioo.dout(3), gpioo.oen(3), gpioi.din(3));
626 --pio_pad_4 : iopad
600 --pio_pad_4 : iopad
627 -- GENERIC MAP (tech => CFG_PADTECH)
601 -- GENERIC MAP (tech => CFG_PADTECH)
628 -- PORT MAP (IO4, gpioo.dout(4), gpioo.oen(4), gpioi.din(4));
602 -- PORT MAP (IO4, gpioo.dout(4), gpioo.oen(4), gpioi.din(4));
629 --pio_pad_5 : iopad
603 --pio_pad_5 : iopad
630 -- GENERIC MAP (tech => CFG_PADTECH)
604 -- GENERIC MAP (tech => CFG_PADTECH)
631 -- PORT MAP (IO5, gpioo.dout(5), gpioo.oen(5), gpioi.din(5));
605 -- PORT MAP (IO5, gpioo.dout(5), gpioo.oen(5), gpioi.din(5));
632 --pio_pad_6 : iopad
606 --pio_pad_6 : iopad
633 -- GENERIC MAP (tech => CFG_PADTECH)
607 -- GENERIC MAP (tech => CFG_PADTECH)
634 -- PORT MAP (IO6, gpioo.dout(6), gpioo.oen(6), gpioi.din(6));
608 -- PORT MAP (IO6, gpioo.dout(6), gpioo.oen(6), gpioi.din(6));
635 --pio_pad_7 : iopad
609 --pio_pad_7 : iopad
636 -- GENERIC MAP (tech => CFG_PADTECH)
610 -- GENERIC MAP (tech => CFG_PADTECH)
637 -- PORT MAP (IO7, gpioo.dout(7), gpioo.oen(7), gpioi.din(7));
611 -- PORT MAP (IO7, gpioo.dout(7), gpioo.oen(7), gpioi.din(7));
638
612
639 PROCESS (clk_25, rstn_25)
613 PROCESS (clk_25, rstn_25)
640 BEGIN -- PROCESS
614 BEGIN -- PROCESS
641 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
615 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
642 -- --IO0 <= '0';
616 -- --IO0 <= '0';
643 -- IO1 <= '0';
617 -- IO1 <= '0';
644 -- IO2 <= '0';
618 -- IO2 <= '0';
645 -- IO3 <= '0';
619 -- IO3 <= '0';
646 -- IO4 <= '0';
620 -- IO4 <= '0';
647 -- IO5 <= '0';
621 -- IO5 <= '0';
648 -- IO6 <= '0';
622 -- IO6 <= '0';
649 -- IO7 <= '0';
623 -- IO7 <= '0';
650 IO8 <= '0';
624 IO8 <= '0';
651 IO9 <= '0';
625 IO9 <= '0';
652 IO10 <= '0';
626 IO10 <= '0';
653 IO11 <= '0';
627 IO11 <= '0';
654 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
628 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
655 CASE gpioo.dout(2 DOWNTO 0) IS
629 CASE gpioo.dout(2 DOWNTO 0) IS
656 WHEN "011" =>
630 WHEN "011" =>
657 -- --IO0 <= observation_reg(0 );
631 -- --IO0 <= observation_reg(0 );
658 -- IO1 <= observation_reg(1 );
632 -- IO1 <= observation_reg(1 );
659 -- IO2 <= observation_reg(2 );
633 -- IO2 <= observation_reg(2 );
660 -- IO3 <= observation_reg(3 );
634 -- IO3 <= observation_reg(3 );
661 -- IO4 <= observation_reg(4 );
635 -- IO4 <= observation_reg(4 );
662 -- IO5 <= observation_reg(5 );
636 -- IO5 <= observation_reg(5 );
663 -- IO6 <= observation_reg(6 );
637 -- IO6 <= observation_reg(6 );
664 -- IO7 <= observation_reg(7 );
638 -- IO7 <= observation_reg(7 );
665 IO8 <= observation_reg(8);
639 IO8 <= observation_reg(8);
666 IO9 <= observation_reg(9);
640 IO9 <= observation_reg(9);
667 IO10 <= observation_reg(10);
641 IO10 <= observation_reg(10);
668 IO11 <= observation_reg(11);
642 IO11 <= observation_reg(11);
669 WHEN "001" =>
643 WHEN "001" =>
670 -- --IO0 <= observation_reg(0 + 12);
644 -- --IO0 <= observation_reg(0 + 12);
671 -- IO1 <= observation_reg(1 + 12);
645 -- IO1 <= observation_reg(1 + 12);
672 -- IO2 <= observation_reg(2 + 12);
646 -- IO2 <= observation_reg(2 + 12);
673 -- IO3 <= observation_reg(3 + 12);
647 -- IO3 <= observation_reg(3 + 12);
674 -- IO4 <= observation_reg(4 + 12);
648 -- IO4 <= observation_reg(4 + 12);
675 -- IO5 <= observation_reg(5 + 12);
649 -- IO5 <= observation_reg(5 + 12);
676 -- IO6 <= observation_reg(6 + 12);
650 -- IO6 <= observation_reg(6 + 12);
677 -- IO7 <= observation_reg(7 + 12);
651 -- IO7 <= observation_reg(7 + 12);
678 IO8 <= observation_reg(8 + 12);
652 IO8 <= observation_reg(8 + 12);
679 IO9 <= observation_reg(9 + 12);
653 IO9 <= observation_reg(9 + 12);
680 IO10 <= observation_reg(10 + 12);
654 IO10 <= observation_reg(10 + 12);
681 IO11 <= observation_reg(11 + 12);
655 IO11 <= observation_reg(11 + 12);
682 WHEN "010" =>
656 WHEN "010" =>
683 -- --IO0 <= observation_reg(0 + 12 + 12);
657 -- --IO0 <= observation_reg(0 + 12 + 12);
684 -- IO1 <= observation_reg(1 + 12 + 12);
658 -- IO1 <= observation_reg(1 + 12 + 12);
685 -- IO2 <= observation_reg(2 + 12 + 12);
659 -- IO2 <= observation_reg(2 + 12 + 12);
686 -- IO3 <= observation_reg(3 + 12 + 12);
660 -- IO3 <= observation_reg(3 + 12 + 12);
687 -- IO4 <= observation_reg(4 + 12 + 12);
661 -- IO4 <= observation_reg(4 + 12 + 12);
688 -- IO5 <= observation_reg(5 + 12 + 12);
662 -- IO5 <= observation_reg(5 + 12 + 12);
689 -- IO6 <= observation_reg(6 + 12 + 12);
663 -- IO6 <= observation_reg(6 + 12 + 12);
690 -- IO7 <= observation_reg(7 + 12 + 12);
664 -- IO7 <= observation_reg(7 + 12 + 12);
691 IO8 <= '0';
665 IO8 <= '0';
692 IO9 <= '0';
666 IO9 <= '0';
693 IO10 <= '0';
667 IO10 <= '0';
694 IO11 <= '0';
668 IO11 <= '0';
695 WHEN "000" =>
669 WHEN "000" =>
696 -- --IO0 <= observation_vector_0(0 );
670 -- --IO0 <= observation_vector_0(0 );
697 -- IO1 <= observation_vector_0(1 );
671 -- IO1 <= observation_vector_0(1 );
698 -- IO2 <= observation_vector_0(2 );
672 -- IO2 <= observation_vector_0(2 );
699 -- IO3 <= observation_vector_0(3 );
673 -- IO3 <= observation_vector_0(3 );
700 -- IO4 <= observation_vector_0(4 );
674 -- IO4 <= observation_vector_0(4 );
701 -- IO5 <= observation_vector_0(5 );
675 -- IO5 <= observation_vector_0(5 );
702 -- IO6 <= observation_vector_0(6 );
676 -- IO6 <= observation_vector_0(6 );
703 -- IO7 <= observation_vector_0(7 );
677 -- IO7 <= observation_vector_0(7 );
704 IO8 <= observation_vector_0(8);
678 IO8 <= observation_vector_0(8);
705 IO9 <= observation_vector_0(9);
679 IO9 <= observation_vector_0(9);
706 IO10 <= observation_vector_0(10);
680 IO10 <= observation_vector_0(10);
707 IO11 <= observation_vector_0(11);
681 IO11 <= observation_vector_0(11);
708 WHEN "100" =>
682 WHEN "100" =>
709 -- --IO0 <= observation_vector_1(0 );
683 -- --IO0 <= observation_vector_1(0 );
710 -- IO1 <= observation_vector_1(1 );
684 -- IO1 <= observation_vector_1(1 );
711 -- IO2 <= observation_vector_1(2 );
685 -- IO2 <= observation_vector_1(2 );
712 -- IO3 <= observation_vector_1(3 );
686 -- IO3 <= observation_vector_1(3 );
713 -- IO4 <= observation_vector_1(4 );
687 -- IO4 <= observation_vector_1(4 );
714 -- IO5 <= observation_vector_1(5 );
688 -- IO5 <= observation_vector_1(5 );
715 -- IO6 <= observation_vector_1(6 );
689 -- IO6 <= observation_vector_1(6 );
716 -- IO7 <= observation_vector_1(7 );
690 -- IO7 <= observation_vector_1(7 );
717 IO8 <= observation_vector_1(8);
691 IO8 <= observation_vector_1(8);
718 IO9 <= observation_vector_1(9);
692 IO9 <= observation_vector_1(9);
719 IO10 <= observation_vector_1(10);
693 IO10 <= observation_vector_1(10);
720 IO11 <= observation_vector_1(11);
694 IO11 <= observation_vector_1(11);
721 WHEN OTHERS => NULL;
695 WHEN OTHERS => NULL;
722 END CASE;
696 END CASE;
723
697
724 END IF;
698 END IF;
725 END PROCESS;
699 END PROCESS;
726 -----------------------------------------------------------------------------
700 -----------------------------------------------------------------------------
727 --
701 --
728 -----------------------------------------------------------------------------
702 -----------------------------------------------------------------------------
729 all_apbo_ext : FOR I IN NB_APB_SLAVE-1+5 DOWNTO 5 GENERATE
703 all_apbo_ext : FOR I IN NB_APB_SLAVE-1+5 DOWNTO 5 GENERATE
730 apbo_ext_not_used : IF I /= 5 AND I /= 6 AND I /= 7 AND I /= 11 AND I /= 15 GENERATE
704 apbo_ext_not_used : IF I /= 5 AND I /= 6 AND I /= 11 AND I /= 15 GENERATE
731 apbo_ext(I) <= apb_none;
705 apbo_ext(I) <= apb_none;
732 END GENERATE apbo_ext_not_used;
706 END GENERATE apbo_ext_not_used;
733 END GENERATE all_apbo_ext;
707 END GENERATE all_apbo_ext;
734
708
735
709
736 all_ahbo_ext : FOR I IN NB_AHB_SLAVE-1+3 DOWNTO 3 GENERATE
710 all_ahbo_ext : FOR I IN NB_AHB_SLAVE-1+3 DOWNTO 3 GENERATE
737 ahbo_s_ext(I) <= ahbs_none;
711 ahbo_s_ext(I) <= ahbs_none;
738 END GENERATE all_ahbo_ext;
712 END GENERATE all_ahbo_ext;
739
713
740 all_ahbo_m_ext : FOR I IN NB_AHB_MASTER-1+1 DOWNTO 1 GENERATE
714 all_ahbo_m_ext : FOR I IN NB_AHB_MASTER-1+1 DOWNTO 1 GENERATE
741 ahbo_m_ext_not_used : IF I /= 1 AND I /= 2 GENERATE
715 ahbo_m_ext_not_used : IF I /= 1 AND I /= 2 GENERATE
742 ahbo_m_ext(I) <= ahbm_none;
716 ahbo_m_ext(I) <= ahbm_none;
743 END GENERATE ahbo_m_ext_not_used;
717 END GENERATE ahbo_m_ext_not_used;
744 END GENERATE all_ahbo_m_ext;
718 END GENERATE all_ahbo_m_ext;
745
719
746 END beh;
720 END beh;
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@@ -1,385 +1,384
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- jean-christophe.pellion@easii-ic.com
21 -- jean-christophe.pellion@easii-ic.com
22 ----------------------------------------------------------------------------
22 ----------------------------------------------------------------------------
23
23
24 LIBRARY ieee;
24 LIBRARY ieee;
25 USE ieee.std_logic_1164.ALL;
25 USE ieee.std_logic_1164.ALL;
26 USE ieee.numeric_std.all;
26 USE ieee.numeric_std.all;
27
27
28 LIBRARY lpp;
28 LIBRARY lpp;
29 USE lpp.cic_pkg.ALL;
29 USE lpp.cic_pkg.ALL;
30 USE lpp.data_type_pkg.ALL;
30 USE lpp.data_type_pkg.ALL;
31 USE lpp.iir_filter.ALL;
31 USE lpp.iir_filter.ALL;
32
32
33 LIBRARY techmap;
33 LIBRARY techmap;
34 USE techmap.gencomp.ALL;
34 USE techmap.gencomp.ALL;
35
35
36 ENTITY cic_lfr IS
36 ENTITY cic_lfr IS
37 GENERIC(
37 GENERIC(
38 tech : INTEGER := 0;
38 tech : INTEGER := 0;
39 use_RAM_nCEL : INTEGER := 0 -- 1 => RAM(tech) , 0 => RAM_CEL
39 use_RAM_nCEL : INTEGER := 1 -- 1 => RAM(tech) , 0 => RAM_CEL
40 );
40 );
41 PORT (
41 PORT (
42 clk : IN STD_LOGIC;
42 clk : IN STD_LOGIC;
43 rstn : IN STD_LOGIC;
43 rstn : IN STD_LOGIC;
44 run : IN STD_LOGIC;
44 run : IN STD_LOGIC;
45
45
46 data_in : IN sample_vector(5 DOWNTO 0,15 DOWNTO 0);
46 data_in : IN sample_vector(5 DOWNTO 0,15 DOWNTO 0);
47 data_in_valid : IN STD_LOGIC;
47 data_in_valid : IN STD_LOGIC;
48
48
49 data_out_16 : OUT sample_vector(5 DOWNTO 0,15 DOWNTO 0);
49 data_out_16 : OUT sample_vector(5 DOWNTO 0,15 DOWNTO 0);
50 data_out_16_valid : OUT STD_LOGIC;
50 data_out_16_valid : OUT STD_LOGIC;
51 data_out_256 : OUT sample_vector(5 DOWNTO 0,15 DOWNTO 0);
51 data_out_256 : OUT sample_vector(5 DOWNTO 0,15 DOWNTO 0);
52 data_out_256_valid : OUT STD_LOGIC
52 data_out_256_valid : OUT STD_LOGIC
53 );
53 );
54
54
55 END cic_lfr;
55 END cic_lfr;
56
56
57 ARCHITECTURE beh OF cic_lfr IS
57 ARCHITECTURE beh OF cic_lfr IS
58 --
58 --
59 SIGNAL sel_sample : STD_LOGIC_VECTOR(2 DOWNTO 0);
59 SIGNAL sel_sample : STD_LOGIC_VECTOR(2 DOWNTO 0);
60 SIGNAL sample_temp : sample_vector(5 DOWNTO 0,15 DOWNTO 0);
60 SIGNAL sample_temp : sample_vector(5 DOWNTO 0,15 DOWNTO 0);
61 SIGNAL sample : STD_LOGIC_VECTOR(15 DOWNTO 0);
61 SIGNAL sample : STD_LOGIC_VECTOR(15 DOWNTO 0);
62 --
62 --
63 SIGNAL sel_A : STD_LOGIC_VECTOR(1 DOWNTO 0);
63 SIGNAL sel_A : STD_LOGIC_VECTOR(1 DOWNTO 0);
64 SIGNAL data_A_temp : sample_vector(2 DOWNTO 0,15 DOWNTO 0);
64 SIGNAL data_A_temp : sample_vector(2 DOWNTO 0,15 DOWNTO 0);
65 SIGNAL data_A : STD_LOGIC_VECTOR(15 DOWNTO 0);
65 SIGNAL data_A : STD_LOGIC_VECTOR(15 DOWNTO 0);
66 --
66 --
67 SIGNAL ALU_OP : STD_LOGIC_VECTOR(1 DOWNTO 0);
67 SIGNAL ALU_OP : STD_LOGIC_VECTOR(1 DOWNTO 0);
68 SIGNAL data_B : STD_LOGIC_VECTOR(15 DOWNTO 0);
68 SIGNAL data_B : STD_LOGIC_VECTOR(15 DOWNTO 0);
69 SIGNAL data_B_reg : STD_LOGIC_VECTOR(15 DOWNTO 0);
69 SIGNAL data_B_reg : STD_LOGIC_VECTOR(15 DOWNTO 0);
70 SIGNAL data_out : STD_LOGIC_VECTOR(15 DOWNTO 0);
70 SIGNAL data_out : STD_LOGIC_VECTOR(15 DOWNTO 0);
71 SIGNAL data_in_Carry : STD_LOGIC;
71 SIGNAL data_in_Carry : STD_LOGIC;
72 SIGNAL data_out_Carry : STD_LOGIC;
72 SIGNAL data_out_Carry : STD_LOGIC;
73 --
73 --
74 CONSTANT S_parameter : INTEGER := 3;
74 CONSTANT S_parameter : INTEGER := 3;
75 SIGNAL carry_reg : STD_LOGIC_VECTOR(S_parameter-1 DOWNTO 0);
75 SIGNAL carry_reg : STD_LOGIC_VECTOR(S_parameter-1 DOWNTO 0);
76 SIGNAL CARRY_PUSH : STD_LOGIC;
76 SIGNAL CARRY_PUSH : STD_LOGIC;
77 SIGNAL CARRY_POP : STD_LOGIC;
77 SIGNAL CARRY_POP : STD_LOGIC;
78 --
78 --
79
79
80 SIGNAL OPERATION : STD_LOGIC_VECTOR(15 DOWNTO 0);
80 SIGNAL OPERATION : STD_LOGIC_VECTOR(15 DOWNTO 0);
81 SIGNAL OPERATION_reg: STD_LOGIC_VECTOR(15 DOWNTO 0);
81 SIGNAL OPERATION_reg: STD_LOGIC_VECTOR(15 DOWNTO 0);
82 SIGNAL OPERATION_reg2: STD_LOGIC_VECTOR(15 DOWNTO 0);
82 SIGNAL OPERATION_reg2: STD_LOGIC_VECTOR(15 DOWNTO 0);
83
83
84 -----------------------------------------------------------------------------
84 -----------------------------------------------------------------------------
85 TYPE ARRAY_OF_ADDR IS ARRAY (5 DOWNTO 0) OF STD_LOGIC_VECTOR(7 DOWNTO 0);
85 TYPE ARRAY_OF_ADDR IS ARRAY (5 DOWNTO 0) OF STD_LOGIC_VECTOR(7 DOWNTO 0);
86 SIGNAL base_addr_INT : ARRAY_OF_ADDR;
86 SIGNAL base_addr_INT : ARRAY_OF_ADDR;
87 CONSTANT base_addr_delta : INTEGER := 40;
87 CONSTANT base_addr_delta : INTEGER := 40;
88 SIGNAL addr_base_sel : STD_LOGIC_VECTOR(7 DOWNTO 0);
88 SIGNAL addr_base_sel : STD_LOGIC_VECTOR(7 DOWNTO 0);
89 SIGNAL addr_gen: STD_LOGIC_VECTOR(7 DOWNTO 0);
89 SIGNAL addr_gen: STD_LOGIC_VECTOR(7 DOWNTO 0);
90 SIGNAL addr_read: STD_LOGIC_VECTOR(7 DOWNTO 0);
90 SIGNAL addr_read: STD_LOGIC_VECTOR(7 DOWNTO 0);
91 SIGNAL addr_write: STD_LOGIC_VECTOR(7 DOWNTO 0);
91 SIGNAL addr_write: STD_LOGIC_VECTOR(7 DOWNTO 0);
92 SIGNAL addr_write_mux: STD_LOGIC_VECTOR(7 DOWNTO 0);
92 SIGNAL addr_write_mux: STD_LOGIC_VECTOR(7 DOWNTO 0);
93 SIGNAL addr_write_s: STD_LOGIC_VECTOR(7 DOWNTO 0);
93 SIGNAL addr_write_s: STD_LOGIC_VECTOR(7 DOWNTO 0);
94 SIGNAL data_we: STD_LOGIC;
94 SIGNAL data_we: STD_LOGIC;
95 SIGNAL data_we_s: STD_LOGIC;
95 SIGNAL data_we_s: STD_LOGIC;
96 SIGNAL data_wen : STD_LOGIC;
96 SIGNAL data_wen : STD_LOGIC;
97 -- SIGNAL data_write : STD_LOGIC_VECTOR(15 DOWNTO 0);
97 -- SIGNAL data_write : STD_LOGIC_VECTOR(15 DOWNTO 0);
98 -- SIGNAL data_read : STD_LOGIC_VECTOR(15 DOWNTO 0);
98 -- SIGNAL data_read : STD_LOGIC_VECTOR(15 DOWNTO 0);
99 -- SIGNAL data_read_pre : STD_LOGIC_VECTOR(15 DOWNTO 0);
99 -- SIGNAL data_read_pre : STD_LOGIC_VECTOR(15 DOWNTO 0);
100 -----------------------------------------------------------------------------
100 -----------------------------------------------------------------------------
101 SIGNAL sample_out_reg16 : sample_vector(6*2-1 DOWNTO 0, 15 DOWNTO 0);
101 SIGNAL sample_out_reg16 : sample_vector(6*2-1 DOWNTO 0, 15 DOWNTO 0);
102 SIGNAL sample_out_reg256 : sample_vector(6*3-1 DOWNTO 0, 15 DOWNTO 0);
102 SIGNAL sample_out_reg256 : sample_vector(6*3-1 DOWNTO 0, 15 DOWNTO 0);
103 SIGNAL sample_valid_reg16 : STD_LOGIC_VECTOR(6*2 DOWNTO 0);
103 SIGNAL sample_valid_reg16 : STD_LOGIC_VECTOR(6*2 DOWNTO 0);
104 SIGNAL sample_valid_reg256: STD_LOGIC_VECTOR(6*3 DOWNTO 0);
104 SIGNAL sample_valid_reg256: STD_LOGIC_VECTOR(6*3 DOWNTO 0);
105 SIGNAL data_out_16_valid_s : STD_LOGIC;
105 SIGNAL data_out_16_valid_s : STD_LOGIC;
106 SIGNAL data_out_256_valid_s : STD_LOGIC;
106 SIGNAL data_out_256_valid_s : STD_LOGIC;
107 SIGNAL data_out_16_valid_s1 : STD_LOGIC;
107 SIGNAL data_out_16_valid_s1 : STD_LOGIC;
108 SIGNAL data_out_256_valid_s1 : STD_LOGIC;
108 SIGNAL data_out_256_valid_s1 : STD_LOGIC;
109 SIGNAL data_out_16_valid_s2 : STD_LOGIC;
109 SIGNAL data_out_16_valid_s2 : STD_LOGIC;
110 SIGNAL data_out_256_valid_s2 : STD_LOGIC;
110 SIGNAL data_out_256_valid_s2 : STD_LOGIC;
111 -----------------------------------------------------------------------------
111 -----------------------------------------------------------------------------
112 SIGNAL sample_out_reg16_s : sample_vector(5 DOWNTO 0, 16*2-1 DOWNTO 0);
112 SIGNAL sample_out_reg16_s : sample_vector(5 DOWNTO 0, 16*2-1 DOWNTO 0);
113 SIGNAL sample_out_reg256_s : sample_vector(5 DOWNTO 0, 16*3-1 DOWNTO 0);
113 SIGNAL sample_out_reg256_s : sample_vector(5 DOWNTO 0, 16*3-1 DOWNTO 0);
114 -----------------------------------------------------------------------------
114 -----------------------------------------------------------------------------
115
115
116
116
117 BEGIN
117 BEGIN
118
118
119
119
120 PROCESS (clk, rstn)
120 PROCESS (clk, rstn)
121 BEGIN -- PROCESS
121 BEGIN -- PROCESS
122 IF rstn = '0' THEN -- asynchronous reset (active low)
122 IF rstn = '0' THEN -- asynchronous reset (active low)
123 data_B_reg <= (OTHERS => '0');
123 data_B_reg <= (OTHERS => '0');
124 OPERATION_reg <= (OTHERS => '0');
124 OPERATION_reg <= (OTHERS => '0');
125 OPERATION_reg2 <= (OTHERS => '0');
125 OPERATION_reg2 <= (OTHERS => '0');
126 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
126 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
127 OPERATION_reg <= OPERATION;
127 OPERATION_reg <= OPERATION;
128 OPERATION_reg2 <= OPERATION_reg;
128 OPERATION_reg2 <= OPERATION_reg;
129 data_B_reg <= data_B;
129 data_B_reg <= data_B;
130 END IF;
130 END IF;
131 END PROCESS;
131 END PROCESS;
132
132
133
133
134 -----------------------------------------------------------------------------
134 -----------------------------------------------------------------------------
135 -- SEL_SAMPLE
135 -- SEL_SAMPLE
136 -----------------------------------------------------------------------------
136 -----------------------------------------------------------------------------
137 sel_sample <= OPERATION_reg(2 DOWNTO 0);
137 sel_sample <= OPERATION_reg(2 DOWNTO 0);
138
138
139 all_bit: FOR I IN 15 DOWNTO 0 GENERATE
139 all_bit: FOR I IN 15 DOWNTO 0 GENERATE
140 sample_temp(0,I) <= data_in(0,I) WHEN sel_sample(0) = '0' ELSE data_in(1,I);
140 sample_temp(0,I) <= data_in(0,I) WHEN sel_sample(0) = '0' ELSE data_in(1,I);
141 sample_temp(1,I) <= data_in(2,I) WHEN sel_sample(0) = '0' ELSE data_in(3,I);
141 sample_temp(1,I) <= data_in(2,I) WHEN sel_sample(0) = '0' ELSE data_in(3,I);
142 sample_temp(2,I) <= data_in(4,I) WHEN sel_sample(0) = '0' ELSE data_in(5,I);
142 sample_temp(2,I) <= data_in(4,I) WHEN sel_sample(0) = '0' ELSE data_in(5,I);
143
143
144 sample_temp(4,I) <= sample_temp(0,I) WHEN sel_sample(1) = '0' ELSE sample_temp(1,I);
144 sample_temp(4,I) <= sample_temp(0,I) WHEN sel_sample(1) = '0' ELSE sample_temp(1,I);
145 sample_temp(5,I) <= sample_temp(2,I) WHEN sel_sample(1) = '0' ELSE '0';
145 sample_temp(5,I) <= sample_temp(2,I) WHEN sel_sample(1) = '0' ELSE '0';
146
146
147 sample(I) <= sample_temp(4,I) WHEN sel_sample(2) = '0' ELSE sample_temp(5,I);
147 sample(I) <= sample_temp(4,I) WHEN sel_sample(2) = '0' ELSE sample_temp(5,I);
148 END GENERATE all_bit;
148 END GENERATE all_bit;
149
149
150 -----------------------------------------------------------------------------
150 -----------------------------------------------------------------------------
151 -- SEL_DATA_IN_A
151 -- SEL_DATA_IN_A
152 -----------------------------------------------------------------------------
152 -----------------------------------------------------------------------------
153 sel_A <= OPERATION_reg(4 DOWNTO 3);
153 sel_A <= OPERATION_reg(4 DOWNTO 3);
154
154
155 all_data_mux_A: FOR I IN 15 DOWNTO 0 GENERATE
155 all_data_mux_A: FOR I IN 15 DOWNTO 0 GENERATE
156 data_A_temp(0,I) <= sample(I) WHEN sel_A(0) = '0' ELSE data_out(I);
156 data_A_temp(0,I) <= sample(I) WHEN sel_A(0) = '0' ELSE data_out(I);
157 data_A_temp(1,I) <= '0' WHEN sel_A(0) = '0' ELSE sample(15);
157 data_A_temp(1,I) <= '0' WHEN sel_A(0) = '0' ELSE sample(15);
158 data_A_temp(2,I) <= data_A_temp(0,I) WHEN sel_A(1) = '0' ELSE data_A_temp(1,I);
158 data_A_temp(2,I) <= data_A_temp(0,I) WHEN sel_A(1) = '0' ELSE data_A_temp(1,I);
159 data_A(I) <= data_A_temp(2,I) WHEN OPERATION_reg(14) = '0' ELSE data_B_reg(I);
159 data_A(I) <= data_A_temp(2,I) WHEN OPERATION_reg(14) = '0' ELSE data_B_reg(I);
160 END GENERATE all_data_mux_A;
160 END GENERATE all_data_mux_A;
161
161
162
162
163
163
164 -----------------------------------------------------------------------------
164 -----------------------------------------------------------------------------
165 -- ALU
165 -- ALU
166 -----------------------------------------------------------------------------
166 -----------------------------------------------------------------------------
167 ALU_OP <= OPERATION_reg(6 DOWNTO 5);
167 ALU_OP <= OPERATION_reg(6 DOWNTO 5);
168
168
169 ALU: cic_lfr_add_sub
169 ALU: cic_lfr_add_sub
170 PORT MAP (
170 PORT MAP (
171 clk => clk,
171 clk => clk,
172 rstn => rstn,
172 rstn => rstn,
173 run => run,
173 run => run,
174
174
175 OP => ALU_OP,
175 OP => ALU_OP,
176
176
177 data_in_A => data_A,
177 data_in_A => data_A,
178 data_in_B => data_B,
178 data_in_B => data_B,
179 data_in_Carry => data_in_Carry,
179 data_in_Carry => data_in_Carry,
180
180
181 data_out => data_out,
181 data_out => data_out,
182 data_out_Carry => data_out_Carry);
182 data_out_Carry => data_out_Carry);
183
183
184 -----------------------------------------------------------------------------
184 -----------------------------------------------------------------------------
185 -- CARRY_MANAGER
185 -- CARRY_MANAGER
186 -----------------------------------------------------------------------------
186 -----------------------------------------------------------------------------
187 data_in_Carry <= carry_reg(S_parameter-2) WHEN OPERATION_reg(7) = '0' ELSE carry_reg(S_parameter-1);
187 data_in_Carry <= carry_reg(S_parameter-2) WHEN OPERATION_reg(7) = '0' ELSE carry_reg(S_parameter-1);
188
188
189 -- CARRY_PUSH <= OPERATION_reg(7);
189 -- CARRY_PUSH <= OPERATION_reg(7);
190 -- CARRY_POP <= OPERATION_reg(6);
190 -- CARRY_POP <= OPERATION_reg(6);
191
191
192 PROCESS (clk, rstn)
192 PROCESS (clk, rstn)
193 BEGIN -- PROCESS
193 BEGIN -- PROCESS
194 IF rstn = '0' THEN -- asynchronous reset (active low)
194 IF rstn = '0' THEN -- asynchronous reset (active low)
195 carry_reg <= (OTHERS => '0');
195 carry_reg <= (OTHERS => '0');
196 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
196 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
197 --IF CARRY_POP = '1' OR CARRY_PUSH = '1' THEN
197 --IF CARRY_POP = '1' OR CARRY_PUSH = '1' THEN
198 carry_reg(S_parameter-1 DOWNTO 1) <= carry_reg(S_parameter-2 DOWNTO 0);
198 carry_reg(S_parameter-1 DOWNTO 1) <= carry_reg(S_parameter-2 DOWNTO 0);
199 carry_reg(0) <= data_out_Carry;
199 carry_reg(0) <= data_out_Carry;
200 --END IF;
200 --END IF;
201 END IF;
201 END IF;
202 END PROCESS;
202 END PROCESS;
203
203
204 -----------------------------------------------------------------------------
204 -----------------------------------------------------------------------------
205 -- MEMORY
205 -- MEMORY
206 -----------------------------------------------------------------------------
206 -----------------------------------------------------------------------------
207 all_channel: FOR I IN 5 DOWNTO 0 GENERATE
207 all_channel: FOR I IN 5 DOWNTO 0 GENERATE
208 all_bit: FOR J IN 7 DOWNTO 0 GENERATE
208 all_bit: FOR J IN 7 DOWNTO 0 GENERATE
209 base_addr_INT(I)(J) <= '1' WHEN (base_addr_delta * I/(2**J)) MOD 2 = 1 ELSE '0';
209 base_addr_INT(I)(J) <= '1' WHEN (base_addr_delta * I/(2**J)) MOD 2 = 1 ELSE '0';
210 END GENERATE all_bit;
210 END GENERATE all_bit;
211 END GENERATE all_channel;
211 END GENERATE all_channel;
212 addr_base_sel <= base_addr_INT(to_integer(UNSIGNED(OPERATION(2 DOWNTO 0))));
212 addr_base_sel <= base_addr_INT(to_integer(UNSIGNED(OPERATION(2 DOWNTO 0))));
213
213
214 cic_lfr_address_gen_1: cic_lfr_address_gen
214 cic_lfr_address_gen_1: cic_lfr_address_gen
215 PORT MAP (
215 PORT MAP (
216 clk => clk,
216 clk => clk,
217 rstn => rstn,
217 rstn => rstn,
218 run => run,
218 run => run,
219
219
220 addr_base => addr_base_sel,
220 addr_base => addr_base_sel,
221 addr_init => OPERATION(8),
221 addr_init => OPERATION(8),
222 addr_add_1 => OPERATION(9),
222 addr_add_1 => OPERATION(9),
223 addr => addr_gen);
223 addr => addr_gen);
224
224
225
225
226 addr_read <= addr_gen WHEN OPERATION(12 DOWNTO 10) = "000" ELSE
226 addr_read <= addr_gen WHEN OPERATION(12 DOWNTO 10) = "000" ELSE
227 STD_LOGIC_VECTOR(to_unsigned(to_integer(UNSIGNED(addr_base_sel))+2,8)) WHEN OPERATION(12 DOWNTO 10) = "001" ELSE
227 STD_LOGIC_VECTOR(to_unsigned(to_integer(UNSIGNED(addr_base_sel))+2,8)) WHEN OPERATION(12 DOWNTO 10) = "001" ELSE
228 STD_LOGIC_VECTOR(to_unsigned(to_integer(UNSIGNED(addr_base_sel))+5,8)) WHEN OPERATION(12 DOWNTO 10) = "010" ELSE
228 STD_LOGIC_VECTOR(to_unsigned(to_integer(UNSIGNED(addr_base_sel))+5,8)) WHEN OPERATION(12 DOWNTO 10) = "010" ELSE
229 STD_LOGIC_VECTOR(to_unsigned(to_integer(UNSIGNED(addr_base_sel))+8,8)) WHEN OPERATION(12 DOWNTO 10) = "011" ELSE
229 STD_LOGIC_VECTOR(to_unsigned(to_integer(UNSIGNED(addr_base_sel))+8,8)) WHEN OPERATION(12 DOWNTO 10) = "011" ELSE
230 STD_LOGIC_VECTOR(to_unsigned(to_integer(UNSIGNED(addr_gen ))+6,8)) WHEN OPERATION(12 DOWNTO 10) = "100" ELSE
230 STD_LOGIC_VECTOR(to_unsigned(to_integer(UNSIGNED(addr_gen ))+6,8)) WHEN OPERATION(12 DOWNTO 10) = "100" ELSE
231 STD_LOGIC_VECTOR(to_unsigned(to_integer(UNSIGNED(addr_gen ))+15,8));
231 STD_LOGIC_VECTOR(to_unsigned(to_integer(UNSIGNED(addr_gen ))+15,8));
232
232
233 PROCESS (clk, rstn)
233 PROCESS (clk, rstn)
234 BEGIN -- PROCESS
234 BEGIN -- PROCESS
235 IF rstn = '0' THEN -- asynchronous reset (active low)
235 IF rstn = '0' THEN -- asynchronous reset (active low)
236 addr_write <= (OTHERS => '0');
236 addr_write <= (OTHERS => '0');
237 data_we <= '0';
237 data_we <= '0';
238 addr_write_s <= (OTHERS => '0');
238 addr_write_s <= (OTHERS => '0');
239 data_we_s <= '0';
239 data_we_s <= '0';
240 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
240 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
241 addr_write_s <= addr_read;
241 addr_write_s <= addr_read;
242 data_we_s <= OPERATION(13);
242 data_we_s <= OPERATION(13);
243 IF OPERATION_reg(15) = '0' THEN
243 IF OPERATION_reg(15) = '0' THEN
244 addr_write <= addr_write_s;
244 addr_write <= addr_write_s;
245 ELSE
245 ELSE
246 addr_write <= addr_read;
246 addr_write <= addr_read;
247 END IF;
247 END IF;
248 data_we <= data_we_s;
248 data_we <= data_we_s;
249 END IF;
249 END IF;
250 END PROCESS;
250 END PROCESS;
251
251
252 memCEL : IF use_RAM_nCEL = 0 GENERATE
252 memCEL : IF use_RAM_nCEL = 0 GENERATE
253 data_wen <= NOT data_we;
253 data_wen <= NOT data_we;
254 RAMblk : RAM_CEL
254 RAMblk : RAM_CEL
255 GENERIC MAP(16, 8)
255 GENERIC MAP(16, 8)
256 PORT MAP(
256 PORT MAP(
257 WD => data_out,
257 WD => data_out,
258 RD => data_B,
258 RD => data_B,
259 WEN => data_wen,
259 WEN => data_wen,
260 REN => '0',
260 REN => '0',
261 WADDR => addr_write,
261 WADDR => addr_write,
262 RADDR => addr_read,
262 RADDR => addr_read,
263 RWCLK => clk,
263 RWCLK => clk,
264 RESET => rstn
264 RESET => rstn
265 ) ;
265 ) ;
266 END GENERATE;
266 END GENERATE;
267
267
268 memRAM : IF use_RAM_nCEL = 1 GENERATE
268 memRAM : IF use_RAM_nCEL = 1 GENERATE
269 SRAM : syncram_2p
269 SRAM : syncram_2p
270 GENERIC MAP(tech, 8, 16)
270 GENERIC MAP(tech, 8, 16)
271 PORT MAP(clk, '1', addr_read, data_B,
271 PORT MAP(clk, '1', addr_read, data_B,
272 clk, data_we, addr_write, data_out);
272 clk, data_we, addr_write, data_out);
273 END GENERATE;
273 END GENERATE;
274
274
275 -----------------------------------------------------------------------------
275 -----------------------------------------------------------------------------
276 -- CONTROL
276 -- CONTROL
277 -----------------------------------------------------------------------------
277 -----------------------------------------------------------------------------
278 cic_lfr_control_1: cic_lfr_control
278 cic_lfr_control_1: cic_lfr_control
279 PORT MAP (
279 PORT MAP (
280 clk => clk,
280 clk => clk,
281 rstn => rstn,
281 rstn => rstn,
282 run => run,
282 run => run,
283 data_in_valid => data_in_valid,
283 data_in_valid => data_in_valid,
284 data_out_16_valid => data_out_16_valid_s,
284 data_out_16_valid => data_out_16_valid_s,
285 data_out_256_valid => data_out_256_valid_s,
285 data_out_256_valid => data_out_256_valid_s,
286 OPERATION => OPERATION);
286 OPERATION => OPERATION);
287
287
288 -----------------------------------------------------------------------------
288 -----------------------------------------------------------------------------
289 PROCESS (clk, rstn)
289 PROCESS (clk, rstn)
290 BEGIN -- PROCESS
290 BEGIN -- PROCESS
291 IF rstn = '0' THEN -- asynchronous reset (active low)
291 IF rstn = '0' THEN -- asynchronous reset (active low)
292 data_out_16_valid_s1 <= '0';
292 data_out_16_valid_s1 <= '0';
293 data_out_256_valid_s1 <= '0';
293 data_out_256_valid_s1 <= '0';
294 data_out_16_valid_s2 <= '0';
294 data_out_16_valid_s2 <= '0';
295 data_out_256_valid_s2 <= '0';
295 data_out_256_valid_s2 <= '0';
296 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
296 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
297 data_out_16_valid_s1 <= data_out_16_valid_s;
297 data_out_16_valid_s1 <= data_out_16_valid_s;
298 data_out_256_valid_s1 <= data_out_256_valid_s;
298 data_out_256_valid_s1 <= data_out_256_valid_s;
299 data_out_16_valid_s2 <= data_out_16_valid_s1;
299 data_out_16_valid_s2 <= data_out_16_valid_s1;
300 data_out_256_valid_s2 <= data_out_256_valid_s1;
300 data_out_256_valid_s2 <= data_out_256_valid_s1;
301 END IF;
301 END IF;
302 END PROCESS;
302 END PROCESS;
303
303
304 PROCESS (clk, rstn)
304 PROCESS (clk, rstn)
305 BEGIN -- PROCESS
305 BEGIN -- PROCESS
306 IF rstn = '0' THEN -- asynchronous reset (active low)
306 IF rstn = '0' THEN -- asynchronous reset (active low)
307 sample_valid_reg16 <= '0' & "000000" & "000001";
307 sample_valid_reg16 <= '0' & "000000" & "000001";
308 sample_valid_reg256 <= '0' & "000000" & "000000" & "000001";
308 sample_valid_reg256 <= '0' & "000000" & "000000" & "000001";
309 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
309 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
310 IF run = '0' THEN
310 IF run = '0' THEN
311 sample_valid_reg16 <= '0' & "000000" & "000001";
311 sample_valid_reg16 <= '0' & "000000" & "000001";
312 sample_valid_reg256 <= '0' & "000000" & "000000" & "000001";
312 sample_valid_reg256 <= '0' & "000000" & "000000" & "000001";
313 ELSE
313 ELSE
314 IF data_out_16_valid_s2 = '1' OR sample_valid_reg16(6*2) = '1' THEN
314 IF data_out_16_valid_s2 = '1' OR sample_valid_reg16(6*2) = '1' THEN
315 sample_valid_reg16 <= sample_valid_reg16(6*2-1 DOWNTO 0) & sample_valid_reg16(6*2);
315 sample_valid_reg16 <= sample_valid_reg16(6*2-1 DOWNTO 0) & sample_valid_reg16(6*2);
316 END IF;
316 END IF;
317 IF data_out_256_valid_s2 = '1' OR sample_valid_reg256(6*3) = '1' THEN
317 IF data_out_256_valid_s2 = '1' OR sample_valid_reg256(6*3) = '1' THEN
318 sample_valid_reg256 <= sample_valid_reg256(6*3-1 DOWNTO 0) & sample_valid_reg256(6*3);
318 sample_valid_reg256 <= sample_valid_reg256(6*3-1 DOWNTO 0) & sample_valid_reg256(6*3);
319 END IF;
319 END IF;
320 END IF;
320 END IF;
321 END IF;
321 END IF;
322 END PROCESS;
322 END PROCESS;
323
323
324 data_out_16_valid <= sample_valid_reg16(6*2);
324 data_out_16_valid <= sample_valid_reg16(6*2);
325 data_out_256_valid <= sample_valid_reg256(6*3);
325 data_out_256_valid <= sample_valid_reg256(6*3);
326
326
327 -----------------------------------------------------------------------------
327 -----------------------------------------------------------------------------
328
328
329 all_bits: FOR J IN 15 DOWNTO 0 GENERATE
329 all_bits: FOR J IN 15 DOWNTO 0 GENERATE
330 all_channel_out16: FOR I IN 6*2-1 DOWNTO 0 GENERATE
330 all_channel_out16: FOR I IN 6*2-1 DOWNTO 0 GENERATE
331 PROCESS (clk, rstn)
331 PROCESS (clk, rstn)
332 BEGIN -- PROCESS
332 BEGIN -- PROCESS
333 IF rstn = '0' THEN -- asynchronous reset (active low)
333 IF rstn = '0' THEN -- asynchronous reset (active low)
334 sample_out_reg16(I,J) <= '0';
334 sample_out_reg16(I,J) <= '0';
335 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
335 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
336 IF run = '0' THEN
336 IF run = '0' THEN
337 sample_out_reg16(I,J) <= '0';
337 sample_out_reg16(I,J) <= '0';
338 ELSE
338 ELSE
339 IF sample_valid_reg16(I) = '1' AND data_out_16_valid_s2 = '1' THEN
339 IF sample_valid_reg16(I) = '1' AND data_out_16_valid_s2 = '1' THEN
340 sample_out_reg16(I,J) <= data_out(J);
340 sample_out_reg16(I,J) <= data_out(J);
341 END IF;
341 END IF;
342 END IF;
342 END IF;
343 END IF;
343 END IF;
344 END PROCESS;
344 END PROCESS;
345 END GENERATE all_channel_out16;
345 END GENERATE all_channel_out16;
346
346
347 all_channel_out256: FOR I IN 6*3-1 DOWNTO 0 GENERATE
347 all_channel_out256: FOR I IN 6*3-1 DOWNTO 0 GENERATE
348 PROCESS (clk, rstn)
348 PROCESS (clk, rstn)
349 BEGIN -- PROCESS
349 BEGIN -- PROCESS
350 IF rstn = '0' THEN -- asynchronous reset (active low)
350 IF rstn = '0' THEN -- asynchronous reset (active low)
351 sample_out_reg256(I,J) <= '0';
351 sample_out_reg256(I,J) <= '0';
352 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
352 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
353 IF run = '0' THEN
353 IF run = '0' THEN
354 sample_out_reg256(I,J) <= '0';
354 sample_out_reg256(I,J) <= '0';
355 ELSE
355 ELSE
356 IF sample_valid_reg256(I) = '1' AND data_out_256_valid_s2 = '1' THEN
356 IF sample_valid_reg256(I) = '1' AND data_out_256_valid_s2 = '1' THEN
357 sample_out_reg256(I,J) <= data_out(J);
357 sample_out_reg256(I,J) <= data_out(J);
358 END IF;
358 END IF;
359 END IF;
359 END IF;
360 END IF;
360 END IF;
361 END PROCESS;
361 END PROCESS;
362 END GENERATE all_channel_out256;
362 END GENERATE all_channel_out256;
363 END GENERATE all_bits;
363 END GENERATE all_bits;
364
364
365
365
366 all_channel_out: FOR I IN 5 DOWNTO 0 GENERATE
366 all_channel_out: FOR I IN 5 DOWNTO 0 GENERATE
367 all_bits: FOR J IN 15 DOWNTO 0 GENERATE
367 all_bits: FOR J IN 15 DOWNTO 0 GENERATE
368 all_reg_16: FOR K IN 1 DOWNTO 0 GENERATE
368 all_reg_16: FOR K IN 1 DOWNTO 0 GENERATE
369 sample_out_reg16_s(I,J+(K*16)) <= sample_out_reg16(2*I+K,J);
369 sample_out_reg16_s(I,J+(K*16)) <= sample_out_reg16(2*I+K,J);
370 END GENERATE all_reg_16;
370 END GENERATE all_reg_16;
371 all_reg_256: FOR K IN 2 DOWNTO 0 GENERATE
371 all_reg_256: FOR K IN 2 DOWNTO 0 GENERATE
372 sample_out_reg256_s(I,J+(K*16)) <= sample_out_reg256(3*I+K,J);
372 sample_out_reg256_s(I,J+(K*16)) <= sample_out_reg256(3*I+K,J);
373 END GENERATE all_reg_256;
373 END GENERATE all_reg_256;
374 END GENERATE all_bits;
374 END GENERATE all_bits;
375 END GENERATE all_channel_out;
375 END GENERATE all_channel_out;
376
376
377 all_channel_out_v: FOR I IN 5 DOWNTO 0 GENERATE
377 all_channel_out_v: FOR I IN 5 DOWNTO 0 GENERATE
378 all_bits: FOR J IN 15 DOWNTO 0 GENERATE
378 all_bits: FOR J IN 15 DOWNTO 0 GENERATE
379 data_out_256(I,J) <= sample_out_reg256_s(I,J+16*2-32+27);
379 data_out_256(I,J) <= sample_out_reg256_s(I,J+16*2-32+27);
380 data_out_16(I,J) <= sample_out_reg16_s (I,J+16 -16+15);
380 data_out_16(I,J) <= sample_out_reg16_s (I,J+16 -16+15);
381 END GENERATE all_bits;
381 END GENERATE all_bits;
382 END GENERATE all_channel_out_v;
382 END GENERATE all_channel_out_v;
383
383
384 END beh;
384 END beh;
385
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