@@ -195,10 +195,6 ARCHITECTURE beh OF MINI_LFR_top IS | |||||
195 |
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195 | |||
196 | -- |
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196 | -- | |
197 | SIGNAL SRAM_CE_s : STD_LOGIC_VECTOR(1 DOWNTO 0); |
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197 | SIGNAL SRAM_CE_s : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
198 |
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199 | -- |
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200 | SIGNAL sample_hk : STD_LOGIC_VECTOR(15 DOWNTO 0); |
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201 | SIGNAL HK_SEL : STD_LOGIC_VECTOR( 1 DOWNTO 0); |
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202 |
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198 | |||
203 | BEGIN -- beh |
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199 | BEGIN -- beh | |
204 |
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200 | |||
@@ -515,7 +511,7 BEGIN -- beh | |||||
515 | pirq_ms => 6, |
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511 | pirq_ms => 6, | |
516 | pirq_wfp => 14, |
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512 | pirq_wfp => 14, | |
517 | hindex => 2, |
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513 | hindex => 2, | |
518 |
top_lfr_version => X"0001 |
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514 | top_lfr_version => X"000130") -- aa.bb.cc version | |
519 | PORT MAP ( |
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515 | PORT MAP ( | |
520 | clk => clk_25, |
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516 | clk => clk_25, | |
521 | rstn => LFR_rstn, |
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517 | rstn => LFR_rstn, | |
@@ -578,28 +574,6 BEGIN -- beh | |||||
578 | ADC_CLK <= ADC_CLK_sig; |
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574 | ADC_CLK <= ADC_CLK_sig; | |
579 | ADC_SDO_sig <= ADC_SDO; |
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575 | ADC_SDO_sig <= ADC_SDO; | |
580 |
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576 | |||
581 | lpp_lfr_hk_1: lpp_lfr_hk |
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582 | GENERIC MAP ( |
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583 | pindex => 7, |
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584 | paddr => 7, |
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585 | pmask => 16#fff#) |
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586 | PORT MAP ( |
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587 | clk => clk_25, |
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588 | rstn => rstn_25, |
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589 |
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590 | apbi => apbi_ext, |
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591 | apbo => apbo_ext(7), |
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592 |
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593 | sample_val => sample_val, |
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594 | sample => sample_hk, |
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595 | HK_SEL => HK_SEL); |
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596 |
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597 | sample_hk <= "0001000100010001" WHEN HK_SEL = "00" ELSE |
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598 | "0010001000100010" WHEN HK_SEL = "10" ELSE |
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599 | "0100010001000100" WHEN HK_SEL = "10" ELSE |
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600 | (OTHERS => '0'); |
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601 |
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602 |
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603 | ---------------------------------------------------------------------- |
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577 | ---------------------------------------------------------------------- | |
604 | --- GPIO ----------------------------------------------------------- |
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578 | --- GPIO ----------------------------------------------------------- | |
605 | ---------------------------------------------------------------------- |
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579 | ---------------------------------------------------------------------- | |
@@ -727,7 +701,7 BEGIN -- beh | |||||
727 | -- |
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701 | -- | |
728 | ----------------------------------------------------------------------------- |
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702 | ----------------------------------------------------------------------------- | |
729 | all_apbo_ext : FOR I IN NB_APB_SLAVE-1+5 DOWNTO 5 GENERATE |
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703 | all_apbo_ext : FOR I IN NB_APB_SLAVE-1+5 DOWNTO 5 GENERATE | |
730 |
apbo_ext_not_used : IF I /= 5 AND I /= 6 AND I /= |
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704 | apbo_ext_not_used : IF I /= 5 AND I /= 6 AND I /= 11 AND I /= 15 GENERATE | |
731 | apbo_ext(I) <= apb_none; |
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705 | apbo_ext(I) <= apb_none; | |
732 | END GENERATE apbo_ext_not_used; |
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706 | END GENERATE apbo_ext_not_used; | |
733 | END GENERATE all_apbo_ext; |
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707 | END GENERATE all_apbo_ext; |
@@ -36,7 +36,7 USE techmap.gencomp.ALL; | |||||
36 | ENTITY cic_lfr IS |
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36 | ENTITY cic_lfr IS | |
37 | GENERIC( |
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37 | GENERIC( | |
38 | tech : INTEGER := 0; |
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38 | tech : INTEGER := 0; | |
39 |
use_RAM_nCEL : INTEGER := |
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39 | use_RAM_nCEL : INTEGER := 1 -- 1 => RAM(tech) , 0 => RAM_CEL | |
40 | ); |
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40 | ); | |
41 | PORT ( |
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41 | PORT ( | |
42 | clk : IN STD_LOGIC; |
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42 | clk : IN STD_LOGIC; | |
@@ -382,4 +382,3 BEGIN | |||||
382 | END GENERATE all_channel_out_v; |
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382 | END GENERATE all_channel_out_v; | |
383 |
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383 | |||
384 | END beh; |
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384 | END beh; | |
385 |
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