HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib Commit - r463:832e74562224

1.1.34 : idem 1.1.33 avec reset soft pour LFR subsystem

pellion -

r463:832e74562224 (LFR-EM) WFP_MS-1-1-34 JC

parent child

Context file:

r463:832e74562224

Collapse all files

designs/LFR-em-WFP_MS/LFR-em.vhd +10 -3

               -----------------------------------------------------------------------------
               SIGNAL rstn : STD_LOGIC;
+              SIGNAL LFR_soft_rstn  : STD_LOGIC;
+              SIGNAL LFR_rstn       : STD_LOGIC;
               SIGNAL ADC_smpclk_s : STD_LOGIC;
             BEGIN  -- beh
                   apbi         => apbi_ext,
                   apbo         => apbo_ext(6),
                   coarse_time  => coarse_time,
-                  fine_time    => fine_time);
+                  fine_time    => fine_time,
+                  LFR_soft_rstn => LFR_soft_rstn
+                  );
             -----------------------------------------------------------------------
             ---  SpaceWire --------------------------------------------------------
             -------------------------------------------------------------------------------
             -- LFR ------------------------------------------------------------------------
             -------------------------------------------------------------------------------
+              LFR_rstn <= LFR_soft_rstn AND rstn;
               lpp_lfr_1 : lpp_lfr
                 GENERIC MAP (
                   Mem_use                => use_RAM,
                   pirq_ms                => 6,
                   pirq_wfp               => 14,
                   hindex                 => 2,
-                  top_lfr_version        => X"010121")  -- aa.bb.cc version
+                  top_lfr_version        => X"010122")  -- aa.bb.cc version
                                                         -- AA : BOARD NUMBER
                                                         --      0 => MINI_LFR
                                                         --      1 => EM
                 PORT MAP (
                   clk             => clk_25,
-                  rstn            => rstn,
+                  rstn            => LFR_rstn,
                   sample_B        => sample_s(2 DOWNTO 0),
                   sample_E        => sample_s(7 DOWNTO 3),
                   sample_val      => sample_val,

designs/MINI-LFR_WFP_MS/MINI_LFR_top.vhd +14 -7

               --
               SIGNAL errorn      : STD_LOGIC;
               -- UART AHB ---------------------------------------------------------------
-              SIGNAL ahbrxd      : STD_ULOGIC;      -- DSU rx data
+            --  SIGNAL ahbrxd      : STD_ULOGIC;      -- DSU rx data
-              SIGNAL ahbtxd      : STD_ULOGIC;      -- DSU tx data
+            --  SIGNAL ahbtxd      : STD_ULOGIC;      -- DSU tx data
               -- UART APB ---------------------------------------------------------------
-              SIGNAL urxd1 : STD_ULOGIC;            -- UART1 rx data
+            --  SIGNAL urxd1 : STD_ULOGIC;            -- UART1 rx data
-              SIGNAL utxd1 : STD_ULOGIC;            -- UART1 tx data
+            --  SIGNAL utxd1 : STD_ULOGIC;            -- UART1 tx data
                                                     --
               SIGNAL I00_s : STD_LOGIC;
                     dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
               END GENERATE spw_inputloop;
+              swni.rmapnodeaddr <= (others => '0');
               -- SPW core
               sw0 : grspwm GENERIC MAP(
                 tech         => apa3e,
                   fine_time       => fine_time,
                   data_shaping_BW => bias_fail_sw_sig);
+              observation_reg      <= (others => '0');
+              observation_vector_0 <= (others => '0');
+              observation_vector_1 <= (others => '0');
               all_sample: FOR I IN 7 DOWNTO 0 GENERATE
                 sample_s(I) <= sample(I)(11 DOWNTO 0) & '0' & '0' & '0' & '0';
               END GENERATE all_sample;
               top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2
                 GENERIC MAP(
                   ChannelCount    => 8,
                 GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8)
                 PORT MAP(rstn_25, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo);
+              gpioi.sig_en <= (others => '0');
+              gpioi.sig_in <= (others => '0');
+              gpioi.din    <= (others => '0');
               --pio_pad_0 : iopad
               --  GENERIC MAP (tech => CFG_PADTECH)
               --  PORT MAP (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0));
                 END GENERATE ahbo_m_ext_not_used;
               END GENERATE all_ahbo_m_ext;
-            END beh;
+            END beh;
  No newline at end of file

designs/MINI-LFR_WFP_MS/testbench.vhd +3 0

             USE lpp.lpp_lfr_apbreg_pkg.ALL;
             USE lpp.lpp_lfr_time_management_apbreg_pkg.ALL;
+            LIBRARY postlayout;
+            USE postlayout.ALL;
             ENTITY testbench IS
             END;

lib/lpp/general_purpose/MAC.vhd +12 -13

             --  SIGNAL clr_MAC_D_D      : STD_LOGIC;
             --  SIGNAL MAC_MUL_ADD_2C_D : STD_LOGIC_VECTOR(1 DOWNTO 0);
-              SIGNAL load_mult_result   : STD_LOGIC;
+            --  SIGNAL load_mult_result   : STD_LOGIC;
-              SIGNAL load_mult_result_D : STD_LOGIC;
+            --  SIGNAL load_mult_result_D : STD_LOGIC;
             BEGIN
                   ctrl        => MAC_MUL_ADD_s,
                   MULT        => mult,
                   ADD         => add,
-                  LOAD_ADDER  => load_mult_result,
+                  --LOAD_ADDER  => load_mult_result,
                   MACMUX_sel  => MACMUXsel,
                   MACMUX2_sel => MACMUX2sel
                   );
             --==============================================================
-              PROCESS (clk, reset)
+              --PROCESS (clk, reset)
-              BEGIN  -- PROCESS
+              --BEGIN  -- PROCESS
-                IF reset = '0' THEN                 -- asynchronous reset (active low)
+              --  IF reset = '0' THEN                 -- asynchronous reset (active low)
-                  load_mult_result_D <= '0';
+              --    load_mult_result_D <= '0';
-                ELSIF clk'EVENT AND clk = '1' THEN  -- rising clock edge
+              --  ELSIF clk'EVENT AND clk = '1' THEN  -- rising clock edge
-                  load_mult_result_D <= load_mult_result;
+              --    load_mult_result_D <= load_mult_result;
-                END IF;
+              --  END IF;
-              END PROCESS;
+              --END PROCESS;
             --==============================================================
             --======================A D D E R ==============================
                   clk   => clk,
                   reset => reset,
                   clr   => clr_MAC_D,
-                  load  => load_mult_result_D,
+                  load  => MACMUX2sel_D,            --load_mult_result_D,
                   add   => add_D,
                   OP1   => ADDERinA,
                   OP2   => ADDERinB,
                     RES     => OP2_2C
                     );
                 clr_MACREG_comp : MAC_REG
                   GENERIC MAP(size => 1)
                   PORT MAP(

lib/lpp/general_purpose/MAC_CONTROLER.vhd +2 -2

                 ctrl        :   in  std_logic_vector(1 downto 0);
                 MULT        :   out std_logic;
                 ADD         :   out std_logic;
-                LOAD_ADDER  :   out std_logic;
+            --    LOAD_ADDER  :   out std_logic;
                 MACMUX_sel  :   out std_logic;
                 MACMUX2_sel :   out std_logic
             MULT        <=  '0' when (ctrl = "00" or ctrl = "11") else '1';
             ADD         <=  '0' when (ctrl = "00" or ctrl = "10") else '1';
-            LOAD_ADDER  <=  '1' when (ctrl = "10") else '0';  -- PATCH JC : mem mult result
+            --LOAD_ADDER  <=  '1' when (               ctrl = "10") else '0';  -- PATCH JC : mem mult result
                                                                              -- to permit to compute a
                                                                              -- MULT follow by a MAC
             --MACMUX_sel  <=  '0' when (ctrl = "00" or ctrl = "01") else '1';

lib/lpp/general_purpose/general_purpose.vhd +1 -1

                   ctrl        : IN  STD_LOGIC_VECTOR(1 DOWNTO 0);
                   MULT        : OUT STD_LOGIC;
                   ADD         : OUT STD_LOGIC;
-                  LOAD_ADDER  : out std_logic;
+            --      LOAD_ADDER  : out std_logic;
                   MACMUX_sel  : OUT STD_LOGIC;
                   MACMUX2_sel : OUT STD_LOGIC
                   );

lib/lpp/lpp_ad_Conv/ADS7886_drvr_v2.vhd +4 -4

               SIGNAL cnv_sync_r         : STD_LOGIC;
               SIGNAL cnv_done           : STD_LOGIC;
               SIGNAL sample_bit_counter : INTEGER;
-              SIGNAL shift_reg          : Samples(ChannelCount-1 DOWNTO 0);
+              SIGNAL shift_reg          : Samples_15(ChannelCount-1 DOWNTO 0);
             BEGIN
               BEGIN  -- PROCESS
                 IF rstn = '0' THEN
                   FOR k IN 0 TO ChannelCount-1 LOOP
-                    shift_reg(k)(15 downto 0)	<= (OTHERS => '0');
+                    shift_reg(k)(14 downto 0)	<= (OTHERS => '0');
             	sample(k)(15 downto 0) 		<= (OTHERS => '0');
                   END LOOP;
                   sample_bit_counter <= 0;
                   IF (sample_bit_counter MOD 2) = 1 THEN	-- get data on each channel
                     FOR k IN 0 TO ChannelCount-1 LOOP
                       shift_reg(k)(0)           <= sdo(k);
-                      shift_reg(k)(15 DOWNTO 1) <= shift_reg(k)(14 DOWNTO 0);
+                      shift_reg(k)(14 DOWNTO 1) <= shift_reg(k)(13 DOWNTO 0);
                     END LOOP;
                     SCK <= '0';
                   ELSE
                 END IF;
               END PROCESS;
-            END ar_ADS7886_drvr_v2;
  No newline at end of file
+            END ar_ADS7886_drvr_v2;

lib/lpp/lpp_ad_Conv/lpp_ad_Conv.vhd +1 0

               --TYPE AD7688_in IS ARRAY(NATURAL RANGE <>) OF AD7688_in_element;
               TYPE Samples    IS ARRAY(NATURAL RANGE <>) OF STD_LOGIC_VECTOR(15 DOWNTO 0);
+              TYPE Samples_15 IS ARRAY(NATURAL RANGE <>) OF STD_LOGIC_VECTOR(14 DOWNTO 0);
               SUBTYPE Samples24 IS STD_LOGIC_VECTOR(23 DOWNTO 0);

lib/lpp/lpp_top_lfr/lpp_lfr.vhd +44 -44

               -- SM
               SIGNAL ready_matrix_f0          : STD_LOGIC;
-              SIGNAL ready_matrix_f0_1        : STD_LOGIC;
+            --  SIGNAL ready_matrix_f0_1        : STD_LOGIC;
               SIGNAL ready_matrix_f1          : STD_LOGIC;
               SIGNAL ready_matrix_f2          : STD_LOGIC;
               SIGNAL status_ready_matrix_f0   : STD_LOGIC;
-              SIGNAL status_ready_matrix_f0_1 : STD_LOGIC;
+            --  SIGNAL status_ready_matrix_f0_1 : STD_LOGIC;
               SIGNAL status_ready_matrix_f1   : STD_LOGIC;
               SIGNAL status_ready_matrix_f2   : STD_LOGIC;
               SIGNAL addr_matrix_f0           : STD_LOGIC_VECTOR(31 DOWNTO 0);
               -----------------------------------------------------------------------------
               --
               -----------------------------------------------------------------------------
-              SIGNAL data_f0_addr_out_s             : STD_LOGIC_VECTOR(31 DOWNTO 0);
+            --  SIGNAL data_f0_addr_out_s             : STD_LOGIC_VECTOR(31 DOWNTO 0);
-              SIGNAL data_f0_data_out_valid_s       : STD_LOGIC;
+            --  SIGNAL data_f0_data_out_valid_s       : STD_LOGIC;
-              SIGNAL data_f0_data_out_valid_burst_s : STD_LOGIC;
+            --  SIGNAL data_f0_data_out_valid_burst_s : STD_LOGIC;
               --f1
-              SIGNAL data_f1_addr_out_s             : STD_LOGIC_VECTOR(31 DOWNTO 0);
+            --  SIGNAL data_f1_addr_out_s             : STD_LOGIC_VECTOR(31 DOWNTO 0);
-              SIGNAL data_f1_data_out_valid_s       : STD_LOGIC;
+            --  SIGNAL data_f1_data_out_valid_s       : STD_LOGIC;
-              SIGNAL data_f1_data_out_valid_burst_s : STD_LOGIC;
+            --  SIGNAL data_f1_data_out_valid_burst_s : STD_LOGIC;
               --f2
-              SIGNAL data_f2_addr_out_s             : STD_LOGIC_VECTOR(31 DOWNTO 0);
+            --  SIGNAL data_f2_addr_out_s             : STD_LOGIC_VECTOR(31 DOWNTO 0);
-              SIGNAL data_f2_data_out_valid_s       : STD_LOGIC;
+            --  SIGNAL data_f2_data_out_valid_s       : STD_LOGIC;
-              SIGNAL data_f2_data_out_valid_burst_s : STD_LOGIC;
+            --  SIGNAL data_f2_data_out_valid_burst_s : STD_LOGIC;
               --f3
-              SIGNAL data_f3_addr_out_s             : STD_LOGIC_VECTOR(31 DOWNTO 0);
+            --  SIGNAL data_f3_addr_out_s             : STD_LOGIC_VECTOR(31 DOWNTO 0);
-              SIGNAL data_f3_data_out_valid_s       : STD_LOGIC;
+            --  SIGNAL data_f3_data_out_valid_s       : STD_LOGIC;
-              SIGNAL data_f3_data_out_valid_burst_s : STD_LOGIC;
+            --  SIGNAL data_f3_data_out_valid_burst_s : STD_LOGIC;
               SIGNAL wfp_status_buffer_ready : STD_LOGIC_VECTOR(3 DOWNTO 0);
-              SIGNAL wfp_addr_buffer         : STD_LOGIC_VECTOR(32*4 DOWNTO 0);
+              SIGNAL wfp_addr_buffer         : STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
               SIGNAL wfp_length_buffer       : STD_LOGIC_VECTOR(25 DOWNTO 0);
               SIGNAL wfp_ready_buffer        : STD_LOGIC_VECTOR(3 DOWNTO 0);
               SIGNAL wfp_buffer_time         : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
               -----------------------------------------------------------------------------
               -- DMA RR
               -----------------------------------------------------------------------------
-              SIGNAL dma_sel_valid   : STD_LOGIC;
+            --  SIGNAL dma_sel_valid   : STD_LOGIC;
-              SIGNAL dma_rr_valid    : STD_LOGIC_VECTOR(3 DOWNTO 0);
+            --  SIGNAL dma_rr_valid    : STD_LOGIC_VECTOR(3 DOWNTO 0);
-              SIGNAL dma_rr_grant_s  : STD_LOGIC_VECTOR(3 DOWNTO 0);
+            --  SIGNAL dma_rr_grant_s  : STD_LOGIC_VECTOR(3 DOWNTO 0);
-              SIGNAL dma_rr_grant_ms : STD_LOGIC_VECTOR(3 DOWNTO 0);
+            --  SIGNAL dma_rr_grant_ms : STD_LOGIC_VECTOR(3 DOWNTO 0);
-              SIGNAL dma_rr_valid_ms : STD_LOGIC_VECTOR(3 DOWNTO 0);
+            --  SIGNAL dma_rr_valid_ms : STD_LOGIC_VECTOR(3 DOWNTO 0);
-              SIGNAL dma_rr_grant : STD_LOGIC_VECTOR(4 DOWNTO 0);
+            --  SIGNAL dma_rr_grant : STD_LOGIC_VECTOR(4 DOWNTO 0);
-              SIGNAL dma_sel      : STD_LOGIC_VECTOR(4 DOWNTO 0);
+            --  SIGNAL dma_sel      : STD_LOGIC_VECTOR(4 DOWNTO 0);
               -----------------------------------------------------------------------------
               -- DMA_REG
               -----------------------------------------------------------------------------
-              SIGNAL ongoing_reg         : STD_LOGIC;
+            --  SIGNAL ongoing_reg         : STD_LOGIC;
-              SIGNAL dma_sel_reg         : STD_LOGIC_VECTOR(3 DOWNTO 0);
+            --  SIGNAL dma_sel_reg         : STD_LOGIC_VECTOR(3 DOWNTO 0);
-              SIGNAL dma_send_reg        : STD_LOGIC;
+            --  SIGNAL dma_send_reg        : STD_LOGIC;
-              SIGNAL dma_valid_burst_reg : STD_LOGIC;  -- (1 => BURST , 0 => SINGLE)
+            --  SIGNAL dma_valid_burst_reg : STD_LOGIC;  -- (1 => BURST , 0 => SINGLE)
-              SIGNAL dma_address_reg     : STD_LOGIC_VECTOR(31 DOWNTO 0);
+            --  SIGNAL dma_address_reg     : STD_LOGIC_VECTOR(31 DOWNTO 0);
-              SIGNAL dma_data_reg        : STD_LOGIC_VECTOR(31 DOWNTO 0);
+            --  SIGNAL dma_data_reg        : STD_LOGIC_VECTOR(31 DOWNTO 0);
               -----------------------------------------------------------------------------
               -- DMA
               -----------------------------------------------------------------------------
-              SIGNAL dma_send        : STD_LOGIC;
+            --  SIGNAL dma_send        : STD_LOGIC;
-              SIGNAL dma_valid_burst : STD_LOGIC;   -- (1 => BURST , 0 => SINGLE)
+            --  SIGNAL dma_valid_burst : STD_LOGIC;   -- (1 => BURST , 0 => SINGLE)
-              SIGNAL dma_done        : STD_LOGIC;
+            --  SIGNAL dma_done        : STD_LOGIC;
-              SIGNAL dma_ren         : STD_LOGIC;
+            --  SIGNAL dma_ren         : STD_LOGIC;
-              SIGNAL dma_address     : STD_LOGIC_VECTOR(31 DOWNTO 0);
+            --  SIGNAL dma_address     : STD_LOGIC_VECTOR(31 DOWNTO 0);
-              SIGNAL dma_data        : STD_LOGIC_VECTOR(31 DOWNTO 0);
+            --  SIGNAL dma_data        : STD_LOGIC_VECTOR(31 DOWNTO 0);
-              SIGNAL dma_data_2      : STD_LOGIC_VECTOR(31 DOWNTO 0);
+            --  SIGNAL dma_data_2      : STD_LOGIC_VECTOR(31 DOWNTO 0);
               -----------------------------------------------------------------------------
               -- MS
               -----------------------------------------------------------------------------
-              SIGNAL data_ms_addr        : STD_LOGIC_VECTOR(31 DOWNTO 0);
+            --  SIGNAL data_ms_addr        : STD_LOGIC_VECTOR(31 DOWNTO 0);
-              SIGNAL data_ms_data        : STD_LOGIC_VECTOR(31 DOWNTO 0);
+            --  SIGNAL data_ms_data        : STD_LOGIC_VECTOR(31 DOWNTO 0);
-              SIGNAL data_ms_valid       : STD_LOGIC;
+            --  SIGNAL data_ms_valid       : STD_LOGIC;
-              SIGNAL data_ms_valid_burst : STD_LOGIC;
+            --  SIGNAL data_ms_valid_burst : STD_LOGIC;
-              SIGNAL data_ms_ren         : STD_LOGIC;
+            --  SIGNAL data_ms_ren         : STD_LOGIC;
-              SIGNAL data_ms_done        : STD_LOGIC;
+            --  SIGNAL data_ms_done        : STD_LOGIC;
-              SIGNAL dma_ms_ongoing      : STD_LOGIC;
+            --  SIGNAL dma_ms_ongoing      : STD_LOGIC;
             --  SIGNAL run_ms              : STD_LOGIC;
-              SIGNAL ms_softandhard_rstn : STD_LOGIC;
+            --  SIGNAL ms_softandhard_rstn : STD_LOGIC;
               SIGNAL matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
             --  SIGNAL matrix_time_f0_1    : STD_LOGIC_VECTOR(47 DOWNTO 0);
               SIGNAL error_input_fifo_write : STD_LOGIC_VECTOR(2 DOWNTO 0);
             --  SIGNAL debug_ms : STD_LOGIC_VECTOR(31 DOWNTO 0);
-              SIGNAL debug_signal : STD_LOGIC_VECTOR(31 DOWNTO 0);
+            --  SIGNAL debug_signal : STD_LOGIC_VECTOR(31 DOWNTO 0);
               -----------------------------------------------------------------------------
               SIGNAL dma_fifo_burst_valid : STD_LOGIC_VECTOR(4 DOWNTO 0);

lib/lpp/lpp_top_lfr/lpp_lfr_apbreg.vhd +14 -14

                 start_date   : OUT STD_LOGIC_VECTOR(30 DOWNTO 0);
                 wfp_status_buffer_ready : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
-                wfp_addr_buffer         : OUT STD_LOGIC_VECTOR(32*4 DOWNTO 0);
+                wfp_addr_buffer         : OUT STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
                 wfp_length_buffer       : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
                 wfp_ready_buffer        : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
                 wfp_buffer_time         : IN STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
               --
               -----------------------------------------------------------------------------
               SIGNAL reg0_ready_matrix_f0 : STD_LOGIC;
-              SIGNAL reg0_addr_matrix_f0  : STD_LOGIC_VECTOR(31 DOWNTO 0);
+            --  SIGNAL reg0_addr_matrix_f0  : STD_LOGIC_VECTOR(31 DOWNTO 0);
-              SIGNAL reg0_matrix_time_f0  : STD_LOGIC_VECTOR(47 DOWNTO 0);
+            --  SIGNAL reg0_matrix_time_f0  : STD_LOGIC_VECTOR(47 DOWNTO 0);
               SIGNAL reg1_ready_matrix_f0 : STD_LOGIC;
-              SIGNAL reg1_addr_matrix_f0  : STD_LOGIC_VECTOR(31 DOWNTO 0);
+            --  SIGNAL reg1_addr_matrix_f0  : STD_LOGIC_VECTOR(31 DOWNTO 0);
-              SIGNAL reg1_matrix_time_f0  : STD_LOGIC_VECTOR(47 DOWNTO 0);
+            --  SIGNAL reg1_matrix_time_f0  : STD_LOGIC_VECTOR(47 DOWNTO 0);
               SIGNAL reg0_ready_matrix_f1 : STD_LOGIC;
-              SIGNAL reg0_addr_matrix_f1  : STD_LOGIC_VECTOR(31 DOWNTO 0);
+            --  SIGNAL reg0_addr_matrix_f1  : STD_LOGIC_VECTOR(31 DOWNTO 0);
-              SIGNAL reg0_matrix_time_f1  : STD_LOGIC_VECTOR(47 DOWNTO 0);
+            --  SIGNAL reg0_matrix_time_f1  : STD_LOGIC_VECTOR(47 DOWNTO 0);
               SIGNAL reg1_ready_matrix_f1 : STD_LOGIC;
-              SIGNAL reg1_addr_matrix_f1  : STD_LOGIC_VECTOR(31 DOWNTO 0);
+            --  SIGNAL reg1_addr_matrix_f1  : STD_LOGIC_VECTOR(31 DOWNTO 0);
-              SIGNAL reg1_matrix_time_f1  : STD_LOGIC_VECTOR(47 DOWNTO 0);
+            --  SIGNAL reg1_matrix_time_f1  : STD_LOGIC_VECTOR(47 DOWNTO 0);
               SIGNAL reg0_ready_matrix_f2 : STD_LOGIC;
-              SIGNAL reg0_addr_matrix_f2  : STD_LOGIC_VECTOR(31 DOWNTO 0);
+            --  SIGNAL reg0_addr_matrix_f2  : STD_LOGIC_VECTOR(31 DOWNTO 0);
-              SIGNAL reg0_matrix_time_f2  : STD_LOGIC_VECTOR(47 DOWNTO 0);
+            --  SIGNAL reg0_matrix_time_f2  : STD_LOGIC_VECTOR(47 DOWNTO 0);
               SIGNAL reg1_ready_matrix_f2 : STD_LOGIC;
-              SIGNAL reg1_addr_matrix_f2  : STD_LOGIC_VECTOR(31 DOWNTO 0);
+            --  SIGNAL reg1_addr_matrix_f2  : STD_LOGIC_VECTOR(31 DOWNTO 0);
-              SIGNAL reg1_matrix_time_f2  : STD_LOGIC_VECTOR(47 DOWNTO 0);
+            --  SIGNAL reg1_matrix_time_f2  : STD_LOGIC_VECTOR(47 DOWNTO 0);
               SIGNAL apbo_irq_ms : STD_LOGIC;
               SIGNAL apbo_irq_wfp : STD_LOGIC;
               -----------------------------------------------------------------------------
             END beh;
-            -------------------------------------------------------------------------------
+            -------------------------------------------------------------------------------
  No newline at end of file

lib/lpp/lpp_top_lfr/lpp_lfr_ms.vhd +51 -18

               -----------------------------------------------------------------------------
               TYPE   fsm_select_channel IS (IDLE, SWITCH_F0_A, SWITCH_F0_B, SWITCH_F1, SWITCH_F2);
               SIGNAL state_fsm_select_channel     : fsm_select_channel;
-              SIGNAL pre_state_fsm_select_channel : fsm_select_channel;
+            --  SIGNAL pre_state_fsm_select_channel : fsm_select_channel;
+              SIGNAL select_channel     : STD_LOGIC_VECTOR(1 DOWNTO 0);
+              SIGNAL select_channel_reg : STD_LOGIC_VECTOR(1 DOWNTO 0);
               SIGNAL sample_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
               SIGNAL sample_ren   : STD_LOGIC_VECTOR(4 DOWNTO 0);
               -----------------------------------------------------------------------------
               TYPE   fsm_load_FFT IS (IDLE, FIFO_1, FIFO_2, FIFO_3, FIFO_4, FIFO_5);
               SIGNAL state_fsm_load_FFT      : fsm_load_FFT;
-              SIGNAL next_state_fsm_load_FFT : fsm_load_FFT;
+            --  SIGNAL next_state_fsm_load_FFT : fsm_load_FFT;
+              SIGNAL select_fifo     : STD_LOGIC_VECTOR(2 DOWNTO 0);
+              SIGNAL select_fifo_reg : STD_LOGIC_VECTOR(2 DOWNTO 0);
               SIGNAL sample_ren_s   : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL sample_load    : STD_LOGIC;
               SIGNAL FSM_DMA_fifo_empty  : STD_LOGIC;
               SIGNAL FSM_DMA_fifo_empty_threshold  : STD_LOGIC;
               SIGNAL FSM_DMA_fifo_data   : STD_LOGIC_VECTOR(31 DOWNTO 0);
-              SIGNAL FSM_DMA_fifo_status : STD_LOGIC_VECTOR(53 DOWNTO 0);
+              SIGNAL FSM_DMA_fifo_status : STD_LOGIC_VECTOR(53 DOWNTO 4);
               -----------------------------------------------------------------------------
               SIGNAL MEM_OUT_SM_Write    : STD_LOGIC_VECTOR(1 DOWNTO 0);
               SIGNAL MEM_OUT_SM_Read     : STD_LOGIC_VECTOR(1 DOWNTO 0);
               SIGNAL status_MS_input  : STD_LOGIC_VECTOR(49 DOWNTO 0);
               SIGNAL status_component : STD_LOGIC_VECTOR(53 DOWNTO 0);
-              SIGNAL status_component_fifo_0     : STD_LOGIC_VECTOR(53 DOWNTO 0);
+              SIGNAL status_component_fifo_0     : STD_LOGIC_VECTOR(53 DOWNTO 4);
-              SIGNAL status_component_fifo_1     : STD_LOGIC_VECTOR(53 DOWNTO 0);
+              SIGNAL status_component_fifo_1     : STD_LOGIC_VECTOR(53 DOWNTO 4);
               SIGNAL status_component_fifo_0_end : STD_LOGIC;
               SIGNAL status_component_fifo_1_end : STD_LOGIC;
               -----------------------------------------------------------------------------
               BEGIN
                 IF rstn = '0' THEN
                   state_fsm_select_channel <= IDLE;
+                  select_channel <= (OTHERS => '0');
                 ELSIF clk'EVENT AND clk = '1' THEN
                   CASE state_fsm_select_channel IS
                     WHEN IDLE =>
                       IF sample_f1_full = "11111" THEN
                         state_fsm_select_channel <= SWITCH_F1;
+                        select_channel <= "10";
                       ELSIF sample_f1_almost_full = "00000" THEN
                         IF sample_f0_A_full = "11111" THEN
                           state_fsm_select_channel <= SWITCH_F0_A;
+                          select_channel <= "00";
                         ELSIF sample_f0_B_full = "11111" THEN
                           state_fsm_select_channel <= SWITCH_F0_B;
+                          select_channel <= "01";
                         ELSIF sample_f2_full = "11111" THEN
                           state_fsm_select_channel <= SWITCH_F2;
+                          select_channel <= "11";
                         END IF;
                       END IF;
                     WHEN SWITCH_F0_A =>
                       IF sample_f0_A_empty = "11111" THEN
                         state_fsm_select_channel <= IDLE;
+                        select_channel <= (OTHERS => '0');
                       END IF;
                     WHEN SWITCH_F0_B =>
                       IF sample_f0_B_empty = "11111" THEN
                         state_fsm_select_channel <= IDLE;
+                        select_channel <= (OTHERS => '0');
                       END IF;
                     WHEN SWITCH_F1 =>
                       IF sample_f1_empty = "11111" THEN
                         state_fsm_select_channel <= IDLE;
+                        select_channel <= (OTHERS => '0');
                       END IF;
                     WHEN SWITCH_F2 =>
                       IF sample_f2_empty = "11111" THEN
                         state_fsm_select_channel <= IDLE;
+                        select_channel <= (OTHERS => '0');
                       END IF;
                     WHEN OTHERS => NULL;
                   END CASE;
               PROCESS (clk, rstn)
               BEGIN
                 IF rstn = '0' THEN
-                  pre_state_fsm_select_channel <= IDLE;
+                  select_channel_reg <= (OTHERS => '0');
+                  --pre_state_fsm_select_channel <= IDLE;
                 ELSIF clk'EVENT AND clk = '1' THEN
-                  pre_state_fsm_select_channel <= state_fsm_select_channel;
+                  select_channel_reg <= select_channel;
+                  --pre_state_fsm_select_channel <= state_fsm_select_channel;
                 END IF;
               END PROCESS;
                              sample_f2_full   WHEN state_fsm_select_channel = SWITCH_F2   ELSE
                              (OTHERS => '0');
-              sample_rdata <= sample_f0_A_rdata WHEN pre_state_fsm_select_channel = SWITCH_F0_A ELSE
+              --sample_rdata <= sample_f0_A_rdata WHEN pre_state_fsm_select_channel = SWITCH_F0_A ELSE
-                              sample_f0_B_rdata WHEN pre_state_fsm_select_channel = SWITCH_F0_B ELSE
+              --                sample_f0_B_rdata WHEN pre_state_fsm_select_channel = SWITCH_F0_B ELSE
-                              sample_f1_rdata   WHEN pre_state_fsm_select_channel = SWITCH_F1   ELSE
+              --                sample_f1_rdata   WHEN pre_state_fsm_select_channel = SWITCH_F1   ELSE
+              --                sample_f2_rdata;  -- WHEN state_fsm_select_channel = SWITCH_F2   ELSE
+              sample_rdata <= sample_f0_A_rdata WHEN select_channel_reg = "00" ELSE
+                              sample_f0_B_rdata WHEN select_channel_reg = "01" ELSE
+                              sample_f1_rdata   WHEN select_channel_reg = "10"   ELSE
                               sample_f2_rdata;  -- WHEN state_fsm_select_channel = SWITCH_F2   ELSE
                   sample_ren_s       <= (OTHERS => '1');
                   state_fsm_load_FFT <= IDLE;
                   status_MS_input    <= (OTHERS => '0');
+                  select_fifo        <= "000";
                   --next_state_fsm_load_FFT <= IDLE;
                   --sample_valid              <= '0';
                 ELSIF clk'EVENT AND clk = '1' THEN
                       IF sample_full = "11111" AND sample_load = '1' THEN
                         state_fsm_load_FFT <= FIFO_1;
                         status_MS_input    <= status_channel;
+                        select_fifo <= "000";
                       END IF;
                     WHEN FIFO_1 =>
                       IF sample_empty(0) = '1' THEN
                         sample_ren_s       <= (OTHERS => '1');
                         state_fsm_load_FFT <= FIFO_2;
+                        select_fifo <= "001";
                       END IF;
                     WHEN FIFO_2 =>
                       IF sample_empty(1) = '1' THEN
                         sample_ren_s       <= (OTHERS => '1');
                         state_fsm_load_FFT <= FIFO_3;
+                        select_fifo <= "010";
                       END IF;
                     WHEN FIFO_3 =>
                       IF sample_empty(2) = '1' THEN
                         sample_ren_s       <= (OTHERS => '1');
                         state_fsm_load_FFT <= FIFO_4;
+                        select_fifo <= "011";
                       END IF;
                     WHEN FIFO_4 =>
                       IF sample_empty(3) = '1' THEN
                         sample_ren_s       <= (OTHERS => '1');
                         state_fsm_load_FFT <= FIFO_5;
+                        select_fifo <= "100";
                       END IF;
                     WHEN FIFO_5 =>
                       IF sample_empty(4) = '1' THEN
                         sample_ren_s       <= (OTHERS => '1');
                         state_fsm_load_FFT <= IDLE;
+                        select_fifo <= "000";
                       END IF;
                     WHEN OTHERS => NULL;
                   END CASE;
               BEGIN
                 IF rstn = '0' THEN
                   sample_valid_r          <= '0';
-                  next_state_fsm_load_FFT <= IDLE;
+                  select_fifo_reg <= (OTHERS => '0');
+                  --next_state_fsm_load_FFT <= IDLE;
                 ELSIF clk'EVENT AND clk = '1' THEN
-                  next_state_fsm_load_FFT <= state_fsm_load_FFT;
+                  select_fifo_reg <= select_fifo;
+                  --next_state_fsm_load_FFT <= state_fsm_load_FFT;
                   IF sample_ren_s = "11111" THEN
                     sample_valid_r <= '0';
                   ELSE
               sample_valid <= '0' WHEN fft_ongoing_counter = '1' ELSE sample_valid_r AND sample_load;
-              sample_data <= sample_rdata(16*1-1 DOWNTO 16*0) WHEN next_state_fsm_load_FFT = FIFO_1 ELSE
+              --sample_data <= sample_rdata(16*1-1 DOWNTO 16*0) WHEN next_state_fsm_load_FFT = FIFO_1 ELSE
-                             sample_rdata(16*2-1 DOWNTO 16*1) WHEN next_state_fsm_load_FFT = FIFO_2 ELSE
+              --               sample_rdata(16*2-1 DOWNTO 16*1) WHEN next_state_fsm_load_FFT = FIFO_2 ELSE
-                             sample_rdata(16*3-1 DOWNTO 16*2) WHEN next_state_fsm_load_FFT = FIFO_3 ELSE
+              --               sample_rdata(16*3-1 DOWNTO 16*2) WHEN next_state_fsm_load_FFT = FIFO_3 ELSE
-                             sample_rdata(16*4-1 DOWNTO 16*3) WHEN next_state_fsm_load_FFT = FIFO_4 ELSE
+              --               sample_rdata(16*4-1 DOWNTO 16*3) WHEN next_state_fsm_load_FFT = FIFO_4 ELSE
+              --               sample_rdata(16*5-1 DOWNTO 16*4);  --WHEN next_state_fsm_load_FFT = FIFO_5 ELSE
+              sample_data <= sample_rdata(16*1-1 DOWNTO 16*0) WHEN select_fifo_reg = "000" ELSE
+                             sample_rdata(16*2-1 DOWNTO 16*1) WHEN select_fifo_reg = "001" ELSE
+                             sample_rdata(16*3-1 DOWNTO 16*2) WHEN select_fifo_reg = "010" ELSE
+                             sample_rdata(16*4-1 DOWNTO 16*3) WHEN select_fifo_reg = "011"  ELSE
                              sample_rdata(16*5-1 DOWNTO 16*4);  --WHEN next_state_fsm_load_FFT = FIFO_5 ELSE
               -----------------------------------------------------------------------------
                   status_component_fifo_1_end <= '0';
                   IF SM_correlation_begin = '1' THEN
                     IF current_matrix_write = '0' THEN
-                      status_component_fifo_0 <= status_component;
+                      status_component_fifo_0 <= status_component(53 DOWNTO 4);
                     ELSE
-                      status_component_fifo_1 <= status_component;
+                      status_component_fifo_1 <= status_component(53 DOWNTO 4);
                     END IF;
                   END IF;

lib/lpp/lpp_top_lfr/lpp_lfr_pkg.vhd +1 -1

                   run                     : OUT STD_LOGIC;
                   start_date              : OUT STD_LOGIC_VECTOR(30 DOWNTO 0);
                   wfp_status_buffer_ready : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
-                  wfp_addr_buffer         : OUT STD_LOGIC_VECTOR(32*4 DOWNTO 0);
+                  wfp_addr_buffer         : OUT STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
                   wfp_length_buffer       : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
                   wfp_ready_buffer        : IN  STD_LOGIC_VECTOR(3 DOWNTO 0);
                   wfp_buffer_time         : IN  STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);

lib/lpp/lpp_waveform/lpp_waveform.vhd +1 -1

                 -- REG DMA
                 status_buffer_ready : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
-                addr_buffer         : IN STD_LOGIC_VECTOR(32*4 DOWNTO 0);
+                addr_buffer         : IN STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
                 length_buffer       : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
                 ready_buffer        : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);

lib/lpp/lpp_waveform/lpp_waveform_fifo_arbiter.vhd +5 -6

               -- DATA MUX
               -----------------------------------------------------------------------------
               TYPE WORD_VECTOR IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR(31 DOWNTO 0);
-              SIGNAL data_0   : WORD_VECTOR(3 DOWNTO 0);
+              SIGNAL data_0   : WORD_VECTOR(2 DOWNTO 0);
-              SIGNAL data_1   : WORD_VECTOR(3 DOWNTO 0);
+              SIGNAL data_1   : WORD_VECTOR(2 DOWNTO 0);
-              SIGNAL data_2   : WORD_VECTOR(3 DOWNTO 0);
+              SIGNAL data_2   : WORD_VECTOR(2 DOWNTO 0);
-              SIGNAL data_3   : WORD_VECTOR(3 DOWNTO 0);
+              SIGNAL data_3   : WORD_VECTOR(2 DOWNTO 0);
-              SIGNAL data_sel : WORD_VECTOR(3 DOWNTO 0);
+              SIGNAL data_sel : WORD_VECTOR(2 DOWNTO 0);
               -----------------------------------------------------------------------------
               -- RR and SELECTION

lib/lpp/lpp_waveform/lpp_waveform_fifo_arbiter_reg.vhd 0 -1

	@@ -113,4 +113,3 END ARCHITECTURE;
	113			113
	114			114
	115			115
	116

lib/lpp/lpp_waveform/lpp_waveform_pkg.vhd +1 -1

                   nb_snapshot_param            : IN  STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
                   status_new_err               : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
                   status_buffer_ready : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
-                  addr_buffer         : IN STD_LOGIC_VECTOR(32*4 DOWNTO 0);
+                  addr_buffer         : IN STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
                   length_buffer       : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
                   ready_buffer        : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
                   buffer_time         : OUT STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);

General Comments 0

Write
Preview

You need to be logged in to leave comments. Login now

No TODOs yet

	Site-wide shortcuts
/	Use quick search box
g h	Goto home page
g g	Goto my private gists page
g G	Goto my public gists page
g 0-9	Goto bookmarked items from 0-9
n r	New repository page
n g	New gist page

	Repositories
g s	Goto summary page
g c	Goto changelog page
g f	Goto files page
g F	Goto files page with file search activated
g p	Goto pull requests page
g o	Goto repository settings
g O	Goto repository access permissions settings
t s	Toggle sidebar on some pages