diff --git a/designs/LFR-em-WFP_MS/LFR-em.vhd b/designs/LFR-em-WFP_MS/LFR-em.vhd
--- a/designs/LFR-em-WFP_MS/LFR-em.vhd
+++ b/designs/LFR-em-WFP_MS/LFR-em.vhd
@@ -138,7 +138,10 @@ ARCHITECTURE beh OF LFR_em IS
 
   -----------------------------------------------------------------------------
   SIGNAL rstn : STD_LOGIC;
-
+  
+  SIGNAL LFR_soft_rstn  : STD_LOGIC;
+  SIGNAL LFR_rstn       : STD_LOGIC;
+  
   SIGNAL ADC_smpclk_s : STD_LOGIC;
 
 BEGIN  -- beh
@@ -252,7 +255,9 @@ BEGIN  -- beh
       apbi         => apbi_ext,
       apbo         => apbo_ext(6),
       coarse_time  => coarse_time,
-      fine_time    => fine_time);
+      fine_time    => fine_time,
+      LFR_soft_rstn => LFR_soft_rstn
+      );
 
 -----------------------------------------------------------------------
 ---  SpaceWire --------------------------------------------------------
@@ -343,6 +348,8 @@ BEGIN  -- beh
 -------------------------------------------------------------------------------
 -- LFR ------------------------------------------------------------------------
 -------------------------------------------------------------------------------
+  LFR_rstn <= LFR_soft_rstn AND rstn;
+  
   lpp_lfr_1 : lpp_lfr
     GENERIC MAP (
       Mem_use                => use_RAM,
@@ -357,13 +364,13 @@ BEGIN  -- beh
       pirq_ms                => 6,
       pirq_wfp               => 14,
       hindex                 => 2,
-      top_lfr_version        => X"010121")  -- aa.bb.cc version
+      top_lfr_version        => X"010122")  -- aa.bb.cc version
                                             -- AA : BOARD NUMBER
                                             --      0 => MINI_LFR
                                             --      1 => EM
     PORT MAP (
       clk             => clk_25,
-      rstn            => rstn,
+      rstn            => LFR_rstn,
       sample_B        => sample_s(2 DOWNTO 0),
       sample_E        => sample_s(7 DOWNTO 3),
       sample_val      => sample_val,
diff --git a/designs/MINI-LFR_WFP_MS/MINI_LFR_top.vhd b/designs/MINI-LFR_WFP_MS/MINI_LFR_top.vhd
--- a/designs/MINI-LFR_WFP_MS/MINI_LFR_top.vhd
+++ b/designs/MINI-LFR_WFP_MS/MINI_LFR_top.vhd
@@ -122,12 +122,12 @@ ARCHITECTURE beh OF MINI_LFR_top IS
   --
   SIGNAL errorn      : STD_LOGIC;
   -- UART AHB ---------------------------------------------------------------
-  SIGNAL ahbrxd      : STD_ULOGIC;      -- DSU rx data  
-  SIGNAL ahbtxd      : STD_ULOGIC;      -- DSU tx data
+--  SIGNAL ahbrxd      : STD_ULOGIC;      -- DSU rx data  
+--  SIGNAL ahbtxd      : STD_ULOGIC;      -- DSU tx data
 
   -- UART APB ---------------------------------------------------------------
-  SIGNAL urxd1 : STD_ULOGIC;            -- UART1 rx data
-  SIGNAL utxd1 : STD_ULOGIC;            -- UART1 tx data
+--  SIGNAL urxd1 : STD_ULOGIC;            -- UART1 rx data
+--  SIGNAL utxd1 : STD_ULOGIC;            -- UART1 tx data
                                         --
   SIGNAL I00_s : STD_LOGIC;
 
@@ -439,6 +439,8 @@ BEGIN  -- beh
         dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
   END GENERATE spw_inputloop;
 
+  swni.rmapnodeaddr <= (others => '0');
+
   -- SPW core
   sw0 : grspwm GENERIC MAP(
     tech         => apa3e,
@@ -514,12 +516,14 @@ BEGIN  -- beh
       fine_time       => fine_time,
       data_shaping_BW => bias_fail_sw_sig);
 
+  observation_reg      <= (others => '0');
+  observation_vector_0 <= (others => '0');
+  observation_vector_1 <= (others => '0');
+
   all_sample: FOR I IN 7 DOWNTO 0 GENERATE
     sample_s(I) <= sample(I)(11 DOWNTO 0) & '0' & '0' & '0' & '0';
   END GENERATE all_sample;
 
-  
-
   top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2
     GENERIC MAP(
       ChannelCount    => 8,
@@ -556,6 +560,9 @@ BEGIN  -- beh
     GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8)
     PORT MAP(rstn_25, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo);
   
+  gpioi.sig_en <= (others => '0');
+  gpioi.sig_in <= (others => '0');
+  gpioi.din    <= (others => '0');
   --pio_pad_0 : iopad
   --  GENERIC MAP (tech => CFG_PADTECH)
   --  PORT MAP (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0));
@@ -688,4 +695,4 @@ BEGIN  -- beh
     END GENERATE ahbo_m_ext_not_used;
   END GENERATE all_ahbo_m_ext;
 
-END beh;
+END beh;
\ No newline at end of file
diff --git a/designs/MINI-LFR_WFP_MS/testbench.vhd b/designs/MINI-LFR_WFP_MS/testbench.vhd
--- a/designs/MINI-LFR_WFP_MS/testbench.vhd
+++ b/designs/MINI-LFR_WFP_MS/testbench.vhd
@@ -1,270 +1,273 @@
-LIBRARY ieee;
-USE ieee.std_logic_1164.ALL;
-USE ieee.numeric_std.ALL;
-use IEEE.std_logic_textio.all;
-LIBRARY STD;
-use std.textio.all;
-
-LIBRARY grlib;
-USE grlib.stdlib.ALL;
-LIBRARY gaisler;
-USE gaisler.libdcom.ALL;
-USE gaisler.sim.ALL;
-USE gaisler.jtagtst.ALL;
-LIBRARY techmap;
-USE techmap.gencomp.ALL;
-
-LIBRARY lpp;
-USE lpp.lpp_sim_pkg.ALL;
-USE lpp.lpp_lfr_apbreg_pkg.ALL;
-USE lpp.lpp_lfr_time_management_apbreg_pkg.ALL;
-
-ENTITY testbench IS
-END;
-
-ARCHITECTURE behav OF testbench IS
-
-  COMPONENT MINI_LFR_top
-    PORT (
-      clk_50       : IN    STD_LOGIC;
-      clk_49       : IN    STD_LOGIC;
-      reset        : IN    STD_LOGIC;
-      BP0          : IN    STD_LOGIC;
-      BP1          : IN    STD_LOGIC;
-      LED0         : OUT   STD_LOGIC;
-      LED1         : OUT   STD_LOGIC;
-      LED2         : OUT   STD_LOGIC;
-      TXD1         : IN    STD_LOGIC;
-      RXD1         : OUT   STD_LOGIC;
-      nCTS1        : OUT   STD_LOGIC;
-      nRTS1        : IN    STD_LOGIC;
-      TXD2         : IN    STD_LOGIC;
-      RXD2         : OUT   STD_LOGIC;
-      nCTS2        : OUT   STD_LOGIC;
-      nDTR2        : IN    STD_LOGIC;
-      nRTS2        : IN    STD_LOGIC;
-      nDCD2        : OUT   STD_LOGIC;
-      IO0          : INOUT STD_LOGIC;
-      IO1          : INOUT STD_LOGIC;
-      IO2          : INOUT STD_LOGIC;
-      IO3          : INOUT STD_LOGIC;
-      IO4          : INOUT STD_LOGIC;
-      IO5          : INOUT STD_LOGIC;
-      IO6          : INOUT STD_LOGIC;
-      IO7          : INOUT STD_LOGIC;
-      IO8          : INOUT STD_LOGIC;
-      IO9          : INOUT STD_LOGIC;
-      IO10         : INOUT STD_LOGIC;
-      IO11         : INOUT STD_LOGIC;
-      SPW_EN       : OUT   STD_LOGIC;
-      SPW_NOM_DIN  : IN    STD_LOGIC;
-      SPW_NOM_SIN  : IN    STD_LOGIC;
-      SPW_NOM_DOUT : OUT   STD_LOGIC;
-      SPW_NOM_SOUT : OUT   STD_LOGIC;
-      SPW_RED_DIN  : IN    STD_LOGIC;
-      SPW_RED_SIN  : IN    STD_LOGIC;
-      SPW_RED_DOUT : OUT   STD_LOGIC;
-      SPW_RED_SOUT : OUT   STD_LOGIC;
-      ADC_nCS      : OUT   STD_LOGIC;
-      ADC_CLK      : OUT   STD_LOGIC;
-      ADC_SDO      : IN    STD_LOGIC_VECTOR(7 DOWNTO 0);
-      SRAM_nWE     : OUT   STD_LOGIC;
-      SRAM_CE      : OUT   STD_LOGIC;
-      SRAM_nOE     : OUT   STD_LOGIC;
-      SRAM_nBE     : OUT   STD_LOGIC_VECTOR(3 DOWNTO 0);
-      SRAM_A       : OUT   STD_LOGIC_VECTOR(19 DOWNTO 0);
-      SRAM_DQ      : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0));
-  END COMPONENT;
-
-  -----------------------------------------------------------------------------
-  SIGNAL clk_50 : STD_LOGIC := '0';
-  SIGNAL clk_49 : STD_LOGIC := '0';
-  SIGNAL reset        : STD_LOGIC;
-  SIGNAL BP0          : STD_LOGIC;
-  SIGNAL BP1          : STD_LOGIC;
-  SIGNAL LED0         : STD_LOGIC;
-  SIGNAL LED1         : STD_LOGIC;
-  SIGNAL LED2         : STD_LOGIC;
-  SIGNAL TXD1         : STD_LOGIC;
-  SIGNAL RXD1         : STD_LOGIC;
-  SIGNAL nCTS1        : STD_LOGIC;
-  SIGNAL nRTS1        : STD_LOGIC;
-  SIGNAL TXD2         : STD_LOGIC;
-  SIGNAL RXD2         : STD_LOGIC;
-  SIGNAL nCTS2        : STD_LOGIC;
-  SIGNAL nDTR2        : STD_LOGIC;
-  SIGNAL nRTS2        : STD_LOGIC;
-  SIGNAL nDCD2        : STD_LOGIC;
-  SIGNAL IO0          : STD_LOGIC;
-  SIGNAL IO1          : STD_LOGIC;
-  SIGNAL IO2          : STD_LOGIC;
-  SIGNAL IO3          : STD_LOGIC;
-  SIGNAL IO4          : STD_LOGIC;
-  SIGNAL IO5          : STD_LOGIC;
-  SIGNAL IO6          : STD_LOGIC;
-  SIGNAL IO7          : STD_LOGIC;
-  SIGNAL IO8          : STD_LOGIC;
-  SIGNAL IO9          : STD_LOGIC;
-  SIGNAL IO10         : STD_LOGIC;
-  SIGNAL IO11         : STD_LOGIC;
-  SIGNAL SPW_EN       : STD_LOGIC;
-  SIGNAL SPW_NOM_DIN  : STD_LOGIC;
-  SIGNAL SPW_NOM_SIN  : STD_LOGIC;
-  SIGNAL SPW_NOM_DOUT : STD_LOGIC;
-  SIGNAL SPW_NOM_SOUT : STD_LOGIC;
-  SIGNAL SPW_RED_DIN  : STD_LOGIC;
-  SIGNAL SPW_RED_SIN  : STD_LOGIC;
-  SIGNAL SPW_RED_DOUT : STD_LOGIC;
-  SIGNAL SPW_RED_SOUT : STD_LOGIC;
-  SIGNAL ADC_nCS      : STD_LOGIC;
-  SIGNAL ADC_CLK      : STD_LOGIC;
-  SIGNAL ADC_SDO      : STD_LOGIC_VECTOR(7 DOWNTO 0);
-  SIGNAL SRAM_nWE     : STD_LOGIC;
-  SIGNAL SRAM_CE      : STD_LOGIC;
-  SIGNAL SRAM_nOE     : STD_LOGIC;
-  SIGNAL SRAM_nBE     : STD_LOGIC_VECTOR(3 DOWNTO 0);
-  SIGNAL SRAM_A       : STD_LOGIC_VECTOR(19 DOWNTO 0);
-  SIGNAL SRAM_DQ      : STD_LOGIC_VECTOR(31 DOWNTO 0);
-  -----------------------------------------------------------------------------
-
-  CONSTANT ADDR_BASE_LFR            : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"80000F";
-  CONSTANT ADDR_BASE_TIME_MANAGMENT : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"800006";
-  CONSTANT ADDR_BASE_GPIO           : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"80000B";
-
-
-  SIGNAL message_simu : STRING(1 TO 15) := "---------------";
-  
-BEGIN
-
-  -----------------------------------------------------------------------------
-  -- TB
-  -----------------------------------------------------------------------------
-  PROCESS
-    CONSTANT txp : TIME := 320 ns;
-  BEGIN  -- PROCESS
-    TXD1  <= '1';
-    reset <= '0';
-    WAIT FOR 500 ns;
-    reset <= '1';
-    WAIT FOR 10000 ns;
-    message_simu <= "0 - UART init  ";
-    UART_INIT(TXD1,txp);
-    
-    message_simu <= "1 - UART test  ";
-    UART_WRITE(TXD1,txp,ADDR_BASE_GPIO & "000010",X"0000FFFF");
-    UART_WRITE(TXD1,txp,ADDR_BASE_GPIO & "000001",X"00000A0A");
-    UART_WRITE(TXD1,txp,ADDR_BASE_GPIO & "000001",X"00000B0B");
-
-    -- UNSET the LFR reset
-    message_simu <= "2 - LFR UNRESET";
-    UART_WRITE(TXD1,txp,ADDR_BASE_TIME_MANAGMENT & ADDR_LFR_TM_CONTROL   , X"00000000");
-    UART_WRITE(TXD1,txp,ADDR_BASE_TIME_MANAGMENT & ADDR_LFR_TM_TIME_LOAD , X"00000000");
-    --
-    message_simu <= "3 - LFR CONFIG ";
-    UART_WRITE(TXD1,txp,ADDR_BASE_LFR & ADDR_LFR_SM_F0_0_ADDR , X"00000B0B");
-    
-    WAIT;
-  END PROCESS;
-
-  -----------------------------------------------------------------------------
-  -- CLOCK
-  -----------------------------------------------------------------------------
-  clk_50    <= NOT clk_50 AFTER 5 ns;
-  clk_49    <= NOT clk_49 AFTER 10172 ps;
-  
-  -----------------------------------------------------------------------------
-  -- DON'T CARE
-  -----------------------------------------------------------------------------
-  BP0   <= '0';
-  BP1   <= '0';
-  nRTS1 <= '0' ;
-
-  TXD2  <= '1';
-  nRTS2 <= '1';
-  nDTR2 <= '1';
-  
-  SPW_NOM_DIN  <= '1';
-  SPW_NOM_SIN  <= '1';
-  SPW_RED_DIN  <= '1';
-  SPW_RED_SIN  <= '1';
-  
-  ADC_SDO      <= x"AA";
-
-  SRAM_DQ      <= (OTHERS => 'Z');
-  IO0          <= 'Z';
-  IO1          <= 'Z';
-  IO2          <= 'Z';
-  IO3          <= 'Z';
-  IO4          <= 'Z';
-  IO5          <= 'Z';
-  IO6          <= 'Z';
-  IO7          <= 'Z';
-  IO8          <= 'Z';
-  IO9          <= 'Z';
-  IO10         <= 'Z';
-  IO11         <= 'Z';
-
-  -----------------------------------------------------------------------------
-  -- DUT
-  -----------------------------------------------------------------------------
-  MINI_LFR_top_1: MINI_LFR_top
-    PORT MAP (
-      clk_50       => clk_50,
-      clk_49       => clk_49,
-      reset        => reset,
-      
-      BP0          => BP0,
-      BP1          => BP1,
-
-      LED0         => LED0,
-      LED1         => LED1,
-      LED2         => LED2,
-
-      TXD1         => TXD1,
-      RXD1         => RXD1,
-      nCTS1        => nCTS1,
-      nRTS1        => nRTS1,
-      
-      TXD2         => TXD2,
-      RXD2         => RXD2,
-      nCTS2        => nCTS2,
-      nDTR2        => nDTR2,
-      nRTS2        => nRTS2,
-      nDCD2        => nDCD2,
-      
-      IO0          => IO0,
-      IO1          => IO1,
-      IO2          => IO2,
-      IO3          => IO3,
-      IO4          => IO4,
-      IO5          => IO5,
-      IO6          => IO6,
-      IO7          => IO7,
-      IO8          => IO8,
-      IO9          => IO9,
-      IO10         => IO10,
-      IO11         => IO11,
-      
-      SPW_EN       => SPW_EN,
-      SPW_NOM_DIN  => SPW_NOM_DIN,
-      SPW_NOM_SIN  => SPW_NOM_SIN,
-      SPW_NOM_DOUT => SPW_NOM_DOUT,
-      SPW_NOM_SOUT => SPW_NOM_SOUT,
-      SPW_RED_DIN  => SPW_RED_DIN,
-      SPW_RED_SIN  => SPW_RED_SIN,
-      SPW_RED_DOUT => SPW_RED_DOUT,
-      SPW_RED_SOUT => SPW_RED_SOUT,
-      
-      ADC_nCS      => ADC_nCS,
-      ADC_CLK      => ADC_CLK,
-      ADC_SDO      => ADC_SDO,
-      
-      SRAM_nWE     => SRAM_nWE,
-      SRAM_CE      => SRAM_CE,
-      SRAM_nOE     => SRAM_nOE,
-      SRAM_nBE     => SRAM_nBE,
-      SRAM_A       => SRAM_A,
-      SRAM_DQ      => SRAM_DQ);
-
-  
-END;
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+use IEEE.std_logic_textio.all;
+LIBRARY STD;
+use std.textio.all;
+
+LIBRARY grlib;
+USE grlib.stdlib.ALL;
+LIBRARY gaisler;
+USE gaisler.libdcom.ALL;
+USE gaisler.sim.ALL;
+USE gaisler.jtagtst.ALL;
+LIBRARY techmap;
+USE techmap.gencomp.ALL;
+
+LIBRARY lpp;
+USE lpp.lpp_sim_pkg.ALL;
+USE lpp.lpp_lfr_apbreg_pkg.ALL;
+USE lpp.lpp_lfr_time_management_apbreg_pkg.ALL;
+
+LIBRARY postlayout;
+USE postlayout.ALL;
+
+ENTITY testbench IS
+END;
+
+ARCHITECTURE behav OF testbench IS
+
+  COMPONENT MINI_LFR_top
+    PORT (
+      clk_50       : IN    STD_LOGIC;
+      clk_49       : IN    STD_LOGIC;
+      reset        : IN    STD_LOGIC;
+      BP0          : IN    STD_LOGIC;
+      BP1          : IN    STD_LOGIC;
+      LED0         : OUT   STD_LOGIC;
+      LED1         : OUT   STD_LOGIC;
+      LED2         : OUT   STD_LOGIC;
+      TXD1         : IN    STD_LOGIC;
+      RXD1         : OUT   STD_LOGIC;
+      nCTS1        : OUT   STD_LOGIC;
+      nRTS1        : IN    STD_LOGIC;
+      TXD2         : IN    STD_LOGIC;
+      RXD2         : OUT   STD_LOGIC;
+      nCTS2        : OUT   STD_LOGIC;
+      nDTR2        : IN    STD_LOGIC;
+      nRTS2        : IN    STD_LOGIC;
+      nDCD2        : OUT   STD_LOGIC;
+      IO0          : INOUT STD_LOGIC;
+      IO1          : INOUT STD_LOGIC;
+      IO2          : INOUT STD_LOGIC;
+      IO3          : INOUT STD_LOGIC;
+      IO4          : INOUT STD_LOGIC;
+      IO5          : INOUT STD_LOGIC;
+      IO6          : INOUT STD_LOGIC;
+      IO7          : INOUT STD_LOGIC;
+      IO8          : INOUT STD_LOGIC;
+      IO9          : INOUT STD_LOGIC;
+      IO10         : INOUT STD_LOGIC;
+      IO11         : INOUT STD_LOGIC;
+      SPW_EN       : OUT   STD_LOGIC;
+      SPW_NOM_DIN  : IN    STD_LOGIC;
+      SPW_NOM_SIN  : IN    STD_LOGIC;
+      SPW_NOM_DOUT : OUT   STD_LOGIC;
+      SPW_NOM_SOUT : OUT   STD_LOGIC;
+      SPW_RED_DIN  : IN    STD_LOGIC;
+      SPW_RED_SIN  : IN    STD_LOGIC;
+      SPW_RED_DOUT : OUT   STD_LOGIC;
+      SPW_RED_SOUT : OUT   STD_LOGIC;
+      ADC_nCS      : OUT   STD_LOGIC;
+      ADC_CLK      : OUT   STD_LOGIC;
+      ADC_SDO      : IN    STD_LOGIC_VECTOR(7 DOWNTO 0);
+      SRAM_nWE     : OUT   STD_LOGIC;
+      SRAM_CE      : OUT   STD_LOGIC;
+      SRAM_nOE     : OUT   STD_LOGIC;
+      SRAM_nBE     : OUT   STD_LOGIC_VECTOR(3 DOWNTO 0);
+      SRAM_A       : OUT   STD_LOGIC_VECTOR(19 DOWNTO 0);
+      SRAM_DQ      : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0));
+  END COMPONENT;
+
+  -----------------------------------------------------------------------------
+  SIGNAL clk_50 : STD_LOGIC := '0';
+  SIGNAL clk_49 : STD_LOGIC := '0';
+  SIGNAL reset        : STD_LOGIC;
+  SIGNAL BP0          : STD_LOGIC;
+  SIGNAL BP1          : STD_LOGIC;
+  SIGNAL LED0         : STD_LOGIC;
+  SIGNAL LED1         : STD_LOGIC;
+  SIGNAL LED2         : STD_LOGIC;
+  SIGNAL TXD1         : STD_LOGIC;
+  SIGNAL RXD1         : STD_LOGIC;
+  SIGNAL nCTS1        : STD_LOGIC;
+  SIGNAL nRTS1        : STD_LOGIC;
+  SIGNAL TXD2         : STD_LOGIC;
+  SIGNAL RXD2         : STD_LOGIC;
+  SIGNAL nCTS2        : STD_LOGIC;
+  SIGNAL nDTR2        : STD_LOGIC;
+  SIGNAL nRTS2        : STD_LOGIC;
+  SIGNAL nDCD2        : STD_LOGIC;
+  SIGNAL IO0          : STD_LOGIC;
+  SIGNAL IO1          : STD_LOGIC;
+  SIGNAL IO2          : STD_LOGIC;
+  SIGNAL IO3          : STD_LOGIC;
+  SIGNAL IO4          : STD_LOGIC;
+  SIGNAL IO5          : STD_LOGIC;
+  SIGNAL IO6          : STD_LOGIC;
+  SIGNAL IO7          : STD_LOGIC;
+  SIGNAL IO8          : STD_LOGIC;
+  SIGNAL IO9          : STD_LOGIC;
+  SIGNAL IO10         : STD_LOGIC;
+  SIGNAL IO11         : STD_LOGIC;
+  SIGNAL SPW_EN       : STD_LOGIC;
+  SIGNAL SPW_NOM_DIN  : STD_LOGIC;
+  SIGNAL SPW_NOM_SIN  : STD_LOGIC;
+  SIGNAL SPW_NOM_DOUT : STD_LOGIC;
+  SIGNAL SPW_NOM_SOUT : STD_LOGIC;
+  SIGNAL SPW_RED_DIN  : STD_LOGIC;
+  SIGNAL SPW_RED_SIN  : STD_LOGIC;
+  SIGNAL SPW_RED_DOUT : STD_LOGIC;
+  SIGNAL SPW_RED_SOUT : STD_LOGIC;
+  SIGNAL ADC_nCS      : STD_LOGIC;
+  SIGNAL ADC_CLK      : STD_LOGIC;
+  SIGNAL ADC_SDO      : STD_LOGIC_VECTOR(7 DOWNTO 0);
+  SIGNAL SRAM_nWE     : STD_LOGIC;
+  SIGNAL SRAM_CE      : STD_LOGIC;
+  SIGNAL SRAM_nOE     : STD_LOGIC;
+  SIGNAL SRAM_nBE     : STD_LOGIC_VECTOR(3 DOWNTO 0);
+  SIGNAL SRAM_A       : STD_LOGIC_VECTOR(19 DOWNTO 0);
+  SIGNAL SRAM_DQ      : STD_LOGIC_VECTOR(31 DOWNTO 0);
+  -----------------------------------------------------------------------------
+
+  CONSTANT ADDR_BASE_LFR            : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"80000F";
+  CONSTANT ADDR_BASE_TIME_MANAGMENT : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"800006";
+  CONSTANT ADDR_BASE_GPIO           : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"80000B";
+
+
+  SIGNAL message_simu : STRING(1 TO 15) := "---------------";
+  
+BEGIN
+
+  -----------------------------------------------------------------------------
+  -- TB
+  -----------------------------------------------------------------------------
+  PROCESS
+    CONSTANT txp : TIME := 320 ns;
+  BEGIN  -- PROCESS
+    TXD1  <= '1';
+    reset <= '0';
+    WAIT FOR 500 ns;
+    reset <= '1';
+    WAIT FOR 10000 ns;
+    message_simu <= "0 - UART init  ";
+    UART_INIT(TXD1,txp);
+    
+    message_simu <= "1 - UART test  ";
+    UART_WRITE(TXD1,txp,ADDR_BASE_GPIO & "000010",X"0000FFFF");
+    UART_WRITE(TXD1,txp,ADDR_BASE_GPIO & "000001",X"00000A0A");
+    UART_WRITE(TXD1,txp,ADDR_BASE_GPIO & "000001",X"00000B0B");
+
+    -- UNSET the LFR reset
+    message_simu <= "2 - LFR UNRESET";
+    UART_WRITE(TXD1,txp,ADDR_BASE_TIME_MANAGMENT & ADDR_LFR_TM_CONTROL   , X"00000000");
+    UART_WRITE(TXD1,txp,ADDR_BASE_TIME_MANAGMENT & ADDR_LFR_TM_TIME_LOAD , X"00000000");
+    --
+    message_simu <= "3 - LFR CONFIG ";
+    UART_WRITE(TXD1,txp,ADDR_BASE_LFR & ADDR_LFR_SM_F0_0_ADDR , X"00000B0B");
+    
+    WAIT;
+  END PROCESS;
+
+  -----------------------------------------------------------------------------
+  -- CLOCK
+  -----------------------------------------------------------------------------
+  clk_50    <= NOT clk_50 AFTER 5 ns;
+  clk_49    <= NOT clk_49 AFTER 10172 ps;
+  
+  -----------------------------------------------------------------------------
+  -- DON'T CARE
+  -----------------------------------------------------------------------------
+  BP0   <= '0';
+  BP1   <= '0';
+  nRTS1 <= '0' ;
+
+  TXD2  <= '1';
+  nRTS2 <= '1';
+  nDTR2 <= '1';
+  
+  SPW_NOM_DIN  <= '1';
+  SPW_NOM_SIN  <= '1';
+  SPW_RED_DIN  <= '1';
+  SPW_RED_SIN  <= '1';
+  
+  ADC_SDO      <= x"AA";
+
+  SRAM_DQ      <= (OTHERS => 'Z');
+  IO0          <= 'Z';
+  IO1          <= 'Z';
+  IO2          <= 'Z';
+  IO3          <= 'Z';
+  IO4          <= 'Z';
+  IO5          <= 'Z';
+  IO6          <= 'Z';
+  IO7          <= 'Z';
+  IO8          <= 'Z';
+  IO9          <= 'Z';
+  IO10         <= 'Z';
+  IO11         <= 'Z';
+
+  -----------------------------------------------------------------------------
+  -- DUT
+  -----------------------------------------------------------------------------
+  MINI_LFR_top_1: MINI_LFR_top
+    PORT MAP (
+      clk_50       => clk_50,
+      clk_49       => clk_49,
+      reset        => reset,
+      
+      BP0          => BP0,
+      BP1          => BP1,
+
+      LED0         => LED0,
+      LED1         => LED1,
+      LED2         => LED2,
+
+      TXD1         => TXD1,
+      RXD1         => RXD1,
+      nCTS1        => nCTS1,
+      nRTS1        => nRTS1,
+      
+      TXD2         => TXD2,
+      RXD2         => RXD2,
+      nCTS2        => nCTS2,
+      nDTR2        => nDTR2,
+      nRTS2        => nRTS2,
+      nDCD2        => nDCD2,
+      
+      IO0          => IO0,
+      IO1          => IO1,
+      IO2          => IO2,
+      IO3          => IO3,
+      IO4          => IO4,
+      IO5          => IO5,
+      IO6          => IO6,
+      IO7          => IO7,
+      IO8          => IO8,
+      IO9          => IO9,
+      IO10         => IO10,
+      IO11         => IO11,
+      
+      SPW_EN       => SPW_EN,
+      SPW_NOM_DIN  => SPW_NOM_DIN,
+      SPW_NOM_SIN  => SPW_NOM_SIN,
+      SPW_NOM_DOUT => SPW_NOM_DOUT,
+      SPW_NOM_SOUT => SPW_NOM_SOUT,
+      SPW_RED_DIN  => SPW_RED_DIN,
+      SPW_RED_SIN  => SPW_RED_SIN,
+      SPW_RED_DOUT => SPW_RED_DOUT,
+      SPW_RED_SOUT => SPW_RED_SOUT,
+      
+      ADC_nCS      => ADC_nCS,
+      ADC_CLK      => ADC_CLK,
+      ADC_SDO      => ADC_SDO,
+      
+      SRAM_nWE     => SRAM_nWE,
+      SRAM_CE      => SRAM_CE,
+      SRAM_nOE     => SRAM_nOE,
+      SRAM_nBE     => SRAM_nBE,
+      SRAM_A       => SRAM_A,
+      SRAM_DQ      => SRAM_DQ);
+
+  
+END;
diff --git a/lib/lpp/general_purpose/MAC.vhd b/lib/lpp/general_purpose/MAC.vhd
--- a/lib/lpp/general_purpose/MAC.vhd
+++ b/lib/lpp/general_purpose/MAC.vhd
@@ -73,19 +73,19 @@ ARCHITECTURE ar_MAC OF MAC IS
 
   SIGNAL MACMUX2sel : STD_LOGIC;
 
-  SIGNAL add_D            : STD_LOGIC;
-  SIGNAL OP1_2C_D         : STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
-  SIGNAL OP2_2C_D         : STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
-  SIGNAL MULTout_D        : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0);
-  SIGNAL MACMUXsel_D      : STD_LOGIC;
-  SIGNAL MACMUX2sel_D     : STD_LOGIC;
-  SIGNAL MACMUX2sel_D_D   : STD_LOGIC;
-  SIGNAL clr_MAC_D        : STD_LOGIC;
+  SIGNAL add_D          : STD_LOGIC;
+  SIGNAL OP1_2C_D       : STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
+  SIGNAL OP2_2C_D       : STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
+  SIGNAL MULTout_D      : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0);
+  SIGNAL MACMUXsel_D    : STD_LOGIC;
+  SIGNAL MACMUX2sel_D   : STD_LOGIC;
+  SIGNAL MACMUX2sel_D_D : STD_LOGIC;
+  SIGNAL clr_MAC_D      : STD_LOGIC;
 --  SIGNAL clr_MAC_D_D      : STD_LOGIC;
 --  SIGNAL MAC_MUL_ADD_2C_D : STD_LOGIC_VECTOR(1 DOWNTO 0);
 
-  SIGNAL load_mult_result   : STD_LOGIC;
-  SIGNAL load_mult_result_D : STD_LOGIC;
+--  SIGNAL load_mult_result   : STD_LOGIC;
+--  SIGNAL load_mult_result_D : STD_LOGIC;
 
 BEGIN
 
@@ -100,7 +100,7 @@ BEGIN
       ctrl        => MAC_MUL_ADD_s,
       MULT        => mult,
       ADD         => add,
-      LOAD_ADDER  => load_mult_result,
+      --LOAD_ADDER  => load_mult_result,
       MACMUX_sel  => MACMUXsel,
       MACMUX2_sel => MACMUX2sel
 
@@ -128,14 +128,14 @@ BEGIN
       );
 --==============================================================
 
-  PROCESS (clk, reset)
-  BEGIN  -- PROCESS
-    IF reset = '0' THEN                 -- asynchronous reset (active low)
-      load_mult_result_D <= '0';
-    ELSIF clk'EVENT AND clk = '1' THEN  -- rising clock edge
-      load_mult_result_D <= load_mult_result;
-    END IF;
-  END PROCESS;
+  --PROCESS (clk, reset)
+  --BEGIN  -- PROCESS
+  --  IF reset = '0' THEN                 -- asynchronous reset (active low)
+  --    load_mult_result_D <= '0';
+  --  ELSIF clk'EVENT AND clk = '1' THEN  -- rising clock edge
+  --    load_mult_result_D <= load_mult_result;
+  --  END IF;
+  --END PROCESS;
 
 --==============================================================
 --======================A D D E R ==============================
@@ -149,7 +149,7 @@ BEGIN
       clk   => clk,
       reset => reset,
       clr   => clr_MAC_D,
-      load  => load_mult_result_D,
+      load  => MACMUX2sel_D,            --load_mult_result_D,
       add   => add_D,
       OP1   => ADDERinA,
       OP2   => ADDERinB,
@@ -167,7 +167,7 @@ BEGIN
       PORT MAP(
         clk     => clk,
         reset   => reset,
-        clr     => '0',--clr_MAC,
+        clr     => '0',                 --clr_MAC,
         TwoComp => Comp_2C(0),
         OP      => OP1,
         RES     => OP1_2C
@@ -180,13 +180,12 @@ BEGIN
       PORT MAP(
         clk     => clk,
         reset   => reset,
-        clr     => '0',--clr_MAC,
+        clr     => '0',                 --clr_MAC,
         TwoComp => Comp_2C(1),
         OP      => OP2,
         RES     => OP2_2C
         );
-    
-    
+
     clr_MACREG_comp : MAC_REG
       GENERIC MAP(size => 1)
       PORT MAP(
@@ -195,18 +194,18 @@ BEGIN
         D(0)  => clr_MAC,
         Q(0)  => clr_MAC_s
         );
-    
+
     MAC_MUL_ADD_REG : MAC_REG
-    GENERIC MAP(size => 2)
-    PORT MAP(
-      reset => reset,
-      clk   => clk,
-      D     => MAC_MUL_ADD,
-      Q     => MAC_MUL_ADD_s
-      );
-    
+      GENERIC MAP(size => 2)
+      PORT MAP(
+        reset => reset,
+        clk   => clk,
+        D     => MAC_MUL_ADD,
+        Q     => MAC_MUL_ADD_s
+        );
+
   END GENERATE gen_comp;
-  
+
   no_gen_comp : IF COMP_EN = 1 GENERATE
     OP2_2C <= OP2;
     OP1_2C <= OP1;
diff --git a/lib/lpp/general_purpose/MAC_CONTROLER.vhd b/lib/lpp/general_purpose/MAC_CONTROLER.vhd
--- a/lib/lpp/general_purpose/MAC_CONTROLER.vhd
+++ b/lib/lpp/general_purpose/MAC_CONTROLER.vhd
@@ -31,7 +31,7 @@ port(
     ctrl        :   in  std_logic_vector(1 downto 0);
     MULT        :   out std_logic;
     ADD         :   out std_logic;
-    LOAD_ADDER  :   out std_logic;
+--    LOAD_ADDER  :   out std_logic;
     MACMUX_sel  :   out std_logic;
     MACMUX2_sel :   out std_logic
 
@@ -50,9 +50,9 @@ begin
 
 MULT        <=  '0' when (ctrl = "00" or ctrl = "11") else '1';
 ADD         <=  '0' when (ctrl = "00" or ctrl = "10") else '1';
-LOAD_ADDER  <=  '1' when (ctrl = "10") else '0';  -- PATCH JC : mem mult result
-                                                  -- to permit to compute a
-                                                  -- MULT follow by a MAC
+--LOAD_ADDER  <=  '1' when (               ctrl = "10") else '0';  -- PATCH JC : mem mult result
+                                                                 -- to permit to compute a
+                                                                 -- MULT follow by a MAC
 --MACMUX_sel  <=  '0' when (ctrl = "00" or ctrl = "01") else '1';
 MACMUX_sel  <=  '0' when (ctrl = "00" or ctrl = "01" OR ctrl = "10") else '1';
 MACMUX2_sel <=  '0' when (ctrl = "00" or ctrl = "01" or ctrl = "11") else '1';
diff --git a/lib/lpp/general_purpose/general_purpose.vhd b/lib/lpp/general_purpose/general_purpose.vhd
--- a/lib/lpp/general_purpose/general_purpose.vhd
+++ b/lib/lpp/general_purpose/general_purpose.vhd
@@ -217,7 +217,7 @@ Constant CLR_MAC_V0 : std_logic_vector(3
       ctrl        : IN  STD_LOGIC_VECTOR(1 DOWNTO 0);
       MULT        : OUT STD_LOGIC;
       ADD         : OUT STD_LOGIC;
-      LOAD_ADDER  : out std_logic;
+--      LOAD_ADDER  : out std_logic;
       MACMUX_sel  : OUT STD_LOGIC;
       MACMUX2_sel : OUT STD_LOGIC
       );
diff --git a/lib/lpp/lpp_ad_Conv/ADS7886_drvr_v2.vhd b/lib/lpp/lpp_ad_Conv/ADS7886_drvr_v2.vhd
--- a/lib/lpp/lpp_ad_Conv/ADS7886_drvr_v2.vhd
+++ b/lib/lpp/lpp_ad_Conv/ADS7886_drvr_v2.vhd
@@ -57,7 +57,7 @@ ARCHITECTURE ar_ADS7886_drvr_v2 OF ADS78
   SIGNAL cnv_sync_r         : STD_LOGIC;
   SIGNAL cnv_done           : STD_LOGIC;
   SIGNAL sample_bit_counter : INTEGER;
-  SIGNAL shift_reg          : Samples(ChannelCount-1 DOWNTO 0);
+  SIGNAL shift_reg          : Samples_15(ChannelCount-1 DOWNTO 0);
   
 BEGIN
 
@@ -82,8 +82,8 @@ cnv_sync <= cnv_clk;
   BEGIN  -- PROCESS
     IF rstn = '0' THEN
       FOR k IN 0 TO ChannelCount-1 LOOP
-        shift_reg(k)(15 downto 0)	<= (OTHERS => '0');
-		sample(k)(15 downto 0) 		<= (OTHERS => '0');
+        shift_reg(k)(14 downto 0)	<= (OTHERS => '0');
+	sample(k)(15 downto 0) 		<= (OTHERS => '0');
       END LOOP;
       sample_bit_counter <= 0;
       sample_val         <= '0';
@@ -107,7 +107,7 @@ cnv_sync <= cnv_clk;
       IF (sample_bit_counter MOD 2) = 1 THEN	-- get data on each channel
         FOR k IN 0 TO ChannelCount-1 LOOP
           shift_reg(k)(0)           <= sdo(k);
-          shift_reg(k)(15 DOWNTO 1) <= shift_reg(k)(14 DOWNTO 0);
+          shift_reg(k)(14 DOWNTO 1) <= shift_reg(k)(13 DOWNTO 0);
         END LOOP;
         SCK <= '0';
       ELSE
@@ -116,4 +116,4 @@ cnv_sync <= cnv_clk;
     END IF;
   END PROCESS;
   
-END ar_ADS7886_drvr_v2;
\ No newline at end of file
+END ar_ADS7886_drvr_v2;
diff --git a/lib/lpp/lpp_ad_Conv/lpp_ad_Conv.vhd b/lib/lpp/lpp_ad_Conv/lpp_ad_Conv.vhd
--- a/lib/lpp/lpp_ad_Conv/lpp_ad_Conv.vhd
+++ b/lib/lpp/lpp_ad_Conv/lpp_ad_Conv.vhd
@@ -47,7 +47,8 @@ PACKAGE lpp_ad_conv IS
 
   --TYPE AD7688_in IS ARRAY(NATURAL RANGE <>) OF AD7688_in_element;
 
-  TYPE Samples IS ARRAY(NATURAL RANGE <>) OF STD_LOGIC_VECTOR(15 DOWNTO 0);
+  TYPE Samples    IS ARRAY(NATURAL RANGE <>) OF STD_LOGIC_VECTOR(15 DOWNTO 0);
+  TYPE Samples_15 IS ARRAY(NATURAL RANGE <>) OF STD_LOGIC_VECTOR(14 DOWNTO 0);
 
   SUBTYPE Samples24 IS STD_LOGIC_VECTOR(23 DOWNTO 0);
 
diff --git a/lib/lpp/lpp_top_lfr/lpp_lfr.vhd b/lib/lpp/lpp_top_lfr/lpp_lfr.vhd
--- a/lib/lpp/lpp_top_lfr/lpp_lfr.vhd
+++ b/lib/lpp/lpp_top_lfr/lpp_lfr.vhd
@@ -91,11 +91,11 @@ ARCHITECTURE beh OF lpp_lfr IS
 
   -- SM
   SIGNAL ready_matrix_f0          : STD_LOGIC;
-  SIGNAL ready_matrix_f0_1        : STD_LOGIC;
+--  SIGNAL ready_matrix_f0_1        : STD_LOGIC;
   SIGNAL ready_matrix_f1          : STD_LOGIC;
   SIGNAL ready_matrix_f2          : STD_LOGIC;
   SIGNAL status_ready_matrix_f0   : STD_LOGIC;
-  SIGNAL status_ready_matrix_f0_1 : STD_LOGIC;
+--  SIGNAL status_ready_matrix_f0_1 : STD_LOGIC;
   SIGNAL status_ready_matrix_f1   : STD_LOGIC;
   SIGNAL status_ready_matrix_f2   : STD_LOGIC;
   SIGNAL addr_matrix_f0           : STD_LOGIC_VECTOR(31 DOWNTO 0);
@@ -129,24 +129,24 @@ ARCHITECTURE beh OF lpp_lfr IS
   -----------------------------------------------------------------------------
   -- 
   -----------------------------------------------------------------------------
-  SIGNAL data_f0_addr_out_s             : STD_LOGIC_VECTOR(31 DOWNTO 0);
-  SIGNAL data_f0_data_out_valid_s       : STD_LOGIC;
-  SIGNAL data_f0_data_out_valid_burst_s : STD_LOGIC;
+--  SIGNAL data_f0_addr_out_s             : STD_LOGIC_VECTOR(31 DOWNTO 0);
+--  SIGNAL data_f0_data_out_valid_s       : STD_LOGIC;
+--  SIGNAL data_f0_data_out_valid_burst_s : STD_LOGIC;
   --f1
-  SIGNAL data_f1_addr_out_s             : STD_LOGIC_VECTOR(31 DOWNTO 0);
-  SIGNAL data_f1_data_out_valid_s       : STD_LOGIC;
-  SIGNAL data_f1_data_out_valid_burst_s : STD_LOGIC;
+--  SIGNAL data_f1_addr_out_s             : STD_LOGIC_VECTOR(31 DOWNTO 0);
+--  SIGNAL data_f1_data_out_valid_s       : STD_LOGIC;
+--  SIGNAL data_f1_data_out_valid_burst_s : STD_LOGIC;
   --f2
-  SIGNAL data_f2_addr_out_s             : STD_LOGIC_VECTOR(31 DOWNTO 0);
-  SIGNAL data_f2_data_out_valid_s       : STD_LOGIC;
-  SIGNAL data_f2_data_out_valid_burst_s : STD_LOGIC;
+--  SIGNAL data_f2_addr_out_s             : STD_LOGIC_VECTOR(31 DOWNTO 0);
+--  SIGNAL data_f2_data_out_valid_s       : STD_LOGIC;
+--  SIGNAL data_f2_data_out_valid_burst_s : STD_LOGIC;
   --f3
-  SIGNAL data_f3_addr_out_s             : STD_LOGIC_VECTOR(31 DOWNTO 0);
-  SIGNAL data_f3_data_out_valid_s       : STD_LOGIC;
-  SIGNAL data_f3_data_out_valid_burst_s : STD_LOGIC;
+--  SIGNAL data_f3_addr_out_s             : STD_LOGIC_VECTOR(31 DOWNTO 0);
+--  SIGNAL data_f3_data_out_valid_s       : STD_LOGIC;
+--  SIGNAL data_f3_data_out_valid_burst_s : STD_LOGIC;
 
   SIGNAL wfp_status_buffer_ready : STD_LOGIC_VECTOR(3 DOWNTO 0);
-  SIGNAL wfp_addr_buffer         : STD_LOGIC_VECTOR(32*4 DOWNTO 0);
+  SIGNAL wfp_addr_buffer         : STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
   SIGNAL wfp_length_buffer       : STD_LOGIC_VECTOR(25 DOWNTO 0);
   SIGNAL wfp_ready_buffer        : STD_LOGIC_VECTOR(3 DOWNTO 0);
   SIGNAL wfp_buffer_time         : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
@@ -154,51 +154,51 @@ ARCHITECTURE beh OF lpp_lfr IS
   -----------------------------------------------------------------------------
   -- DMA RR
   -----------------------------------------------------------------------------
-  SIGNAL dma_sel_valid   : STD_LOGIC;
-  SIGNAL dma_rr_valid    : STD_LOGIC_VECTOR(3 DOWNTO 0);
-  SIGNAL dma_rr_grant_s  : STD_LOGIC_VECTOR(3 DOWNTO 0);
-  SIGNAL dma_rr_grant_ms : STD_LOGIC_VECTOR(3 DOWNTO 0);
-  SIGNAL dma_rr_valid_ms : STD_LOGIC_VECTOR(3 DOWNTO 0);
+--  SIGNAL dma_sel_valid   : STD_LOGIC;
+--  SIGNAL dma_rr_valid    : STD_LOGIC_VECTOR(3 DOWNTO 0);
+--  SIGNAL dma_rr_grant_s  : STD_LOGIC_VECTOR(3 DOWNTO 0);
+--  SIGNAL dma_rr_grant_ms : STD_LOGIC_VECTOR(3 DOWNTO 0);
+--  SIGNAL dma_rr_valid_ms : STD_LOGIC_VECTOR(3 DOWNTO 0);
 
-  SIGNAL dma_rr_grant : STD_LOGIC_VECTOR(4 DOWNTO 0);
-  SIGNAL dma_sel      : STD_LOGIC_VECTOR(4 DOWNTO 0);
+--  SIGNAL dma_rr_grant : STD_LOGIC_VECTOR(4 DOWNTO 0);
+--  SIGNAL dma_sel      : STD_LOGIC_VECTOR(4 DOWNTO 0);
 
   -----------------------------------------------------------------------------
   -- DMA_REG
   -----------------------------------------------------------------------------
-  SIGNAL ongoing_reg         : STD_LOGIC;
-  SIGNAL dma_sel_reg         : STD_LOGIC_VECTOR(3 DOWNTO 0);
-  SIGNAL dma_send_reg        : STD_LOGIC;
-  SIGNAL dma_valid_burst_reg : STD_LOGIC;  -- (1 => BURST , 0 => SINGLE)
-  SIGNAL dma_address_reg     : STD_LOGIC_VECTOR(31 DOWNTO 0);
-  SIGNAL dma_data_reg        : STD_LOGIC_VECTOR(31 DOWNTO 0);
+--  SIGNAL ongoing_reg         : STD_LOGIC;
+--  SIGNAL dma_sel_reg         : STD_LOGIC_VECTOR(3 DOWNTO 0);
+--  SIGNAL dma_send_reg        : STD_LOGIC;
+--  SIGNAL dma_valid_burst_reg : STD_LOGIC;  -- (1 => BURST , 0 => SINGLE)
+--  SIGNAL dma_address_reg     : STD_LOGIC_VECTOR(31 DOWNTO 0);
+--  SIGNAL dma_data_reg        : STD_LOGIC_VECTOR(31 DOWNTO 0);
 
 
   -----------------------------------------------------------------------------
   -- DMA
   -----------------------------------------------------------------------------
-  SIGNAL dma_send        : STD_LOGIC;
-  SIGNAL dma_valid_burst : STD_LOGIC;   -- (1 => BURST , 0 => SINGLE)
-  SIGNAL dma_done        : STD_LOGIC;
-  SIGNAL dma_ren         : STD_LOGIC;
-  SIGNAL dma_address     : STD_LOGIC_VECTOR(31 DOWNTO 0);
-  SIGNAL dma_data        : STD_LOGIC_VECTOR(31 DOWNTO 0);
-  SIGNAL dma_data_2      : STD_LOGIC_VECTOR(31 DOWNTO 0);
+--  SIGNAL dma_send        : STD_LOGIC;
+--  SIGNAL dma_valid_burst : STD_LOGIC;   -- (1 => BURST , 0 => SINGLE)
+--  SIGNAL dma_done        : STD_LOGIC;
+--  SIGNAL dma_ren         : STD_LOGIC;
+--  SIGNAL dma_address     : STD_LOGIC_VECTOR(31 DOWNTO 0);
+--  SIGNAL dma_data        : STD_LOGIC_VECTOR(31 DOWNTO 0);
+--  SIGNAL dma_data_2      : STD_LOGIC_VECTOR(31 DOWNTO 0);
 
   -----------------------------------------------------------------------------
   -- MS
   -----------------------------------------------------------------------------
 
-  SIGNAL data_ms_addr        : STD_LOGIC_VECTOR(31 DOWNTO 0);
-  SIGNAL data_ms_data        : STD_LOGIC_VECTOR(31 DOWNTO 0);
-  SIGNAL data_ms_valid       : STD_LOGIC;
-  SIGNAL data_ms_valid_burst : STD_LOGIC;
-  SIGNAL data_ms_ren         : STD_LOGIC;
-  SIGNAL data_ms_done        : STD_LOGIC;
-  SIGNAL dma_ms_ongoing      : STD_LOGIC;
+--  SIGNAL data_ms_addr        : STD_LOGIC_VECTOR(31 DOWNTO 0);
+--  SIGNAL data_ms_data        : STD_LOGIC_VECTOR(31 DOWNTO 0);
+--  SIGNAL data_ms_valid       : STD_LOGIC;
+--  SIGNAL data_ms_valid_burst : STD_LOGIC;
+--  SIGNAL data_ms_ren         : STD_LOGIC;
+--  SIGNAL data_ms_done        : STD_LOGIC;
+--  SIGNAL dma_ms_ongoing      : STD_LOGIC;
 
 --  SIGNAL run_ms              : STD_LOGIC;
-  SIGNAL ms_softandhard_rstn : STD_LOGIC;
+--  SIGNAL ms_softandhard_rstn : STD_LOGIC;
 
   SIGNAL matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
 --  SIGNAL matrix_time_f0_1    : STD_LOGIC_VECTOR(47 DOWNTO 0);
@@ -210,7 +210,7 @@ ARCHITECTURE beh OF lpp_lfr IS
   SIGNAL error_input_fifo_write : STD_LOGIC_VECTOR(2 DOWNTO 0);
 
 --  SIGNAL debug_ms : STD_LOGIC_VECTOR(31 DOWNTO 0);
-  SIGNAL debug_signal : STD_LOGIC_VECTOR(31 DOWNTO 0);
+--  SIGNAL debug_signal : STD_LOGIC_VECTOR(31 DOWNTO 0);
 
   -----------------------------------------------------------------------------
   SIGNAL dma_fifo_burst_valid : STD_LOGIC_VECTOR(4 DOWNTO 0);
diff --git a/lib/lpp/lpp_top_lfr/lpp_lfr_apbreg.vhd b/lib/lpp/lpp_top_lfr/lpp_lfr_apbreg.vhd
--- a/lib/lpp/lpp_top_lfr/lpp_lfr_apbreg.vhd
+++ b/lib/lpp/lpp_top_lfr/lpp_lfr_apbreg.vhd
@@ -133,7 +133,7 @@ ENTITY lpp_lfr_apbreg IS
     start_date   : OUT STD_LOGIC_VECTOR(30 DOWNTO 0);
     
     wfp_status_buffer_ready : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
-    wfp_addr_buffer         : OUT STD_LOGIC_VECTOR(32*4 DOWNTO 0);
+    wfp_addr_buffer         : OUT STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
     wfp_length_buffer       : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
     wfp_ready_buffer        : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
     wfp_buffer_time         : IN STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
@@ -238,28 +238,28 @@ ARCHITECTURE beh OF lpp_lfr_apbreg IS
   -- 
   -----------------------------------------------------------------------------
   SIGNAL reg0_ready_matrix_f0 : STD_LOGIC;
-  SIGNAL reg0_addr_matrix_f0  : STD_LOGIC_VECTOR(31 DOWNTO 0);
-  SIGNAL reg0_matrix_time_f0  : STD_LOGIC_VECTOR(47 DOWNTO 0);
+--  SIGNAL reg0_addr_matrix_f0  : STD_LOGIC_VECTOR(31 DOWNTO 0);
+--  SIGNAL reg0_matrix_time_f0  : STD_LOGIC_VECTOR(47 DOWNTO 0);
 
   SIGNAL reg1_ready_matrix_f0 : STD_LOGIC;
-  SIGNAL reg1_addr_matrix_f0  : STD_LOGIC_VECTOR(31 DOWNTO 0);
-  SIGNAL reg1_matrix_time_f0  : STD_LOGIC_VECTOR(47 DOWNTO 0);
+--  SIGNAL reg1_addr_matrix_f0  : STD_LOGIC_VECTOR(31 DOWNTO 0);
+--  SIGNAL reg1_matrix_time_f0  : STD_LOGIC_VECTOR(47 DOWNTO 0);
 
   SIGNAL reg0_ready_matrix_f1 : STD_LOGIC;
-  SIGNAL reg0_addr_matrix_f1  : STD_LOGIC_VECTOR(31 DOWNTO 0);
-  SIGNAL reg0_matrix_time_f1  : STD_LOGIC_VECTOR(47 DOWNTO 0);
+--  SIGNAL reg0_addr_matrix_f1  : STD_LOGIC_VECTOR(31 DOWNTO 0);
+--  SIGNAL reg0_matrix_time_f1  : STD_LOGIC_VECTOR(47 DOWNTO 0);
 
   SIGNAL reg1_ready_matrix_f1 : STD_LOGIC;
-  SIGNAL reg1_addr_matrix_f1  : STD_LOGIC_VECTOR(31 DOWNTO 0);
-  SIGNAL reg1_matrix_time_f1  : STD_LOGIC_VECTOR(47 DOWNTO 0);
+--  SIGNAL reg1_addr_matrix_f1  : STD_LOGIC_VECTOR(31 DOWNTO 0);
+--  SIGNAL reg1_matrix_time_f1  : STD_LOGIC_VECTOR(47 DOWNTO 0);
 
   SIGNAL reg0_ready_matrix_f2 : STD_LOGIC;
-  SIGNAL reg0_addr_matrix_f2  : STD_LOGIC_VECTOR(31 DOWNTO 0);
-  SIGNAL reg0_matrix_time_f2  : STD_LOGIC_VECTOR(47 DOWNTO 0);
+--  SIGNAL reg0_addr_matrix_f2  : STD_LOGIC_VECTOR(31 DOWNTO 0);
+--  SIGNAL reg0_matrix_time_f2  : STD_LOGIC_VECTOR(47 DOWNTO 0);
 
   SIGNAL reg1_ready_matrix_f2 : STD_LOGIC;
-  SIGNAL reg1_addr_matrix_f2  : STD_LOGIC_VECTOR(31 DOWNTO 0);
-  SIGNAL reg1_matrix_time_f2  : STD_LOGIC_VECTOR(47 DOWNTO 0);
+--  SIGNAL reg1_addr_matrix_f2  : STD_LOGIC_VECTOR(31 DOWNTO 0);
+--  SIGNAL reg1_matrix_time_f2  : STD_LOGIC_VECTOR(47 DOWNTO 0);
   SIGNAL apbo_irq_ms : STD_LOGIC;
   SIGNAL apbo_irq_wfp : STD_LOGIC;
   -----------------------------------------------------------------------------
@@ -778,4 +778,4 @@ BEGIN  -- beh
         
 END beh;
 
--------------------------------------------------------------------------------
+-------------------------------------------------------------------------------
\ No newline at end of file
diff --git a/lib/lpp/lpp_top_lfr/lpp_lfr_ms.vhd b/lib/lpp/lpp_top_lfr/lpp_lfr_ms.vhd
--- a/lib/lpp/lpp_top_lfr/lpp_lfr_ms.vhd
+++ b/lib/lpp/lpp_top_lfr/lpp_lfr_ms.vhd
@@ -121,8 +121,10 @@ ARCHITECTURE Behavioral OF lpp_lfr_ms IS
   -----------------------------------------------------------------------------
   TYPE   fsm_select_channel IS (IDLE, SWITCH_F0_A, SWITCH_F0_B, SWITCH_F1, SWITCH_F2);
   SIGNAL state_fsm_select_channel     : fsm_select_channel;
-  SIGNAL pre_state_fsm_select_channel : fsm_select_channel;
-
+--  SIGNAL pre_state_fsm_select_channel : fsm_select_channel;
+  SIGNAL select_channel     : STD_LOGIC_VECTOR(1 DOWNTO 0);
+  SIGNAL select_channel_reg : STD_LOGIC_VECTOR(1 DOWNTO 0);
+    
   SIGNAL sample_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
   SIGNAL sample_ren   : STD_LOGIC_VECTOR(4 DOWNTO 0);
   SIGNAL sample_full  : STD_LOGIC_VECTOR(4 DOWNTO 0);
@@ -133,7 +135,9 @@ ARCHITECTURE Behavioral OF lpp_lfr_ms IS
   -----------------------------------------------------------------------------
   TYPE   fsm_load_FFT IS (IDLE, FIFO_1, FIFO_2, FIFO_3, FIFO_4, FIFO_5);
   SIGNAL state_fsm_load_FFT      : fsm_load_FFT;
-  SIGNAL next_state_fsm_load_FFT : fsm_load_FFT;
+--  SIGNAL next_state_fsm_load_FFT : fsm_load_FFT;
+  SIGNAL select_fifo     : STD_LOGIC_VECTOR(2 DOWNTO 0);
+  SIGNAL select_fifo_reg : STD_LOGIC_VECTOR(2 DOWNTO 0);
 
   SIGNAL sample_ren_s   : STD_LOGIC_VECTOR(4 DOWNTO 0);
   SIGNAL sample_load    : STD_LOGIC;
@@ -199,7 +203,7 @@ ARCHITECTURE Behavioral OF lpp_lfr_ms IS
   SIGNAL FSM_DMA_fifo_empty  : STD_LOGIC;
   SIGNAL FSM_DMA_fifo_empty_threshold  : STD_LOGIC;
   SIGNAL FSM_DMA_fifo_data   : STD_LOGIC_VECTOR(31 DOWNTO 0);
-  SIGNAL FSM_DMA_fifo_status : STD_LOGIC_VECTOR(53 DOWNTO 0);
+  SIGNAL FSM_DMA_fifo_status : STD_LOGIC_VECTOR(53 DOWNTO 4);
   -----------------------------------------------------------------------------
   SIGNAL MEM_OUT_SM_Write    : STD_LOGIC_VECTOR(1 DOWNTO 0);
   SIGNAL MEM_OUT_SM_Read     : STD_LOGIC_VECTOR(1 DOWNTO 0);
@@ -233,8 +237,8 @@ ARCHITECTURE Behavioral OF lpp_lfr_ms IS
   SIGNAL status_MS_input  : STD_LOGIC_VECTOR(49 DOWNTO 0);
   SIGNAL status_component : STD_LOGIC_VECTOR(53 DOWNTO 0);
 
-  SIGNAL status_component_fifo_0     : STD_LOGIC_VECTOR(53 DOWNTO 0);
-  SIGNAL status_component_fifo_1     : STD_LOGIC_VECTOR(53 DOWNTO 0);
+  SIGNAL status_component_fifo_0     : STD_LOGIC_VECTOR(53 DOWNTO 4);
+  SIGNAL status_component_fifo_1     : STD_LOGIC_VECTOR(53 DOWNTO 4);
   SIGNAL status_component_fifo_0_end : STD_LOGIC;
   SIGNAL status_component_fifo_1_end : STD_LOGIC;
   -----------------------------------------------------------------------------
@@ -471,36 +475,45 @@ BEGIN
   BEGIN
     IF rstn = '0' THEN
       state_fsm_select_channel <= IDLE;
+      select_channel <= (OTHERS => '0');
     ELSIF clk'EVENT AND clk = '1' THEN
       CASE state_fsm_select_channel IS
         WHEN IDLE =>
           IF sample_f1_full = "11111" THEN
             state_fsm_select_channel <= SWITCH_F1;
+            select_channel <= "10";
           ELSIF sample_f1_almost_full = "00000" THEN
             IF sample_f0_A_full = "11111" THEN
               state_fsm_select_channel <= SWITCH_F0_A;
+              select_channel <= "00";
             ELSIF sample_f0_B_full = "11111" THEN
               state_fsm_select_channel <= SWITCH_F0_B;
+              select_channel <= "01";
             ELSIF sample_f2_full = "11111" THEN
               state_fsm_select_channel <= SWITCH_F2;
+              select_channel <= "11";
             END IF;
           END IF;
           
         WHEN SWITCH_F0_A =>
           IF sample_f0_A_empty = "11111" THEN
             state_fsm_select_channel <= IDLE;
+            select_channel <= (OTHERS => '0');
           END IF;
         WHEN SWITCH_F0_B =>
           IF sample_f0_B_empty = "11111" THEN
             state_fsm_select_channel <= IDLE;
+            select_channel <= (OTHERS => '0');
           END IF;
         WHEN SWITCH_F1 =>
           IF sample_f1_empty = "11111" THEN
             state_fsm_select_channel <= IDLE;
+            select_channel <= (OTHERS => '0');
           END IF;
         WHEN SWITCH_F2 =>
           IF sample_f2_empty = "11111" THEN
             state_fsm_select_channel <= IDLE;
+            select_channel <= (OTHERS => '0');
           END IF;
         WHEN OTHERS => NULL;
       END CASE;
@@ -511,9 +524,11 @@ BEGIN
   PROCESS (clk, rstn)
   BEGIN
     IF rstn = '0' THEN
-      pre_state_fsm_select_channel <= IDLE;
+      select_channel_reg <= (OTHERS => '0');
+      --pre_state_fsm_select_channel <= IDLE;
     ELSIF clk'EVENT AND clk = '1' THEN
-      pre_state_fsm_select_channel <= state_fsm_select_channel;
+      select_channel_reg <= select_channel;
+      --pre_state_fsm_select_channel <= state_fsm_select_channel;
     END IF;
   END PROCESS;
 
@@ -533,9 +548,13 @@ BEGIN
                  sample_f2_full   WHEN state_fsm_select_channel = SWITCH_F2   ELSE
                  (OTHERS => '0');
   
-  sample_rdata <= sample_f0_A_rdata WHEN pre_state_fsm_select_channel = SWITCH_F0_A ELSE
-                  sample_f0_B_rdata WHEN pre_state_fsm_select_channel = SWITCH_F0_B ELSE
-                  sample_f1_rdata   WHEN pre_state_fsm_select_channel = SWITCH_F1   ELSE
+  --sample_rdata <= sample_f0_A_rdata WHEN pre_state_fsm_select_channel = SWITCH_F0_A ELSE
+  --                sample_f0_B_rdata WHEN pre_state_fsm_select_channel = SWITCH_F0_B ELSE
+  --                sample_f1_rdata   WHEN pre_state_fsm_select_channel = SWITCH_F1   ELSE
+  --                sample_f2_rdata;  -- WHEN state_fsm_select_channel = SWITCH_F2   ELSE
+  sample_rdata <= sample_f0_A_rdata WHEN select_channel_reg = "00" ELSE
+                  sample_f0_B_rdata WHEN select_channel_reg = "01" ELSE
+                  sample_f1_rdata   WHEN select_channel_reg = "10"   ELSE
                   sample_f2_rdata;  -- WHEN state_fsm_select_channel = SWITCH_F2   ELSE
 
 
@@ -564,6 +583,7 @@ BEGIN
       sample_ren_s       <= (OTHERS => '1');
       state_fsm_load_FFT <= IDLE;
       status_MS_input    <= (OTHERS => '0');
+      select_fifo        <= "000";
       --next_state_fsm_load_FFT <= IDLE;
       --sample_valid              <= '0';
     ELSIF clk'EVENT AND clk = '1' THEN
@@ -574,6 +594,7 @@ BEGIN
           IF sample_full = "11111" AND sample_load = '1' THEN
             state_fsm_load_FFT <= FIFO_1;
             status_MS_input    <= status_channel;
+            select_fifo <= "000";
           END IF;
           
         WHEN FIFO_1 =>
@@ -581,6 +602,7 @@ BEGIN
           IF sample_empty(0) = '1' THEN
             sample_ren_s       <= (OTHERS => '1');
             state_fsm_load_FFT <= FIFO_2;
+            select_fifo <= "001";
           END IF;
           
         WHEN FIFO_2 =>
@@ -588,6 +610,7 @@ BEGIN
           IF sample_empty(1) = '1' THEN
             sample_ren_s       <= (OTHERS => '1');
             state_fsm_load_FFT <= FIFO_3;
+            select_fifo <= "010";
           END IF;
           
         WHEN FIFO_3 =>
@@ -595,6 +618,7 @@ BEGIN
           IF sample_empty(2) = '1' THEN
             sample_ren_s       <= (OTHERS => '1');
             state_fsm_load_FFT <= FIFO_4;
+            select_fifo <= "011";
           END IF;
           
         WHEN FIFO_4 =>
@@ -602,6 +626,7 @@ BEGIN
           IF sample_empty(3) = '1' THEN
             sample_ren_s       <= (OTHERS => '1');
             state_fsm_load_FFT <= FIFO_5;
+            select_fifo <= "100";
           END IF;
           
         WHEN FIFO_5 =>
@@ -609,6 +634,7 @@ BEGIN
           IF sample_empty(4) = '1' THEN
             sample_ren_s       <= (OTHERS => '1');
             state_fsm_load_FFT <= IDLE;
+            select_fifo <= "000";
           END IF;
         WHEN OTHERS => NULL;
       END CASE;
@@ -619,9 +645,11 @@ BEGIN
   BEGIN
     IF rstn = '0' THEN
       sample_valid_r          <= '0';
-      next_state_fsm_load_FFT <= IDLE;
+      select_fifo_reg <= (OTHERS => '0');
+      --next_state_fsm_load_FFT <= IDLE;
     ELSIF clk'EVENT AND clk = '1' THEN
-      next_state_fsm_load_FFT <= state_fsm_load_FFT;
+      select_fifo_reg <= select_fifo;
+      --next_state_fsm_load_FFT <= state_fsm_load_FFT;
       IF sample_ren_s = "11111" THEN
         sample_valid_r <= '0';
       ELSE
@@ -632,12 +660,17 @@ BEGIN
 
   sample_valid <= '0' WHEN fft_ongoing_counter = '1' ELSE sample_valid_r AND sample_load;
 
-  sample_data <= sample_rdata(16*1-1 DOWNTO 16*0) WHEN next_state_fsm_load_FFT = FIFO_1 ELSE
-                 sample_rdata(16*2-1 DOWNTO 16*1) WHEN next_state_fsm_load_FFT = FIFO_2 ELSE
-                 sample_rdata(16*3-1 DOWNTO 16*2) WHEN next_state_fsm_load_FFT = FIFO_3 ELSE
-                 sample_rdata(16*4-1 DOWNTO 16*3) WHEN next_state_fsm_load_FFT = FIFO_4 ELSE
+  --sample_data <= sample_rdata(16*1-1 DOWNTO 16*0) WHEN next_state_fsm_load_FFT = FIFO_1 ELSE
+  --               sample_rdata(16*2-1 DOWNTO 16*1) WHEN next_state_fsm_load_FFT = FIFO_2 ELSE
+  --               sample_rdata(16*3-1 DOWNTO 16*2) WHEN next_state_fsm_load_FFT = FIFO_3 ELSE
+  --               sample_rdata(16*4-1 DOWNTO 16*3) WHEN next_state_fsm_load_FFT = FIFO_4 ELSE
+  --               sample_rdata(16*5-1 DOWNTO 16*4);  --WHEN next_state_fsm_load_FFT = FIFO_5 ELSE
+  sample_data <= sample_rdata(16*1-1 DOWNTO 16*0) WHEN select_fifo_reg = "000" ELSE
+                 sample_rdata(16*2-1 DOWNTO 16*1) WHEN select_fifo_reg = "001" ELSE
+                 sample_rdata(16*3-1 DOWNTO 16*2) WHEN select_fifo_reg = "010" ELSE
+                 sample_rdata(16*4-1 DOWNTO 16*3) WHEN select_fifo_reg = "011"  ELSE
                  sample_rdata(16*5-1 DOWNTO 16*4);  --WHEN next_state_fsm_load_FFT = FIFO_5 ELSE
-
+  
   -----------------------------------------------------------------------------
   -- FFT
   -----------------------------------------------------------------------------
@@ -852,9 +885,9 @@ BEGIN
       status_component_fifo_1_end <= '0';
       IF SM_correlation_begin = '1' THEN
         IF current_matrix_write = '0' THEN
-          status_component_fifo_0 <= status_component;
+          status_component_fifo_0 <= status_component(53 DOWNTO 4);
         ELSE
-          status_component_fifo_1 <= status_component;
+          status_component_fifo_1 <= status_component(53 DOWNTO 4);
         END IF;
       END IF;
 
diff --git a/lib/lpp/lpp_top_lfr/lpp_lfr_pkg.vhd b/lib/lpp/lpp_top_lfr/lpp_lfr_pkg.vhd
--- a/lib/lpp/lpp_top_lfr/lpp_lfr_pkg.vhd
+++ b/lib/lpp/lpp_top_lfr/lpp_lfr_pkg.vhd
@@ -311,7 +311,7 @@ PACKAGE lpp_lfr_pkg IS
       run                     : OUT STD_LOGIC;
       start_date              : OUT STD_LOGIC_VECTOR(30 DOWNTO 0);
       wfp_status_buffer_ready : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
-      wfp_addr_buffer         : OUT STD_LOGIC_VECTOR(32*4 DOWNTO 0);
+      wfp_addr_buffer         : OUT STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
       wfp_length_buffer       : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
       wfp_ready_buffer        : IN  STD_LOGIC_VECTOR(3 DOWNTO 0);
       wfp_buffer_time         : IN  STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
diff --git a/lib/lpp/lpp_waveform/lpp_waveform.vhd b/lib/lpp/lpp_waveform/lpp_waveform.vhd
--- a/lib/lpp/lpp_waveform/lpp_waveform.vhd
+++ b/lib/lpp/lpp_waveform/lpp_waveform.vhd
@@ -84,7 +84,7 @@ ENTITY lpp_waveform IS
 
     -- REG DMA
     status_buffer_ready : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
-    addr_buffer         : IN STD_LOGIC_VECTOR(32*4 DOWNTO 0);
+    addr_buffer         : IN STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
     length_buffer       : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
     
     ready_buffer        : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
diff --git a/lib/lpp/lpp_waveform/lpp_waveform_fifo_arbiter.vhd b/lib/lpp/lpp_waveform/lpp_waveform_fifo_arbiter.vhd
--- a/lib/lpp/lpp_waveform/lpp_waveform_fifo_arbiter.vhd
+++ b/lib/lpp/lpp_waveform/lpp_waveform_fifo_arbiter.vhd
@@ -73,11 +73,11 @@ ARCHITECTURE ar_lpp_waveform_fifo_arbite
   -- DATA MUX
   -----------------------------------------------------------------------------
   TYPE WORD_VECTOR IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR(31 DOWNTO 0); 
-  SIGNAL data_0   : WORD_VECTOR(3 DOWNTO 0);
-  SIGNAL data_1   : WORD_VECTOR(3 DOWNTO 0);
-  SIGNAL data_2   : WORD_VECTOR(3 DOWNTO 0);
-  SIGNAL data_3   : WORD_VECTOR(3 DOWNTO 0);
-  SIGNAL data_sel : WORD_VECTOR(3 DOWNTO 0);  
+  SIGNAL data_0   : WORD_VECTOR(2 DOWNTO 0);
+  SIGNAL data_1   : WORD_VECTOR(2 DOWNTO 0);
+  SIGNAL data_2   : WORD_VECTOR(2 DOWNTO 0);
+  SIGNAL data_3   : WORD_VECTOR(2 DOWNTO 0);
+  SIGNAL data_sel : WORD_VECTOR(2 DOWNTO 0);  
   
   -----------------------------------------------------------------------------
   -- RR and SELECTION
@@ -267,4 +267,3 @@ END ARCHITECTURE;
 
 
 
-
diff --git a/lib/lpp/lpp_waveform/lpp_waveform_fifo_arbiter_reg.vhd b/lib/lpp/lpp_waveform/lpp_waveform_fifo_arbiter_reg.vhd
--- a/lib/lpp/lpp_waveform/lpp_waveform_fifo_arbiter_reg.vhd
+++ b/lib/lpp/lpp_waveform/lpp_waveform_fifo_arbiter_reg.vhd
@@ -80,7 +80,7 @@ BEGIN
              reg(2) WHEN sel(2) = '1' ELSE
              reg(3);
 
-  reg_sel_s <= reg_sel WHEN enable = '0' ELSE
+  reg_sel_s <= reg_sel     WHEN enable = '0' ELSE
                reg_sel + 1 WHEN reg_sel < UNSIGNED(max_count) ELSE
                0;
 
@@ -113,4 +113,3 @@ END ARCHITECTURE;
 
 
 
-
diff --git a/lib/lpp/lpp_waveform/lpp_waveform_pkg.vhd b/lib/lpp/lpp_waveform/lpp_waveform_pkg.vhd
--- a/lib/lpp/lpp_waveform/lpp_waveform_pkg.vhd
+++ b/lib/lpp/lpp_waveform/lpp_waveform_pkg.vhd
@@ -129,7 +129,7 @@ PACKAGE lpp_waveform_pkg IS
       nb_snapshot_param            : IN  STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
       status_new_err               : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
       status_buffer_ready : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
-      addr_buffer         : IN STD_LOGIC_VECTOR(32*4 DOWNTO 0);
+      addr_buffer         : IN STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
       length_buffer       : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
       ready_buffer        : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
       buffer_time         : OUT STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);