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1.1.34 : idem 1.1.33 avec reset soft pour LFR subsystem
pellion -
r463:832e74562224 (LFR-EM) WFP_MS-1-1-34 JC
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@@ -138,7 +138,10 ARCHITECTURE beh OF LFR_em IS
138 138
139 139 -----------------------------------------------------------------------------
140 140 SIGNAL rstn : STD_LOGIC;
141
141
142 SIGNAL LFR_soft_rstn : STD_LOGIC;
143 SIGNAL LFR_rstn : STD_LOGIC;
144
142 145 SIGNAL ADC_smpclk_s : STD_LOGIC;
143 146
144 147 BEGIN -- beh
@@ -252,7 +255,9 BEGIN -- beh
252 255 apbi => apbi_ext,
253 256 apbo => apbo_ext(6),
254 257 coarse_time => coarse_time,
255 fine_time => fine_time);
258 fine_time => fine_time,
259 LFR_soft_rstn => LFR_soft_rstn
260 );
256 261
257 262 -----------------------------------------------------------------------
258 263 --- SpaceWire --------------------------------------------------------
@@ -343,6 +348,8 BEGIN -- beh
343 348 -------------------------------------------------------------------------------
344 349 -- LFR ------------------------------------------------------------------------
345 350 -------------------------------------------------------------------------------
351 LFR_rstn <= LFR_soft_rstn AND rstn;
352
346 353 lpp_lfr_1 : lpp_lfr
347 354 GENERIC MAP (
348 355 Mem_use => use_RAM,
@@ -357,13 +364,13 BEGIN -- beh
357 364 pirq_ms => 6,
358 365 pirq_wfp => 14,
359 366 hindex => 2,
360 top_lfr_version => X"010121") -- aa.bb.cc version
367 top_lfr_version => X"010122") -- aa.bb.cc version
361 368 -- AA : BOARD NUMBER
362 369 -- 0 => MINI_LFR
363 370 -- 1 => EM
364 371 PORT MAP (
365 372 clk => clk_25,
366 rstn => rstn,
373 rstn => LFR_rstn,
367 374 sample_B => sample_s(2 DOWNTO 0),
368 375 sample_E => sample_s(7 DOWNTO 3),
369 376 sample_val => sample_val,
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@@ -122,12 +122,12 ARCHITECTURE beh OF MINI_LFR_top IS
122 122 --
123 123 SIGNAL errorn : STD_LOGIC;
124 124 -- UART AHB ---------------------------------------------------------------
125 SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data
126 SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data
125 -- SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data
126 -- SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data
127 127
128 128 -- UART APB ---------------------------------------------------------------
129 SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data
130 SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data
129 -- SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data
130 -- SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data
131 131 --
132 132 SIGNAL I00_s : STD_LOGIC;
133 133
@@ -439,6 +439,8 BEGIN -- beh
439 439 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
440 440 END GENERATE spw_inputloop;
441 441
442 swni.rmapnodeaddr <= (others => '0');
443
442 444 -- SPW core
443 445 sw0 : grspwm GENERIC MAP(
444 446 tech => apa3e,
@@ -514,12 +516,14 BEGIN -- beh
514 516 fine_time => fine_time,
515 517 data_shaping_BW => bias_fail_sw_sig);
516 518
519 observation_reg <= (others => '0');
520 observation_vector_0 <= (others => '0');
521 observation_vector_1 <= (others => '0');
522
517 523 all_sample: FOR I IN 7 DOWNTO 0 GENERATE
518 524 sample_s(I) <= sample(I)(11 DOWNTO 0) & '0' & '0' & '0' & '0';
519 525 END GENERATE all_sample;
520 526
521
522
523 527 top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2
524 528 GENERIC MAP(
525 529 ChannelCount => 8,
@@ -556,6 +560,9 BEGIN -- beh
556 560 GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8)
557 561 PORT MAP(rstn_25, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo);
558 562
563 gpioi.sig_en <= (others => '0');
564 gpioi.sig_in <= (others => '0');
565 gpioi.din <= (others => '0');
559 566 --pio_pad_0 : iopad
560 567 -- GENERIC MAP (tech => CFG_PADTECH)
561 568 -- PORT MAP (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0));
@@ -688,4 +695,4 BEGIN -- beh
688 695 END GENERATE ahbo_m_ext_not_used;
689 696 END GENERATE all_ahbo_m_ext;
690 697
691 END beh;
698 END beh; No newline at end of file
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@@ -1,270 +1,273
1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
3 USE ieee.numeric_std.ALL;
4 use IEEE.std_logic_textio.all;
5 LIBRARY STD;
6 use std.textio.all;
7
8 LIBRARY grlib;
9 USE grlib.stdlib.ALL;
10 LIBRARY gaisler;
11 USE gaisler.libdcom.ALL;
12 USE gaisler.sim.ALL;
13 USE gaisler.jtagtst.ALL;
14 LIBRARY techmap;
15 USE techmap.gencomp.ALL;
16
17 LIBRARY lpp;
18 USE lpp.lpp_sim_pkg.ALL;
19 USE lpp.lpp_lfr_apbreg_pkg.ALL;
20 USE lpp.lpp_lfr_time_management_apbreg_pkg.ALL;
21
22 ENTITY testbench IS
23 END;
24
25 ARCHITECTURE behav OF testbench IS
26
27 COMPONENT MINI_LFR_top
28 PORT (
29 clk_50 : IN STD_LOGIC;
30 clk_49 : IN STD_LOGIC;
31 reset : IN STD_LOGIC;
32 BP0 : IN STD_LOGIC;
33 BP1 : IN STD_LOGIC;
34 LED0 : OUT STD_LOGIC;
35 LED1 : OUT STD_LOGIC;
36 LED2 : OUT STD_LOGIC;
37 TXD1 : IN STD_LOGIC;
38 RXD1 : OUT STD_LOGIC;
39 nCTS1 : OUT STD_LOGIC;
40 nRTS1 : IN STD_LOGIC;
41 TXD2 : IN STD_LOGIC;
42 RXD2 : OUT STD_LOGIC;
43 nCTS2 : OUT STD_LOGIC;
44 nDTR2 : IN STD_LOGIC;
45 nRTS2 : IN STD_LOGIC;
46 nDCD2 : OUT STD_LOGIC;
47 IO0 : INOUT STD_LOGIC;
48 IO1 : INOUT STD_LOGIC;
49 IO2 : INOUT STD_LOGIC;
50 IO3 : INOUT STD_LOGIC;
51 IO4 : INOUT STD_LOGIC;
52 IO5 : INOUT STD_LOGIC;
53 IO6 : INOUT STD_LOGIC;
54 IO7 : INOUT STD_LOGIC;
55 IO8 : INOUT STD_LOGIC;
56 IO9 : INOUT STD_LOGIC;
57 IO10 : INOUT STD_LOGIC;
58 IO11 : INOUT STD_LOGIC;
59 SPW_EN : OUT STD_LOGIC;
60 SPW_NOM_DIN : IN STD_LOGIC;
61 SPW_NOM_SIN : IN STD_LOGIC;
62 SPW_NOM_DOUT : OUT STD_LOGIC;
63 SPW_NOM_SOUT : OUT STD_LOGIC;
64 SPW_RED_DIN : IN STD_LOGIC;
65 SPW_RED_SIN : IN STD_LOGIC;
66 SPW_RED_DOUT : OUT STD_LOGIC;
67 SPW_RED_SOUT : OUT STD_LOGIC;
68 ADC_nCS : OUT STD_LOGIC;
69 ADC_CLK : OUT STD_LOGIC;
70 ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
71 SRAM_nWE : OUT STD_LOGIC;
72 SRAM_CE : OUT STD_LOGIC;
73 SRAM_nOE : OUT STD_LOGIC;
74 SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
75 SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
76 SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0));
77 END COMPONENT;
78
79 -----------------------------------------------------------------------------
80 SIGNAL clk_50 : STD_LOGIC := '0';
81 SIGNAL clk_49 : STD_LOGIC := '0';
82 SIGNAL reset : STD_LOGIC;
83 SIGNAL BP0 : STD_LOGIC;
84 SIGNAL BP1 : STD_LOGIC;
85 SIGNAL LED0 : STD_LOGIC;
86 SIGNAL LED1 : STD_LOGIC;
87 SIGNAL LED2 : STD_LOGIC;
88 SIGNAL TXD1 : STD_LOGIC;
89 SIGNAL RXD1 : STD_LOGIC;
90 SIGNAL nCTS1 : STD_LOGIC;
91 SIGNAL nRTS1 : STD_LOGIC;
92 SIGNAL TXD2 : STD_LOGIC;
93 SIGNAL RXD2 : STD_LOGIC;
94 SIGNAL nCTS2 : STD_LOGIC;
95 SIGNAL nDTR2 : STD_LOGIC;
96 SIGNAL nRTS2 : STD_LOGIC;
97 SIGNAL nDCD2 : STD_LOGIC;
98 SIGNAL IO0 : STD_LOGIC;
99 SIGNAL IO1 : STD_LOGIC;
100 SIGNAL IO2 : STD_LOGIC;
101 SIGNAL IO3 : STD_LOGIC;
102 SIGNAL IO4 : STD_LOGIC;
103 SIGNAL IO5 : STD_LOGIC;
104 SIGNAL IO6 : STD_LOGIC;
105 SIGNAL IO7 : STD_LOGIC;
106 SIGNAL IO8 : STD_LOGIC;
107 SIGNAL IO9 : STD_LOGIC;
108 SIGNAL IO10 : STD_LOGIC;
109 SIGNAL IO11 : STD_LOGIC;
110 SIGNAL SPW_EN : STD_LOGIC;
111 SIGNAL SPW_NOM_DIN : STD_LOGIC;
112 SIGNAL SPW_NOM_SIN : STD_LOGIC;
113 SIGNAL SPW_NOM_DOUT : STD_LOGIC;
114 SIGNAL SPW_NOM_SOUT : STD_LOGIC;
115 SIGNAL SPW_RED_DIN : STD_LOGIC;
116 SIGNAL SPW_RED_SIN : STD_LOGIC;
117 SIGNAL SPW_RED_DOUT : STD_LOGIC;
118 SIGNAL SPW_RED_SOUT : STD_LOGIC;
119 SIGNAL ADC_nCS : STD_LOGIC;
120 SIGNAL ADC_CLK : STD_LOGIC;
121 SIGNAL ADC_SDO : STD_LOGIC_VECTOR(7 DOWNTO 0);
122 SIGNAL SRAM_nWE : STD_LOGIC;
123 SIGNAL SRAM_CE : STD_LOGIC;
124 SIGNAL SRAM_nOE : STD_LOGIC;
125 SIGNAL SRAM_nBE : STD_LOGIC_VECTOR(3 DOWNTO 0);
126 SIGNAL SRAM_A : STD_LOGIC_VECTOR(19 DOWNTO 0);
127 SIGNAL SRAM_DQ : STD_LOGIC_VECTOR(31 DOWNTO 0);
128 -----------------------------------------------------------------------------
129
130 CONSTANT ADDR_BASE_LFR : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"80000F";
131 CONSTANT ADDR_BASE_TIME_MANAGMENT : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"800006";
132 CONSTANT ADDR_BASE_GPIO : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"80000B";
133
134
135 SIGNAL message_simu : STRING(1 TO 15) := "---------------";
136
137 BEGIN
138
139 -----------------------------------------------------------------------------
140 -- TB
141 -----------------------------------------------------------------------------
142 PROCESS
143 CONSTANT txp : TIME := 320 ns;
144 BEGIN -- PROCESS
145 TXD1 <= '1';
146 reset <= '0';
147 WAIT FOR 500 ns;
148 reset <= '1';
149 WAIT FOR 10000 ns;
150 message_simu <= "0 - UART init ";
151 UART_INIT(TXD1,txp);
152
153 message_simu <= "1 - UART test ";
154 UART_WRITE(TXD1,txp,ADDR_BASE_GPIO & "000010",X"0000FFFF");
155 UART_WRITE(TXD1,txp,ADDR_BASE_GPIO & "000001",X"00000A0A");
156 UART_WRITE(TXD1,txp,ADDR_BASE_GPIO & "000001",X"00000B0B");
157
158 -- UNSET the LFR reset
159 message_simu <= "2 - LFR UNRESET";
160 UART_WRITE(TXD1,txp,ADDR_BASE_TIME_MANAGMENT & ADDR_LFR_TM_CONTROL , X"00000000");
161 UART_WRITE(TXD1,txp,ADDR_BASE_TIME_MANAGMENT & ADDR_LFR_TM_TIME_LOAD , X"00000000");
162 --
163 message_simu <= "3 - LFR CONFIG ";
164 UART_WRITE(TXD1,txp,ADDR_BASE_LFR & ADDR_LFR_SM_F0_0_ADDR , X"00000B0B");
165
166 WAIT;
167 END PROCESS;
168
169 -----------------------------------------------------------------------------
170 -- CLOCK
171 -----------------------------------------------------------------------------
172 clk_50 <= NOT clk_50 AFTER 5 ns;
173 clk_49 <= NOT clk_49 AFTER 10172 ps;
174
175 -----------------------------------------------------------------------------
176 -- DON'T CARE
177 -----------------------------------------------------------------------------
178 BP0 <= '0';
179 BP1 <= '0';
180 nRTS1 <= '0' ;
181
182 TXD2 <= '1';
183 nRTS2 <= '1';
184 nDTR2 <= '1';
185
186 SPW_NOM_DIN <= '1';
187 SPW_NOM_SIN <= '1';
188 SPW_RED_DIN <= '1';
189 SPW_RED_SIN <= '1';
190
191 ADC_SDO <= x"AA";
192
193 SRAM_DQ <= (OTHERS => 'Z');
194 IO0 <= 'Z';
195 IO1 <= 'Z';
196 IO2 <= 'Z';
197 IO3 <= 'Z';
198 IO4 <= 'Z';
199 IO5 <= 'Z';
200 IO6 <= 'Z';
201 IO7 <= 'Z';
202 IO8 <= 'Z';
203 IO9 <= 'Z';
204 IO10 <= 'Z';
205 IO11 <= 'Z';
206
207 -----------------------------------------------------------------------------
208 -- DUT
209 -----------------------------------------------------------------------------
210 MINI_LFR_top_1: MINI_LFR_top
211 PORT MAP (
212 clk_50 => clk_50,
213 clk_49 => clk_49,
214 reset => reset,
215
216 BP0 => BP0,
217 BP1 => BP1,
218
219 LED0 => LED0,
220 LED1 => LED1,
221 LED2 => LED2,
222
223 TXD1 => TXD1,
224 RXD1 => RXD1,
225 nCTS1 => nCTS1,
226 nRTS1 => nRTS1,
227
228 TXD2 => TXD2,
229 RXD2 => RXD2,
230 nCTS2 => nCTS2,
231 nDTR2 => nDTR2,
232 nRTS2 => nRTS2,
233 nDCD2 => nDCD2,
234
235 IO0 => IO0,
236 IO1 => IO1,
237 IO2 => IO2,
238 IO3 => IO3,
239 IO4 => IO4,
240 IO5 => IO5,
241 IO6 => IO6,
242 IO7 => IO7,
243 IO8 => IO8,
244 IO9 => IO9,
245 IO10 => IO10,
246 IO11 => IO11,
247
248 SPW_EN => SPW_EN,
249 SPW_NOM_DIN => SPW_NOM_DIN,
250 SPW_NOM_SIN => SPW_NOM_SIN,
251 SPW_NOM_DOUT => SPW_NOM_DOUT,
252 SPW_NOM_SOUT => SPW_NOM_SOUT,
253 SPW_RED_DIN => SPW_RED_DIN,
254 SPW_RED_SIN => SPW_RED_SIN,
255 SPW_RED_DOUT => SPW_RED_DOUT,
256 SPW_RED_SOUT => SPW_RED_SOUT,
257
258 ADC_nCS => ADC_nCS,
259 ADC_CLK => ADC_CLK,
260 ADC_SDO => ADC_SDO,
261
262 SRAM_nWE => SRAM_nWE,
263 SRAM_CE => SRAM_CE,
264 SRAM_nOE => SRAM_nOE,
265 SRAM_nBE => SRAM_nBE,
266 SRAM_A => SRAM_A,
267 SRAM_DQ => SRAM_DQ);
268
269
270 END;
1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
3 USE ieee.numeric_std.ALL;
4 use IEEE.std_logic_textio.all;
5 LIBRARY STD;
6 use std.textio.all;
7
8 LIBRARY grlib;
9 USE grlib.stdlib.ALL;
10 LIBRARY gaisler;
11 USE gaisler.libdcom.ALL;
12 USE gaisler.sim.ALL;
13 USE gaisler.jtagtst.ALL;
14 LIBRARY techmap;
15 USE techmap.gencomp.ALL;
16
17 LIBRARY lpp;
18 USE lpp.lpp_sim_pkg.ALL;
19 USE lpp.lpp_lfr_apbreg_pkg.ALL;
20 USE lpp.lpp_lfr_time_management_apbreg_pkg.ALL;
21
22 LIBRARY postlayout;
23 USE postlayout.ALL;
24
25 ENTITY testbench IS
26 END;
27
28 ARCHITECTURE behav OF testbench IS
29
30 COMPONENT MINI_LFR_top
31 PORT (
32 clk_50 : IN STD_LOGIC;
33 clk_49 : IN STD_LOGIC;
34 reset : IN STD_LOGIC;
35 BP0 : IN STD_LOGIC;
36 BP1 : IN STD_LOGIC;
37 LED0 : OUT STD_LOGIC;
38 LED1 : OUT STD_LOGIC;
39 LED2 : OUT STD_LOGIC;
40 TXD1 : IN STD_LOGIC;
41 RXD1 : OUT STD_LOGIC;
42 nCTS1 : OUT STD_LOGIC;
43 nRTS1 : IN STD_LOGIC;
44 TXD2 : IN STD_LOGIC;
45 RXD2 : OUT STD_LOGIC;
46 nCTS2 : OUT STD_LOGIC;
47 nDTR2 : IN STD_LOGIC;
48 nRTS2 : IN STD_LOGIC;
49 nDCD2 : OUT STD_LOGIC;
50 IO0 : INOUT STD_LOGIC;
51 IO1 : INOUT STD_LOGIC;
52 IO2 : INOUT STD_LOGIC;
53 IO3 : INOUT STD_LOGIC;
54 IO4 : INOUT STD_LOGIC;
55 IO5 : INOUT STD_LOGIC;
56 IO6 : INOUT STD_LOGIC;
57 IO7 : INOUT STD_LOGIC;
58 IO8 : INOUT STD_LOGIC;
59 IO9 : INOUT STD_LOGIC;
60 IO10 : INOUT STD_LOGIC;
61 IO11 : INOUT STD_LOGIC;
62 SPW_EN : OUT STD_LOGIC;
63 SPW_NOM_DIN : IN STD_LOGIC;
64 SPW_NOM_SIN : IN STD_LOGIC;
65 SPW_NOM_DOUT : OUT STD_LOGIC;
66 SPW_NOM_SOUT : OUT STD_LOGIC;
67 SPW_RED_DIN : IN STD_LOGIC;
68 SPW_RED_SIN : IN STD_LOGIC;
69 SPW_RED_DOUT : OUT STD_LOGIC;
70 SPW_RED_SOUT : OUT STD_LOGIC;
71 ADC_nCS : OUT STD_LOGIC;
72 ADC_CLK : OUT STD_LOGIC;
73 ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
74 SRAM_nWE : OUT STD_LOGIC;
75 SRAM_CE : OUT STD_LOGIC;
76 SRAM_nOE : OUT STD_LOGIC;
77 SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
78 SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
79 SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0));
80 END COMPONENT;
81
82 -----------------------------------------------------------------------------
83 SIGNAL clk_50 : STD_LOGIC := '0';
84 SIGNAL clk_49 : STD_LOGIC := '0';
85 SIGNAL reset : STD_LOGIC;
86 SIGNAL BP0 : STD_LOGIC;
87 SIGNAL BP1 : STD_LOGIC;
88 SIGNAL LED0 : STD_LOGIC;
89 SIGNAL LED1 : STD_LOGIC;
90 SIGNAL LED2 : STD_LOGIC;
91 SIGNAL TXD1 : STD_LOGIC;
92 SIGNAL RXD1 : STD_LOGIC;
93 SIGNAL nCTS1 : STD_LOGIC;
94 SIGNAL nRTS1 : STD_LOGIC;
95 SIGNAL TXD2 : STD_LOGIC;
96 SIGNAL RXD2 : STD_LOGIC;
97 SIGNAL nCTS2 : STD_LOGIC;
98 SIGNAL nDTR2 : STD_LOGIC;
99 SIGNAL nRTS2 : STD_LOGIC;
100 SIGNAL nDCD2 : STD_LOGIC;
101 SIGNAL IO0 : STD_LOGIC;
102 SIGNAL IO1 : STD_LOGIC;
103 SIGNAL IO2 : STD_LOGIC;
104 SIGNAL IO3 : STD_LOGIC;
105 SIGNAL IO4 : STD_LOGIC;
106 SIGNAL IO5 : STD_LOGIC;
107 SIGNAL IO6 : STD_LOGIC;
108 SIGNAL IO7 : STD_LOGIC;
109 SIGNAL IO8 : STD_LOGIC;
110 SIGNAL IO9 : STD_LOGIC;
111 SIGNAL IO10 : STD_LOGIC;
112 SIGNAL IO11 : STD_LOGIC;
113 SIGNAL SPW_EN : STD_LOGIC;
114 SIGNAL SPW_NOM_DIN : STD_LOGIC;
115 SIGNAL SPW_NOM_SIN : STD_LOGIC;
116 SIGNAL SPW_NOM_DOUT : STD_LOGIC;
117 SIGNAL SPW_NOM_SOUT : STD_LOGIC;
118 SIGNAL SPW_RED_DIN : STD_LOGIC;
119 SIGNAL SPW_RED_SIN : STD_LOGIC;
120 SIGNAL SPW_RED_DOUT : STD_LOGIC;
121 SIGNAL SPW_RED_SOUT : STD_LOGIC;
122 SIGNAL ADC_nCS : STD_LOGIC;
123 SIGNAL ADC_CLK : STD_LOGIC;
124 SIGNAL ADC_SDO : STD_LOGIC_VECTOR(7 DOWNTO 0);
125 SIGNAL SRAM_nWE : STD_LOGIC;
126 SIGNAL SRAM_CE : STD_LOGIC;
127 SIGNAL SRAM_nOE : STD_LOGIC;
128 SIGNAL SRAM_nBE : STD_LOGIC_VECTOR(3 DOWNTO 0);
129 SIGNAL SRAM_A : STD_LOGIC_VECTOR(19 DOWNTO 0);
130 SIGNAL SRAM_DQ : STD_LOGIC_VECTOR(31 DOWNTO 0);
131 -----------------------------------------------------------------------------
132
133 CONSTANT ADDR_BASE_LFR : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"80000F";
134 CONSTANT ADDR_BASE_TIME_MANAGMENT : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"800006";
135 CONSTANT ADDR_BASE_GPIO : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"80000B";
136
137
138 SIGNAL message_simu : STRING(1 TO 15) := "---------------";
139
140 BEGIN
141
142 -----------------------------------------------------------------------------
143 -- TB
144 -----------------------------------------------------------------------------
145 PROCESS
146 CONSTANT txp : TIME := 320 ns;
147 BEGIN -- PROCESS
148 TXD1 <= '1';
149 reset <= '0';
150 WAIT FOR 500 ns;
151 reset <= '1';
152 WAIT FOR 10000 ns;
153 message_simu <= "0 - UART init ";
154 UART_INIT(TXD1,txp);
155
156 message_simu <= "1 - UART test ";
157 UART_WRITE(TXD1,txp,ADDR_BASE_GPIO & "000010",X"0000FFFF");
158 UART_WRITE(TXD1,txp,ADDR_BASE_GPIO & "000001",X"00000A0A");
159 UART_WRITE(TXD1,txp,ADDR_BASE_GPIO & "000001",X"00000B0B");
160
161 -- UNSET the LFR reset
162 message_simu <= "2 - LFR UNRESET";
163 UART_WRITE(TXD1,txp,ADDR_BASE_TIME_MANAGMENT & ADDR_LFR_TM_CONTROL , X"00000000");
164 UART_WRITE(TXD1,txp,ADDR_BASE_TIME_MANAGMENT & ADDR_LFR_TM_TIME_LOAD , X"00000000");
165 --
166 message_simu <= "3 - LFR CONFIG ";
167 UART_WRITE(TXD1,txp,ADDR_BASE_LFR & ADDR_LFR_SM_F0_0_ADDR , X"00000B0B");
168
169 WAIT;
170 END PROCESS;
171
172 -----------------------------------------------------------------------------
173 -- CLOCK
174 -----------------------------------------------------------------------------
175 clk_50 <= NOT clk_50 AFTER 5 ns;
176 clk_49 <= NOT clk_49 AFTER 10172 ps;
177
178 -----------------------------------------------------------------------------
179 -- DON'T CARE
180 -----------------------------------------------------------------------------
181 BP0 <= '0';
182 BP1 <= '0';
183 nRTS1 <= '0' ;
184
185 TXD2 <= '1';
186 nRTS2 <= '1';
187 nDTR2 <= '1';
188
189 SPW_NOM_DIN <= '1';
190 SPW_NOM_SIN <= '1';
191 SPW_RED_DIN <= '1';
192 SPW_RED_SIN <= '1';
193
194 ADC_SDO <= x"AA";
195
196 SRAM_DQ <= (OTHERS => 'Z');
197 IO0 <= 'Z';
198 IO1 <= 'Z';
199 IO2 <= 'Z';
200 IO3 <= 'Z';
201 IO4 <= 'Z';
202 IO5 <= 'Z';
203 IO6 <= 'Z';
204 IO7 <= 'Z';
205 IO8 <= 'Z';
206 IO9 <= 'Z';
207 IO10 <= 'Z';
208 IO11 <= 'Z';
209
210 -----------------------------------------------------------------------------
211 -- DUT
212 -----------------------------------------------------------------------------
213 MINI_LFR_top_1: MINI_LFR_top
214 PORT MAP (
215 clk_50 => clk_50,
216 clk_49 => clk_49,
217 reset => reset,
218
219 BP0 => BP0,
220 BP1 => BP1,
221
222 LED0 => LED0,
223 LED1 => LED1,
224 LED2 => LED2,
225
226 TXD1 => TXD1,
227 RXD1 => RXD1,
228 nCTS1 => nCTS1,
229 nRTS1 => nRTS1,
230
231 TXD2 => TXD2,
232 RXD2 => RXD2,
233 nCTS2 => nCTS2,
234 nDTR2 => nDTR2,
235 nRTS2 => nRTS2,
236 nDCD2 => nDCD2,
237
238 IO0 => IO0,
239 IO1 => IO1,
240 IO2 => IO2,
241 IO3 => IO3,
242 IO4 => IO4,
243 IO5 => IO5,
244 IO6 => IO6,
245 IO7 => IO7,
246 IO8 => IO8,
247 IO9 => IO9,
248 IO10 => IO10,
249 IO11 => IO11,
250
251 SPW_EN => SPW_EN,
252 SPW_NOM_DIN => SPW_NOM_DIN,
253 SPW_NOM_SIN => SPW_NOM_SIN,
254 SPW_NOM_DOUT => SPW_NOM_DOUT,
255 SPW_NOM_SOUT => SPW_NOM_SOUT,
256 SPW_RED_DIN => SPW_RED_DIN,
257 SPW_RED_SIN => SPW_RED_SIN,
258 SPW_RED_DOUT => SPW_RED_DOUT,
259 SPW_RED_SOUT => SPW_RED_SOUT,
260
261 ADC_nCS => ADC_nCS,
262 ADC_CLK => ADC_CLK,
263 ADC_SDO => ADC_SDO,
264
265 SRAM_nWE => SRAM_nWE,
266 SRAM_CE => SRAM_CE,
267 SRAM_nOE => SRAM_nOE,
268 SRAM_nBE => SRAM_nBE,
269 SRAM_A => SRAM_A,
270 SRAM_DQ => SRAM_DQ);
271
272
273 END;
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@@ -73,19 +73,19 ARCHITECTURE ar_MAC OF MAC IS
73 73
74 74 SIGNAL MACMUX2sel : STD_LOGIC;
75 75
76 SIGNAL add_D : STD_LOGIC;
77 SIGNAL OP1_2C_D : STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
78 SIGNAL OP2_2C_D : STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
79 SIGNAL MULTout_D : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0);
80 SIGNAL MACMUXsel_D : STD_LOGIC;
81 SIGNAL MACMUX2sel_D : STD_LOGIC;
82 SIGNAL MACMUX2sel_D_D : STD_LOGIC;
83 SIGNAL clr_MAC_D : STD_LOGIC;
76 SIGNAL add_D : STD_LOGIC;
77 SIGNAL OP1_2C_D : STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
78 SIGNAL OP2_2C_D : STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
79 SIGNAL MULTout_D : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0);
80 SIGNAL MACMUXsel_D : STD_LOGIC;
81 SIGNAL MACMUX2sel_D : STD_LOGIC;
82 SIGNAL MACMUX2sel_D_D : STD_LOGIC;
83 SIGNAL clr_MAC_D : STD_LOGIC;
84 84 -- SIGNAL clr_MAC_D_D : STD_LOGIC;
85 85 -- SIGNAL MAC_MUL_ADD_2C_D : STD_LOGIC_VECTOR(1 DOWNTO 0);
86 86
87 SIGNAL load_mult_result : STD_LOGIC;
88 SIGNAL load_mult_result_D : STD_LOGIC;
87 -- SIGNAL load_mult_result : STD_LOGIC;
88 -- SIGNAL load_mult_result_D : STD_LOGIC;
89 89
90 90 BEGIN
91 91
@@ -100,7 +100,7 BEGIN
100 100 ctrl => MAC_MUL_ADD_s,
101 101 MULT => mult,
102 102 ADD => add,
103 LOAD_ADDER => load_mult_result,
103 --LOAD_ADDER => load_mult_result,
104 104 MACMUX_sel => MACMUXsel,
105 105 MACMUX2_sel => MACMUX2sel
106 106
@@ -128,14 +128,14 BEGIN
128 128 );
129 129 --==============================================================
130 130
131 PROCESS (clk, reset)
132 BEGIN -- PROCESS
133 IF reset = '0' THEN -- asynchronous reset (active low)
134 load_mult_result_D <= '0';
135 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
136 load_mult_result_D <= load_mult_result;
137 END IF;
138 END PROCESS;
131 --PROCESS (clk, reset)
132 --BEGIN -- PROCESS
133 -- IF reset = '0' THEN -- asynchronous reset (active low)
134 -- load_mult_result_D <= '0';
135 -- ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
136 -- load_mult_result_D <= load_mult_result;
137 -- END IF;
138 --END PROCESS;
139 139
140 140 --==============================================================
141 141 --======================A D D E R ==============================
@@ -149,7 +149,7 BEGIN
149 149 clk => clk,
150 150 reset => reset,
151 151 clr => clr_MAC_D,
152 load => load_mult_result_D,
152 load => MACMUX2sel_D, --load_mult_result_D,
153 153 add => add_D,
154 154 OP1 => ADDERinA,
155 155 OP2 => ADDERinB,
@@ -167,7 +167,7 BEGIN
167 167 PORT MAP(
168 168 clk => clk,
169 169 reset => reset,
170 clr => '0',--clr_MAC,
170 clr => '0', --clr_MAC,
171 171 TwoComp => Comp_2C(0),
172 172 OP => OP1,
173 173 RES => OP1_2C
@@ -180,13 +180,12 BEGIN
180 180 PORT MAP(
181 181 clk => clk,
182 182 reset => reset,
183 clr => '0',--clr_MAC,
183 clr => '0', --clr_MAC,
184 184 TwoComp => Comp_2C(1),
185 185 OP => OP2,
186 186 RES => OP2_2C
187 187 );
188
189
188
190 189 clr_MACREG_comp : MAC_REG
191 190 GENERIC MAP(size => 1)
192 191 PORT MAP(
@@ -195,18 +194,18 BEGIN
195 194 D(0) => clr_MAC,
196 195 Q(0) => clr_MAC_s
197 196 );
198
197
199 198 MAC_MUL_ADD_REG : MAC_REG
200 GENERIC MAP(size => 2)
201 PORT MAP(
202 reset => reset,
203 clk => clk,
204 D => MAC_MUL_ADD,
205 Q => MAC_MUL_ADD_s
206 );
207
199 GENERIC MAP(size => 2)
200 PORT MAP(
201 reset => reset,
202 clk => clk,
203 D => MAC_MUL_ADD,
204 Q => MAC_MUL_ADD_s
205 );
206
208 207 END GENERATE gen_comp;
209
208
210 209 no_gen_comp : IF COMP_EN = 1 GENERATE
211 210 OP2_2C <= OP2;
212 211 OP1_2C <= OP1;
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@@ -31,7 +31,7 port(
31 31 ctrl : in std_logic_vector(1 downto 0);
32 32 MULT : out std_logic;
33 33 ADD : out std_logic;
34 LOAD_ADDER : out std_logic;
34 -- LOAD_ADDER : out std_logic;
35 35 MACMUX_sel : out std_logic;
36 36 MACMUX2_sel : out std_logic
37 37
@@ -50,9 +50,9 begin
50 50
51 51 MULT <= '0' when (ctrl = "00" or ctrl = "11") else '1';
52 52 ADD <= '0' when (ctrl = "00" or ctrl = "10") else '1';
53 LOAD_ADDER <= '1' when (ctrl = "10") else '0'; -- PATCH JC : mem mult result
54 -- to permit to compute a
55 -- MULT follow by a MAC
53 --LOAD_ADDER <= '1' when ( ctrl = "10") else '0'; -- PATCH JC : mem mult result
54 -- to permit to compute a
55 -- MULT follow by a MAC
56 56 --MACMUX_sel <= '0' when (ctrl = "00" or ctrl = "01") else '1';
57 57 MACMUX_sel <= '0' when (ctrl = "00" or ctrl = "01" OR ctrl = "10") else '1';
58 58 MACMUX2_sel <= '0' when (ctrl = "00" or ctrl = "01" or ctrl = "11") else '1';
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@@ -217,7 +217,7 Constant CLR_MAC_V0 : std_logic_vector(3
217 217 ctrl : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
218 218 MULT : OUT STD_LOGIC;
219 219 ADD : OUT STD_LOGIC;
220 LOAD_ADDER : out std_logic;
220 -- LOAD_ADDER : out std_logic;
221 221 MACMUX_sel : OUT STD_LOGIC;
222 222 MACMUX2_sel : OUT STD_LOGIC
223 223 );
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@@ -57,7 +57,7 ARCHITECTURE ar_ADS7886_drvr_v2 OF ADS78
57 57 SIGNAL cnv_sync_r : STD_LOGIC;
58 58 SIGNAL cnv_done : STD_LOGIC;
59 59 SIGNAL sample_bit_counter : INTEGER;
60 SIGNAL shift_reg : Samples(ChannelCount-1 DOWNTO 0);
60 SIGNAL shift_reg : Samples_15(ChannelCount-1 DOWNTO 0);
61 61
62 62 BEGIN
63 63
@@ -82,8 +82,8 cnv_sync <= cnv_clk;
82 82 BEGIN -- PROCESS
83 83 IF rstn = '0' THEN
84 84 FOR k IN 0 TO ChannelCount-1 LOOP
85 shift_reg(k)(15 downto 0) <= (OTHERS => '0');
86 sample(k)(15 downto 0) <= (OTHERS => '0');
85 shift_reg(k)(14 downto 0) <= (OTHERS => '0');
86 sample(k)(15 downto 0) <= (OTHERS => '0');
87 87 END LOOP;
88 88 sample_bit_counter <= 0;
89 89 sample_val <= '0';
@@ -107,7 +107,7 cnv_sync <= cnv_clk;
107 107 IF (sample_bit_counter MOD 2) = 1 THEN -- get data on each channel
108 108 FOR k IN 0 TO ChannelCount-1 LOOP
109 109 shift_reg(k)(0) <= sdo(k);
110 shift_reg(k)(15 DOWNTO 1) <= shift_reg(k)(14 DOWNTO 0);
110 shift_reg(k)(14 DOWNTO 1) <= shift_reg(k)(13 DOWNTO 0);
111 111 END LOOP;
112 112 SCK <= '0';
113 113 ELSE
@@ -116,4 +116,4 cnv_sync <= cnv_clk;
116 116 END IF;
117 117 END PROCESS;
118 118
119 END ar_ADS7886_drvr_v2; No newline at end of file
119 END ar_ADS7886_drvr_v2;
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@@ -47,7 +47,8 PACKAGE lpp_ad_conv IS
47 47
48 48 --TYPE AD7688_in IS ARRAY(NATURAL RANGE <>) OF AD7688_in_element;
49 49
50 TYPE Samples IS ARRAY(NATURAL RANGE <>) OF STD_LOGIC_VECTOR(15 DOWNTO 0);
50 TYPE Samples IS ARRAY(NATURAL RANGE <>) OF STD_LOGIC_VECTOR(15 DOWNTO 0);
51 TYPE Samples_15 IS ARRAY(NATURAL RANGE <>) OF STD_LOGIC_VECTOR(14 DOWNTO 0);
51 52
52 53 SUBTYPE Samples24 IS STD_LOGIC_VECTOR(23 DOWNTO 0);
53 54
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@@ -91,11 +91,11 ARCHITECTURE beh OF lpp_lfr IS
91 91
92 92 -- SM
93 93 SIGNAL ready_matrix_f0 : STD_LOGIC;
94 SIGNAL ready_matrix_f0_1 : STD_LOGIC;
94 -- SIGNAL ready_matrix_f0_1 : STD_LOGIC;
95 95 SIGNAL ready_matrix_f1 : STD_LOGIC;
96 96 SIGNAL ready_matrix_f2 : STD_LOGIC;
97 97 SIGNAL status_ready_matrix_f0 : STD_LOGIC;
98 SIGNAL status_ready_matrix_f0_1 : STD_LOGIC;
98 -- SIGNAL status_ready_matrix_f0_1 : STD_LOGIC;
99 99 SIGNAL status_ready_matrix_f1 : STD_LOGIC;
100 100 SIGNAL status_ready_matrix_f2 : STD_LOGIC;
101 101 SIGNAL addr_matrix_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
@@ -129,24 +129,24 ARCHITECTURE beh OF lpp_lfr IS
129 129 -----------------------------------------------------------------------------
130 130 --
131 131 -----------------------------------------------------------------------------
132 SIGNAL data_f0_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
133 SIGNAL data_f0_data_out_valid_s : STD_LOGIC;
134 SIGNAL data_f0_data_out_valid_burst_s : STD_LOGIC;
132 -- SIGNAL data_f0_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
133 -- SIGNAL data_f0_data_out_valid_s : STD_LOGIC;
134 -- SIGNAL data_f0_data_out_valid_burst_s : STD_LOGIC;
135 135 --f1
136 SIGNAL data_f1_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
137 SIGNAL data_f1_data_out_valid_s : STD_LOGIC;
138 SIGNAL data_f1_data_out_valid_burst_s : STD_LOGIC;
136 -- SIGNAL data_f1_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
137 -- SIGNAL data_f1_data_out_valid_s : STD_LOGIC;
138 -- SIGNAL data_f1_data_out_valid_burst_s : STD_LOGIC;
139 139 --f2
140 SIGNAL data_f2_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
141 SIGNAL data_f2_data_out_valid_s : STD_LOGIC;
142 SIGNAL data_f2_data_out_valid_burst_s : STD_LOGIC;
140 -- SIGNAL data_f2_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
141 -- SIGNAL data_f2_data_out_valid_s : STD_LOGIC;
142 -- SIGNAL data_f2_data_out_valid_burst_s : STD_LOGIC;
143 143 --f3
144 SIGNAL data_f3_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
145 SIGNAL data_f3_data_out_valid_s : STD_LOGIC;
146 SIGNAL data_f3_data_out_valid_burst_s : STD_LOGIC;
144 -- SIGNAL data_f3_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
145 -- SIGNAL data_f3_data_out_valid_s : STD_LOGIC;
146 -- SIGNAL data_f3_data_out_valid_burst_s : STD_LOGIC;
147 147
148 148 SIGNAL wfp_status_buffer_ready : STD_LOGIC_VECTOR(3 DOWNTO 0);
149 SIGNAL wfp_addr_buffer : STD_LOGIC_VECTOR(32*4 DOWNTO 0);
149 SIGNAL wfp_addr_buffer : STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
150 150 SIGNAL wfp_length_buffer : STD_LOGIC_VECTOR(25 DOWNTO 0);
151 151 SIGNAL wfp_ready_buffer : STD_LOGIC_VECTOR(3 DOWNTO 0);
152 152 SIGNAL wfp_buffer_time : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
@@ -154,51 +154,51 ARCHITECTURE beh OF lpp_lfr IS
154 154 -----------------------------------------------------------------------------
155 155 -- DMA RR
156 156 -----------------------------------------------------------------------------
157 SIGNAL dma_sel_valid : STD_LOGIC;
158 SIGNAL dma_rr_valid : STD_LOGIC_VECTOR(3 DOWNTO 0);
159 SIGNAL dma_rr_grant_s : STD_LOGIC_VECTOR(3 DOWNTO 0);
160 SIGNAL dma_rr_grant_ms : STD_LOGIC_VECTOR(3 DOWNTO 0);
161 SIGNAL dma_rr_valid_ms : STD_LOGIC_VECTOR(3 DOWNTO 0);
157 -- SIGNAL dma_sel_valid : STD_LOGIC;
158 -- SIGNAL dma_rr_valid : STD_LOGIC_VECTOR(3 DOWNTO 0);
159 -- SIGNAL dma_rr_grant_s : STD_LOGIC_VECTOR(3 DOWNTO 0);
160 -- SIGNAL dma_rr_grant_ms : STD_LOGIC_VECTOR(3 DOWNTO 0);
161 -- SIGNAL dma_rr_valid_ms : STD_LOGIC_VECTOR(3 DOWNTO 0);
162 162
163 SIGNAL dma_rr_grant : STD_LOGIC_VECTOR(4 DOWNTO 0);
164 SIGNAL dma_sel : STD_LOGIC_VECTOR(4 DOWNTO 0);
163 -- SIGNAL dma_rr_grant : STD_LOGIC_VECTOR(4 DOWNTO 0);
164 -- SIGNAL dma_sel : STD_LOGIC_VECTOR(4 DOWNTO 0);
165 165
166 166 -----------------------------------------------------------------------------
167 167 -- DMA_REG
168 168 -----------------------------------------------------------------------------
169 SIGNAL ongoing_reg : STD_LOGIC;
170 SIGNAL dma_sel_reg : STD_LOGIC_VECTOR(3 DOWNTO 0);
171 SIGNAL dma_send_reg : STD_LOGIC;
172 SIGNAL dma_valid_burst_reg : STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
173 SIGNAL dma_address_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
174 SIGNAL dma_data_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
169 -- SIGNAL ongoing_reg : STD_LOGIC;
170 -- SIGNAL dma_sel_reg : STD_LOGIC_VECTOR(3 DOWNTO 0);
171 -- SIGNAL dma_send_reg : STD_LOGIC;
172 -- SIGNAL dma_valid_burst_reg : STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
173 -- SIGNAL dma_address_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
174 -- SIGNAL dma_data_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
175 175
176 176
177 177 -----------------------------------------------------------------------------
178 178 -- DMA
179 179 -----------------------------------------------------------------------------
180 SIGNAL dma_send : STD_LOGIC;
181 SIGNAL dma_valid_burst : STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
182 SIGNAL dma_done : STD_LOGIC;
183 SIGNAL dma_ren : STD_LOGIC;
184 SIGNAL dma_address : STD_LOGIC_VECTOR(31 DOWNTO 0);
185 SIGNAL dma_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
186 SIGNAL dma_data_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
180 -- SIGNAL dma_send : STD_LOGIC;
181 -- SIGNAL dma_valid_burst : STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
182 -- SIGNAL dma_done : STD_LOGIC;
183 -- SIGNAL dma_ren : STD_LOGIC;
184 -- SIGNAL dma_address : STD_LOGIC_VECTOR(31 DOWNTO 0);
185 -- SIGNAL dma_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
186 -- SIGNAL dma_data_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
187 187
188 188 -----------------------------------------------------------------------------
189 189 -- MS
190 190 -----------------------------------------------------------------------------
191 191
192 SIGNAL data_ms_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
193 SIGNAL data_ms_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
194 SIGNAL data_ms_valid : STD_LOGIC;
195 SIGNAL data_ms_valid_burst : STD_LOGIC;
196 SIGNAL data_ms_ren : STD_LOGIC;
197 SIGNAL data_ms_done : STD_LOGIC;
198 SIGNAL dma_ms_ongoing : STD_LOGIC;
192 -- SIGNAL data_ms_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
193 -- SIGNAL data_ms_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
194 -- SIGNAL data_ms_valid : STD_LOGIC;
195 -- SIGNAL data_ms_valid_burst : STD_LOGIC;
196 -- SIGNAL data_ms_ren : STD_LOGIC;
197 -- SIGNAL data_ms_done : STD_LOGIC;
198 -- SIGNAL dma_ms_ongoing : STD_LOGIC;
199 199
200 200 -- SIGNAL run_ms : STD_LOGIC;
201 SIGNAL ms_softandhard_rstn : STD_LOGIC;
201 -- SIGNAL ms_softandhard_rstn : STD_LOGIC;
202 202
203 203 SIGNAL matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
204 204 -- SIGNAL matrix_time_f0_1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
@@ -210,7 +210,7 ARCHITECTURE beh OF lpp_lfr IS
210 210 SIGNAL error_input_fifo_write : STD_LOGIC_VECTOR(2 DOWNTO 0);
211 211
212 212 -- SIGNAL debug_ms : STD_LOGIC_VECTOR(31 DOWNTO 0);
213 SIGNAL debug_signal : STD_LOGIC_VECTOR(31 DOWNTO 0);
213 -- SIGNAL debug_signal : STD_LOGIC_VECTOR(31 DOWNTO 0);
214 214
215 215 -----------------------------------------------------------------------------
216 216 SIGNAL dma_fifo_burst_valid : STD_LOGIC_VECTOR(4 DOWNTO 0);
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@@ -133,7 +133,7 ENTITY lpp_lfr_apbreg IS
133 133 start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0);
134 134
135 135 wfp_status_buffer_ready : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
136 wfp_addr_buffer : OUT STD_LOGIC_VECTOR(32*4 DOWNTO 0);
136 wfp_addr_buffer : OUT STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
137 137 wfp_length_buffer : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
138 138 wfp_ready_buffer : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
139 139 wfp_buffer_time : IN STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
@@ -238,28 +238,28 ARCHITECTURE beh OF lpp_lfr_apbreg IS
238 238 --
239 239 -----------------------------------------------------------------------------
240 240 SIGNAL reg0_ready_matrix_f0 : STD_LOGIC;
241 SIGNAL reg0_addr_matrix_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
242 SIGNAL reg0_matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
241 -- SIGNAL reg0_addr_matrix_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
242 -- SIGNAL reg0_matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
243 243
244 244 SIGNAL reg1_ready_matrix_f0 : STD_LOGIC;
245 SIGNAL reg1_addr_matrix_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
246 SIGNAL reg1_matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
245 -- SIGNAL reg1_addr_matrix_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
246 -- SIGNAL reg1_matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
247 247
248 248 SIGNAL reg0_ready_matrix_f1 : STD_LOGIC;
249 SIGNAL reg0_addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
250 SIGNAL reg0_matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
249 -- SIGNAL reg0_addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
250 -- SIGNAL reg0_matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
251 251
252 252 SIGNAL reg1_ready_matrix_f1 : STD_LOGIC;
253 SIGNAL reg1_addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
254 SIGNAL reg1_matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
253 -- SIGNAL reg1_addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
254 -- SIGNAL reg1_matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
255 255
256 256 SIGNAL reg0_ready_matrix_f2 : STD_LOGIC;
257 SIGNAL reg0_addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
258 SIGNAL reg0_matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
257 -- SIGNAL reg0_addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
258 -- SIGNAL reg0_matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
259 259
260 260 SIGNAL reg1_ready_matrix_f2 : STD_LOGIC;
261 SIGNAL reg1_addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
262 SIGNAL reg1_matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
261 -- SIGNAL reg1_addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
262 -- SIGNAL reg1_matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
263 263 SIGNAL apbo_irq_ms : STD_LOGIC;
264 264 SIGNAL apbo_irq_wfp : STD_LOGIC;
265 265 -----------------------------------------------------------------------------
@@ -778,4 +778,4 BEGIN -- beh
778 778
779 779 END beh;
780 780
781 -------------------------------------------------------------------------------
781 ------------------------------------------------------------------------------- No newline at end of file
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@@ -121,8 +121,10 ARCHITECTURE Behavioral OF lpp_lfr_ms IS
121 121 -----------------------------------------------------------------------------
122 122 TYPE fsm_select_channel IS (IDLE, SWITCH_F0_A, SWITCH_F0_B, SWITCH_F1, SWITCH_F2);
123 123 SIGNAL state_fsm_select_channel : fsm_select_channel;
124 SIGNAL pre_state_fsm_select_channel : fsm_select_channel;
125
124 -- SIGNAL pre_state_fsm_select_channel : fsm_select_channel;
125 SIGNAL select_channel : STD_LOGIC_VECTOR(1 DOWNTO 0);
126 SIGNAL select_channel_reg : STD_LOGIC_VECTOR(1 DOWNTO 0);
127
126 128 SIGNAL sample_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
127 129 SIGNAL sample_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
128 130 SIGNAL sample_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
@@ -133,7 +135,9 ARCHITECTURE Behavioral OF lpp_lfr_ms IS
133 135 -----------------------------------------------------------------------------
134 136 TYPE fsm_load_FFT IS (IDLE, FIFO_1, FIFO_2, FIFO_3, FIFO_4, FIFO_5);
135 137 SIGNAL state_fsm_load_FFT : fsm_load_FFT;
136 SIGNAL next_state_fsm_load_FFT : fsm_load_FFT;
138 -- SIGNAL next_state_fsm_load_FFT : fsm_load_FFT;
139 SIGNAL select_fifo : STD_LOGIC_VECTOR(2 DOWNTO 0);
140 SIGNAL select_fifo_reg : STD_LOGIC_VECTOR(2 DOWNTO 0);
137 141
138 142 SIGNAL sample_ren_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
139 143 SIGNAL sample_load : STD_LOGIC;
@@ -199,7 +203,7 ARCHITECTURE Behavioral OF lpp_lfr_ms IS
199 203 SIGNAL FSM_DMA_fifo_empty : STD_LOGIC;
200 204 SIGNAL FSM_DMA_fifo_empty_threshold : STD_LOGIC;
201 205 SIGNAL FSM_DMA_fifo_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
202 SIGNAL FSM_DMA_fifo_status : STD_LOGIC_VECTOR(53 DOWNTO 0);
206 SIGNAL FSM_DMA_fifo_status : STD_LOGIC_VECTOR(53 DOWNTO 4);
203 207 -----------------------------------------------------------------------------
204 208 SIGNAL MEM_OUT_SM_Write : STD_LOGIC_VECTOR(1 DOWNTO 0);
205 209 SIGNAL MEM_OUT_SM_Read : STD_LOGIC_VECTOR(1 DOWNTO 0);
@@ -233,8 +237,8 ARCHITECTURE Behavioral OF lpp_lfr_ms IS
233 237 SIGNAL status_MS_input : STD_LOGIC_VECTOR(49 DOWNTO 0);
234 238 SIGNAL status_component : STD_LOGIC_VECTOR(53 DOWNTO 0);
235 239
236 SIGNAL status_component_fifo_0 : STD_LOGIC_VECTOR(53 DOWNTO 0);
237 SIGNAL status_component_fifo_1 : STD_LOGIC_VECTOR(53 DOWNTO 0);
240 SIGNAL status_component_fifo_0 : STD_LOGIC_VECTOR(53 DOWNTO 4);
241 SIGNAL status_component_fifo_1 : STD_LOGIC_VECTOR(53 DOWNTO 4);
238 242 SIGNAL status_component_fifo_0_end : STD_LOGIC;
239 243 SIGNAL status_component_fifo_1_end : STD_LOGIC;
240 244 -----------------------------------------------------------------------------
@@ -471,36 +475,45 BEGIN
471 475 BEGIN
472 476 IF rstn = '0' THEN
473 477 state_fsm_select_channel <= IDLE;
478 select_channel <= (OTHERS => '0');
474 479 ELSIF clk'EVENT AND clk = '1' THEN
475 480 CASE state_fsm_select_channel IS
476 481 WHEN IDLE =>
477 482 IF sample_f1_full = "11111" THEN
478 483 state_fsm_select_channel <= SWITCH_F1;
484 select_channel <= "10";
479 485 ELSIF sample_f1_almost_full = "00000" THEN
480 486 IF sample_f0_A_full = "11111" THEN
481 487 state_fsm_select_channel <= SWITCH_F0_A;
488 select_channel <= "00";
482 489 ELSIF sample_f0_B_full = "11111" THEN
483 490 state_fsm_select_channel <= SWITCH_F0_B;
491 select_channel <= "01";
484 492 ELSIF sample_f2_full = "11111" THEN
485 493 state_fsm_select_channel <= SWITCH_F2;
494 select_channel <= "11";
486 495 END IF;
487 496 END IF;
488 497
489 498 WHEN SWITCH_F0_A =>
490 499 IF sample_f0_A_empty = "11111" THEN
491 500 state_fsm_select_channel <= IDLE;
501 select_channel <= (OTHERS => '0');
492 502 END IF;
493 503 WHEN SWITCH_F0_B =>
494 504 IF sample_f0_B_empty = "11111" THEN
495 505 state_fsm_select_channel <= IDLE;
506 select_channel <= (OTHERS => '0');
496 507 END IF;
497 508 WHEN SWITCH_F1 =>
498 509 IF sample_f1_empty = "11111" THEN
499 510 state_fsm_select_channel <= IDLE;
511 select_channel <= (OTHERS => '0');
500 512 END IF;
501 513 WHEN SWITCH_F2 =>
502 514 IF sample_f2_empty = "11111" THEN
503 515 state_fsm_select_channel <= IDLE;
516 select_channel <= (OTHERS => '0');
504 517 END IF;
505 518 WHEN OTHERS => NULL;
506 519 END CASE;
@@ -511,9 +524,11 BEGIN
511 524 PROCESS (clk, rstn)
512 525 BEGIN
513 526 IF rstn = '0' THEN
514 pre_state_fsm_select_channel <= IDLE;
527 select_channel_reg <= (OTHERS => '0');
528 --pre_state_fsm_select_channel <= IDLE;
515 529 ELSIF clk'EVENT AND clk = '1' THEN
516 pre_state_fsm_select_channel <= state_fsm_select_channel;
530 select_channel_reg <= select_channel;
531 --pre_state_fsm_select_channel <= state_fsm_select_channel;
517 532 END IF;
518 533 END PROCESS;
519 534
@@ -533,9 +548,13 BEGIN
533 548 sample_f2_full WHEN state_fsm_select_channel = SWITCH_F2 ELSE
534 549 (OTHERS => '0');
535 550
536 sample_rdata <= sample_f0_A_rdata WHEN pre_state_fsm_select_channel = SWITCH_F0_A ELSE
537 sample_f0_B_rdata WHEN pre_state_fsm_select_channel = SWITCH_F0_B ELSE
538 sample_f1_rdata WHEN pre_state_fsm_select_channel = SWITCH_F1 ELSE
551 --sample_rdata <= sample_f0_A_rdata WHEN pre_state_fsm_select_channel = SWITCH_F0_A ELSE
552 -- sample_f0_B_rdata WHEN pre_state_fsm_select_channel = SWITCH_F0_B ELSE
553 -- sample_f1_rdata WHEN pre_state_fsm_select_channel = SWITCH_F1 ELSE
554 -- sample_f2_rdata; -- WHEN state_fsm_select_channel = SWITCH_F2 ELSE
555 sample_rdata <= sample_f0_A_rdata WHEN select_channel_reg = "00" ELSE
556 sample_f0_B_rdata WHEN select_channel_reg = "01" ELSE
557 sample_f1_rdata WHEN select_channel_reg = "10" ELSE
539 558 sample_f2_rdata; -- WHEN state_fsm_select_channel = SWITCH_F2 ELSE
540 559
541 560
@@ -564,6 +583,7 BEGIN
564 583 sample_ren_s <= (OTHERS => '1');
565 584 state_fsm_load_FFT <= IDLE;
566 585 status_MS_input <= (OTHERS => '0');
586 select_fifo <= "000";
567 587 --next_state_fsm_load_FFT <= IDLE;
568 588 --sample_valid <= '0';
569 589 ELSIF clk'EVENT AND clk = '1' THEN
@@ -574,6 +594,7 BEGIN
574 594 IF sample_full = "11111" AND sample_load = '1' THEN
575 595 state_fsm_load_FFT <= FIFO_1;
576 596 status_MS_input <= status_channel;
597 select_fifo <= "000";
577 598 END IF;
578 599
579 600 WHEN FIFO_1 =>
@@ -581,6 +602,7 BEGIN
581 602 IF sample_empty(0) = '1' THEN
582 603 sample_ren_s <= (OTHERS => '1');
583 604 state_fsm_load_FFT <= FIFO_2;
605 select_fifo <= "001";
584 606 END IF;
585 607
586 608 WHEN FIFO_2 =>
@@ -588,6 +610,7 BEGIN
588 610 IF sample_empty(1) = '1' THEN
589 611 sample_ren_s <= (OTHERS => '1');
590 612 state_fsm_load_FFT <= FIFO_3;
613 select_fifo <= "010";
591 614 END IF;
592 615
593 616 WHEN FIFO_3 =>
@@ -595,6 +618,7 BEGIN
595 618 IF sample_empty(2) = '1' THEN
596 619 sample_ren_s <= (OTHERS => '1');
597 620 state_fsm_load_FFT <= FIFO_4;
621 select_fifo <= "011";
598 622 END IF;
599 623
600 624 WHEN FIFO_4 =>
@@ -602,6 +626,7 BEGIN
602 626 IF sample_empty(3) = '1' THEN
603 627 sample_ren_s <= (OTHERS => '1');
604 628 state_fsm_load_FFT <= FIFO_5;
629 select_fifo <= "100";
605 630 END IF;
606 631
607 632 WHEN FIFO_5 =>
@@ -609,6 +634,7 BEGIN
609 634 IF sample_empty(4) = '1' THEN
610 635 sample_ren_s <= (OTHERS => '1');
611 636 state_fsm_load_FFT <= IDLE;
637 select_fifo <= "000";
612 638 END IF;
613 639 WHEN OTHERS => NULL;
614 640 END CASE;
@@ -619,9 +645,11 BEGIN
619 645 BEGIN
620 646 IF rstn = '0' THEN
621 647 sample_valid_r <= '0';
622 next_state_fsm_load_FFT <= IDLE;
648 select_fifo_reg <= (OTHERS => '0');
649 --next_state_fsm_load_FFT <= IDLE;
623 650 ELSIF clk'EVENT AND clk = '1' THEN
624 next_state_fsm_load_FFT <= state_fsm_load_FFT;
651 select_fifo_reg <= select_fifo;
652 --next_state_fsm_load_FFT <= state_fsm_load_FFT;
625 653 IF sample_ren_s = "11111" THEN
626 654 sample_valid_r <= '0';
627 655 ELSE
@@ -632,12 +660,17 BEGIN
632 660
633 661 sample_valid <= '0' WHEN fft_ongoing_counter = '1' ELSE sample_valid_r AND sample_load;
634 662
635 sample_data <= sample_rdata(16*1-1 DOWNTO 16*0) WHEN next_state_fsm_load_FFT = FIFO_1 ELSE
636 sample_rdata(16*2-1 DOWNTO 16*1) WHEN next_state_fsm_load_FFT = FIFO_2 ELSE
637 sample_rdata(16*3-1 DOWNTO 16*2) WHEN next_state_fsm_load_FFT = FIFO_3 ELSE
638 sample_rdata(16*4-1 DOWNTO 16*3) WHEN next_state_fsm_load_FFT = FIFO_4 ELSE
663 --sample_data <= sample_rdata(16*1-1 DOWNTO 16*0) WHEN next_state_fsm_load_FFT = FIFO_1 ELSE
664 -- sample_rdata(16*2-1 DOWNTO 16*1) WHEN next_state_fsm_load_FFT = FIFO_2 ELSE
665 -- sample_rdata(16*3-1 DOWNTO 16*2) WHEN next_state_fsm_load_FFT = FIFO_3 ELSE
666 -- sample_rdata(16*4-1 DOWNTO 16*3) WHEN next_state_fsm_load_FFT = FIFO_4 ELSE
667 -- sample_rdata(16*5-1 DOWNTO 16*4); --WHEN next_state_fsm_load_FFT = FIFO_5 ELSE
668 sample_data <= sample_rdata(16*1-1 DOWNTO 16*0) WHEN select_fifo_reg = "000" ELSE
669 sample_rdata(16*2-1 DOWNTO 16*1) WHEN select_fifo_reg = "001" ELSE
670 sample_rdata(16*3-1 DOWNTO 16*2) WHEN select_fifo_reg = "010" ELSE
671 sample_rdata(16*4-1 DOWNTO 16*3) WHEN select_fifo_reg = "011" ELSE
639 672 sample_rdata(16*5-1 DOWNTO 16*4); --WHEN next_state_fsm_load_FFT = FIFO_5 ELSE
640
673
641 674 -----------------------------------------------------------------------------
642 675 -- FFT
643 676 -----------------------------------------------------------------------------
@@ -852,9 +885,9 BEGIN
852 885 status_component_fifo_1_end <= '0';
853 886 IF SM_correlation_begin = '1' THEN
854 887 IF current_matrix_write = '0' THEN
855 status_component_fifo_0 <= status_component;
888 status_component_fifo_0 <= status_component(53 DOWNTO 4);
856 889 ELSE
857 status_component_fifo_1 <= status_component;
890 status_component_fifo_1 <= status_component(53 DOWNTO 4);
858 891 END IF;
859 892 END IF;
860 893
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@@ -311,7 +311,7 PACKAGE lpp_lfr_pkg IS
311 311 run : OUT STD_LOGIC;
312 312 start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0);
313 313 wfp_status_buffer_ready : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
314 wfp_addr_buffer : OUT STD_LOGIC_VECTOR(32*4 DOWNTO 0);
314 wfp_addr_buffer : OUT STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
315 315 wfp_length_buffer : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
316 316 wfp_ready_buffer : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
317 317 wfp_buffer_time : IN STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
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@@ -84,7 +84,7 ENTITY lpp_waveform IS
84 84
85 85 -- REG DMA
86 86 status_buffer_ready : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
87 addr_buffer : IN STD_LOGIC_VECTOR(32*4 DOWNTO 0);
87 addr_buffer : IN STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
88 88 length_buffer : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
89 89
90 90 ready_buffer : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
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@@ -73,11 +73,11 ARCHITECTURE ar_lpp_waveform_fifo_arbite
73 73 -- DATA MUX
74 74 -----------------------------------------------------------------------------
75 75 TYPE WORD_VECTOR IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR(31 DOWNTO 0);
76 SIGNAL data_0 : WORD_VECTOR(3 DOWNTO 0);
77 SIGNAL data_1 : WORD_VECTOR(3 DOWNTO 0);
78 SIGNAL data_2 : WORD_VECTOR(3 DOWNTO 0);
79 SIGNAL data_3 : WORD_VECTOR(3 DOWNTO 0);
80 SIGNAL data_sel : WORD_VECTOR(3 DOWNTO 0);
76 SIGNAL data_0 : WORD_VECTOR(2 DOWNTO 0);
77 SIGNAL data_1 : WORD_VECTOR(2 DOWNTO 0);
78 SIGNAL data_2 : WORD_VECTOR(2 DOWNTO 0);
79 SIGNAL data_3 : WORD_VECTOR(2 DOWNTO 0);
80 SIGNAL data_sel : WORD_VECTOR(2 DOWNTO 0);
81 81
82 82 -----------------------------------------------------------------------------
83 83 -- RR and SELECTION
@@ -267,4 +267,3 END ARCHITECTURE;
267 267
268 268
269 269
270
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@@ -80,7 +80,7 BEGIN
80 80 reg(2) WHEN sel(2) = '1' ELSE
81 81 reg(3);
82 82
83 reg_sel_s <= reg_sel WHEN enable = '0' ELSE
83 reg_sel_s <= reg_sel WHEN enable = '0' ELSE
84 84 reg_sel + 1 WHEN reg_sel < UNSIGNED(max_count) ELSE
85 85 0;
86 86
@@ -113,4 +113,3 END ARCHITECTURE;
113 113
114 114
115 115
116
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@@ -129,7 +129,7 PACKAGE lpp_waveform_pkg IS
129 129 nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
130 130 status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
131 131 status_buffer_ready : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
132 addr_buffer : IN STD_LOGIC_VECTOR(32*4 DOWNTO 0);
132 addr_buffer : IN STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
133 133 length_buffer : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
134 134 ready_buffer : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
135 135 buffer_time : OUT STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
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