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1 #------------------------------------------------------------------------------
2 #-- This file is a part of the LPP VHDL IP LIBRARY
3 #-- Copyright (C) 2010, Laboratory of Plasmas Physic - CNRS
4 #--
5 #-- This program is free software; you can redistribute it and/or modify
6 #-- it under the terms of the GNU General Public License as published by
7 #-- the Free Software Foundation; either version 3 of the License, or
8 #-- (at your option) any later version.
9 #--
10 #-- This program is distributed in the hope that it will be useful,
11 #-- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 #-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 #-- GNU General Public License for more details.
14 #--
15 #-- You should have received a copy of the GNU General Public License
16 #-- along with this program; if not, write to the Free Software
17 #-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 #------------------------------------------------------------------------------
19
20 include ../../rules.mk
21 LIBDIR = ../../lib
22 INCPATH = ../../includes
23 SCRIPTDIR=../../scripts/
24 LIBS=-lapb_dac_Driver -llpp_apb_functions
25 INPUTFILE=main.c
26 EXEC=BenchDAC_CAL.bin
27 OUTBINDIR=bin/
28
29
30 .PHONY:bin
31
32 all:bin
33 @echo $(EXEC)" file created"
34
35 clean:
36 rm -f *.{o,a}
37
38
39
40 help:ruleshelp
41 @echo " all : makes an executable file called "$(EXEC)
42 @echo " in "$(OUTBINDIR)
43 @echo " clean : removes temporary files"
44
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1 #include <stdio.h>
2 #include "lpp_apb_functions.h"
3 #include "apb_dac_Driver.h"
4
5 int main()
6 {
7 printf("\nDebut Main\n\n");
8 int i;
9 int tablo CAL_SignalData
10
11 DAC_Device* dac0 = openDAC(0);
12
13 printf("\nSTART\n\n");
14
15 while(1)
16 {
17 for (i = 0 ; i < 251 ; i++)
18 {
19 while(!((dac0->ConfigReg & DAC_ready) == DAC_ready));
20 dac0->DataReg = tablo[i];
21 while((dac0->ConfigReg & DAC_ready) == DAC_ready);
22 }
23 }
24 return 0;
25 }
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1 -----------------------------------------------------------------------------
2 -- LEON3 Demonstration design
3 -- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 2 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19
20
21 library ieee;
22 use ieee.std_logic_1164.all;
23 library grlib;
24 use grlib.amba.all;
25 use grlib.stdlib.all;
26 library techmap;
27 use techmap.gencomp.all;
28 library gaisler;
29 use gaisler.memctrl.all;
30 use gaisler.leon3.all;
31 use gaisler.uart.all;
32 use gaisler.misc.all;
33 library esa;
34 use esa.memoryctrl.all;
35 use work.config.all;
36 library lpp;
37 use lpp.lpp_amba.all;
38 use lpp.lpp_memory.all;
39 use lpp.lpp_uart.all;
40 use lpp.lpp_matrix.all;
41 use lpp.lpp_delay.all;
42 use lpp.lpp_fft.all;
43 use lpp.fft_components.all;
44 use lpp.lpp_ad_conv.all;
45 use lpp.iir_filter.all;
46 use lpp.general_purpose.all;
47 use lpp.Filtercfg.all;
48 use lpp.lpp_cna.all;
49
50 entity leon3mp is
51 generic (
52 fabtech : integer := CFG_FABTECH;
53 memtech : integer := CFG_MEMTECH;
54 padtech : integer := CFG_PADTECH;
55 clktech : integer := CFG_CLKTECH;
56 disas : integer := CFG_DISAS; -- Enable disassembly to console
57 dbguart : integer := CFG_DUART; -- Print UART on console
58 pclow : integer := CFG_PCLOW
59 );
60 port (
61 clk50MHz : in std_ulogic;
62 reset : in std_ulogic;
63 ramclk : out std_logic;
64
65 ahbrxd : in std_ulogic; -- DSU rx data
66 ahbtxd : out std_ulogic; -- DSU tx data
67 dsubre : in std_ulogic;
68 dsuact : out std_ulogic;
69 urxd1 : in std_ulogic; -- UART1 rx data
70 utxd1 : out std_ulogic; -- UART1 tx data
71 errorn : out std_ulogic;
72
73 address : out std_logic_vector(18 downto 0);
74 data : inout std_logic_vector(31 downto 0);
75 gpio : inout std_logic_vector(6 downto 0); -- I/O port
76
77 nBWa : out std_logic;
78 nBWb : out std_logic;
79 nBWc : out std_logic;
80 nBWd : out std_logic;
81 nBWE : out std_logic;
82 nADSC : out std_logic;
83 nADSP : out std_logic;
84 nADV : out std_logic;
85 nGW : out std_logic;
86 nCE1 : out std_logic;
87 CE2 : out std_logic;
88 nCE3 : out std_logic;
89 nOE : out std_logic;
90 MODE : out std_logic;
91 SSRAM_CLK : out std_logic;
92 ZZ : out std_logic;
93 ---------------------------------------------------------------------
94 --- AJOUT TEST ------------------------In/Out-----------------------
95 ---------------------------------------------------------------------
96 -- DAC
97 DAC_EN : out std_logic;
98 DAC_SYNC : out std_logic;
99 DAC_SCLK : out std_logic;
100 DAC_DATA : out std_logic;
101 -- UART
102 UART_RXD : in std_logic;
103 UART_TXD : out std_logic;
104 ---------------------------------------------------------------------
105 led : out std_logic_vector(1 downto 0)
106 );
107 end;
108
109 architecture Behavioral of leon3mp is
110
111 constant maxahbmsp : integer := CFG_NCPU+CFG_AHB_UART+
112 CFG_GRETH+CFG_AHB_JTAG;
113 constant maxahbm : integer := maxahbmsp;
114
115 --Clk & Rst g�n�
116 signal vcc : std_logic_vector(4 downto 0);
117 signal gnd : std_logic_vector(4 downto 0);
118 signal resetnl : std_ulogic;
119 signal clk2x : std_ulogic;
120 signal lclk : std_ulogic;
121 signal lclk2x : std_ulogic;
122 signal clkm : std_ulogic;
123 signal rstn : std_ulogic;
124 signal rstraw : std_ulogic;
125 signal pciclk : std_ulogic;
126 signal sdclkl : std_ulogic;
127 signal cgi : clkgen_in_type;
128 signal cgo : clkgen_out_type;
129 --- AHB / APB
130 signal apbi : apb_slv_in_type;
131 signal apbo : apb_slv_out_vector := (others => apb_none);
132 signal ahbsi : ahb_slv_in_type;
133 signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
134 signal ahbmi : ahb_mst_in_type;
135 signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
136 --UART
137 signal ahbuarti : uart_in_type;
138 signal ahbuarto : uart_out_type;
139 signal apbuarti : uart_in_type;
140 signal apbuarto : uart_out_type;
141 --MEM CTRLR
142 signal memi : memory_in_type;
143 signal memo : memory_out_type;
144 signal wpo : wprot_out_type;
145 signal sdo : sdram_out_type;
146 --IRQ
147 signal irqi : irq_in_vector(0 to CFG_NCPU-1);
148 signal irqo : irq_out_vector(0 to CFG_NCPU-1);
149 --Timer
150 signal gpti : gptimer_in_type;
151 signal gpto : gptimer_out_type;
152 --GPIO
153 signal gpioi : gpio_in_type;
154 signal gpioo : gpio_out_type;
155 --DSU
156 signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
157 signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
158 signal dsui : dsu_in_type;
159 signal dsuo : dsu_out_type;
160
161 ---------------------------------------------------------------------
162 --- AJOUT TEST ------------------------Signaux----------------------
163 ---------------------------------------------------------------------
164
165 ---------------------------------------------------------------------
166 constant IOAEN : integer := CFG_CAN;
167 constant boardfreq : integer := 50000;
168
169 begin
170
171 ---------------------------------------------------------------------
172 --- AJOUT TEST -------------------------------------IPs-------------
173 ---------------------------------------------------------------------
174
175 -- apbo not free : 0 1 2 3 7 11
176
177 --- DAC -------------------------------------------------------------
178
179 CAL0 : APB_CNA
180 generic map (pindex => 4, paddr => 4)
181 port map(clkm,rstn,apbi,apbo(4),DAC_EN,DAC_SYNC,DAC_SCLK,DAC_DATA);
182
183
184 --- UART -------------------------------------------------------------
185
186 COM0 : APB_UART
187 generic map (pindex => 5, paddr => 5)
188 port map (clkm,rstn,apbi,apbo(5),UART_TXD,UART_RXD);
189
190
191 --- FIFO -------------------------------------------------------------
192
193 Memtest : APB_FIFO
194 generic map (pindex => 6, paddr => 6, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '1', R => 1, W => 1)
195 port map (clkm,rstn,clkm,clkm,(others => '0'),(others => '1'),(others => '1'),open,open,open,(others => '0'),open,open,apbi,apbo(6));
196
197
198 ----------------------------------------------------------------------
199 --- Reset and Clock generation -------------------------------------
200 ----------------------------------------------------------------------
201
202 vcc <= (others => '1'); gnd <= (others => '0');
203 cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
204
205 rst0 : rstgen port map (reset, clkm, cgo.clklock, rstn, rstraw);
206
207
208 clk_pad : clkpad generic map (tech => padtech) port map (clk50MHz, lclk2x);
209
210 clkgen0 : clkgen -- clock generator
211 generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN,
212 CFG_CLK_NOFB, 0, 0, 0, boardfreq, 0, 0, CFG_OCLKDIV)
213 port map (lclk, lclk, clkm, open, clk2x, sdclkl, pciclk, cgi, cgo);
214
215 ramclk <= clkm;
216 process(lclk2x)
217 begin
218 if lclk2x'event and lclk2x = '1' then
219 lclk <= not lclk;
220 end if;
221 end process;
222
223 ----------------------------------------------------------------------
224 --- LEON3 processor / DSU / IRQ ------------------------------------
225 ----------------------------------------------------------------------
226
227 l3 : if CFG_LEON3 = 1 generate
228 cpu : for i in 0 to CFG_NCPU-1 generate
229 u0 : leon3s -- LEON3 processor
230 generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
231 0, CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
232 CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
233 CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
234 CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
235 CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1)
236 port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
237 irqi(i), irqo(i), dbgi(i), dbgo(i));
238 end generate;
239 errorn_pad : outpad generic map (tech => padtech) port map (errorn, dbgo(0).error);
240
241 dsugen : if CFG_DSU = 1 generate
242 dsu0 : dsu3 -- LEON3 Debug Support Unit
243 generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
244 ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
245 port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
246 -- dsuen_pad : inpad generic map (tech => padtech) port map (dsuen, dsui.enable);
247 dsui.enable <= '1';
248 dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break);
249 dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, dsuo.active);
250 end generate;
251 end generate;
252
253 nodsu : if CFG_DSU = 0 generate
254 ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
255 end generate;
256
257 irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
258 irqctrl0 : irqmp -- interrupt controller
259 generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
260 port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
261 end generate;
262 irq3 : if CFG_IRQ3_ENABLE = 0 generate
263 x : for i in 0 to CFG_NCPU-1 generate
264 irqi(i).irl <= "0000";
265 end generate;
266 apbo(2) <= apb_none;
267 end generate;
268
269 ----------------------------------------------------------------------
270 --- Memory controllers ---------------------------------------------
271 ----------------------------------------------------------------------
272
273 memctrlr : mctrl generic map (hindex => 0,pindex => 0, paddr => 0)
274 port map (rstn, clkm, memi, memo, ahbsi, ahbso(0),apbi,apbo(0),wpo, sdo);
275
276 memi.brdyn <= '1'; memi.bexcn <= '1';
277 memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "10";
278
279 bdr : for i in 0 to 3 generate
280 data_pad : iopadv generic map (tech => padtech, width => 8)
281 port map (data(31-i*8 downto 24-i*8), memo.data(31-i*8 downto 24-i*8),
282 memo.bdrive(i), memi.data(31-i*8 downto 24-i*8));
283 end generate;
284
285
286 addr_pad : outpadv generic map (width => 19, tech => padtech)
287 port map (address, memo.address(20 downto 2));
288
289
290 SSRAM_0:entity ssram_plugin
291 generic map (tech => padtech)
292 port map
293 (lclk2x,memo,SSRAM_CLK,nBWa,nBWb,nBWc,nBWd,nBWE,nADSC,nADSP,nADV,nGW,nCE1,CE2,nCE3,nOE,MODE,ZZ);
294
295 ----------------------------------------------------------------------
296 --- AHB CONTROLLER -------------------------------------------------
297 ----------------------------------------------------------------------
298
299 ahb0 : ahbctrl -- AHB arbiter/multiplexer
300 generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
301 rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
302 ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
303 port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
304
305 ----------------------------------------------------------------------
306 --- AHB UART -------------------------------------------------------
307 ----------------------------------------------------------------------
308
309 dcomgen : if CFG_AHB_UART = 1 generate
310 dcom0: ahbuart -- Debug UART
311 generic map (hindex => CFG_NCPU, pindex => 7, paddr => 7)
312 port map (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(7), ahbmi, ahbmo(CFG_NCPU));
313 dsurx_pad : inpad generic map (tech => padtech) port map (ahbrxd, ahbuarti.rxd);
314 dsutx_pad : outpad generic map (tech => padtech) port map (ahbtxd, ahbuarto.txd);
315 -- led(0) <= not ahbuarti.rxd; led(1) <= not ahbuarto.txd;
316 end generate;
317 nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate;
318
319 ----------------------------------------------------------------------
320 --- APB Bridge -----------------------------------------------------
321 ----------------------------------------------------------------------
322
323 apb0 : apbctrl -- AHB/APB bridge
324 generic map (hindex => 1, haddr => CFG_APBADDR)
325 port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
326
327 ----------------------------------------------------------------------
328 --- GPT Timer ------------------------------------------------------
329 ----------------------------------------------------------------------
330
331 gpt : if CFG_GPT_ENABLE /= 0 generate
332 timer0 : gptimer -- timer unit
333 generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
334 sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
335 nbits => CFG_GPT_TW)
336 port map (rstn, clkm, apbi, apbo(3), gpti, gpto);
337 gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
338 -- led(4) <= gpto.wdog;
339 end generate;
340 notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
341
342
343 ----------------------------------------------------------------------
344 --- APB UART -------------------------------------------------------
345 ----------------------------------------------------------------------
346
347 ua1 : if CFG_UART1_ENABLE /= 0 generate
348 uart1 : apbuart -- UART 1
349 generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
350 fifosize => CFG_UART1_FIFO)
351 port map (rstn, clkm, apbi, apbo(1), ahbuarti, apbuarto);
352 apbuarti.rxd <= urxd1; apbuarti.extclk <= '0'; utxd1 <= apbuarto.txd;
353 apbuarti.ctsn <= '0'; --rtsn1 <= apbuarto.rtsn;
354 -- led(0) <= not apbuarti.rxd; led(1) <= not apbuarto.txd;
355 end generate;
356 noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
357
358 ----------------------------------------------------------------------
359 --- GPIO -----------------------------------------------------------
360 ----------------------------------------------------------------------
361 led(0) <= gpio(0); led(1) <= gpio(1);
362
363 gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GR GPIO unit
364 grgpio0: grgpio
365 generic map( pindex => 11, paddr => 11, imask => CFG_GRGPIO_IMASK, nbits => 7)
366 port map( rstn, clkm, apbi, apbo(11), gpioi, gpioo);
367
368 pio_pads : for i in 0 to 6 generate
369 pio_pad : iopad generic map (tech => padtech)
370 port map (gpio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
371 end generate;
372 end generate;
373
374
375 end Behavioral; No newline at end of file
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
22 library ieee;
23 use ieee.std_logic_1164.all;
24 library grlib;
25 use grlib.amba.all;
26 use grlib.stdlib.all;
27 use grlib.devices.all;
28 library lpp;
29 use lpp.lpp_amba.all;
30 use lpp.apb_devices_list.all;
31 use lpp.lpp_cna.all;
32
33 --! Driver APB, va faire le lien entre l'IP VHDL du convertisseur et le bus Amba
34
35 entity APB_DAC is
36 generic (
37 pindex : integer := 0;
38 paddr : integer := 0;
39 pmask : integer := 16#fff#;
40 pirq : integer := 0;
41 abits : integer := 8);
42 port (
43 clk : in std_logic; --! Horloge du composant
44 rst : in std_logic; --! Reset general du composant
45 apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus
46 apbo : out apb_slv_out_type; --! Registre de gestion des sorties du bus
47 Cal_EN : out std_logic; --! Signal Enable du multiplex pour la CAL
48 SYNC : out std_logic; --! Signal de synchronisation du convertisseur
49 SCLK : out std_logic; --! Horloge systeme du convertisseur
50 DATA : out std_logic --! Donn�e num�rique s�rialis�
51 );
52 end entity;
53
54 --! @details Les deux registres (apbi,apbo) permettent de g�rer la communication sur le bus
55 --! et les sorties seront cabl�es vers le convertisseur.
56
57 architecture ar_APB_DAC of APB_DAC is
58
59 constant REVISION : integer := 1;
60
61 constant pconfig : apb_config_type := (
62 0 => ahb_device_reg (VENDOR_LPP, LPP_CNA, 0, REVISION, 0),
63 1 => apb_iobar(paddr, pmask));
64
65 signal enable : std_logic;
66 signal flag_sd : std_logic;
67
68 type DAC_ctrlr_Reg is record
69 DAC_Cfg : std_logic_vector(1 downto 0);
70 DAC_Data : std_logic_vector(15 downto 0);
71 end record;
72
73 signal Rec : DAC_ctrlr_Reg;
74 signal Rdata : std_logic_vector(31 downto 0);
75
76 begin
77
78 enable <= Rec.DAC_Cfg(0);
79 Rec.DAC_Cfg(1) <= flag_sd;
80
81 CONV0 : DacDriver
82 port map(clk,rst,enable,Rec.CNA_Data,SYNC,SCLK,flag_sd,Data);
83
84
85 process(rst,clk)
86 begin
87 if(rst='0')then
88 Rec.DAC_Data <= (others => '0');
89
90 elsif(clk'event and clk='1')then
91
92
93 --APB Write OP
94 if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
95 case apbi.paddr(abits-1 downto 2) is
96 when "000000" =>
97 Rec.DAC_Cfg(0) <= apbi.pwdata(0);
98 when "000001" =>
99 Rec.DAC_Data <= apbi.pwdata(15 downto 0);
100 when others =>
101 null;
102 end case;
103 end if;
104
105 --APB Read OP
106 if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
107 case apbi.paddr(abits-1 downto 2) is
108 when "000000" =>
109 Rdata(31 downto 2) <= X"ABCDEF5" & "00";
110 Rdata(1 downto 0) <= Rec.DAC_Cfg;
111 when "000001" =>
112 Rdata(31 downto 16) <= X"FD18";
113 Rdata(15 downto 0) <= Rec.DAC_Data;
114 when others =>
115 Rdata <= (others => '0');
116 end case;
117 end if;
118
119 end if;
120 apbo.pconfig <= pconfig;
121 end process;
122
123 apbo.prdata <= Rdata when apbi.penable = '1';
124 Cal_EN <= enable;
125 end architecture;
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
22 library IEEE;
23 use IEEE.std_logic_1164.all;
24 use IEEE.numeric_std.all;
25 use work.Convertisseur_config.all;
26 use lpp.lpp_cna.all;
27
28 --! Programme du Convertisseur Num�rique/Analogique
29
30 entity DacDriver is
31 port(
32 clk : in std_logic; --! Horloge du composant
33 rst : in std_logic; --! Reset general du composant
34 enable : in std_logic; --! Autorise ou non l'utilisation du composant
35 Data_C : in std_logic_vector(15 downto 0); --! Donn�e Num�rique d'entr�e sur 16 bits
36 SYNC : out std_logic; --! Signal de synchronisation du convertisseur
37 SCLK : out std_logic; --! Horloge systeme du convertisseur
38 flag_sd : out std_logic; --! Flag, signale la fin de la s�rialisation d'une donn�e
39 Data : out std_logic --! Donn�e num�rique s�rialis�
40 );
41 end entity;
42
43 --! @details Un driver C va permettre de g�nerer un tableau de donn�es sur 16 bits,
44 --! qui seront s�rialis� pour �tre ensuite dirig�es vers le convertisseur.
45
46 architecture ar_DacDriver of DacDriver is
47
48 signal s_SCLK : std_logic;
49 signal OKAI_send : std_logic;
50
51 begin
52
53 SystemCLK : Systeme_Clock
54 generic map (nb_serial)
55 port map (clk,rst,s_SCLK);
56
57
58 Signal_sync : Gene_SYNC
59 port map (s_SCLK,rst,enable,OKAI_send,SYNC);
60
61
62 Serial : serialize
63 port map (clk,rst,s_SCLK,Data_C,OKAI_send,flag_sd,Data);
64
65
66 SCLK <= s_SCLK;
67
68 end architecture; No newline at end of file
Show file before | Show file after | Hide comments
@@ -27,4 +27,5 all:
27 make all -C BenchFFT
27 make all -C BenchFFT
28 make all -C BenchGPIO
28 make all -C BenchGPIO
29 make all -C BenchMatrix
29 make all -C BenchMatrix
30 make all -C BenchFFT+Matrix No newline at end of file
30 make all -C BenchFFT+Matrix
31 make all -C BenchDAC_CAL No newline at end of file
Show file before | Show file after | Hide comments
@@ -1,34 +1,42
1 /*------------------------------------------------------------------------------
1 /*------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Martin Morlot
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 -----------------------------------------------------------------------------*/
21 -----------------------------------------------------------------------------*/
22 #ifndef APB_CNA_DRIVER_H
22 #ifndef APB_CNA_DRIVER_H
23 #define APB_CNA_DRIVER_H
23 #define APB_CNA_DRIVER_H
24
24
25 #define DAC_ready 3
25 #define DAC_ready 3
26 #define DAC_enable 1
26 #define DAC_enable 1
27 #define DAC_disable 0
27 #define DAC_disable 0
28
29
28
30 /*===================================================
29 #define CAL_SignalData [251] = {0x9555,0x1800,0x19AA,0x1B15,0x1C0A,0x1C66,0x1C1F,0x1B44,0x19FC,0x187F,0x170F,0x15EA,0x1542,0x1537,0x15CE,0x16F2,0x187A,0x1A2B,0x1BC2,0x1D04,0x1DBF,0x1DDB,0x1D56,0x1C49,0x1AE3,0x195F,0x1800,0x1700,0x168D,0x16BA,0x1785,0x18D0,0x1A69,0x1C12,0x1D8A,0x1E98,0x1F13,\
31 T Y P E S D E F
30 0x1EEB,0x1E28,0x1CEC,0x1FFF,0x19E8,0x189F,0x17C8,0x1788,0x17EA,0x18E2,0x1A48,0x1BE7,0x1D7C,0x1ECA,0x1F9C,0x1FD2,0x1F64,0x1E66,0x1D00,0x1B6E,0x19EF,0x18C1,0x1817,0x180A,0x189D,0x19BA,0x1B33,0x1CCC,0x1E44,0x1F5F,0x1FEE,0x1FDC,0x1F2B,0x1DF6,0x1C6E,0x1AD1,0x1960,0x1855,0x17D9,0x1800,\
31 0x18C1,0x19FD,0x1B80,0x1D0A,0x1E5C,0x1F3D,0x1F87,0x1F2E,0x1E3E,0x1CDA,0x1B39,0x199C,0x1842,0x1760,0x1717,0x1771,0x185D,0x19B1,0x1B36,0x1CAA,0x1DCF,0x1E73,0x1E79,0x1DDD,0x1CB4,0x1B2B,0x197C,0x17EA,0x16B1,0x15FF,0x15EE,0x167C,0x178F,0x18F7,0x1A78,0x1BCF,0x1CC4,0x1D2A,0x1CED,0x1C14,\
32 0x1ABC,0x191A,0x176B,0x15F0,0x14E2,0x1467,0x1490,0x1552,0x1689,0x1800,0x1977,0x1AAE,0x1B70,0x1B99,0x1B1E,0x1A10,0x1895,0x16E6,0x1544,0x13EC,0x1313,0x12D6,0x133C,0x1431,0x1588,0x1709,0x1871,0x1984,0x1A12,0x1A01,0x194F,0x1816,0x1684,0x14D5,0x134C,0x1223,0x1187,0x118D,0x1231,0x1356,\
33 0x14CA,0x164F,0x17A3,0x188F,0x18E9,0x18A0,0x17BE,0x1664,0x14C7,0x1326,0x11C2,0x10D2,0x1079,0x10C3,0x11A4,0x12F6,0x1480,0x1603,0x173F,0x1800,0x1827,0x17AB,0x16A0,0x152F,0x1392,0x120A,0x10D5,0x1024,0x1012,0x10A1,0x11BC,0x1334,0x14CD,0x1646,0x1763,0x17F6,0x17E9,0x173F,0x1611,0x1492,\
34 0x1300,0x119A,0x109C,0x102E,0x1064,0x1136,0x1284,0x1419,0x15B8,0x171E,0x1816,0x1878,0x1838,0x1761,0x1618,0x1494,0x1314,0x11D8,0x1115,0x10ED,0x1168,0x1276,0x13EE,0x1597,0x1730,0x187B,0x1946,0x1973,0x1900,0x1800,0x16A1,0x151D,0x13B7,0x12AA,0x1225,0x1241,0x12FC,0x143E,0x15D5,0x1786,\
35 0x190E,0x1A32,0x1AC9,0x1ABE,0x1A16,0x18F1,0x1781,0x1604,0x14BC,0x13E1,0x139A,0x13F6,0x14EB,0x1656};
36 //Sinus (10Khz + 625hz)
37
38 /*===================================================
39 T Y P E S D E F
32 ====================================================*/
40 ====================================================*/
33
41
34 /** Structure repr�sentant le registre du CNA */
42 /** Structure repr�sentant le registre du CNA */
@@ -40,21 +48,12 struct DAC_Driver
40
48
41 typedef volatile struct DAC_Driver DAC_Device;
49 typedef volatile struct DAC_Driver DAC_Device;
42
50
43 /*===================================================
51 /*===================================================
44 F U N C T I O N S
52 F U N C T I O N S
45 ====================================================*/
53 ====================================================*/
46
54
47 /** Ouvre l'acc� au CNA */
55 /** Ouvre l'acc� au CNA */
48 DAC_Device* DacOpen(int count);
56 DAC_Device* openDAC(int count);
49
50 //DAC_Device* DacClose(int count);
51
52 /** Les donn�es sont lus a partir d'un tableau pour obtenir le signal de CAL (10Khz + 625hz) */
53 int DacTable();
54
55 /** Les donn�es sont entr�e par l'utilisateur, la conversion se fait a chaque nouvelle donn�e */
56 int DacConst();
57
58
57
59
58
60 #endif
59 #endif
Show file before | Show file after | Hide comments
@@ -24,55 +24,15
24 #include <stdio.h>
24 #include <stdio.h>
25
25
26
26
27 DAC_Device* DacOpen(int count)
27 DAC_Device* openDAC(int count)
28 {
28 {
29 DAC_Device* dac0;
29 DAC_Device* dac0;
30 dac0 = (DAC_Device*) apbgetdevice(LPP_CNA,VENDOR_LPP,count);
30 dac0 = (DAC_Device*) apbgetdevice(LPP_CNA,VENDOR_LPP,count);
31 dac0->configReg = DAC_enable;
31 dac0->ConfigReg = DAC_enable;
32 return dac0;
32 return dac0;
33 }
33 }
34
34
35 /*
35 /*int DacConst()
36 DAC_Device* DacClose(int count)
37 {
38 DAC_Device* dac1;
39 dac1 = (DAC_Device*) apbgetdevice(LPP_CNA,VENDOR_LPP,count);
40 dac1->configReg = DAC_disable;
41 return dac1;
42 }
43 */
44
45
46 int DacTable()
47 {
48 int i;
49 DAC_Device* dac2;
50 int tablo[251] = {0x9555,0x1800,0x19AA,0x1B15,0x1C0A,0x1C66,0x1C1F,0x1B44,0x19FC,0x187F,0x170F,0x15EA,0x1542,0x1537,0x15CE,0x16F2,0x187A,0x1A2B,0x1BC2,0x1D04,0x1DBF,0x1DDB,0x1D56,0x1C49,0x1AE3,0x195F,0x1800,0x1700,0x168D,0x16BA,0x1785,0x18D0,0x1A69,0x1C12,0x1D8A,0x1E98,0x1F13,
51 0x1EEB,0x1E28,0x1CEC,0x1FFF,0x19E8,0x189F,0x17C8,0x1788,0x17EA,0x18E2,0x1A48,0x1BE7,0x1D7C,0x1ECA,0x1F9C,0x1FD2,0x1F64,0x1E66,0x1D00,0x1B6E,0x19EF,0x18C1,0x1817,0x180A,0x189D,0x19BA,0x1B33,0x1CCC,0x1E44,0x1F5F,0x1FEE,0x1FDC,0x1F2B,0x1DF6,0x1C6E,0x1AD1,0x1960,0x1855,0x17D9,0x1800,
52 0x18C1,0x19FD,0x1B80,0x1D0A,0x1E5C,0x1F3D,0x1F87,0x1F2E,0x1E3E,0x1CDA,0x1B39,0x199C,0x1842,0x1760,0x1717,0x1771,0x185D,0x19B1,0x1B36,0x1CAA,0x1DCF,0x1E73,0x1E79,0x1DDD,0x1CB4,0x1B2B,0x197C,0x17EA,0x16B1,0x15FF,0x15EE,0x167C,0x178F,0x18F7,0x1A78,0x1BCF,0x1CC4,0x1D2A,0x1CED,0x1C14,
53 0x1ABC,0x191A,0x176B,0x15F0,0x14E2,0x1467,0x1490,0x1552,0x1689,0x1800,0x1977,0x1AAE,0x1B70,0x1B99,0x1B1E,0x1A10,0x1895,0x16E6,0x1544,0x13EC,0x1313,0x12D6,0x133C,0x1431,0x1588,0x1709,0x1871,0x1984,0x1A12,0x1A01,0x194F,0x1816,0x1684,0x14D5,0x134C,0x1223,0x1187,0x118D,0x1231,0x1356,
54 0x14CA,0x164F,0x17A3,0x188F,0x18E9,0x18A0,0x17BE,0x1664,0x14C7,0x1326,0x11C2,0x10D2,0x1079,0x10C3,0x11A4,0x12F6,0x1480,0x1603,0x173F,0x1800,0x1827,0x17AB,0x16A0,0x152F,0x1392,0x120A,0x10D5,0x1024,0x1012,0x10A1,0x11BC,0x1334,0x14CD,0x1646,0x1763,0x17F6,0x17E9,0x173F,0x1611,0x1492,
55 0x1300,0x119A,0x109C,0x102E,0x1064,0x1136,0x1284,0x1419,0x15B8,0x171E,0x1816,0x1878,0x1838,0x1761,0x1618,0x1494,0x1314,0x11D8,0x1115,0x10ED,0x1168,0x1276,0x13EE,0x1597,0x1730,0x187B,0x1946,0x1973,0x1900,0x1800,0x16A1,0x151D,0x13B7,0x12AA,0x1225,0x1241,0x12FC,0x143E,0x15D5,0x1786,
56 0x190E,0x1A32,0x1AC9,0x1ABE,0x1A16,0x18F1,0x1781,0x1604,0x14BC,0x13E1,0x139A,0x13F6,0x14EB,0x1656};
57 dac2 = (DAC_Device*)0x80000800;
58 dac2->configReg = DAC_enable;
59 dac2->dataReg = tablo[0];
60
61 while(1)
62 {
63 for (i = 0 ; i < 251 ; i++)
64 {
65 while(!((dac2->configReg & DAC_ready) == DAC_ready));
66 dac2->dataReg = tablo[i];
67 while((dac2->configReg & DAC_ready) == DAC_ready);
68 }
69 }
70 return 0;
71 }
72
73
74
75 int DacConst()
76 {
36 {
77 DAC_Device* dac3;
37 DAC_Device* dac3;
78 int Value = 0x1FFF;
38 int Value = 0x1FFF;
@@ -85,5 +45,5 int DacConst()
85 dac3->dataReg = Value;
45 dac3->dataReg = Value;
86 }
46 }
87 return 0;
47 return 0;
88 }
48 } */
89
49
Show file before | Show file after | Hide comments
@@ -1,34 +1,42
1 /*------------------------------------------------------------------------------
1 /*------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Martin Morlot
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 -----------------------------------------------------------------------------*/
21 -----------------------------------------------------------------------------*/
22 #ifndef APB_CNA_DRIVER_H
22 #ifndef APB_CNA_DRIVER_H
23 #define APB_CNA_DRIVER_H
23 #define APB_CNA_DRIVER_H
24
24
25 #define DAC_ready 3
25 #define DAC_ready 3
26 #define DAC_enable 1
26 #define DAC_enable 1
27 #define DAC_disable 0
27 #define DAC_disable 0
28
29
28
30 /*===================================================
29 #define CAL_SignalData [251] = {0x9555,0x1800,0x19AA,0x1B15,0x1C0A,0x1C66,0x1C1F,0x1B44,0x19FC,0x187F,0x170F,0x15EA,0x1542,0x1537,0x15CE,0x16F2,0x187A,0x1A2B,0x1BC2,0x1D04,0x1DBF,0x1DDB,0x1D56,0x1C49,0x1AE3,0x195F,0x1800,0x1700,0x168D,0x16BA,0x1785,0x18D0,0x1A69,0x1C12,0x1D8A,0x1E98,0x1F13,\
31 T Y P E S D E F
30 0x1EEB,0x1E28,0x1CEC,0x1FFF,0x19E8,0x189F,0x17C8,0x1788,0x17EA,0x18E2,0x1A48,0x1BE7,0x1D7C,0x1ECA,0x1F9C,0x1FD2,0x1F64,0x1E66,0x1D00,0x1B6E,0x19EF,0x18C1,0x1817,0x180A,0x189D,0x19BA,0x1B33,0x1CCC,0x1E44,0x1F5F,0x1FEE,0x1FDC,0x1F2B,0x1DF6,0x1C6E,0x1AD1,0x1960,0x1855,0x17D9,0x1800,\
31 0x18C1,0x19FD,0x1B80,0x1D0A,0x1E5C,0x1F3D,0x1F87,0x1F2E,0x1E3E,0x1CDA,0x1B39,0x199C,0x1842,0x1760,0x1717,0x1771,0x185D,0x19B1,0x1B36,0x1CAA,0x1DCF,0x1E73,0x1E79,0x1DDD,0x1CB4,0x1B2B,0x197C,0x17EA,0x16B1,0x15FF,0x15EE,0x167C,0x178F,0x18F7,0x1A78,0x1BCF,0x1CC4,0x1D2A,0x1CED,0x1C14,\
32 0x1ABC,0x191A,0x176B,0x15F0,0x14E2,0x1467,0x1490,0x1552,0x1689,0x1800,0x1977,0x1AAE,0x1B70,0x1B99,0x1B1E,0x1A10,0x1895,0x16E6,0x1544,0x13EC,0x1313,0x12D6,0x133C,0x1431,0x1588,0x1709,0x1871,0x1984,0x1A12,0x1A01,0x194F,0x1816,0x1684,0x14D5,0x134C,0x1223,0x1187,0x118D,0x1231,0x1356,\
33 0x14CA,0x164F,0x17A3,0x188F,0x18E9,0x18A0,0x17BE,0x1664,0x14C7,0x1326,0x11C2,0x10D2,0x1079,0x10C3,0x11A4,0x12F6,0x1480,0x1603,0x173F,0x1800,0x1827,0x17AB,0x16A0,0x152F,0x1392,0x120A,0x10D5,0x1024,0x1012,0x10A1,0x11BC,0x1334,0x14CD,0x1646,0x1763,0x17F6,0x17E9,0x173F,0x1611,0x1492,\
34 0x1300,0x119A,0x109C,0x102E,0x1064,0x1136,0x1284,0x1419,0x15B8,0x171E,0x1816,0x1878,0x1838,0x1761,0x1618,0x1494,0x1314,0x11D8,0x1115,0x10ED,0x1168,0x1276,0x13EE,0x1597,0x1730,0x187B,0x1946,0x1973,0x1900,0x1800,0x16A1,0x151D,0x13B7,0x12AA,0x1225,0x1241,0x12FC,0x143E,0x15D5,0x1786,\
35 0x190E,0x1A32,0x1AC9,0x1ABE,0x1A16,0x18F1,0x1781,0x1604,0x14BC,0x13E1,0x139A,0x13F6,0x14EB,0x1656};
36 //Sinus (10Khz + 625hz)
37
38 /*===================================================
39 T Y P E S D E F
32 ====================================================*/
40 ====================================================*/
33
41
34 /** Structure repr�sentant le registre du CNA */
42 /** Structure repr�sentant le registre du CNA */
@@ -40,21 +48,12 struct DAC_Driver
40
48
41 typedef volatile struct DAC_Driver DAC_Device;
49 typedef volatile struct DAC_Driver DAC_Device;
42
50
43 /*===================================================
51 /*===================================================
44 F U N C T I O N S
52 F U N C T I O N S
45 ====================================================*/
53 ====================================================*/
46
54
47 /** Ouvre l'acc� au CNA */
55 /** Ouvre l'acc� au CNA */
48 DAC_Device* DacOpen(int count);
56 DAC_Device* openDAC(int count);
49
50 //DAC_Device* DacClose(int count);
51
52 /** Les donn�es sont lus a partir d'un tableau pour obtenir le signal de CAL (10Khz + 625hz) */
53 int DacTable();
54
55 /** Les donn�es sont entr�e par l'utilisateur, la conversion se fait a chaque nouvelle donn�e */
56 int DacConst();
57
58
57
59
58
60 #endif
59 #endif
Show file before | Show file after | Hide comments
@@ -30,7 +30,6 entity HeaderBuilder is
30 clkm : in std_logic;
30 clkm : in std_logic;
31 rstn : in std_logic;
31 rstn : in std_logic;
32
32
33 pong : in std_logic;
34 Statu : in std_logic_vector(3 downto 0);
33 Statu : in std_logic_vector(3 downto 0);
35 Matrix_Type : in std_logic_vector(1 downto 0);
34 Matrix_Type : in std_logic_vector(1 downto 0);
36 Matrix_Write : in std_logic;
35 Matrix_Write : in std_logic;
@@ -57,7 +56,6 signal Matrix_Param : std_logic_vect
57 signal Write_reg : std_logic;
56 signal Write_reg : std_logic;
58 signal Data_cpt : integer;
57 signal Data_cpt : integer;
59 signal MAX : integer;
58 signal MAX : integer;
60 signal pong_reg : std_logic;
61
59
62 type etat is (idle0,idle1,pong0,pong1);
60 type etat is (idle0,idle1,pong0,pong1);
63 signal ect : etat;
61 signal ect : etat;
@@ -69,7 +67,6 begin
69 if(rstn='0')then
67 if(rstn='0')then
70 ect <= idle0;
68 ect <= idle0;
71 Valid <= '0';
69 Valid <= '0';
72 pong_reg <= '0';
73 header_val <= '0';
70 header_val <= '0';
74 header(5 downto 0) <= (others => '0');
71 header(5 downto 0) <= (others => '0');
75 Write_reg <= '0';
72 Write_reg <= '0';
@@ -79,7 +76,6 begin
79
76
80 elsif(clkm' event and clkm='1')then
77 elsif(clkm' event and clkm='1')then
81 Write_reg <= Matrix_Write;
78 Write_reg <= Matrix_Write;
82 pong_reg <= pong;
83
79
84 if(Statu="0001" or Statu="0011" or Statu="0110" or Statu="1010" or Statu="1111")then
80 if(Statu="0001" or Statu="0011" or Statu="0110" or Statu="1010" or Statu="1111")then
85 MAX <= 128;
81 MAX <= 128;
@@ -87,17 +83,6 begin
87 MAX <= 256;
83 MAX <= 256;
88 end if;
84 end if;
89
85
90 -- if(Write_reg = '0' and Matrix_Write = '1')then
91 -- if(Data_cpt = MAX)then
92 -- Data_cpt <= 0;
93 -- Valid <= '1';
94 -- header_val <= '1';
95 -- else
96 -- Data_cpt <= Data_cpt + 1;
97 -- Valid <= '0';
98 -- end if;
99 -- end if;
100
101 if(Write_reg = '0' and Matrix_Write = '1')then
86 if(Write_reg = '0' and Matrix_Write = '1')then
102 Data_cpt <= Data_cpt + 1;
87 Data_cpt <= Data_cpt + 1;
103 Valid <= '0';
88 Valid <= '0';
@@ -107,19 +92,7 begin
107 header_val <= '1';
92 header_val <= '1';
108 else
93 else
109 Valid <= '0';
94 Valid <= '0';
110 end if;
95 end if;
111
112 -- if(header_ack = '1')then
113 -- header_val <= '0';
114 -- end if;
115
116 -- if(emptyIN = "10")then
117 -- ping <= '0';
118 -- elsif(emptyIN = "01")then
119 -- ping <= '1';
120 -- else
121 -- ping <= ping;
122 -- end if;
123
96
124
97
125 case ect is
98 case ect is
@@ -127,11 +100,7 begin
127 when idle0 =>
100 when idle0 =>
128 if(header_ack = '1')then
101 if(header_ack = '1')then
129 header_val <= '0';
102 header_val <= '0';
130 --if(pong = '1')then
103 ect <= pong0;
131 ect <= pong0;
132 --elsif(pong = '0')then
133 --ect <= pong1;
134 --end if;
135 end if;
104 end if;
136
105
137 when pong0 =>
106 when pong0 =>
@@ -160,8 +129,6 begin
160
129
161 Matrix_Param <= std_logic_vector(to_unsigned(to_integer(unsigned(Statu))-1,4));
130 Matrix_Param <= std_logic_vector(to_unsigned(to_integer(unsigned(Statu))-1,4));
162
131
163 --header(1 downto 0) <= Matrix_Type;
164 --header(5 downto 2) <= Matrix_Param;
165 header(31 downto 6) <= (others => '0');
132 header(31 downto 6) <= (others => '0');
166
133
167 with ect select
134 with ect select
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@@ -38,7 +38,6 component HeaderBuilder is
38 clkm : in std_logic;
38 clkm : in std_logic;
39 rstn : in std_logic;
39 rstn : in std_logic;
40
40
41 pong : in std_logic;
42 Statu : in std_logic_vector(3 downto 0);
41 Statu : in std_logic_vector(3 downto 0);
43 Matrix_Type : in std_logic_vector(1 downto 0);
42 Matrix_Type : in std_logic_vector(1 downto 0);
44 Matrix_Write : in std_logic;
43 Matrix_Write : in std_logic;
Show file before | Show file after | Hide comments
@@ -31,7 +31,7 use lpp.lpp_amba.all;
31
31
32 package lpp_cna is
32 package lpp_cna is
33
33
34 component APB_CNA is
34 component APB_DAC is
35 generic (
35 generic (
36 pindex : integer := 0;
36 pindex : integer := 0;
37 paddr : integer := 0;
37 paddr : integer := 0;
@@ -43,6 +43,7 component APB_CNA is
43 rst : in std_logic;
43 rst : in std_logic;
44 apbi : in apb_slv_in_type;
44 apbi : in apb_slv_in_type;
45 apbo : out apb_slv_out_type;
45 apbo : out apb_slv_out_type;
46 Cal_EN : out std_logic;
46 SYNC : out std_logic;
47 SYNC : out std_logic;
47 SCLK : out std_logic;
48 SCLK : out std_logic;
48 DATA : out std_logic
49 DATA : out std_logic
@@ -50,9 +51,9 component APB_CNA is
50 end component;
51 end component;
51
52
52
53
53 component CNA_TabloC is
54 component DacDriver is
54 port(
55 port(
55 clock : in std_logic;
56 clk : in std_logic;
56 rst : in std_logic;
57 rst : in std_logic;
57 enable : in std_logic;
58 enable : in std_logic;
58 Data_C : in std_logic_vector(15 downto 0);
59 Data_C : in std_logic_vector(15 downto 0);
Show file before | Show file after | Hide comments
@@ -29,14 +29,12 generic(
29 port(
29 port(
30 clk : in std_logic;
30 clk : in std_logic;
31 reset : in std_logic;
31 reset : in std_logic;
32 Acq : in std_logic;
32 Ack : in std_logic;
33 Data : in std_logic_vector(Data_SZ-1 downto 0);
33 Data : in std_logic_vector(Data_SZ-1 downto 0);
34 Write : in std_logic;
34 Write : in std_logic;
35 Valid : in std_logic;
35 Valid : in std_logic;
36 -- Full : in std_logic_vector(1 downto 0);
37 FifoData : out std_logic_vector(2*Data_SZ-1 downto 0);
36 FifoData : out std_logic_vector(2*Data_SZ-1 downto 0);
38 FifoWrite : out std_logic_vector(1 downto 0);
37 FifoWrite : out std_logic_vector(1 downto 0);
39 Pong : out std_logic;
40 Error : out std_logic
38 Error : out std_logic
41 );
39 );
42 end entity;
40 end entity;
@@ -47,15 +45,14 architecture ar_Dispatch of Dispatch is
47 type etat is (eX,e0,e1,e2);
45 type etat is (eX,e0,e1,e2);
48 signal ect : etat;
46 signal ect : etat;
49
47
50 signal Pong_int : std_logic;
48 signal Pong : std_logic;
51 --signal FifoCpt : integer range 0 to 1 := 0;
52
49
53 begin
50 begin
54
51
55 process (clk,reset)
52 process (clk,reset)
56 begin
53 begin
57 if(reset='0')then
54 if(reset='0')then
58 Pong_int <= '0';
55 Pong <= '0';
59 Error <= '0';
56 Error <= '0';
60 ect <= e0;
57 ect <= e0;
61
58
@@ -64,14 +61,13 begin
64 case ect is
61 case ect is
65
62
66 when e0 =>
63 when e0 =>
67 -- if(Full(FifoCpt) = '1')then
68 if(Valid = '1')then
64 if(Valid = '1')then
69 Pong_int <= not Pong_int;
65 Pong <= not Pong;
70 ect <= e1;
66 ect <= e1;
71 end if;
67 end if;
72
68
73 when e1 =>
69 when e1 =>
74 if(Acq = '0')then
70 if(Ack = '0')then
75 Error <= '1';
71 Error <= '1';
76 ect <= e1;
72 ect <= e1;
77 else
73 else
@@ -80,7 +76,7 begin
80 end if;
76 end if;
81
77
82 when others =>
78 when others =>
83 null;
79 null;
84
80
85 end case;
81 end case;
86
82
@@ -88,10 +84,6 begin
88 end process;
84 end process;
89
85
90 FifoData <= Data & Data;
86 FifoData <= Data & Data;
91 Pong <= Pong_int;
87 FifoWrite <= '1' & not Write when Pong='0' else not Write & '1';
92
93 --FifoCpt <= 0 when Pong_int='0' else 1;
94
95 FifoWrite <= '1' & not Write when Pong_int='0' else not Write & '1';
96
88
97 end architecture; No newline at end of file
89 end architecture;
Show file before | Show file after | Hide comments
@@ -35,13 +35,11 entity MatriceSpectrale is
35
35
36 FifoIN_Full : in std_logic_vector(4 downto 0);
36 FifoIN_Full : in std_logic_vector(4 downto 0);
37 SetReUse : in std_logic_vector(4 downto 0);
37 SetReUse : in std_logic_vector(4 downto 0);
38 -- FifoOUT_Full : in std_logic_vector(1 downto 0);
39 Valid : in std_logic;
38 Valid : in std_logic;
40 Data_IN : in std_logic_vector((5*Input_SZ)-1 downto 0);
39 Data_IN : in std_logic_vector((5*Input_SZ)-1 downto 0);
41 ACQ : in std_logic;
40 ACK : in std_logic;
42 SM_Write : out std_logic;
41 SM_Write : out std_logic;
43 FlagError : out std_logic;
42 FlagError : out std_logic;
44 Pong : out std_logic;
45 Statu : out std_logic_vector(3 downto 0);
43 Statu : out std_logic_vector(3 downto 0);
46 Write : out std_logic_vector(1 downto 0);
44 Write : out std_logic_vector(1 downto 0);
47 Read : out std_logic_vector(4 downto 0);
45 Read : out std_logic_vector(4 downto 0);
@@ -78,7 +76,7 begin
78
76
79 DISP : Dispatch
77 DISP : Dispatch
80 generic map(Result_SZ)
78 generic map(Result_SZ)
81 port map(clkm,rstn,ACQ,Matrix_Result,Matrix_Write,Valid,Data_OUT,Write,Pong,FlagError);
79 port map(clkm,rstn,ACK,Matrix_Result,Matrix_Write,Valid,Data_OUT,Write,FlagError);
82
80
83 Statu <= TopSM_Statu;
81 Statu <= TopSM_Statu;
84 SM_Write <= Matrix_Write;
82 SM_Write <= Matrix_Write;
Show file before | Show file after | Hide comments
@@ -66,13 +66,11 component MatriceSpectrale is
66
66
67 FifoIN_Full : in std_logic_vector(4 downto 0);
67 FifoIN_Full : in std_logic_vector(4 downto 0);
68 SetReUse : in std_logic_vector(4 downto 0);
68 SetReUse : in std_logic_vector(4 downto 0);
69 -- FifoOUT_Full : in std_logic_vector(1 downto 0);
70 Valid : in std_logic;
69 Valid : in std_logic;
71 Data_IN : in std_logic_vector((5*Input_SZ)-1 downto 0);
70 Data_IN : in std_logic_vector((5*Input_SZ)-1 downto 0);
72 ACQ : in std_logic;
71 ACK : in std_logic;
73 SM_Write : out std_logic;
72 SM_Write : out std_logic;
74 FlagError : out std_logic;
73 FlagError : out std_logic;
75 Pong : out std_logic;
76 Statu : out std_logic_vector(3 downto 0);
74 Statu : out std_logic_vector(3 downto 0);
77 Write : out std_logic_vector(1 downto 0);
75 Write : out std_logic_vector(1 downto 0);
78 Read : out std_logic_vector(4 downto 0);
76 Read : out std_logic_vector(4 downto 0);
@@ -199,14 +197,12 generic(
199 port(
197 port(
200 clk : in std_logic;
198 clk : in std_logic;
201 reset : in std_logic;
199 reset : in std_logic;
202 Acq : in std_logic;
200 Ack : in std_logic;
203 Data : in std_logic_vector(Data_SZ-1 downto 0);
201 Data : in std_logic_vector(Data_SZ-1 downto 0);
204 Write : in std_logic;
202 Write : in std_logic;
205 Valid : in std_logic;
203 Valid : in std_logic;
206 -- Full : in std_logic_vector(1 downto 0);
207 FifoData : out std_logic_vector(2*Data_SZ-1 downto 0);
204 FifoData : out std_logic_vector(2*Data_SZ-1 downto 0);
208 FifoWrite : out std_logic_vector(1 downto 0);
205 FifoWrite : out std_logic_vector(1 downto 0);
209 Pong : out std_logic;
210 Error : out std_logic
206 Error : out std_logic
211 );
207 );
212 end component;
208 end component;
Show file before | Show file after | Hide comments
@@ -1,66 +1,65
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
21 ------------------------------------------------------------------------------
22 library IEEE;
22 library IEEE;
23 use IEEE.std_logic_1164.all;
23 use IEEE.std_logic_1164.all;
24 use IEEE.numeric_std.all;
24 use IEEE.numeric_std.all;
25 library lpp;
25 library lpp;
26 use lpp.lpp_memory.all;
26 use lpp.lpp_memory.all;
27 use lpp.iir_filter.all;
27 use lpp.iir_filter.all;
28 library techmap;
28 library techmap;
29 use techmap.gencomp.all;
29 use techmap.gencomp.all;
30
30
31 entity lppFIFOxN is
31 entity lppFIFOxN is
32 generic(
32 generic(
33 tech : integer := 0;
33 tech : integer := 0;
34 Mem_use : integer := use_RAM;
34 Mem_use : integer := use_RAM;
35 Data_sz : integer range 1 to 32 := 8;
35 Data_sz : integer range 1 to 32 := 8;
36 Addr_sz : integer range 1 to 32 := 8;
36 Addr_sz : integer range 2 to 12 := 8;
37 FifoCnt : integer := 1;
37 FifoCnt : integer := 1;
38 Enable_ReUse : std_logic := '0'
38 Enable_ReUse : std_logic := '0'
39 );
39 );
40 port(
40 port(
41 rst : in std_logic;
41 rstn : in std_logic;
42 wclk : in std_logic;
42 wclk : in std_logic;
43 rclk : in std_logic;
43 rclk : in std_logic;
44 ReUse : in std_logic_vector(FifoCnt-1 downto 0);
44 ReUse : in std_logic_vector(FifoCnt-1 downto 0);
45 wen : in std_logic_vector(FifoCnt-1 downto 0);
45 wen : in std_logic_vector(FifoCnt-1 downto 0);
46 ren : in std_logic_vector(FifoCnt-1 downto 0);
46 ren : in std_logic_vector(FifoCnt-1 downto 0);
47 wdata : in std_logic_vector((FifoCnt*Data_sz)-1 downto 0);
47 wdata : in std_logic_vector((FifoCnt*Data_sz)-1 downto 0);
48 rdata : out std_logic_vector((FifoCnt*Data_sz)-1 downto 0);
48 rdata : out std_logic_vector((FifoCnt*Data_sz)-1 downto 0);
49 full : out std_logic_vector(FifoCnt-1 downto 0);
49 full : out std_logic_vector(FifoCnt-1 downto 0);
50 empty : out std_logic_vector(FifoCnt-1 downto 0)
50 empty : out std_logic_vector(FifoCnt-1 downto 0)
51 );
51 );
52 end entity;
52 end entity;
53
53
54
54
55 architecture ar_lppFIFOxN of lppFIFOxN is
55 architecture ar_lppFIFOxN of lppFIFOxN is
56
56
57 begin
57 begin
58
58
59 fifos: for i in 0 to FifoCnt-1 generate
59 fifos: for i in 0 to FifoCnt-1 generate
60 FIFO0 : lpp_fifo
60 FIFO0 : lpp_fifo
61 generic map (tech,Mem_use,Enable_ReUse,Data_sz,Addr_sz)
61 generic map (tech,Mem_use,Enable_ReUse,Data_sz,Addr_sz)
62 port map(rst,ReUse(i),rclk,ren(i),rdata((i+1)*Data_sz-1 downto i*Data_sz),empty(i),open,wclk,wen(i),wdata((i+1)*Data_sz-1 downto i*Data_sz),full(i),open);
62 port map(rstn,ReUse(i),rclk,ren(i),rdata((i+1)*Data_sz-1 downto i*Data_sz),empty(i),open,wclk,wen(i),wdata((i+1)*Data_sz-1 downto i*Data_sz),full(i),open);
63 end generate;
63 end generate;
64
64
65 end architecture;
65 end architecture;
66
Show file before | Show file after | Hide comments
@@ -34,7 +34,7 generic(
34 Mem_use : integer := use_RAM;
34 Mem_use : integer := use_RAM;
35 Enable_ReUse : std_logic := '0';
35 Enable_ReUse : std_logic := '0';
36 DataSz : integer range 1 to 32 := 8;
36 DataSz : integer range 1 to 32 := 8;
37 abits : integer range 2 to 12 := 8
37 AddrSz : integer range 2 to 12 := 8
38 );
38 );
39 port(
39 port(
40 rstn : in std_logic;
40 rstn : in std_logic;
@@ -43,12 +43,12 port(
43 ren : in std_logic;
43 ren : in std_logic;
44 rdata : out std_logic_vector(DataSz-1 downto 0);
44 rdata : out std_logic_vector(DataSz-1 downto 0);
45 empty : out std_logic;
45 empty : out std_logic;
46 raddr : out std_logic_vector(abits-1 downto 0);
46 raddr : out std_logic_vector(AddrSz-1 downto 0);
47 wclk : in std_logic;
47 wclk : in std_logic;
48 wen : in std_logic;
48 wen : in std_logic;
49 wdata : in std_logic_vector(DataSz-1 downto 0);
49 wdata : in std_logic_vector(DataSz-1 downto 0);
50 full : out std_logic;
50 full : out std_logic;
51 waddr : out std_logic_vector(abits-1 downto 0)
51 waddr : out std_logic_vector(AddrSz-1 downto 0)
52 );
52 );
53 end entity;
53 end entity;
54
54
@@ -65,10 +65,10 signal sWEN : std_logic;
65 signal sRE : std_logic;
65 signal sRE : std_logic;
66 signal sWE : std_logic;
66 signal sWE : std_logic;
67
67
68 signal Waddr_vect : std_logic_vector(abits-1 downto 0):=(others =>'0');
68 signal Waddr_vect : std_logic_vector(AddrSz-1 downto 0):=(others =>'0');
69 signal Raddr_vect : std_logic_vector(abits-1 downto 0):=(others =>'0');
69 signal Raddr_vect : std_logic_vector(AddrSz-1 downto 0):=(others =>'0');
70 signal Waddr_vect_s : std_logic_vector(abits-1 downto 0):=(others =>'0');
70 signal Waddr_vect_s : std_logic_vector(AddrSz-1 downto 0):=(others =>'0');
71 signal Raddr_vect_s : std_logic_vector(abits-1 downto 0):=(others =>'0');
71 signal Raddr_vect_s : std_logic_vector(AddrSz-1 downto 0):=(others =>'0');
72
72
73 begin
73 begin
74
74
@@ -78,13 +78,13 begin
78 --==================================================================================
78 --==================================================================================
79 memRAM : IF Mem_use = use_RAM GENERATE
79 memRAM : IF Mem_use = use_RAM GENERATE
80 SRAM : syncram_2p
80 SRAM : syncram_2p
81 generic map(tech,abits,DataSz)
81 generic map(tech,AddrSz,DataSz)
82 port map(RCLK,sRE,Raddr_vect,rdata,WCLK,sWE,Waddr_vect,wdata);
82 port map(RCLK,sRE,Raddr_vect,rdata,WCLK,sWE,Waddr_vect,wdata);
83 END GENERATE;
83 END GENERATE;
84 --==================================================================================
84 --==================================================================================
85 memCEL : IF Mem_use = use_CEL GENERATE
85 memCEL : IF Mem_use = use_CEL GENERATE
86 CRAM : RAM_CEL
86 CRAM : RAM_CEL
87 generic map(DataSz,abits)
87 generic map(DataSz,AddrSz)
88 port map(wdata, rdata, sWEN, sREN, Waddr_vect, Raddr_vect, WCLK, rstn);
88 port map(wdata, rdata, sWEN, sREN, Waddr_vect, Raddr_vect, WCLK, rstn);
89 END GENERATE;
89 END GENERATE;
90 --==================================================================================
90 --==================================================================================
@@ -177,4 +177,3 end architecture;
177
177
178
178
179
179
180
Show file before | Show file after | Hide comments
@@ -1,186 +1,186
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
21 ------------------------------------------------------------------------------
22 library ieee;
22 library ieee;
23 use ieee.std_logic_1164.all;
23 use ieee.std_logic_1164.all;
24 library grlib;
24 library grlib;
25 use grlib.amba.all;
25 use grlib.amba.all;
26 use std.textio.all;
26 use std.textio.all;
27 library lpp;
27 library lpp;
28 use lpp.lpp_amba.all;
28 use lpp.lpp_amba.all;
29 use lpp.iir_filter.all;
29 use lpp.iir_filter.all;
30 library gaisler;
30 library gaisler;
31 use gaisler.misc.all;
31 use gaisler.misc.all;
32 use gaisler.memctrl.all;
32 use gaisler.memctrl.all;
33 library techmap;
33 library techmap;
34 use techmap.gencomp.all;
34 use techmap.gencomp.all;
35
35
36 --! Package contenant tous les programmes qui forment le composant int�gr� dans le l�on
36 --! Package contenant tous les programmes qui forment le composant int�gr� dans le l�on
37
37
38 package lpp_memory is
38 package lpp_memory is
39
39
40 component APB_FIFO is
40 component APB_FIFO is
41 generic (
41 generic (
42 tech : integer := apa3;
42 tech : integer := apa3;
43 pindex : integer := 0;
43 pindex : integer := 0;
44 paddr : integer := 0;
44 paddr : integer := 0;
45 pmask : integer := 16#fff#;
45 pmask : integer := 16#fff#;
46 pirq : integer := 0;
46 pirq : integer := 0;
47 abits : integer := 8;
47 abits : integer := 8;
48 FifoCnt : integer := 2;
48 FifoCnt : integer := 2;
49 Data_sz : integer := 16;
49 Data_sz : integer := 16;
50 Addr_sz : integer := 9;
50 Addr_sz : integer := 9;
51 Enable_ReUse : std_logic := '0';
51 Enable_ReUse : std_logic := '0';
52 Mem_use : integer := use_RAM;
52 Mem_use : integer := use_RAM;
53 R : integer := 1;
53 R : integer := 1;
54 W : integer := 1
54 W : integer := 1
55 );
55 );
56 port (
56 port (
57 clk : in std_logic; --! Horloge du composant
57 clk : in std_logic; --! Horloge du composant
58 rst : in std_logic; --! Reset general du composant
58 rst : in std_logic; --! Reset general du composant
59 rclk : in std_logic;
59 rclk : in std_logic;
60 wclk : in std_logic;
60 wclk : in std_logic;
61 ReUse : in std_logic_vector(FifoCnt-1 downto 0);
61 ReUse : in std_logic_vector(FifoCnt-1 downto 0);
62 REN : in std_logic_vector(FifoCnt-1 downto 0); --! Instruction de lecture en m�moire
62 REN : in std_logic_vector(FifoCnt-1 downto 0); --! Instruction de lecture en m�moire
63 WEN : in std_logic_vector(FifoCnt-1 downto 0); --! Instruction d'�criture en m�moire
63 WEN : in std_logic_vector(FifoCnt-1 downto 0); --! Instruction d'�criture en m�moire
64 Empty : out std_logic_vector(FifoCnt-1 downto 0); --! Flag, M�moire vide
64 Empty : out std_logic_vector(FifoCnt-1 downto 0); --! Flag, M�moire vide
65 Full : out std_logic_vector(FifoCnt-1 downto 0); --! Flag, M�moire pleine
65 Full : out std_logic_vector(FifoCnt-1 downto 0); --! Flag, M�moire pleine
66 RDATA : out std_logic_vector((FifoCnt*Data_sz)-1 downto 0); --! Registre de donn�es en entr�e
66 RDATA : out std_logic_vector((FifoCnt*Data_sz)-1 downto 0); --! Registre de donn�es en entr�e
67 WDATA : in std_logic_vector((FifoCnt*Data_sz)-1 downto 0); --! Registre de donn�es en sortie
67 WDATA : in std_logic_vector((FifoCnt*Data_sz)-1 downto 0); --! Registre de donn�es en sortie
68 WADDR : out std_logic_vector((FifoCnt*Addr_sz)-1 downto 0); --! Registre d'addresse (�criture)
68 WADDR : out std_logic_vector((FifoCnt*Addr_sz)-1 downto 0); --! Registre d'addresse (�criture)
69 RADDR : out std_logic_vector((FifoCnt*Addr_sz)-1 downto 0); --! Registre d'addresse (lecture)
69 RADDR : out std_logic_vector((FifoCnt*Addr_sz)-1 downto 0); --! Registre d'addresse (lecture)
70 apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus
70 apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus
71 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
71 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
72 );
72 );
73 end component;
73 end component;
74
74
75 component FIFO_pipeline is
75 component FIFO_pipeline is
76 generic(
76 generic(
77 tech : integer := 0;
77 tech : integer := 0;
78 Mem_use : integer := use_RAM;
78 Mem_use : integer := use_RAM;
79 fifoCount : integer range 2 to 32 := 8;
79 fifoCount : integer range 2 to 32 := 8;
80 DataSz : integer range 1 to 32 := 8;
80 DataSz : integer range 1 to 32 := 8;
81 abits : integer range 2 to 12 := 8
81 abits : integer range 2 to 12 := 8
82 );
82 );
83 port(
83 port(
84 rstn : in std_logic;
84 rstn : in std_logic;
85 ReUse : in std_logic;
85 ReUse : in std_logic;
86 rclk : in std_logic;
86 rclk : in std_logic;
87 ren : in std_logic;
87 ren : in std_logic;
88 rdata : out std_logic_vector(DataSz-1 downto 0);
88 rdata : out std_logic_vector(DataSz-1 downto 0);
89 empty : out std_logic;
89 empty : out std_logic;
90 raddr : out std_logic_vector(abits-1 downto 0);
90 raddr : out std_logic_vector(abits-1 downto 0);
91 wclk : in std_logic;
91 wclk : in std_logic;
92 wen : in std_logic;
92 wen : in std_logic;
93 wdata : in std_logic_vector(DataSz-1 downto 0);
93 wdata : in std_logic_vector(DataSz-1 downto 0);
94 full : out std_logic;
94 full : out std_logic;
95 waddr : out std_logic_vector(abits-1 downto 0)
95 waddr : out std_logic_vector(abits-1 downto 0)
96 );
96 );
97 end component;
97 end component;
98
98
99 component lpp_fifo is
99 component lpp_fifo is
100 generic(
100 generic(
101 tech : integer := 0;
101 tech : integer := 0;
102 Mem_use : integer := use_RAM;
102 Mem_use : integer := use_RAM;
103 Enable_ReUse : std_logic := '0';
103 Enable_ReUse : std_logic := '0';
104 DataSz : integer range 1 to 32 := 8;
104 DataSz : integer range 1 to 32 := 8;
105 abits : integer range 2 to 12 := 8
105 AddrSz : integer range 2 to 12 := 8
106 );
106 );
107 port(
107 port(
108 rstn : in std_logic;
108 rstn : in std_logic;
109 ReUse : in std_logic; --27/01/12
109 ReUse : in std_logic; --27/01/12
110 rclk : in std_logic;
110 rclk : in std_logic;
111 ren : in std_logic;
111 ren : in std_logic;
112 rdata : out std_logic_vector(DataSz-1 downto 0);
112 rdata : out std_logic_vector(DataSz-1 downto 0);
113 empty : out std_logic;
113 empty : out std_logic;
114 raddr : out std_logic_vector(abits-1 downto 0);
114 raddr : out std_logic_vector(AddrSz-1 downto 0);
115 wclk : in std_logic;
115 wclk : in std_logic;
116 wen : in std_logic;
116 wen : in std_logic;
117 wdata : in std_logic_vector(DataSz-1 downto 0);
117 wdata : in std_logic_vector(DataSz-1 downto 0);
118 full : out std_logic;
118 full : out std_logic;
119 waddr : out std_logic_vector(abits-1 downto 0)
119 waddr : out std_logic_vector(AddrSz-1 downto 0)
120 );
120 );
121 end component;
121 end component;
122
122
123
123
124 component lppFIFOxN is
124 component lppFIFOxN is
125 generic(
125 generic(
126 tech : integer := 0;
126 tech : integer := 0;
127 Mem_use : integer := use_RAM;
127 Mem_use : integer := use_RAM;
128 Data_sz : integer range 1 to 32 := 8;
128 Data_sz : integer range 1 to 32 := 8;
129 Addr_sz : integer range 1 to 32 := 8;
129 Addr_sz : integer range 1 to 32 := 8;
130 FifoCnt : integer := 1;
130 FifoCnt : integer := 1;
131 Enable_ReUse : std_logic := '0'
131 Enable_ReUse : std_logic := '0'
132 );
132 );
133 port(
133 port(
134 rst : in std_logic;
134 rstn : in std_logic;
135 wclk : in std_logic;
135 wclk : in std_logic;
136 rclk : in std_logic;
136 rclk : in std_logic;
137 ReUse : in std_logic_vector(FifoCnt-1 downto 0);
137 ReUse : in std_logic_vector(FifoCnt-1 downto 0);
138 wen : in std_logic_vector(FifoCnt-1 downto 0);
138 wen : in std_logic_vector(FifoCnt-1 downto 0);
139 ren : in std_logic_vector(FifoCnt-1 downto 0);
139 ren : in std_logic_vector(FifoCnt-1 downto 0);
140 wdata : in std_logic_vector((FifoCnt*Data_sz)-1 downto 0);
140 wdata : in std_logic_vector((FifoCnt*Data_sz)-1 downto 0);
141 rdata : out std_logic_vector((FifoCnt*Data_sz)-1 downto 0);
141 rdata : out std_logic_vector((FifoCnt*Data_sz)-1 downto 0);
142 full : out std_logic_vector(FifoCnt-1 downto 0);
142 full : out std_logic_vector(FifoCnt-1 downto 0);
143 empty : out std_logic_vector(FifoCnt-1 downto 0)
143 empty : out std_logic_vector(FifoCnt-1 downto 0)
144 );
144 );
145 end component;
145 end component;
146
146
147 component FillFifo is
147 component FillFifo is
148 generic(
148 generic(
149 Data_sz : integer range 1 to 32 := 16;
149 Data_sz : integer range 1 to 32 := 16;
150 Fifo_cnt : integer range 1 to 8 := 5
150 Fifo_cnt : integer range 1 to 8 := 5
151 );
151 );
152 port(
152 port(
153 clk : in std_logic;
153 clk : in std_logic;
154 raz : in std_logic;
154 raz : in std_logic;
155 write : out std_logic_vector(Fifo_cnt-1 downto 0);
155 write : out std_logic_vector(Fifo_cnt-1 downto 0);
156 reuse : out std_logic_vector(Fifo_cnt-1 downto 0);
156 reuse : out std_logic_vector(Fifo_cnt-1 downto 0);
157 data : out std_logic_vector(Fifo_cnt*Data_sz-1 downto 0)
157 data : out std_logic_vector(Fifo_cnt*Data_sz-1 downto 0)
158 );
158 );
159 end component;
159 end component;
160
160
161 component ssram_plugin is
161 component ssram_plugin is
162 generic (tech : integer := 0);
162 generic (tech : integer := 0);
163 port
163 port
164 (
164 (
165 clk : in std_logic;
165 clk : in std_logic;
166 mem_ctrlr_o : in memory_out_type;
166 mem_ctrlr_o : in memory_out_type;
167 SSRAM_CLK : out std_logic;
167 SSRAM_CLK : out std_logic;
168 nBWa : out std_logic;
168 nBWa : out std_logic;
169 nBWb : out std_logic;
169 nBWb : out std_logic;
170 nBWc : out std_logic;
170 nBWc : out std_logic;
171 nBWd : out std_logic;
171 nBWd : out std_logic;
172 nBWE : out std_logic;
172 nBWE : out std_logic;
173 nADSC : out std_logic;
173 nADSC : out std_logic;
174 nADSP : out std_logic;
174 nADSP : out std_logic;
175 nADV : out std_logic;
175 nADV : out std_logic;
176 nGW : out std_logic;
176 nGW : out std_logic;
177 nCE1 : out std_logic;
177 nCE1 : out std_logic;
178 CE2 : out std_logic;
178 CE2 : out std_logic;
179 nCE3 : out std_logic;
179 nCE3 : out std_logic;
180 nOE : out std_logic;
180 nOE : out std_logic;
181 MODE : out std_logic;
181 MODE : out std_logic;
182 ZZ : out std_logic
182 ZZ : out std_logic
183 );
183 );
184 end component;
184 end component;
185
185
186 end;
186 end; No newline at end of file
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