diff --git a/LPP_drivers/exemples/BenchDAC_CAL/Makefile b/LPP_drivers/exemples/BenchDAC_CAL/Makefile new file mode 100644 --- /dev/null +++ b/LPP_drivers/exemples/BenchDAC_CAL/Makefile @@ -0,0 +1,44 @@ +#------------------------------------------------------------------------------ +#-- This file is a part of the LPP VHDL IP LIBRARY +#-- Copyright (C) 2010, Laboratory of Plasmas Physic - CNRS +#-- +#-- This program is free software; you can redistribute it and/or modify +#-- it under the terms of the GNU General Public License as published by +#-- the Free Software Foundation; either version 3 of the License, or +#-- (at your option) any later version. +#-- +#-- This program is distributed in the hope that it will be useful, +#-- but WITHOUT ANY WARRANTY; without even the implied warranty of +#-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +#-- GNU General Public License for more details. +#-- +#-- You should have received a copy of the GNU General Public License +#-- along with this program; if not, write to the Free Software +#-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +#------------------------------------------------------------------------------ + +include ../../rules.mk +LIBDIR = ../../lib +INCPATH = ../../includes +SCRIPTDIR=../../scripts/ +LIBS=-lapb_dac_Driver -llpp_apb_functions +INPUTFILE=main.c +EXEC=BenchDAC_CAL.bin +OUTBINDIR=bin/ + + +.PHONY:bin + +all:bin + @echo $(EXEC)" file created" + +clean: + rm -f *.{o,a} + + + +help:ruleshelp + @echo " all : makes an executable file called "$(EXEC) + @echo " in "$(OUTBINDIR) + @echo " clean : removes temporary files" + diff --git a/LPP_drivers/exemples/BenchDAC_CAL/main.c b/LPP_drivers/exemples/BenchDAC_CAL/main.c new file mode 100644 --- /dev/null +++ b/LPP_drivers/exemples/BenchDAC_CAL/main.c @@ -0,0 +1,25 @@ +#include +#include "lpp_apb_functions.h" +#include "apb_dac_Driver.h" + +int main() +{ + printf("\nDebut Main\n\n"); + int i; + int tablo CAL_SignalData + + DAC_Device* dac0 = openDAC(0); + + printf("\nSTART\n\n"); + + while(1) + { + for (i = 0 ; i < 251 ; i++) + { + while(!((dac0->ConfigReg & DAC_ready) == DAC_ready)); + dac0->DataReg = tablo[i]; + while((dac0->ConfigReg & DAC_ready) == DAC_ready); + } + } + return 0; +} diff --git a/LPP_drivers/exemples/Makefile b/LPP_drivers/exemples/Makefile --- a/LPP_drivers/exemples/Makefile +++ b/LPP_drivers/exemples/Makefile @@ -27,4 +27,5 @@ all: make all -C BenchFFT make all -C BenchGPIO make all -C BenchMatrix - make all -C BenchFFT+Matrix \ No newline at end of file + make all -C BenchFFT+Matrix + make all -C BenchDAC_CAL \ No newline at end of file diff --git a/LPP_drivers/includes/apb_dac_Driver.h b/LPP_drivers/includes/apb_dac_Driver.h --- a/LPP_drivers/includes/apb_dac_Driver.h +++ b/LPP_drivers/includes/apb_dac_Driver.h @@ -1,34 +1,42 @@ -/*------------------------------------------------------------------------------ --- This file is a part of the LPP VHDL IP LIBRARY --- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program; if not, write to the Free Software --- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -------------------------------------------------------------------------------- --- Author : Martin Morlot --- Mail : martin.morlot@lpp.polytechnique.fr ------------------------------------------------------------------------------*/ -#ifndef APB_CNA_DRIVER_H -#define APB_CNA_DRIVER_H +/*------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Martin Morlot +-- Mail : martin.morlot@lpp.polytechnique.fr +-----------------------------------------------------------------------------*/ +#ifndef APB_CNA_DRIVER_H +#define APB_CNA_DRIVER_H #define DAC_ready 3 #define DAC_enable 1 -#define DAC_disable 0 - +#define DAC_disable 0 -/*=================================================== - T Y P E S D E F +#define CAL_SignalData [251] = {0x9555,0x1800,0x19AA,0x1B15,0x1C0A,0x1C66,0x1C1F,0x1B44,0x19FC,0x187F,0x170F,0x15EA,0x1542,0x1537,0x15CE,0x16F2,0x187A,0x1A2B,0x1BC2,0x1D04,0x1DBF,0x1DDB,0x1D56,0x1C49,0x1AE3,0x195F,0x1800,0x1700,0x168D,0x16BA,0x1785,0x18D0,0x1A69,0x1C12,0x1D8A,0x1E98,0x1F13,\ + 0x1EEB,0x1E28,0x1CEC,0x1FFF,0x19E8,0x189F,0x17C8,0x1788,0x17EA,0x18E2,0x1A48,0x1BE7,0x1D7C,0x1ECA,0x1F9C,0x1FD2,0x1F64,0x1E66,0x1D00,0x1B6E,0x19EF,0x18C1,0x1817,0x180A,0x189D,0x19BA,0x1B33,0x1CCC,0x1E44,0x1F5F,0x1FEE,0x1FDC,0x1F2B,0x1DF6,0x1C6E,0x1AD1,0x1960,0x1855,0x17D9,0x1800,\ + 0x18C1,0x19FD,0x1B80,0x1D0A,0x1E5C,0x1F3D,0x1F87,0x1F2E,0x1E3E,0x1CDA,0x1B39,0x199C,0x1842,0x1760,0x1717,0x1771,0x185D,0x19B1,0x1B36,0x1CAA,0x1DCF,0x1E73,0x1E79,0x1DDD,0x1CB4,0x1B2B,0x197C,0x17EA,0x16B1,0x15FF,0x15EE,0x167C,0x178F,0x18F7,0x1A78,0x1BCF,0x1CC4,0x1D2A,0x1CED,0x1C14,\ + 0x1ABC,0x191A,0x176B,0x15F0,0x14E2,0x1467,0x1490,0x1552,0x1689,0x1800,0x1977,0x1AAE,0x1B70,0x1B99,0x1B1E,0x1A10,0x1895,0x16E6,0x1544,0x13EC,0x1313,0x12D6,0x133C,0x1431,0x1588,0x1709,0x1871,0x1984,0x1A12,0x1A01,0x194F,0x1816,0x1684,0x14D5,0x134C,0x1223,0x1187,0x118D,0x1231,0x1356,\ + 0x14CA,0x164F,0x17A3,0x188F,0x18E9,0x18A0,0x17BE,0x1664,0x14C7,0x1326,0x11C2,0x10D2,0x1079,0x10C3,0x11A4,0x12F6,0x1480,0x1603,0x173F,0x1800,0x1827,0x17AB,0x16A0,0x152F,0x1392,0x120A,0x10D5,0x1024,0x1012,0x10A1,0x11BC,0x1334,0x14CD,0x1646,0x1763,0x17F6,0x17E9,0x173F,0x1611,0x1492,\ + 0x1300,0x119A,0x109C,0x102E,0x1064,0x1136,0x1284,0x1419,0x15B8,0x171E,0x1816,0x1878,0x1838,0x1761,0x1618,0x1494,0x1314,0x11D8,0x1115,0x10ED,0x1168,0x1276,0x13EE,0x1597,0x1730,0x187B,0x1946,0x1973,0x1900,0x1800,0x16A1,0x151D,0x13B7,0x12AA,0x1225,0x1241,0x12FC,0x143E,0x15D5,0x1786,\ + 0x190E,0x1A32,0x1AC9,0x1ABE,0x1A16,0x18F1,0x1781,0x1604,0x14BC,0x13E1,0x139A,0x13F6,0x14EB,0x1656}; +//Sinus (10Khz + 625hz) + +/*=================================================== + T Y P E S D E F ====================================================*/ /** Structure représentant le registre du CNA */ @@ -40,21 +48,12 @@ struct DAC_Driver typedef volatile struct DAC_Driver DAC_Device; -/*=================================================== - F U N C T I O N S +/*=================================================== + F U N C T I O N S ====================================================*/ /** Ouvre l'accé au CNA */ -DAC_Device* DacOpen(int count); - -//DAC_Device* DacClose(int count); - -/** Les données sont lus a partir d'un tableau pour obtenir le signal de CAL (10Khz + 625hz) */ -int DacTable(); - -/** Les données sont entrée par l'utilisateur, la conversion se fait a chaque nouvelle donnée */ -int DacConst(); - +DAC_Device* openDAC(int count); #endif diff --git a/LPP_drivers/libsrc/DAC/apb_dac_Driver.c b/LPP_drivers/libsrc/DAC/apb_dac_Driver.c --- a/LPP_drivers/libsrc/DAC/apb_dac_Driver.c +++ b/LPP_drivers/libsrc/DAC/apb_dac_Driver.c @@ -24,55 +24,15 @@ #include -DAC_Device* DacOpen(int count) +DAC_Device* openDAC(int count) { DAC_Device* dac0; dac0 = (DAC_Device*) apbgetdevice(LPP_CNA,VENDOR_LPP,count); - dac0->configReg = DAC_enable; + dac0->ConfigReg = DAC_enable; return dac0; } -/* -DAC_Device* DacClose(int count) -{ - DAC_Device* dac1; - dac1 = (DAC_Device*) apbgetdevice(LPP_CNA,VENDOR_LPP,count); - dac1->configReg = DAC_disable; - return dac1; -} -*/ - - -int DacTable() -{ - int i; - DAC_Device* dac2; - int tablo[251] = {0x9555,0x1800,0x19AA,0x1B15,0x1C0A,0x1C66,0x1C1F,0x1B44,0x19FC,0x187F,0x170F,0x15EA,0x1542,0x1537,0x15CE,0x16F2,0x187A,0x1A2B,0x1BC2,0x1D04,0x1DBF,0x1DDB,0x1D56,0x1C49,0x1AE3,0x195F,0x1800,0x1700,0x168D,0x16BA,0x1785,0x18D0,0x1A69,0x1C12,0x1D8A,0x1E98,0x1F13, - 0x1EEB,0x1E28,0x1CEC,0x1FFF,0x19E8,0x189F,0x17C8,0x1788,0x17EA,0x18E2,0x1A48,0x1BE7,0x1D7C,0x1ECA,0x1F9C,0x1FD2,0x1F64,0x1E66,0x1D00,0x1B6E,0x19EF,0x18C1,0x1817,0x180A,0x189D,0x19BA,0x1B33,0x1CCC,0x1E44,0x1F5F,0x1FEE,0x1FDC,0x1F2B,0x1DF6,0x1C6E,0x1AD1,0x1960,0x1855,0x17D9,0x1800, - 0x18C1,0x19FD,0x1B80,0x1D0A,0x1E5C,0x1F3D,0x1F87,0x1F2E,0x1E3E,0x1CDA,0x1B39,0x199C,0x1842,0x1760,0x1717,0x1771,0x185D,0x19B1,0x1B36,0x1CAA,0x1DCF,0x1E73,0x1E79,0x1DDD,0x1CB4,0x1B2B,0x197C,0x17EA,0x16B1,0x15FF,0x15EE,0x167C,0x178F,0x18F7,0x1A78,0x1BCF,0x1CC4,0x1D2A,0x1CED,0x1C14, - 0x1ABC,0x191A,0x176B,0x15F0,0x14E2,0x1467,0x1490,0x1552,0x1689,0x1800,0x1977,0x1AAE,0x1B70,0x1B99,0x1B1E,0x1A10,0x1895,0x16E6,0x1544,0x13EC,0x1313,0x12D6,0x133C,0x1431,0x1588,0x1709,0x1871,0x1984,0x1A12,0x1A01,0x194F,0x1816,0x1684,0x14D5,0x134C,0x1223,0x1187,0x118D,0x1231,0x1356, - 0x14CA,0x164F,0x17A3,0x188F,0x18E9,0x18A0,0x17BE,0x1664,0x14C7,0x1326,0x11C2,0x10D2,0x1079,0x10C3,0x11A4,0x12F6,0x1480,0x1603,0x173F,0x1800,0x1827,0x17AB,0x16A0,0x152F,0x1392,0x120A,0x10D5,0x1024,0x1012,0x10A1,0x11BC,0x1334,0x14CD,0x1646,0x1763,0x17F6,0x17E9,0x173F,0x1611,0x1492, - 0x1300,0x119A,0x109C,0x102E,0x1064,0x1136,0x1284,0x1419,0x15B8,0x171E,0x1816,0x1878,0x1838,0x1761,0x1618,0x1494,0x1314,0x11D8,0x1115,0x10ED,0x1168,0x1276,0x13EE,0x1597,0x1730,0x187B,0x1946,0x1973,0x1900,0x1800,0x16A1,0x151D,0x13B7,0x12AA,0x1225,0x1241,0x12FC,0x143E,0x15D5,0x1786, - 0x190E,0x1A32,0x1AC9,0x1ABE,0x1A16,0x18F1,0x1781,0x1604,0x14BC,0x13E1,0x139A,0x13F6,0x14EB,0x1656}; - dac2 = (DAC_Device*)0x80000800; - dac2->configReg = DAC_enable; - dac2->dataReg = tablo[0]; - - while(1) - { - for (i = 0 ; i < 251 ; i++) - { - while(!((dac2->configReg & DAC_ready) == DAC_ready)); - dac2->dataReg = tablo[i]; - while((dac2->configReg & DAC_ready) == DAC_ready); - } - } - return 0; -} - - - -int DacConst() +/*int DacConst() { DAC_Device* dac3; int Value = 0x1FFF; @@ -85,5 +45,5 @@ int DacConst() dac3->dataReg = Value; } return 0; -} +} */ diff --git a/LPP_drivers/libsrc/DAC/apb_dac_Driver.h b/LPP_drivers/libsrc/DAC/apb_dac_Driver.h --- a/LPP_drivers/libsrc/DAC/apb_dac_Driver.h +++ b/LPP_drivers/libsrc/DAC/apb_dac_Driver.h @@ -1,34 +1,42 @@ -/*------------------------------------------------------------------------------ --- This file is a part of the LPP VHDL IP LIBRARY --- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program; if not, write to the Free Software --- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -------------------------------------------------------------------------------- --- Author : Martin Morlot --- Mail : martin.morlot@lpp.polytechnique.fr ------------------------------------------------------------------------------*/ -#ifndef APB_CNA_DRIVER_H -#define APB_CNA_DRIVER_H +/*------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Martin Morlot +-- Mail : martin.morlot@lpp.polytechnique.fr +-----------------------------------------------------------------------------*/ +#ifndef APB_CNA_DRIVER_H +#define APB_CNA_DRIVER_H #define DAC_ready 3 #define DAC_enable 1 -#define DAC_disable 0 - +#define DAC_disable 0 -/*=================================================== - T Y P E S D E F +#define CAL_SignalData [251] = {0x9555,0x1800,0x19AA,0x1B15,0x1C0A,0x1C66,0x1C1F,0x1B44,0x19FC,0x187F,0x170F,0x15EA,0x1542,0x1537,0x15CE,0x16F2,0x187A,0x1A2B,0x1BC2,0x1D04,0x1DBF,0x1DDB,0x1D56,0x1C49,0x1AE3,0x195F,0x1800,0x1700,0x168D,0x16BA,0x1785,0x18D0,0x1A69,0x1C12,0x1D8A,0x1E98,0x1F13,\ + 0x1EEB,0x1E28,0x1CEC,0x1FFF,0x19E8,0x189F,0x17C8,0x1788,0x17EA,0x18E2,0x1A48,0x1BE7,0x1D7C,0x1ECA,0x1F9C,0x1FD2,0x1F64,0x1E66,0x1D00,0x1B6E,0x19EF,0x18C1,0x1817,0x180A,0x189D,0x19BA,0x1B33,0x1CCC,0x1E44,0x1F5F,0x1FEE,0x1FDC,0x1F2B,0x1DF6,0x1C6E,0x1AD1,0x1960,0x1855,0x17D9,0x1800,\ + 0x18C1,0x19FD,0x1B80,0x1D0A,0x1E5C,0x1F3D,0x1F87,0x1F2E,0x1E3E,0x1CDA,0x1B39,0x199C,0x1842,0x1760,0x1717,0x1771,0x185D,0x19B1,0x1B36,0x1CAA,0x1DCF,0x1E73,0x1E79,0x1DDD,0x1CB4,0x1B2B,0x197C,0x17EA,0x16B1,0x15FF,0x15EE,0x167C,0x178F,0x18F7,0x1A78,0x1BCF,0x1CC4,0x1D2A,0x1CED,0x1C14,\ + 0x1ABC,0x191A,0x176B,0x15F0,0x14E2,0x1467,0x1490,0x1552,0x1689,0x1800,0x1977,0x1AAE,0x1B70,0x1B99,0x1B1E,0x1A10,0x1895,0x16E6,0x1544,0x13EC,0x1313,0x12D6,0x133C,0x1431,0x1588,0x1709,0x1871,0x1984,0x1A12,0x1A01,0x194F,0x1816,0x1684,0x14D5,0x134C,0x1223,0x1187,0x118D,0x1231,0x1356,\ + 0x14CA,0x164F,0x17A3,0x188F,0x18E9,0x18A0,0x17BE,0x1664,0x14C7,0x1326,0x11C2,0x10D2,0x1079,0x10C3,0x11A4,0x12F6,0x1480,0x1603,0x173F,0x1800,0x1827,0x17AB,0x16A0,0x152F,0x1392,0x120A,0x10D5,0x1024,0x1012,0x10A1,0x11BC,0x1334,0x14CD,0x1646,0x1763,0x17F6,0x17E9,0x173F,0x1611,0x1492,\ + 0x1300,0x119A,0x109C,0x102E,0x1064,0x1136,0x1284,0x1419,0x15B8,0x171E,0x1816,0x1878,0x1838,0x1761,0x1618,0x1494,0x1314,0x11D8,0x1115,0x10ED,0x1168,0x1276,0x13EE,0x1597,0x1730,0x187B,0x1946,0x1973,0x1900,0x1800,0x16A1,0x151D,0x13B7,0x12AA,0x1225,0x1241,0x12FC,0x143E,0x15D5,0x1786,\ + 0x190E,0x1A32,0x1AC9,0x1ABE,0x1A16,0x18F1,0x1781,0x1604,0x14BC,0x13E1,0x139A,0x13F6,0x14EB,0x1656}; +//Sinus (10Khz + 625hz) + +/*=================================================== + T Y P E S D E F ====================================================*/ /** Structure représentant le registre du CNA */ @@ -40,21 +48,12 @@ struct DAC_Driver typedef volatile struct DAC_Driver DAC_Device; -/*=================================================== - F U N C T I O N S +/*=================================================== + F U N C T I O N S ====================================================*/ /** Ouvre l'accé au CNA */ -DAC_Device* DacOpen(int count); - -//DAC_Device* DacClose(int count); - -/** Les données sont lus a partir d'un tableau pour obtenir le signal de CAL (10Khz + 625hz) */ -int DacTable(); - -/** Les données sont entrée par l'utilisateur, la conversion se fait a chaque nouvelle donnée */ -int DacConst(); - +DAC_Device* openDAC(int count); #endif diff --git a/lib/lpp/leon3mp.vhd b/lib/lpp/leon3mp.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/leon3mp.vhd @@ -0,0 +1,375 @@ +----------------------------------------------------------------------------- +-- LEON3 Demonstration design +-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------ + + +library ieee; +use ieee.std_logic_1164.all; +library grlib; +use grlib.amba.all; +use grlib.stdlib.all; +library techmap; +use techmap.gencomp.all; +library gaisler; +use gaisler.memctrl.all; +use gaisler.leon3.all; +use gaisler.uart.all; +use gaisler.misc.all; +library esa; +use esa.memoryctrl.all; +use work.config.all; +library lpp; +use lpp.lpp_amba.all; +use lpp.lpp_memory.all; +use lpp.lpp_uart.all; +use lpp.lpp_matrix.all; +use lpp.lpp_delay.all; +use lpp.lpp_fft.all; +use lpp.fft_components.all; +use lpp.lpp_ad_conv.all; +use lpp.iir_filter.all; +use lpp.general_purpose.all; +use lpp.Filtercfg.all; +use lpp.lpp_cna.all; + +entity leon3mp is + generic ( + fabtech : integer := CFG_FABTECH; + memtech : integer := CFG_MEMTECH; + padtech : integer := CFG_PADTECH; + clktech : integer := CFG_CLKTECH; + disas : integer := CFG_DISAS; -- Enable disassembly to console + dbguart : integer := CFG_DUART; -- Print UART on console + pclow : integer := CFG_PCLOW + ); + port ( + clk50MHz : in std_ulogic; + reset : in std_ulogic; + ramclk : out std_logic; + + ahbrxd : in std_ulogic; -- DSU rx data + ahbtxd : out std_ulogic; -- DSU tx data + dsubre : in std_ulogic; + dsuact : out std_ulogic; + urxd1 : in std_ulogic; -- UART1 rx data + utxd1 : out std_ulogic; -- UART1 tx data + errorn : out std_ulogic; + + address : out std_logic_vector(18 downto 0); + data : inout std_logic_vector(31 downto 0); + gpio : inout std_logic_vector(6 downto 0); -- I/O port + + nBWa : out std_logic; + nBWb : out std_logic; + nBWc : out std_logic; + nBWd : out std_logic; + nBWE : out std_logic; + nADSC : out std_logic; + nADSP : out std_logic; + nADV : out std_logic; + nGW : out std_logic; + nCE1 : out std_logic; + CE2 : out std_logic; + nCE3 : out std_logic; + nOE : out std_logic; + MODE : out std_logic; + SSRAM_CLK : out std_logic; + ZZ : out std_logic; +--------------------------------------------------------------------- +--- AJOUT TEST ------------------------In/Out----------------------- +--------------------------------------------------------------------- +-- DAC + DAC_EN : out std_logic; + DAC_SYNC : out std_logic; + DAC_SCLK : out std_logic; + DAC_DATA : out std_logic; +-- UART + UART_RXD : in std_logic; + UART_TXD : out std_logic; +--------------------------------------------------------------------- + led : out std_logic_vector(1 downto 0) + ); +end; + +architecture Behavioral of leon3mp is + +constant maxahbmsp : integer := CFG_NCPU+CFG_AHB_UART+ + CFG_GRETH+CFG_AHB_JTAG; +constant maxahbm : integer := maxahbmsp; + +--Clk & Rst géné +signal vcc : std_logic_vector(4 downto 0); +signal gnd : std_logic_vector(4 downto 0); +signal resetnl : std_ulogic; +signal clk2x : std_ulogic; +signal lclk : std_ulogic; +signal lclk2x : std_ulogic; +signal clkm : std_ulogic; +signal rstn : std_ulogic; +signal rstraw : std_ulogic; +signal pciclk : std_ulogic; +signal sdclkl : std_ulogic; +signal cgi : clkgen_in_type; +signal cgo : clkgen_out_type; +--- AHB / APB +signal apbi : apb_slv_in_type; +signal apbo : apb_slv_out_vector := (others => apb_none); +signal ahbsi : ahb_slv_in_type; +signal ahbso : ahb_slv_out_vector := (others => ahbs_none); +signal ahbmi : ahb_mst_in_type; +signal ahbmo : ahb_mst_out_vector := (others => ahbm_none); +--UART +signal ahbuarti : uart_in_type; +signal ahbuarto : uart_out_type; +signal apbuarti : uart_in_type; +signal apbuarto : uart_out_type; +--MEM CTRLR +signal memi : memory_in_type; +signal memo : memory_out_type; +signal wpo : wprot_out_type; +signal sdo : sdram_out_type; +--IRQ +signal irqi : irq_in_vector(0 to CFG_NCPU-1); +signal irqo : irq_out_vector(0 to CFG_NCPU-1); +--Timer +signal gpti : gptimer_in_type; +signal gpto : gptimer_out_type; +--GPIO +signal gpioi : gpio_in_type; +signal gpioo : gpio_out_type; +--DSU +signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1); +signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1); +signal dsui : dsu_in_type; +signal dsuo : dsu_out_type; + +--------------------------------------------------------------------- +--- AJOUT TEST ------------------------Signaux---------------------- +--------------------------------------------------------------------- + +--------------------------------------------------------------------- +constant IOAEN : integer := CFG_CAN; +constant boardfreq : integer := 50000; + +begin + +--------------------------------------------------------------------- +--- AJOUT TEST -------------------------------------IPs------------- +--------------------------------------------------------------------- + +-- apbo not free : 0 1 2 3 7 11 + +--- DAC ------------------------------------------------------------- + + CAL0 : APB_CNA + generic map (pindex => 4, paddr => 4) + port map(clkm,rstn,apbi,apbo(4),DAC_EN,DAC_SYNC,DAC_SCLK,DAC_DATA); + + +--- UART ------------------------------------------------------------- + + COM0 : APB_UART + generic map (pindex => 5, paddr => 5) + port map (clkm,rstn,apbi,apbo(5),UART_TXD,UART_RXD); + + +--- FIFO ------------------------------------------------------------- + + Memtest : APB_FIFO + generic map (pindex => 6, paddr => 6, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '1', R => 1, W => 1) + port map (clkm,rstn,clkm,clkm,(others => '0'),(others => '1'),(others => '1'),open,open,open,(others => '0'),open,open,apbi,apbo(6)); + + +---------------------------------------------------------------------- +--- Reset and Clock generation ------------------------------------- +---------------------------------------------------------------------- + + vcc <= (others => '1'); gnd <= (others => '0'); + cgi.pllctrl <= "00"; cgi.pllrst <= rstraw; + + rst0 : rstgen port map (reset, clkm, cgo.clklock, rstn, rstraw); + + + clk_pad : clkpad generic map (tech => padtech) port map (clk50MHz, lclk2x); + + clkgen0 : clkgen -- clock generator + generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN, + CFG_CLK_NOFB, 0, 0, 0, boardfreq, 0, 0, CFG_OCLKDIV) + port map (lclk, lclk, clkm, open, clk2x, sdclkl, pciclk, cgi, cgo); + + ramclk <= clkm; +process(lclk2x) +begin + if lclk2x'event and lclk2x = '1' then + lclk <= not lclk; + end if; +end process; + +---------------------------------------------------------------------- +--- LEON3 processor / DSU / IRQ ------------------------------------ +---------------------------------------------------------------------- + + l3 : if CFG_LEON3 = 1 generate + cpu : for i in 0 to CFG_NCPU-1 generate + u0 : leon3s -- LEON3 processor + generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8, + 0, CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE, + CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ, + CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN, + CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP, + CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1) + port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso, + irqi(i), irqo(i), dbgi(i), dbgo(i)); + end generate; + errorn_pad : outpad generic map (tech => padtech) port map (errorn, dbgo(0).error); + + dsugen : if CFG_DSU = 1 generate + dsu0 : dsu3 -- LEON3 Debug Support Unit + generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#, + ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ) + port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo); +-- dsuen_pad : inpad generic map (tech => padtech) port map (dsuen, dsui.enable); + dsui.enable <= '1'; + dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break); + dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, dsuo.active); + end generate; + end generate; + + nodsu : if CFG_DSU = 0 generate + ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0'; + end generate; + + irqctrl : if CFG_IRQ3_ENABLE /= 0 generate + irqctrl0 : irqmp -- interrupt controller + generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU) + port map (rstn, clkm, apbi, apbo(2), irqo, irqi); + end generate; + irq3 : if CFG_IRQ3_ENABLE = 0 generate + x : for i in 0 to CFG_NCPU-1 generate + irqi(i).irl <= "0000"; + end generate; + apbo(2) <= apb_none; + end generate; + +---------------------------------------------------------------------- +--- Memory controllers --------------------------------------------- +---------------------------------------------------------------------- + + memctrlr : mctrl generic map (hindex => 0,pindex => 0, paddr => 0) + port map (rstn, clkm, memi, memo, ahbsi, ahbso(0),apbi,apbo(0),wpo, sdo); + + memi.brdyn <= '1'; memi.bexcn <= '1'; + memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "10"; + + bdr : for i in 0 to 3 generate + data_pad : iopadv generic map (tech => padtech, width => 8) + port map (data(31-i*8 downto 24-i*8), memo.data(31-i*8 downto 24-i*8), + memo.bdrive(i), memi.data(31-i*8 downto 24-i*8)); + end generate; + + + addr_pad : outpadv generic map (width => 19, tech => padtech) + port map (address, memo.address(20 downto 2)); + + + SSRAM_0:entity ssram_plugin + generic map (tech => padtech) + port map + (lclk2x,memo,SSRAM_CLK,nBWa,nBWb,nBWc,nBWd,nBWE,nADSC,nADSP,nADV,nGW,nCE1,CE2,nCE3,nOE,MODE,ZZ); + +---------------------------------------------------------------------- +--- AHB CONTROLLER ------------------------------------------------- +---------------------------------------------------------------------- + + ahb0 : ahbctrl -- AHB arbiter/multiplexer + generic map (defmast => CFG_DEFMST, split => CFG_SPLIT, + rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, + ioen => IOAEN, nahbm => maxahbm, nahbs => 8) + port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso); + +---------------------------------------------------------------------- +--- AHB UART ------------------------------------------------------- +---------------------------------------------------------------------- + + dcomgen : if CFG_AHB_UART = 1 generate + dcom0: ahbuart -- Debug UART + generic map (hindex => CFG_NCPU, pindex => 7, paddr => 7) + port map (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(7), ahbmi, ahbmo(CFG_NCPU)); + dsurx_pad : inpad generic map (tech => padtech) port map (ahbrxd, ahbuarti.rxd); + dsutx_pad : outpad generic map (tech => padtech) port map (ahbtxd, ahbuarto.txd); +-- led(0) <= not ahbuarti.rxd; led(1) <= not ahbuarto.txd; + end generate; + nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate; + +---------------------------------------------------------------------- +--- APB Bridge ----------------------------------------------------- +---------------------------------------------------------------------- + + apb0 : apbctrl -- AHB/APB bridge + generic map (hindex => 1, haddr => CFG_APBADDR) + port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo ); + +---------------------------------------------------------------------- +--- GPT Timer ------------------------------------------------------ +---------------------------------------------------------------------- + + gpt : if CFG_GPT_ENABLE /= 0 generate + timer0 : gptimer -- timer unit + generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ, + sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM, + nbits => CFG_GPT_TW) + port map (rstn, clkm, apbi, apbo(3), gpti, gpto); + gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0'; +-- led(4) <= gpto.wdog; + end generate; + notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate; + + +---------------------------------------------------------------------- +--- APB UART ------------------------------------------------------- +---------------------------------------------------------------------- + + ua1 : if CFG_UART1_ENABLE /= 0 generate + uart1 : apbuart -- UART 1 + generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart, + fifosize => CFG_UART1_FIFO) + port map (rstn, clkm, apbi, apbo(1), ahbuarti, apbuarto); + apbuarti.rxd <= urxd1; apbuarti.extclk <= '0'; utxd1 <= apbuarto.txd; + apbuarti.ctsn <= '0'; --rtsn1 <= apbuarto.rtsn; +-- led(0) <= not apbuarti.rxd; led(1) <= not apbuarto.txd; + end generate; + noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate; + +---------------------------------------------------------------------- +--- GPIO ----------------------------------------------------------- +---------------------------------------------------------------------- +led(0) <= gpio(0); led(1) <= gpio(1); + + gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GR GPIO unit + grgpio0: grgpio + generic map( pindex => 11, paddr => 11, imask => CFG_GRGPIO_IMASK, nbits => 7) + port map( rstn, clkm, apbi, apbo(11), gpioi, gpioo); + + pio_pads : for i in 0 to 6 generate + pio_pad : iopad generic map (tech => padtech) + port map (gpio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i)); + end generate; + end generate; + + +end Behavioral; \ No newline at end of file diff --git a/lib/lpp/lpp_Header/HeaderBuilder.vhd b/lib/lpp/lpp_Header/HeaderBuilder.vhd --- a/lib/lpp/lpp_Header/HeaderBuilder.vhd +++ b/lib/lpp/lpp_Header/HeaderBuilder.vhd @@ -30,7 +30,6 @@ entity HeaderBuilder is clkm : in std_logic; rstn : in std_logic; - pong : in std_logic; Statu : in std_logic_vector(3 downto 0); Matrix_Type : in std_logic_vector(1 downto 0); Matrix_Write : in std_logic; @@ -57,7 +56,6 @@ signal Matrix_Param : std_logic_vect signal Write_reg : std_logic; signal Data_cpt : integer; signal MAX : integer; -signal pong_reg : std_logic; type etat is (idle0,idle1,pong0,pong1); signal ect : etat; @@ -69,7 +67,6 @@ begin if(rstn='0')then ect <= idle0; Valid <= '0'; - pong_reg <= '0'; header_val <= '0'; header(5 downto 0) <= (others => '0'); Write_reg <= '0'; @@ -79,7 +76,6 @@ begin elsif(clkm' event and clkm='1')then Write_reg <= Matrix_Write; - pong_reg <= pong; if(Statu="0001" or Statu="0011" or Statu="0110" or Statu="1010" or Statu="1111")then MAX <= 128; @@ -87,17 +83,6 @@ begin MAX <= 256; end if; --- if(Write_reg = '0' and Matrix_Write = '1')then --- if(Data_cpt = MAX)then --- Data_cpt <= 0; --- Valid <= '1'; --- header_val <= '1'; --- else --- Data_cpt <= Data_cpt + 1; --- Valid <= '0'; --- end if; --- end if; - if(Write_reg = '0' and Matrix_Write = '1')then Data_cpt <= Data_cpt + 1; Valid <= '0'; @@ -107,19 +92,7 @@ begin header_val <= '1'; else Valid <= '0'; - end if; - --- if(header_ack = '1')then --- header_val <= '0'; --- end if; - --- if(emptyIN = "10")then --- ping <= '0'; --- elsif(emptyIN = "01")then --- ping <= '1'; --- else --- ping <= ping; --- end if; + end if; case ect is @@ -127,11 +100,7 @@ begin when idle0 => if(header_ack = '1')then header_val <= '0'; - --if(pong = '1')then - ect <= pong0; - --elsif(pong = '0')then - --ect <= pong1; - --end if; + ect <= pong0; end if; when pong0 => @@ -160,8 +129,6 @@ begin Matrix_Param <= std_logic_vector(to_unsigned(to_integer(unsigned(Statu))-1,4)); ---header(1 downto 0) <= Matrix_Type; ---header(5 downto 2) <= Matrix_Param; header(31 downto 6) <= (others => '0'); with ect select diff --git a/lib/lpp/lpp_Header/lpp_Header.vhd b/lib/lpp/lpp_Header/lpp_Header.vhd --- a/lib/lpp/lpp_Header/lpp_Header.vhd +++ b/lib/lpp/lpp_Header/lpp_Header.vhd @@ -38,7 +38,6 @@ component HeaderBuilder is clkm : in std_logic; rstn : in std_logic; - pong : in std_logic; Statu : in std_logic_vector(3 downto 0); Matrix_Type : in std_logic_vector(1 downto 0); Matrix_Write : in std_logic; diff --git a/lib/lpp/lpp_cna/APB_CNA.vhd b/lib/lpp/lpp_cna/APB_CNA.vhd deleted file mode 100644 --- a/lib/lpp/lpp_cna/APB_CNA.vhd +++ /dev/null @@ -1,123 +0,0 @@ ------------------------------------------------------------------------------- --- This file is a part of the LPP VHDL IP LIBRARY --- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program; if not, write to the Free Software --- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ------------------------------------------------------------------------------- --- Author : Martin Morlot --- Mail : martin.morlot@lpp.polytechnique.fr ------------------------------------------------------------------------------- -library ieee; -use ieee.std_logic_1164.all; -library grlib; -use grlib.amba.all; -use grlib.stdlib.all; -use grlib.devices.all; -library lpp; -use lpp.lpp_amba.all; -use lpp.apb_devices_list.all; -use lpp.lpp_cna.all; - ---! Driver APB, va faire le lien entre l'IP VHDL du convertisseur et le bus Amba - -entity APB_CNA is - generic ( - pindex : integer := 0; - paddr : integer := 0; - pmask : integer := 16#fff#; - pirq : integer := 0; - abits : integer := 8); - port ( - clk : in std_logic; --! Horloge du composant - rst : in std_logic; --! Reset general du composant - apbi : in apb_slv_in_type; --! Registre de gestion des entrées du bus - apbo : out apb_slv_out_type; --! Registre de gestion des sorties du bus - SYNC : out std_logic; --! Signal de synchronisation du convertisseur - SCLK : out std_logic; --! Horloge systeme du convertisseur - DATA : out std_logic --! Donnée numérique sérialisé - ); -end APB_CNA; - ---! @details Les deux registres (apbi,apbo) permettent de gérer la communication sur le bus ---! et les sorties seront cablées vers le convertisseur. - -architecture ar_APB_CNA of APB_CNA is - -constant REVISION : integer := 1; - -constant pconfig : apb_config_type := ( - 0 => ahb_device_reg (VENDOR_LPP, LPP_CNA, 0, REVISION, 0), - 1 => apb_iobar(paddr, pmask)); - -signal enable : std_logic; -signal flag_sd : std_logic; - -type CNA_ctrlr_Reg is record - CNA_Cfg : std_logic_vector(1 downto 0); - CNA_Data : std_logic_vector(15 downto 0); -end record; - -signal Rec : CNA_ctrlr_Reg; -signal Rdata : std_logic_vector(31 downto 0); - -begin - -enable <= Rec.CNA_Cfg(0); -Rec.CNA_Cfg(1) <= flag_sd; - - CONVERTER : CNA_TabloC - port map(clk,rst,enable,Rec.CNA_Data,SYNC,SCLK,flag_sd,Data); - - - process(rst,clk) - begin - if(rst='0')then - Rec.CNA_Data <= (others => '0'); - - elsif(clk'event and clk='1')then - - - --APB Write OP - if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then - case apbi.paddr(abits-1 downto 2) is - when "000000" => - Rec.CNA_Cfg(0) <= apbi.pwdata(0); - when "000001" => - Rec.CNA_Data <= apbi.pwdata(15 downto 0); - when others => - null; - end case; - end if; - - --APB READ OP - if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then - case apbi.paddr(abits-1 downto 2) is - when "000000" => - Rdata(31 downto 2) <= X"ABCDEF5" & "00"; - Rdata(1 downto 0) <= Rec.CNA_Cfg; - when "000001" => - Rdata(31 downto 16) <= X"FD18"; - Rdata(15 downto 0) <= Rec.CNA_Data; - when others => - Rdata <= (others => '0'); - end case; - end if; - - end if; - apbo.pconfig <= pconfig; - end process; - -apbo.prdata <= Rdata when apbi.penable = '1'; -end ar_APB_CNA; diff --git a/lib/lpp/lpp_cna/APB_DAC.vhd b/lib/lpp/lpp_cna/APB_DAC.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/lpp_cna/APB_DAC.vhd @@ -0,0 +1,125 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------ +-- Author : Martin Morlot +-- Mail : martin.morlot@lpp.polytechnique.fr +------------------------------------------------------------------------------ +library ieee; +use ieee.std_logic_1164.all; +library grlib; +use grlib.amba.all; +use grlib.stdlib.all; +use grlib.devices.all; +library lpp; +use lpp.lpp_amba.all; +use lpp.apb_devices_list.all; +use lpp.lpp_cna.all; + +--! Driver APB, va faire le lien entre l'IP VHDL du convertisseur et le bus Amba + +entity APB_DAC is + generic ( + pindex : integer := 0; + paddr : integer := 0; + pmask : integer := 16#fff#; + pirq : integer := 0; + abits : integer := 8); + port ( + clk : in std_logic; --! Horloge du composant + rst : in std_logic; --! Reset general du composant + apbi : in apb_slv_in_type; --! Registre de gestion des entrées du bus + apbo : out apb_slv_out_type; --! Registre de gestion des sorties du bus + Cal_EN : out std_logic; --! Signal Enable du multiplex pour la CAL + SYNC : out std_logic; --! Signal de synchronisation du convertisseur + SCLK : out std_logic; --! Horloge systeme du convertisseur + DATA : out std_logic --! Donnée numérique sérialisé + ); +end entity; + +--! @details Les deux registres (apbi,apbo) permettent de gérer la communication sur le bus +--! et les sorties seront cablées vers le convertisseur. + +architecture ar_APB_DAC of APB_DAC is + +constant REVISION : integer := 1; + +constant pconfig : apb_config_type := ( + 0 => ahb_device_reg (VENDOR_LPP, LPP_CNA, 0, REVISION, 0), + 1 => apb_iobar(paddr, pmask)); + +signal enable : std_logic; +signal flag_sd : std_logic; + +type DAC_ctrlr_Reg is record + DAC_Cfg : std_logic_vector(1 downto 0); + DAC_Data : std_logic_vector(15 downto 0); +end record; + +signal Rec : DAC_ctrlr_Reg; +signal Rdata : std_logic_vector(31 downto 0); + +begin + +enable <= Rec.DAC_Cfg(0); +Rec.DAC_Cfg(1) <= flag_sd; + + CONV0 : DacDriver + port map(clk,rst,enable,Rec.CNA_Data,SYNC,SCLK,flag_sd,Data); + + + process(rst,clk) + begin + if(rst='0')then + Rec.DAC_Data <= (others => '0'); + + elsif(clk'event and clk='1')then + + + --APB Write OP + if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then + case apbi.paddr(abits-1 downto 2) is + when "000000" => + Rec.DAC_Cfg(0) <= apbi.pwdata(0); + when "000001" => + Rec.DAC_Data <= apbi.pwdata(15 downto 0); + when others => + null; + end case; + end if; + + --APB Read OP + if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then + case apbi.paddr(abits-1 downto 2) is + when "000000" => + Rdata(31 downto 2) <= X"ABCDEF5" & "00"; + Rdata(1 downto 0) <= Rec.DAC_Cfg; + when "000001" => + Rdata(31 downto 16) <= X"FD18"; + Rdata(15 downto 0) <= Rec.DAC_Data; + when others => + Rdata <= (others => '0'); + end case; + end if; + + end if; + apbo.pconfig <= pconfig; + end process; + +apbo.prdata <= Rdata when apbi.penable = '1'; +Cal_EN <= enable; +end architecture; diff --git a/lib/lpp/lpp_cna/CNA_TabloC.vhd b/lib/lpp/lpp_cna/CNA_TabloC.vhd deleted file mode 100644 --- a/lib/lpp/lpp_cna/CNA_TabloC.vhd +++ /dev/null @@ -1,82 +0,0 @@ ------------------------------------------------------------------------------- --- This file is a part of the LPP VHDL IP LIBRARY --- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program; if not, write to the Free Software --- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ------------------------------------------------------------------------------- --- Author : Martin Morlot --- Mail : martin.morlot@lpp.polytechnique.fr ------------------------------------------------------------------------------- -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; -use work.Convertisseur_config.all; - ---! Programme du Convertisseur Numérique/Analogique - -entity CNA_TabloC is - port( - clock : in std_logic; --! Horloge du composant - rst : in std_logic; --! Reset general du composant - enable : in std_logic; --! Autorise ou non l'utilisation du composant - Data_C : in std_logic_vector(15 downto 0); --! Donnée Numérique d'entrée sur 16 bits - SYNC : out std_logic; --! Signal de synchronisation du convertisseur - SCLK : out std_logic; --! Horloge systeme du convertisseur - flag_sd : out std_logic; --! Flag, signale la fin de la sérialisation d'une donnée - Data : out std_logic --! Donnée numérique sérialisé - ); -end CNA_TabloC; - ---! @details Un driver C va permettre de génerer un tableau de données sur 16 bits, ---! qui seront sérialisé pour étre ensuite dirigées vers le convertisseur. - -architecture ar_CNA_TabloC of CNA_TabloC is - -component CLKINT -port( A : in std_logic := 'U'; - Y : out std_logic); -end component; - -signal clk : std_logic; - -signal raz : std_logic; -signal s_SCLK : std_logic; -signal OKAI_send : std_logic; - -begin - -CLKINT_0 : CLKINT - port map(A => clock, Y => clk); - -CLKINT_1 : CLKINT - port map(A => rst, Y => raz); - - -SystemCLK : entity work.Systeme_Clock - generic map (nb_serial) - port map (clk,raz,s_SCLK); - - -Signal_sync : entity work.Gene_SYNC - port map (s_SCLK,raz,enable,OKAI_send,SYNC); - - -Serial : entity work.serialize - port map (clk,raz,s_SCLK,Data_C,OKAI_send,flag_sd,Data); - - -SCLK <= s_SCLK; - -end ar_CNA_TabloC; \ No newline at end of file diff --git a/lib/lpp/lpp_cna/DacDriver.vhd b/lib/lpp/lpp_cna/DacDriver.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/lpp_cna/DacDriver.vhd @@ -0,0 +1,68 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------ +-- Author : Martin Morlot +-- Mail : martin.morlot@lpp.polytechnique.fr +------------------------------------------------------------------------------ +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.Convertisseur_config.all; +use lpp.lpp_cna.all; + +--! Programme du Convertisseur Numérique/Analogique + +entity DacDriver is + port( + clk : in std_logic; --! Horloge du composant + rst : in std_logic; --! Reset general du composant + enable : in std_logic; --! Autorise ou non l'utilisation du composant + Data_C : in std_logic_vector(15 downto 0); --! Donnée Numérique d'entrée sur 16 bits + SYNC : out std_logic; --! Signal de synchronisation du convertisseur + SCLK : out std_logic; --! Horloge systeme du convertisseur + flag_sd : out std_logic; --! Flag, signale la fin de la sérialisation d'une donnée + Data : out std_logic --! Donnée numérique sérialisé + ); +end entity; + +--! @details Un driver C va permettre de génerer un tableau de données sur 16 bits, +--! qui seront sérialisé pour étre ensuite dirigées vers le convertisseur. + +architecture ar_DacDriver of DacDriver is + +signal s_SCLK : std_logic; +signal OKAI_send : std_logic; + +begin + +SystemCLK : Systeme_Clock + generic map (nb_serial) + port map (clk,rst,s_SCLK); + + +Signal_sync : Gene_SYNC + port map (s_SCLK,rst,enable,OKAI_send,SYNC); + + +Serial : serialize + port map (clk,rst,s_SCLK,Data_C,OKAI_send,flag_sd,Data); + + +SCLK <= s_SCLK; + +end architecture; \ No newline at end of file diff --git a/lib/lpp/lpp_cna/lpp_cna.vhd b/lib/lpp/lpp_cna/lpp_cna.vhd --- a/lib/lpp/lpp_cna/lpp_cna.vhd +++ b/lib/lpp/lpp_cna/lpp_cna.vhd @@ -31,7 +31,7 @@ use lpp.lpp_amba.all; package lpp_cna is -component APB_CNA is +component APB_DAC is generic ( pindex : integer := 0; paddr : integer := 0; @@ -43,6 +43,7 @@ component APB_CNA is rst : in std_logic; apbi : in apb_slv_in_type; apbo : out apb_slv_out_type; + Cal_EN : out std_logic; SYNC : out std_logic; SCLK : out std_logic; DATA : out std_logic @@ -50,9 +51,9 @@ component APB_CNA is end component; -component CNA_TabloC is +component DacDriver is port( - clock : in std_logic; + clk : in std_logic; rst : in std_logic; enable : in std_logic; Data_C : in std_logic_vector(15 downto 0); diff --git a/lib/lpp/lpp_matrix/Dispatch.vhd b/lib/lpp/lpp_matrix/Dispatch.vhd --- a/lib/lpp/lpp_matrix/Dispatch.vhd +++ b/lib/lpp/lpp_matrix/Dispatch.vhd @@ -29,14 +29,12 @@ generic( port( clk : in std_logic; reset : in std_logic; - Acq : in std_logic; + Ack : in std_logic; Data : in std_logic_vector(Data_SZ-1 downto 0); Write : in std_logic; Valid : in std_logic; --- Full : in std_logic_vector(1 downto 0); FifoData : out std_logic_vector(2*Data_SZ-1 downto 0); FifoWrite : out std_logic_vector(1 downto 0); - Pong : out std_logic; Error : out std_logic ); end entity; @@ -47,15 +45,14 @@ architecture ar_Dispatch of Dispatch is type etat is (eX,e0,e1,e2); signal ect : etat; -signal Pong_int : std_logic; ---signal FifoCpt : integer range 0 to 1 := 0; +signal Pong : std_logic; begin process (clk,reset) begin if(reset='0')then - Pong_int <= '0'; + Pong <= '0'; Error <= '0'; ect <= e0; @@ -64,14 +61,13 @@ begin case ect is when e0 => --- if(Full(FifoCpt) = '1')then if(Valid = '1')then - Pong_int <= not Pong_int; + Pong <= not Pong; ect <= e1; end if; when e1 => - if(Acq = '0')then + if(Ack = '0')then Error <= '1'; ect <= e1; else @@ -80,7 +76,7 @@ begin end if; when others => - null; + null; end case; @@ -88,10 +84,6 @@ begin end process; FifoData <= Data & Data; -Pong <= Pong_int; - ---FifoCpt <= 0 when Pong_int='0' else 1; - -FifoWrite <= '1' & not Write when Pong_int='0' else not Write & '1'; +FifoWrite <= '1' & not Write when Pong='0' else not Write & '1'; end architecture; \ No newline at end of file diff --git a/lib/lpp/lpp_matrix/MatriceSpectrale.vhd b/lib/lpp/lpp_matrix/MatriceSpectrale.vhd --- a/lib/lpp/lpp_matrix/MatriceSpectrale.vhd +++ b/lib/lpp/lpp_matrix/MatriceSpectrale.vhd @@ -35,13 +35,11 @@ entity MatriceSpectrale is FifoIN_Full : in std_logic_vector(4 downto 0); SetReUse : in std_logic_vector(4 downto 0); --- FifoOUT_Full : in std_logic_vector(1 downto 0); Valid : in std_logic; Data_IN : in std_logic_vector((5*Input_SZ)-1 downto 0); - ACQ : in std_logic; + ACK : in std_logic; SM_Write : out std_logic; FlagError : out std_logic; - Pong : out std_logic; Statu : out std_logic_vector(3 downto 0); Write : out std_logic_vector(1 downto 0); Read : out std_logic_vector(4 downto 0); @@ -78,7 +76,7 @@ begin DISP : Dispatch generic map(Result_SZ) - port map(clkm,rstn,ACQ,Matrix_Result,Matrix_Write,Valid,Data_OUT,Write,Pong,FlagError); + port map(clkm,rstn,ACK,Matrix_Result,Matrix_Write,Valid,Data_OUT,Write,FlagError); Statu <= TopSM_Statu; SM_Write <= Matrix_Write; diff --git a/lib/lpp/lpp_matrix/lpp_matrix.vhd b/lib/lpp/lpp_matrix/lpp_matrix.vhd --- a/lib/lpp/lpp_matrix/lpp_matrix.vhd +++ b/lib/lpp/lpp_matrix/lpp_matrix.vhd @@ -66,13 +66,11 @@ component MatriceSpectrale is FifoIN_Full : in std_logic_vector(4 downto 0); SetReUse : in std_logic_vector(4 downto 0); --- FifoOUT_Full : in std_logic_vector(1 downto 0); Valid : in std_logic; Data_IN : in std_logic_vector((5*Input_SZ)-1 downto 0); - ACQ : in std_logic; + ACK : in std_logic; SM_Write : out std_logic; FlagError : out std_logic; - Pong : out std_logic; Statu : out std_logic_vector(3 downto 0); Write : out std_logic_vector(1 downto 0); Read : out std_logic_vector(4 downto 0); @@ -199,14 +197,12 @@ generic( port( clk : in std_logic; reset : in std_logic; - Acq : in std_logic; + Ack : in std_logic; Data : in std_logic_vector(Data_SZ-1 downto 0); Write : in std_logic; Valid : in std_logic; --- Full : in std_logic_vector(1 downto 0); FifoData : out std_logic_vector(2*Data_SZ-1 downto 0); FifoWrite : out std_logic_vector(1 downto 0); - Pong : out std_logic; Error : out std_logic ); end component; diff --git a/lib/lpp/lpp_memory/lppFIFOxN.vhd b/lib/lpp/lpp_memory/lppFIFOxN.vhd --- a/lib/lpp/lpp_memory/lppFIFOxN.vhd +++ b/lib/lpp/lpp_memory/lppFIFOxN.vhd @@ -1,66 +1,65 @@ ------------------------------------------------------------------------------- --- This file is a part of the LPP VHDL IP LIBRARY --- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program; if not, write to the Free Software --- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ------------------------------------------------------------------------------- --- Author : Martin Morlot --- Mail : martin.morlot@lpp.polytechnique.fr ------------------------------------------------------------------------------- -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; -library lpp; -use lpp.lpp_memory.all; -use lpp.iir_filter.all; -library techmap; -use techmap.gencomp.all; - -entity lppFIFOxN is -generic( - tech : integer := 0; - Mem_use : integer := use_RAM; - Data_sz : integer range 1 to 32 := 8; - Addr_sz : integer range 1 to 32 := 8; - FifoCnt : integer := 1; - Enable_ReUse : std_logic := '0' - ); -port( - rst : in std_logic; - wclk : in std_logic; - rclk : in std_logic; - ReUse : in std_logic_vector(FifoCnt-1 downto 0); - wen : in std_logic_vector(FifoCnt-1 downto 0); - ren : in std_logic_vector(FifoCnt-1 downto 0); - wdata : in std_logic_vector((FifoCnt*Data_sz)-1 downto 0); - rdata : out std_logic_vector((FifoCnt*Data_sz)-1 downto 0); - full : out std_logic_vector(FifoCnt-1 downto 0); - empty : out std_logic_vector(FifoCnt-1 downto 0) -); -end entity; - - -architecture ar_lppFIFOxN of lppFIFOxN is - -begin - -fifos: for i in 0 to FifoCnt-1 generate - FIFO0 : lpp_fifo - generic map (tech,Mem_use,Enable_ReUse,Data_sz,Addr_sz) - port map(rst,ReUse(i),rclk,ren(i),rdata((i+1)*Data_sz-1 downto i*Data_sz),empty(i),open,wclk,wen(i),wdata((i+1)*Data_sz-1 downto i*Data_sz),full(i),open); -end generate; - -end architecture; - +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------ +-- Author : Martin Morlot +-- Mail : martin.morlot@lpp.polytechnique.fr +------------------------------------------------------------------------------ +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +library lpp; +use lpp.lpp_memory.all; +use lpp.iir_filter.all; +library techmap; +use techmap.gencomp.all; + +entity lppFIFOxN is +generic( + tech : integer := 0; + Mem_use : integer := use_RAM; + Data_sz : integer range 1 to 32 := 8; + Addr_sz : integer range 2 to 12 := 8; + FifoCnt : integer := 1; + Enable_ReUse : std_logic := '0' + ); +port( + rstn : in std_logic; + wclk : in std_logic; + rclk : in std_logic; + ReUse : in std_logic_vector(FifoCnt-1 downto 0); + wen : in std_logic_vector(FifoCnt-1 downto 0); + ren : in std_logic_vector(FifoCnt-1 downto 0); + wdata : in std_logic_vector((FifoCnt*Data_sz)-1 downto 0); + rdata : out std_logic_vector((FifoCnt*Data_sz)-1 downto 0); + full : out std_logic_vector(FifoCnt-1 downto 0); + empty : out std_logic_vector(FifoCnt-1 downto 0) +); +end entity; + + +architecture ar_lppFIFOxN of lppFIFOxN is + +begin + +fifos: for i in 0 to FifoCnt-1 generate + FIFO0 : lpp_fifo + generic map (tech,Mem_use,Enable_ReUse,Data_sz,Addr_sz) + port map(rstn,ReUse(i),rclk,ren(i),rdata((i+1)*Data_sz-1 downto i*Data_sz),empty(i),open,wclk,wen(i),wdata((i+1)*Data_sz-1 downto i*Data_sz),full(i),open); +end generate; + +end architecture; diff --git a/lib/lpp/lpp_memory/lpp_FIFO.vhd b/lib/lpp/lpp_memory/lpp_FIFO.vhd --- a/lib/lpp/lpp_memory/lpp_FIFO.vhd +++ b/lib/lpp/lpp_memory/lpp_FIFO.vhd @@ -34,7 +34,7 @@ generic( Mem_use : integer := use_RAM; Enable_ReUse : std_logic := '0'; DataSz : integer range 1 to 32 := 8; - abits : integer range 2 to 12 := 8 + AddrSz : integer range 2 to 12 := 8 ); port( rstn : in std_logic; @@ -43,12 +43,12 @@ port( ren : in std_logic; rdata : out std_logic_vector(DataSz-1 downto 0); empty : out std_logic; - raddr : out std_logic_vector(abits-1 downto 0); + raddr : out std_logic_vector(AddrSz-1 downto 0); wclk : in std_logic; wen : in std_logic; wdata : in std_logic_vector(DataSz-1 downto 0); full : out std_logic; - waddr : out std_logic_vector(abits-1 downto 0) + waddr : out std_logic_vector(AddrSz-1 downto 0) ); end entity; @@ -65,10 +65,10 @@ signal sWEN : std_logic; signal sRE : std_logic; signal sWE : std_logic; -signal Waddr_vect : std_logic_vector(abits-1 downto 0):=(others =>'0'); -signal Raddr_vect : std_logic_vector(abits-1 downto 0):=(others =>'0'); -signal Waddr_vect_s : std_logic_vector(abits-1 downto 0):=(others =>'0'); -signal Raddr_vect_s : std_logic_vector(abits-1 downto 0):=(others =>'0'); +signal Waddr_vect : std_logic_vector(AddrSz-1 downto 0):=(others =>'0'); +signal Raddr_vect : std_logic_vector(AddrSz-1 downto 0):=(others =>'0'); +signal Waddr_vect_s : std_logic_vector(AddrSz-1 downto 0):=(others =>'0'); +signal Raddr_vect_s : std_logic_vector(AddrSz-1 downto 0):=(others =>'0'); begin @@ -78,13 +78,13 @@ begin --================================================================================== memRAM : IF Mem_use = use_RAM GENERATE SRAM : syncram_2p - generic map(tech,abits,DataSz) + generic map(tech,AddrSz,DataSz) port map(RCLK,sRE,Raddr_vect,rdata,WCLK,sWE,Waddr_vect,wdata); END GENERATE; --================================================================================== memCEL : IF Mem_use = use_CEL GENERATE CRAM : RAM_CEL - generic map(DataSz,abits) + generic map(DataSz,AddrSz) port map(wdata, rdata, sWEN, sREN, Waddr_vect, Raddr_vect, WCLK, rstn); END GENERATE; --================================================================================== @@ -177,4 +177,3 @@ end architecture; - diff --git a/lib/lpp/lpp_memory/lpp_memory.vhd b/lib/lpp/lpp_memory/lpp_memory.vhd --- a/lib/lpp/lpp_memory/lpp_memory.vhd +++ b/lib/lpp/lpp_memory/lpp_memory.vhd @@ -1,186 +1,186 @@ ------------------------------------------------------------------------------- --- This file is a part of the LPP VHDL IP LIBRARY --- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program; if not, write to the Free Software --- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ------------------------------------------------------------------------------- --- Author : Martin Morlot --- Mail : martin.morlot@lpp.polytechnique.fr ------------------------------------------------------------------------------- -library ieee; -use ieee.std_logic_1164.all; -library grlib; -use grlib.amba.all; -use std.textio.all; -library lpp; -use lpp.lpp_amba.all; -use lpp.iir_filter.all; -library gaisler; -use gaisler.misc.all; -use gaisler.memctrl.all; -library techmap; -use techmap.gencomp.all; - ---! Package contenant tous les programmes qui forment le composant intégré dans le léon - -package lpp_memory is - -component APB_FIFO is -generic ( - tech : integer := apa3; - pindex : integer := 0; - paddr : integer := 0; - pmask : integer := 16#fff#; - pirq : integer := 0; - abits : integer := 8; - FifoCnt : integer := 2; - Data_sz : integer := 16; - Addr_sz : integer := 9; - Enable_ReUse : std_logic := '0'; - Mem_use : integer := use_RAM; - R : integer := 1; - W : integer := 1 - ); - port ( - clk : in std_logic; --! Horloge du composant - rst : in std_logic; --! Reset general du composant - rclk : in std_logic; - wclk : in std_logic; - ReUse : in std_logic_vector(FifoCnt-1 downto 0); - REN : in std_logic_vector(FifoCnt-1 downto 0); --! Instruction de lecture en mémoire - WEN : in std_logic_vector(FifoCnt-1 downto 0); --! Instruction d'écriture en mémoire - Empty : out std_logic_vector(FifoCnt-1 downto 0); --! Flag, Mémoire vide - Full : out std_logic_vector(FifoCnt-1 downto 0); --! Flag, Mémoire pleine - RDATA : out std_logic_vector((FifoCnt*Data_sz)-1 downto 0); --! Registre de données en entrée - WDATA : in std_logic_vector((FifoCnt*Data_sz)-1 downto 0); --! Registre de données en sortie - WADDR : out std_logic_vector((FifoCnt*Addr_sz)-1 downto 0); --! Registre d'addresse (écriture) - RADDR : out std_logic_vector((FifoCnt*Addr_sz)-1 downto 0); --! Registre d'addresse (lecture) - apbi : in apb_slv_in_type; --! Registre de gestion des entrées du bus - apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus - ); -end component; - -component FIFO_pipeline is -generic( - tech : integer := 0; - Mem_use : integer := use_RAM; - fifoCount : integer range 2 to 32 := 8; - DataSz : integer range 1 to 32 := 8; - abits : integer range 2 to 12 := 8 - ); -port( - rstn : in std_logic; - ReUse : in std_logic; - rclk : in std_logic; - ren : in std_logic; - rdata : out std_logic_vector(DataSz-1 downto 0); - empty : out std_logic; - raddr : out std_logic_vector(abits-1 downto 0); - wclk : in std_logic; - wen : in std_logic; - wdata : in std_logic_vector(DataSz-1 downto 0); - full : out std_logic; - waddr : out std_logic_vector(abits-1 downto 0) -); -end component; - -component lpp_fifo is -generic( - tech : integer := 0; - Mem_use : integer := use_RAM; - Enable_ReUse : std_logic := '0'; - DataSz : integer range 1 to 32 := 8; - abits : integer range 2 to 12 := 8 - ); -port( - rstn : in std_logic; - ReUse : in std_logic; --27/01/12 - rclk : in std_logic; - ren : in std_logic; - rdata : out std_logic_vector(DataSz-1 downto 0); - empty : out std_logic; - raddr : out std_logic_vector(abits-1 downto 0); - wclk : in std_logic; - wen : in std_logic; - wdata : in std_logic_vector(DataSz-1 downto 0); - full : out std_logic; - waddr : out std_logic_vector(abits-1 downto 0) -); -end component; - - -component lppFIFOxN is -generic( - tech : integer := 0; - Mem_use : integer := use_RAM; - Data_sz : integer range 1 to 32 := 8; - Addr_sz : integer range 1 to 32 := 8; - FifoCnt : integer := 1; - Enable_ReUse : std_logic := '0' - ); -port( - rst : in std_logic; - wclk : in std_logic; - rclk : in std_logic; - ReUse : in std_logic_vector(FifoCnt-1 downto 0); - wen : in std_logic_vector(FifoCnt-1 downto 0); - ren : in std_logic_vector(FifoCnt-1 downto 0); - wdata : in std_logic_vector((FifoCnt*Data_sz)-1 downto 0); - rdata : out std_logic_vector((FifoCnt*Data_sz)-1 downto 0); - full : out std_logic_vector(FifoCnt-1 downto 0); - empty : out std_logic_vector(FifoCnt-1 downto 0) -); -end component; - -component FillFifo is -generic( - Data_sz : integer range 1 to 32 := 16; - Fifo_cnt : integer range 1 to 8 := 5 - ); -port( - clk : in std_logic; - raz : in std_logic; - write : out std_logic_vector(Fifo_cnt-1 downto 0); - reuse : out std_logic_vector(Fifo_cnt-1 downto 0); - data : out std_logic_vector(Fifo_cnt*Data_sz-1 downto 0) -); -end component; - -component ssram_plugin is -generic (tech : integer := 0); -port -( - clk : in std_logic; - mem_ctrlr_o : in memory_out_type; - SSRAM_CLK : out std_logic; - nBWa : out std_logic; - nBWb : out std_logic; - nBWc : out std_logic; - nBWd : out std_logic; - nBWE : out std_logic; - nADSC : out std_logic; - nADSP : out std_logic; - nADV : out std_logic; - nGW : out std_logic; - nCE1 : out std_logic; - CE2 : out std_logic; - nCE3 : out std_logic; - nOE : out std_logic; - MODE : out std_logic; - ZZ : out std_logic -); -end component; - -end; +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------ +-- Author : Martin Morlot +-- Mail : martin.morlot@lpp.polytechnique.fr +------------------------------------------------------------------------------ +library ieee; +use ieee.std_logic_1164.all; +library grlib; +use grlib.amba.all; +use std.textio.all; +library lpp; +use lpp.lpp_amba.all; +use lpp.iir_filter.all; +library gaisler; +use gaisler.misc.all; +use gaisler.memctrl.all; +library techmap; +use techmap.gencomp.all; + +--! Package contenant tous les programmes qui forment le composant intégré dans le léon + +package lpp_memory is + +component APB_FIFO is +generic ( + tech : integer := apa3; + pindex : integer := 0; + paddr : integer := 0; + pmask : integer := 16#fff#; + pirq : integer := 0; + abits : integer := 8; + FifoCnt : integer := 2; + Data_sz : integer := 16; + Addr_sz : integer := 9; + Enable_ReUse : std_logic := '0'; + Mem_use : integer := use_RAM; + R : integer := 1; + W : integer := 1 + ); + port ( + clk : in std_logic; --! Horloge du composant + rst : in std_logic; --! Reset general du composant + rclk : in std_logic; + wclk : in std_logic; + ReUse : in std_logic_vector(FifoCnt-1 downto 0); + REN : in std_logic_vector(FifoCnt-1 downto 0); --! Instruction de lecture en mémoire + WEN : in std_logic_vector(FifoCnt-1 downto 0); --! Instruction d'écriture en mémoire + Empty : out std_logic_vector(FifoCnt-1 downto 0); --! Flag, Mémoire vide + Full : out std_logic_vector(FifoCnt-1 downto 0); --! Flag, Mémoire pleine + RDATA : out std_logic_vector((FifoCnt*Data_sz)-1 downto 0); --! Registre de données en entrée + WDATA : in std_logic_vector((FifoCnt*Data_sz)-1 downto 0); --! Registre de données en sortie + WADDR : out std_logic_vector((FifoCnt*Addr_sz)-1 downto 0); --! Registre d'addresse (écriture) + RADDR : out std_logic_vector((FifoCnt*Addr_sz)-1 downto 0); --! Registre d'addresse (lecture) + apbi : in apb_slv_in_type; --! Registre de gestion des entrées du bus + apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus + ); +end component; + +component FIFO_pipeline is +generic( + tech : integer := 0; + Mem_use : integer := use_RAM; + fifoCount : integer range 2 to 32 := 8; + DataSz : integer range 1 to 32 := 8; + abits : integer range 2 to 12 := 8 + ); +port( + rstn : in std_logic; + ReUse : in std_logic; + rclk : in std_logic; + ren : in std_logic; + rdata : out std_logic_vector(DataSz-1 downto 0); + empty : out std_logic; + raddr : out std_logic_vector(abits-1 downto 0); + wclk : in std_logic; + wen : in std_logic; + wdata : in std_logic_vector(DataSz-1 downto 0); + full : out std_logic; + waddr : out std_logic_vector(abits-1 downto 0) +); +end component; + +component lpp_fifo is +generic( + tech : integer := 0; + Mem_use : integer := use_RAM; + Enable_ReUse : std_logic := '0'; + DataSz : integer range 1 to 32 := 8; + AddrSz : integer range 2 to 12 := 8 + ); +port( + rstn : in std_logic; + ReUse : in std_logic; --27/01/12 + rclk : in std_logic; + ren : in std_logic; + rdata : out std_logic_vector(DataSz-1 downto 0); + empty : out std_logic; + raddr : out std_logic_vector(AddrSz-1 downto 0); + wclk : in std_logic; + wen : in std_logic; + wdata : in std_logic_vector(DataSz-1 downto 0); + full : out std_logic; + waddr : out std_logic_vector(AddrSz-1 downto 0) +); +end component; + + +component lppFIFOxN is +generic( + tech : integer := 0; + Mem_use : integer := use_RAM; + Data_sz : integer range 1 to 32 := 8; + Addr_sz : integer range 1 to 32 := 8; + FifoCnt : integer := 1; + Enable_ReUse : std_logic := '0' + ); +port( + rstn : in std_logic; + wclk : in std_logic; + rclk : in std_logic; + ReUse : in std_logic_vector(FifoCnt-1 downto 0); + wen : in std_logic_vector(FifoCnt-1 downto 0); + ren : in std_logic_vector(FifoCnt-1 downto 0); + wdata : in std_logic_vector((FifoCnt*Data_sz)-1 downto 0); + rdata : out std_logic_vector((FifoCnt*Data_sz)-1 downto 0); + full : out std_logic_vector(FifoCnt-1 downto 0); + empty : out std_logic_vector(FifoCnt-1 downto 0) +); +end component; + +component FillFifo is +generic( + Data_sz : integer range 1 to 32 := 16; + Fifo_cnt : integer range 1 to 8 := 5 + ); +port( + clk : in std_logic; + raz : in std_logic; + write : out std_logic_vector(Fifo_cnt-1 downto 0); + reuse : out std_logic_vector(Fifo_cnt-1 downto 0); + data : out std_logic_vector(Fifo_cnt*Data_sz-1 downto 0) +); +end component; + +component ssram_plugin is +generic (tech : integer := 0); +port +( + clk : in std_logic; + mem_ctrlr_o : in memory_out_type; + SSRAM_CLK : out std_logic; + nBWa : out std_logic; + nBWb : out std_logic; + nBWc : out std_logic; + nBWd : out std_logic; + nBWE : out std_logic; + nADSC : out std_logic; + nADSP : out std_logic; + nADV : out std_logic; + nGW : out std_logic; + nCE1 : out std_logic; + CE2 : out std_logic; + nCE3 : out std_logic; + nOE : out std_logic; + MODE : out std_logic; + ZZ : out std_logic +); +end component; + +end; \ No newline at end of file