HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib Commit - r408:7cbe4feaa1bd

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designs/Validation_FIFO/Makefile created 644 +53 0

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	1	#GRLIB=../..
	2	VHDLIB=../..
	3	SCRIPTSDIR=$(VHDLIB)/scripts/
	4	GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh)
	5	TOP=leon3mp
	6	BOARD=em-LeonLPP-A3PE3kL-v3-core1
	7	include $(GRLIB)/boards/$(BOARD)/Makefile.inc
	8	DEVICE=$(PART)-$(PACKAGE)$(SPEED)
	9	UCF=$(GRLIB)/boards/$(BOARD)/$(TOP).ucf
	10	QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf
	11	EFFORT=high
	12	XSTOPT=
	13	SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0"
	14	#VHDLSYNFILES=config.vhd ahbrom.vhd leon3mp.vhd
	15	VHDLSYNFILES=
	16	VHDLSIMFILES= tb.vhd
	17	SIMTOP=testbench
	18	#SDCFILE=$(GRLIB)/boards/$(BOARD)/synplify.sdc
	19	#SDC=$(GRLIB)/boards/$(BOARD)/leon3mp.sdc
	20	PDC=$(GRLIB)/boards/$(BOARD)/em-LeonLPP-A3PE3kL.pdc
	21	BITGEN=$(GRLIB)/boards/$(BOARD)/default.ut
	22	CLEAN=soft-clean
	23
	24	TECHLIBS = proasic3e
	25
	26	LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
	27	tmtc openchip hynix ihp gleichmann micron usbhc
	28
	29	DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \
	30	pci grusbhc haps slink ascs pwm coremp7 spi ac97 \
	31	./amba_lcd_16x2_ctrlr \
	32	./general_purpose/lpp_AMR \
	33	./general_purpose/lpp_balise \
	34	./general_purpose/lpp_delay \
	35	./lpp_bootloader \
	36	./lpp_cna \
	37	./lpp_uart \
	38	./lpp_usb \
	39	./dsp/lpp_fft_rtax \
	40
	41	FILESKIP = i2cmst.vhd \
	42	APB_MULTI_DIODE.vhd \
	43	APB_MULTI_DIODE.vhd \
	44	Top_MatrixSpec.vhd \
	45	APB_FFT.vhd \
	46	lpp_lfr_apbreg.vhd \
	47	CoreFFT.vhd
	48
	49	include $(GRLIB)/bin/Makefile
	50	include $(GRLIB)/software/leon3/Makefile
	51
	52	################## project specific targets ##########################
	53

designs/Validation_FIFO/run.do created 644 +9 0

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	1	vcom -quiet -93 -work work tb.vhd
	2
	3	vsim work.testbench
	4
	5	log -r *
	6
	7	do wave.do
	8
	9	run -all

designs/Validation_FIFO/tb.vhd created 644 +248 0

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	1
	2	LIBRARY ieee;
	3	USE ieee.std_logic_1164.ALL;
	4	USE IEEE.MATH_REAL.ALL;
	5	USE ieee.numeric_std.ALL;
	6
	7	LIBRARY lpp;
	8	USE lpp.lpp_memory.ALL;
	9	USE lpp.iir_filter.ALL;
	10
	11
	12	ENTITY testbench IS
	13	END;
	14
	15	ARCHITECTURE behav OF testbench IS
	16
	17	-----------------------------------------------------------------------------
	18	-- Common signal
	19	SIGNAL clk : STD_LOGIC := '0';
	20	SIGNAL rstn : STD_LOGIC := '0';
	21	SIGNAL run : STD_LOGIC := '0';
	22
	23	-----------------------------------------------------------------------------
	24
	25	SIGNAL full_almost : STD_LOGIC;
	26	SIGNAL full : STD_LOGIC;
	27	SIGNAL data_wen : STD_LOGIC;
	28	SIGNAL wdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
	29
	30	SIGNAL empty : STD_LOGIC;
	31	SIGNAL data_ren : STD_LOGIC;
	32	SIGNAL data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
	33	SIGNAL data_out_obs : STD_LOGIC_VECTOR(31 DOWNTO 0);
	34
	35	SIGNAL empty_reg : STD_LOGIC;
	36	SIGNAL full_reg : STD_LOGIC;
	37
	38	-----------------------------------------------------------------------------
	39	TYPE DATA_CHANNEL IS ARRAY (0 TO 128-1) OF STD_LOGIC_VECTOR(31 DOWNTO 0);
	40	SIGNAL data_in : DATA_CHANNEL;
	41
	42	-----------------------------------------------------------------------------
	43	CONSTANT RANDOM_VECTOR_SIZE : INTEGER := 1+1; --READ + WRITE + CHANNEL_READ + CHANNEL_WRITE
	44	CONSTANT TWO_POWER_RANDOM_VECTOR_SIZE : REAL := (2*RANDOM_VECTOR_SIZE)1.0;
	45	SIGNAL random_vector : STD_LOGIC_VECTOR(RANDOM_VECTOR_SIZE-1 DOWNTO 0);
	46	--
	47	SIGNAL rand_ren : STD_LOGIC;
	48	SIGNAL rand_wen : STD_LOGIC;
	49
	50	SIGNAL pointer_read : INTEGER;
	51	SIGNAL pointer_write : INTEGER := 0;
	52
	53	SIGNAL error_now : STD_LOGIC;
	54	SIGNAL error_new : STD_LOGIC;
	55
	56	SIGNAL read_stop : STD_LOGIC;
	57	BEGIN
	58
	59
	60	all_J : FOR J IN 0 TO 127 GENERATE
	61	data_in(J) <= STD_LOGIC_VECTOR(to_unsigned(J*2+1, 32));
	62	END GENERATE all_J;
	63
	64
	65	-----------------------------------------------------------------------------
	66	lpp_fifo_1 : lpp_fifo
	67	GENERIC MAP (
	68	tech => 0,
	69	Mem_use => use_CEL,
	70	DataSz => 32,
	71	AddrSz => 8)
	72	PORT MAP (
	73	clk => clk,
	74	rstn => rstn,
	75	reUse => '0',
	76	ren => data_ren,
	77	rdata => data_out,
	78	wen => data_wen,
	79	wdata => wdata,
	80	empty => empty,
	81	full => full,
	82	almost_full => full_almost);
	83
	84	-----------------------------------------------------------------------------
	85
	86
	87
	88	-----------------------------------------------------------------------------
	89	-- READ
	90	-----------------------------------------------------------------------------
	91	PROCESS (clk, rstn)
	92	BEGIN -- PROCESS
	93	IF rstn = '0' THEN -- asynchronous reset (active low)
	94	empty_reg <= '1';
	95	ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
	96	empty_reg <= empty;
	97	END IF;
	98	END PROCESS;
	99
	100	PROCESS (clk, rstn)
	101	BEGIN -- PROCESS
	102	IF rstn = '0' THEN -- asynchronous reset (active low)
	103	data_out_obs <= (OTHERS => '0');
	104
	105	pointer_read <= 0;
	106	error_now <= '0';
	107	error_new <= '0';
	108
	109	ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
	110	error_now <= '0';
	111	IF empty_reg = '0' THEN
	112	IF data_ren = '0' THEN
	113	--IF data_ren_and_not_empty = '0' THEN
	114	error_new <= '0';
	115	data_out_obs <= data_out;
	116
	117	IF pointer_read < 127 THEN
	118	pointer_read <= pointer_read + 1;
	119	ELSE
	120	pointer_read <= 0;
	121	END IF;
	122
	123	IF data_out /= data_in(pointer_read) THEN
	124	error_now <= '1';
	125	error_new <= '1';
	126	END IF;
	127	END IF;
	128
	129	END IF;
	130	END IF;
	131	END PROCESS;
	132	-----------------------------------------------------------------------------
	133
	134
	135
	136
	137	-----------------------------------------------------------------------------
	138	-- WRITE
	139	-----------------------------------------------------------------------------
	140	PROCESS (clk, rstn)
	141	BEGIN -- PROCESS
	142	IF rstn = '0' THEN -- asynchronous reset (active low)
	143	full_reg <= '0';
	144	ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
	145	full_reg <= full;
	146	END IF;
	147	END PROCESS;
	148
	149	proc_verif : PROCESS (clk, rstn)
	150	BEGIN -- PROCESS proc_verif
	151	IF rstn = '0' THEN -- asynchronous reset (active low)
	152	pointer_write <= 0;
	153	ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
	154	IF data_wen = '0' THEN
	155	IF full_reg = '0' THEN
	156	IF pointer_write < 127 THEN
	157	pointer_write <= pointer_write+1;
	158	ELSE
	159	pointer_write <= 0;
	160	END IF;
	161	END IF;
	162	END IF;
	163	END IF;
	164	END PROCESS proc_verif;
	165
	166	wdata <= data_in(pointer_write) WHEN data_wen = '0' ELSE (OTHERS => 'X');
	167	-----------------------------------------------------------------------------
	168
	169
	170
	171	-----------------------------------------------------------------------------
	172	clk <= NOT clk AFTER 5 ns; -- 100 MHz
	173	-----------------------------------------------------------------------------
	174	WaveGen_Proc : PROCESS
	175	BEGIN
	176	-- insert signal assignments here
	177	WAIT UNTIL clk = '1';
	178	read_stop <= '0';
	179	rstn <= '0';
	180	run <= '0';
	181	WAIT UNTIL clk = '1';
	182	WAIT UNTIL clk = '1';
	183	WAIT UNTIL clk = '1';
	184	rstn <= '1';
	185	WAIT UNTIL clk = '1';
	186	WAIT UNTIL clk = '1';
	187	WAIT UNTIL clk = '1';
	188	WAIT UNTIL clk = '1';
	189	WAIT UNTIL clk = '1';
	190	run <= '1';
	191	WAIT UNTIL clk = '1';
	192	WAIT UNTIL clk = '1';
	193	WAIT UNTIL clk = '1';
	194	WAIT UNTIL clk = '1';
	195	WAIT FOR 10 us;
	196	read_stop <= '1';
	197	WAIT FOR 10 us;
	198	read_stop <= '0';
	199	WAIT FOR 80 us;
	200	REPORT "* END simulation *" SEVERITY failure;
	201	WAIT;
	202	END PROCESS WaveGen_Proc;
	203	-----------------------------------------------------------------------------
	204
	205
	206
	207	-----------------------------------------------------------------------------
	208	-- RANDOM GENERATOR
	209	-----------------------------------------------------------------------------
	210	PROCESS (clk, rstn)
	211	VARIABLE seed1, seed2 : POSITIVE;
	212	VARIABLE rand1 : REAL;
	213	VARIABLE RANDOM_VECTOR_VAR : STD_LOGIC_VECTOR(RANDOM_VECTOR_SIZE-1 DOWNTO 0);
	214	BEGIN -- PROCESS
	215	IF rstn = '0' THEN -- asynchronous reset (active low)
	216	random_vector <= (OTHERS => '0');
	217	ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
	218	UNIFORM(seed1, seed2, rand1);
	219	RANDOM_VECTOR_VAR := STD_LOGIC_VECTOR(
	220	to_unsigned(INTEGER(TRUNC(rand1*TWO_POWER_RANDOM_VECTOR_SIZE)),
	221	RANDOM_VECTOR_VAR'LENGTH)
	222	);
	223	random_vector <= RANDOM_VECTOR_VAR;
	224	END IF;
	225	END PROCESS;
	226	-----------------------------------------------------------------------------
	227	rand_wen <= random_vector(1);
	228	rand_ren <= random_vector(0);
	229	-----------------------------------------------------------------------------
	230	PROCESS (clk, rstn)
	231	BEGIN -- PROCESS
	232	IF rstn = '0' THEN -- asynchronous reset (active low)
	233	data_wen <= '1';
	234	data_ren <= '1';
	235	ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
	236	data_wen <= rand_wen;
	237	IF read_stop = '0' THEN
	238	data_ren <= rand_ren;
	239	ELSE
	240	data_ren <= '1';
	241	END IF;
	242	END IF;
	243	END PROCESS;
	244	-----------------------------------------------------------------------------
	245
	246
	247
	248	END;

designs/Validation_FIFO/wave.do created 644 +35 0

@@ -0,0 +1,35
	1	onerror {resume}
	2	quietly WaveActivateNextPane {} 0
	3	add wave -noupdate -expand -group COMMON /testbench/clk
	4	add wave -noupdate -expand -group COMMON /testbench/rstn
	5	add wave -noupdate -expand -group COMMON /testbench/run
	6	add wave -noupdate -expand -group FIFO -expand -group FIFO_IN /testbench/full_almost
	7	add wave -noupdate -expand -group FIFO -expand -group FIFO_IN /testbench/full
	8	add wave -noupdate -expand -group FIFO -expand -group FIFO_IN /testbench/data_wen
	9	add wave -noupdate -expand -group FIFO -expand -group FIFO_IN /testbench/wdata
	10	add wave -noupdate -expand -group FIFO -expand -group FIFO_OUT /testbench/empty
	11	add wave -noupdate -expand -group FIFO -expand -group FIFO_OUT /testbench/data_ren
	12	add wave -noupdate -expand -group FIFO -expand -group FIFO_OUT /testbench/data_out
	13	add wave -noupdate -radix hexadecimal /testbench/data_out_obs
	14	add wave -noupdate /testbench/pointer_read
	15	add wave -noupdate /testbench/pointer_write
	16	add wave -noupdate /testbench/error_now
	17	add wave -noupdate /testbench/error_new
	18	add wave -noupdate /testbench/read_stop
	19	TreeUpdate [SetDefaultTree]
	20	WaveRestoreCursors {{Cursor 1} {56085000 ps} 0}
	21	configure wave -namecolwidth 510
	22	configure wave -valuecolwidth 172
	23	configure wave -justifyvalue left
	24	configure wave -signalnamewidth 0
	25	configure wave -snapdistance 10
	26	configure wave -datasetprefix 0
	27	configure wave -rowmargin 4
	28	configure wave -childrowmargin 2
	29	configure wave -gridoffset 0
	30	configure wave -gridperiod 1
	31	configure wave -griddelta 40
	32	configure wave -timeline 0
	33	configure wave -timelineunits ns
	34	update
	35	WaveRestoreZoom {0 ps} {105131250 ps}

lib/lpp/lpp_waveform/lpp_waveform_fifo_headreg.vhd +11 -10

             ------------------------------------------------------------------------------
             --  This file is a part of the LPP VHDL IP LIBRARY
             --  Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
             --
             --  This program is free software; you can redistribute it and/or modify
             --  it under the terms of the GNU General Public License as published by
             --  the Free Software Foundation; either version 3 of the License, or
             --  (at your option) any later version.
             --
             --  This program is distributed in the hope that it will be useful,
             --  but WITHOUT ANY WARRANTY; without even the implied warranty of
             --  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
             --  GNU General Public License for more details.
             --
             --  You should have received a copy of the GNU General Public License
             --  along with this program; if not, write to the Free Software
             --  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
             ------------------------------------------------------------------------------
             --                    Author : Jean-christophe PELLION
             --                    Mail   : jean-christophe.pellion@lpp.polytechnique.fr
             ------------------------------------------------------------------------------
             LIBRARY IEEE;
             USE IEEE.std_logic_1164.ALL;
             USE IEEE.numeric_std.ALL;
             LIBRARY lpp;
             USE lpp.lpp_memory.ALL;
             USE lpp.iir_filter.ALL;
             USE lpp.lpp_waveform_pkg.ALL;
             LIBRARY techmap;
             USE techmap.gencomp.ALL;
             ENTITY lpp_waveform_fifo_headreg IS
               GENERIC(
                 tech : INTEGER := 0
                 );
               PORT(
                 clk            : IN  STD_LOGIC;
                 rstn           : IN  STD_LOGIC;
                 ---------------------------------------------------------------------------
                 run            : IN  STD_LOGIC;
                 ---------------------------------------------------------------------------
                 o_empty_almost : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);  --occupancy is lesser than 16 * 32b
                 o_empty        : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
                 o_data_ren     : IN  STD_LOGIC_VECTOR(3 DOWNTO 0);
                 o_rdata_0      : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --
                 o_rdata_1      : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --
                 o_rdata_2      : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --
                 o_rdata_3      : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);  --
                 ---------------------------------------------------------------------------
                 i_empty_almost : IN  STD_LOGIC_VECTOR(3 DOWNTO 0);
                 i_empty        : IN  STD_LOGIC_VECTOR(3 DOWNTO 0);
                 i_data_ren     : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);  --
                 i_rdata        : IN  STD_LOGIC_VECTOR(31 DOWNTO 0)
                 );
             END ENTITY;
             ARCHITECTURE ar_lpp_waveform_fifo_headreg OF lpp_waveform_fifo_headreg IS
               SIGNAL reg_full             : STD_LOGIC_VECTOR(3 DOWNTO 0);
               SIGNAL s_ren                : STD_LOGIC_VECTOR(3 DOWNTO 0);
               SIGNAL s_ren_reg            : STD_LOGIC_VECTOR(3 DOWNTO 0);
               SIGNAL one_ren_and_notEmpty : STD_LOGIC;
               SIGNAL ren_and_notEmpty     : STD_LOGIC_VECTOR(3 DOWNTO 0);
               SIGNAL s_empty_almost       : STD_LOGIC_VECTOR(3 DOWNTO 0);
               SIGNAL s_rdata_0      : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL s_rdata_1      : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL s_rdata_2      : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL s_rdata_3      : STD_LOGIC_VECTOR(31 DOWNTO 0);
             BEGIN
               -----------------------------------------------------------------------------
               -- DATA_REN_FIFO
               -----------------------------------------------------------------------------
               i_data_ren <= s_ren;
               PROCESS (clk, rstn)
               BEGIN
                 IF rstn = '0' THEN
                   s_ren_reg <= (OTHERS => '1');
                 ELSIF clk'EVENT AND clk = '1' THEN
                   IF run = '1' THEN
                     s_ren_reg <= s_ren;
                   ELSE
                     s_ren_reg <= (OTHERS => '1');
                   END IF;
                 END IF;
               END PROCESS;
               s_ren(0) <= o_data_ren(0) WHEN one_ren_and_notEmpty = '1' ELSE
                           NOT ((NOT i_empty(0)) AND (NOT reg_full(0)));
-              s_ren(1) <= o_data_ren(1) WHEN one_ren_and_notEmpty = '1' ELSE
+              s_ren(1) <= '1' WHEN s_ren(0) = '0' ELSE
-                          '1' WHEN s_ren(0) = '0' ELSE
+                          o_data_ren(1) WHEN one_ren_and_notEmpty = '1' ELSE
                           NOT ((NOT i_empty(1)) AND (NOT reg_full(1)));
-              s_ren(2) <= o_data_ren(2) WHEN one_ren_and_notEmpty = '1' ELSE
+              s_ren(2) <= '1' WHEN s_ren(0) = '0' ELSE
-                          '1' WHEN s_ren(0) = '0' ELSE
                           '1' WHEN s_ren(1) = '0' ELSE
+                          o_data_ren(2) WHEN one_ren_and_notEmpty = '1' ELSE
                           NOT ((NOT i_empty(2)) AND (NOT reg_full(2)));
-              s_ren(3) <= o_data_ren(3) WHEN one_ren_and_notEmpty = '1' ELSE
+              s_ren(3) <= '1' WHEN s_ren(0) = '0' ELSE
-                          '1' WHEN s_ren(0) = '0' ELSE
                           '1' WHEN s_ren(1) = '0' ELSE
                           '1' WHEN s_ren(2) = '0' ELSE
+                          o_data_ren(3) WHEN one_ren_and_notEmpty = '1' ELSE
                           NOT ((NOT i_empty(3)) AND (NOT reg_full(3)));
               -----------------------------------------------------------------------------
               all_ren : FOR I IN 3 DOWNTO 0 GENERATE
                 ren_and_notEmpty(I) <= (NOT o_data_ren(I)) AND (NOT i_empty(I));
               END GENERATE all_ren;
               one_ren_and_notEmpty <= '0' WHEN ren_and_notEmpty = "0000" ELSE '1';
               -----------------------------------------------------------------------------
               -- DATA
               -----------------------------------------------------------------------------
               o_rdata_0 <= i_rdata WHEN s_ren_reg(0) = '0' AND s_ren(0) = '0' ELSE s_rdata_0;
               o_rdata_1 <= i_rdata WHEN s_ren_reg(1) = '0' AND s_ren(1) = '0' ELSE s_rdata_1;
               o_rdata_2 <= i_rdata WHEN s_ren_reg(2) = '0' AND s_ren(2) = '0' ELSE s_rdata_2;
               o_rdata_3 <= i_rdata WHEN s_ren_reg(3) = '0' AND s_ren(3) = '0' ELSE s_rdata_3;
               PROCESS (clk, rstn)
               BEGIN
                 IF rstn = '0' THEN
                   s_rdata_0 <= (OTHERS => '0');
                   s_rdata_1 <= (OTHERS => '0');
                   s_rdata_2 <= (OTHERS => '0');
                   s_rdata_3 <= (OTHERS => '0');
                 ELSIF clk'EVENT AND clk = '1' THEN
                   IF run = '1' THEN
                     IF s_ren_reg(0) = '0' THEN s_rdata_0 <= i_rdata; END IF;
                     IF s_ren_reg(1) = '0' THEN s_rdata_1 <= i_rdata; END IF;
                     IF s_ren_reg(2) = '0' THEN s_rdata_2 <= i_rdata; END IF;
                     IF s_ren_reg(3) = '0' THEN s_rdata_3 <= i_rdata; END IF;
                   ELSE
-                  s_rdata_0 <= (OTHERS => '0');
+                    s_rdata_0 <= (OTHERS => '0');
-                  s_rdata_1 <= (OTHERS => '0');
+                    s_rdata_1 <= (OTHERS => '0');
-                  s_rdata_2 <= (OTHERS => '0');
+                    s_rdata_2 <= (OTHERS => '0');
-                  s_rdata_3 <= (OTHERS => '0');
+                    s_rdata_3 <= (OTHERS => '0');
                   END IF;
                 END IF;
               END PROCESS;
               all_reg_full : FOR I IN 3 DOWNTO 0 GENERATE
                 PROCESS (clk, rstn)
                 BEGIN
                   IF rstn = '0' THEN
                     reg_full(I) <= '0';
                   ELSIF clk'EVENT AND clk = '1' THEN
             --        IF s_ren_reg(I) = '0' THEN
                     IF run = '1' THEN
                       IF s_ren(I) = '0' THEN
                         reg_full(I) <= '1';
                       ELSIF o_data_ren(I) = '0' THEN
                         reg_full(I) <= '0';
                       END IF;
                     ELSE
                       reg_full(I) <= '0';
                     END IF;
                   END IF;
                 END PROCESS;
               END GENERATE all_reg_full;
               -----------------------------------------------------------------------------
               -- EMPTY
               -----------------------------------------------------------------------------
               o_empty <= NOT reg_full;
               -----------------------------------------------------------------------------
               -- EMPTY_ALMOST
               -----------------------------------------------------------------------------
               o_empty_almost <= s_empty_almost;
               all_empty_almost: FOR I IN 3 DOWNTO 0 GENERATE
                 PROCESS (clk, rstn)
                 BEGIN  -- PROCESS
                   IF rstn = '0' THEN                  -- asynchronous reset (active low)
                     s_empty_almost(I) <= '1';
                   ELSIF clk'event AND clk = '1' THEN  -- rising clock edge
                     IF run = '1' THEN
                       IF s_ren(I) = '0' THEN
                         s_empty_almost(I) <= i_empty_almost(I);
                       ELSIF o_data_ren(I) = '0' THEN
                         s_empty_almost(I) <= '1';
                       ELSE
                         IF i_empty_almost(I) = '0' THEN
                           s_empty_almost(I) <= '0';
                         END IF;
                       END IF;
                     ELSE
                       s_empty_almost(I) <= '1';
                     END IF;
                   END IF;
                 END PROCESS;
               END GENERATE all_empty_almost;
             END ARCHITECTURE;

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