diff --git a/designs/Validation_FIFO/Makefile b/designs/Validation_FIFO/Makefile new file mode 100644 --- /dev/null +++ b/designs/Validation_FIFO/Makefile @@ -0,0 +1,53 @@ +#GRLIB=../.. +VHDLIB=../.. +SCRIPTSDIR=$(VHDLIB)/scripts/ +GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh) +TOP=leon3mp +BOARD=em-LeonLPP-A3PE3kL-v3-core1 +include $(GRLIB)/boards/$(BOARD)/Makefile.inc +DEVICE=$(PART)-$(PACKAGE)$(SPEED) +UCF=$(GRLIB)/boards/$(BOARD)/$(TOP).ucf +QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf +EFFORT=high +XSTOPT= +SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0" +#VHDLSYNFILES=config.vhd ahbrom.vhd leon3mp.vhd +VHDLSYNFILES= +VHDLSIMFILES= tb.vhd +SIMTOP=testbench +#SDCFILE=$(GRLIB)/boards/$(BOARD)/synplify.sdc +#SDC=$(GRLIB)/boards/$(BOARD)/leon3mp.sdc +PDC=$(GRLIB)/boards/$(BOARD)/em-LeonLPP-A3PE3kL.pdc +BITGEN=$(GRLIB)/boards/$(BOARD)/default.ut +CLEAN=soft-clean + +TECHLIBS = proasic3e + +LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \ + tmtc openchip hynix ihp gleichmann micron usbhc + +DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \ + pci grusbhc haps slink ascs pwm coremp7 spi ac97 \ + ./amba_lcd_16x2_ctrlr \ + ./general_purpose/lpp_AMR \ + ./general_purpose/lpp_balise \ + ./general_purpose/lpp_delay \ + ./lpp_bootloader \ + ./lpp_cna \ + ./lpp_uart \ + ./lpp_usb \ + ./dsp/lpp_fft_rtax \ + +FILESKIP = i2cmst.vhd \ + APB_MULTI_DIODE.vhd \ + APB_MULTI_DIODE.vhd \ + Top_MatrixSpec.vhd \ + APB_FFT.vhd \ + lpp_lfr_apbreg.vhd \ + CoreFFT.vhd + +include $(GRLIB)/bin/Makefile +include $(GRLIB)/software/leon3/Makefile + +################## project specific targets ########################## + diff --git a/designs/Validation_FIFO/run.do b/designs/Validation_FIFO/run.do new file mode 100644 --- /dev/null +++ b/designs/Validation_FIFO/run.do @@ -0,0 +1,9 @@ +vcom -quiet -93 -work work tb.vhd + +vsim work.testbench + +log -r * + +do wave.do + +run -all diff --git a/designs/Validation_FIFO/tb.vhd b/designs/Validation_FIFO/tb.vhd new file mode 100644 --- /dev/null +++ b/designs/Validation_FIFO/tb.vhd @@ -0,0 +1,248 @@ + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE IEEE.MATH_REAL.ALL; +USE ieee.numeric_std.ALL; + +LIBRARY lpp; +USE lpp.lpp_memory.ALL; +USE lpp.iir_filter.ALL; + + +ENTITY testbench IS +END; + +ARCHITECTURE behav OF testbench IS + + ----------------------------------------------------------------------------- + -- Common signal + SIGNAL clk : STD_LOGIC := '0'; + SIGNAL rstn : STD_LOGIC := '0'; + SIGNAL run : STD_LOGIC := '0'; + + ----------------------------------------------------------------------------- + + SIGNAL full_almost : STD_LOGIC; + SIGNAL full : STD_LOGIC; + SIGNAL data_wen : STD_LOGIC; + SIGNAL wdata : STD_LOGIC_VECTOR(31 DOWNTO 0); + + SIGNAL empty : STD_LOGIC; + SIGNAL data_ren : STD_LOGIC; + SIGNAL data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL data_out_obs : STD_LOGIC_VECTOR(31 DOWNTO 0); + + SIGNAL empty_reg : STD_LOGIC; + SIGNAL full_reg : STD_LOGIC; + + ----------------------------------------------------------------------------- + TYPE DATA_CHANNEL IS ARRAY (0 TO 128-1) OF STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL data_in : DATA_CHANNEL; + + ----------------------------------------------------------------------------- + CONSTANT RANDOM_VECTOR_SIZE : INTEGER := 1+1; --READ + WRITE + CHANNEL_READ + CHANNEL_WRITE + CONSTANT TWO_POWER_RANDOM_VECTOR_SIZE : REAL := (2**RANDOM_VECTOR_SIZE)*1.0; + SIGNAL random_vector : STD_LOGIC_VECTOR(RANDOM_VECTOR_SIZE-1 DOWNTO 0); + -- + SIGNAL rand_ren : STD_LOGIC; + SIGNAL rand_wen : STD_LOGIC; + + SIGNAL pointer_read : INTEGER; + SIGNAL pointer_write : INTEGER := 0; + + SIGNAL error_now : STD_LOGIC; + SIGNAL error_new : STD_LOGIC; + + SIGNAL read_stop : STD_LOGIC; +BEGIN + + + all_J : FOR J IN 0 TO 127 GENERATE + data_in(J) <= STD_LOGIC_VECTOR(to_unsigned(J*2+1, 32)); + END GENERATE all_J; + + + ----------------------------------------------------------------------------- + lpp_fifo_1 : lpp_fifo + GENERIC MAP ( + tech => 0, + Mem_use => use_CEL, + DataSz => 32, + AddrSz => 8) + PORT MAP ( + clk => clk, + rstn => rstn, + reUse => '0', + ren => data_ren, + rdata => data_out, + wen => data_wen, + wdata => wdata, + empty => empty, + full => full, + almost_full => full_almost); + + ----------------------------------------------------------------------------- + + + + ----------------------------------------------------------------------------- + -- READ + ----------------------------------------------------------------------------- + PROCESS (clk, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + empty_reg <= '1'; + ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge + empty_reg <= empty; + END IF; + END PROCESS; + + PROCESS (clk, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + data_out_obs <= (OTHERS => '0'); + + pointer_read <= 0; + error_now <= '0'; + error_new <= '0'; + + ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge + error_now <= '0'; + IF empty_reg = '0' THEN + IF data_ren = '0' THEN + --IF data_ren_and_not_empty = '0' THEN + error_new <= '0'; + data_out_obs <= data_out; + + IF pointer_read < 127 THEN + pointer_read <= pointer_read + 1; + ELSE + pointer_read <= 0; + END IF; + + IF data_out /= data_in(pointer_read) THEN + error_now <= '1'; + error_new <= '1'; + END IF; + END IF; + + END IF; + END IF; + END PROCESS; + ----------------------------------------------------------------------------- + + + + + ----------------------------------------------------------------------------- + -- WRITE + ----------------------------------------------------------------------------- + PROCESS (clk, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + full_reg <= '0'; + ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge + full_reg <= full; + END IF; + END PROCESS; + + proc_verif : PROCESS (clk, rstn) + BEGIN -- PROCESS proc_verif + IF rstn = '0' THEN -- asynchronous reset (active low) + pointer_write <= 0; + ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge + IF data_wen = '0' THEN + IF full_reg = '0' THEN + IF pointer_write < 127 THEN + pointer_write <= pointer_write+1; + ELSE + pointer_write <= 0; + END IF; + END IF; + END IF; + END IF; + END PROCESS proc_verif; + + wdata <= data_in(pointer_write) WHEN data_wen = '0' ELSE (OTHERS => 'X'); + ----------------------------------------------------------------------------- + + + + ----------------------------------------------------------------------------- + clk <= NOT clk AFTER 5 ns; -- 100 MHz + ----------------------------------------------------------------------------- + WaveGen_Proc : PROCESS + BEGIN + -- insert signal assignments here + WAIT UNTIL clk = '1'; + read_stop <= '0'; + rstn <= '0'; + run <= '0'; + WAIT UNTIL clk = '1'; + WAIT UNTIL clk = '1'; + WAIT UNTIL clk = '1'; + rstn <= '1'; + WAIT UNTIL clk = '1'; + WAIT UNTIL clk = '1'; + WAIT UNTIL clk = '1'; + WAIT UNTIL clk = '1'; + WAIT UNTIL clk = '1'; + run <= '1'; + WAIT UNTIL clk = '1'; + WAIT UNTIL clk = '1'; + WAIT UNTIL clk = '1'; + WAIT UNTIL clk = '1'; + WAIT FOR 10 us; + read_stop <= '1'; + WAIT FOR 10 us; + read_stop <= '0'; + WAIT FOR 80 us; + REPORT "*** END simulation ***" SEVERITY failure; + WAIT; + END PROCESS WaveGen_Proc; + ----------------------------------------------------------------------------- + + + + ----------------------------------------------------------------------------- + -- RANDOM GENERATOR + ----------------------------------------------------------------------------- + PROCESS (clk, rstn) + VARIABLE seed1, seed2 : POSITIVE; + VARIABLE rand1 : REAL; + VARIABLE RANDOM_VECTOR_VAR : STD_LOGIC_VECTOR(RANDOM_VECTOR_SIZE-1 DOWNTO 0); + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + random_vector <= (OTHERS => '0'); + ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge + UNIFORM(seed1, seed2, rand1); + RANDOM_VECTOR_VAR := STD_LOGIC_VECTOR( + to_unsigned(INTEGER(TRUNC(rand1*TWO_POWER_RANDOM_VECTOR_SIZE)), + RANDOM_VECTOR_VAR'LENGTH) + ); + random_vector <= RANDOM_VECTOR_VAR; + END IF; + END PROCESS; + ----------------------------------------------------------------------------- + rand_wen <= random_vector(1); + rand_ren <= random_vector(0); + ----------------------------------------------------------------------------- + PROCESS (clk, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + data_wen <= '1'; + data_ren <= '1'; + ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge + data_wen <= rand_wen; + IF read_stop = '0' THEN + data_ren <= rand_ren; + ELSE + data_ren <= '1'; + END IF; + END IF; + END PROCESS; + ----------------------------------------------------------------------------- + + + +END; diff --git a/designs/Validation_FIFO/wave.do b/designs/Validation_FIFO/wave.do new file mode 100644 --- /dev/null +++ b/designs/Validation_FIFO/wave.do @@ -0,0 +1,35 @@ +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate -expand -group COMMON /testbench/clk +add wave -noupdate -expand -group COMMON /testbench/rstn +add wave -noupdate -expand -group COMMON /testbench/run +add wave -noupdate -expand -group FIFO -expand -group FIFO_IN /testbench/full_almost +add wave -noupdate -expand -group FIFO -expand -group FIFO_IN /testbench/full +add wave -noupdate -expand -group FIFO -expand -group FIFO_IN /testbench/data_wen +add wave -noupdate -expand -group FIFO -expand -group FIFO_IN /testbench/wdata +add wave -noupdate -expand -group FIFO -expand -group FIFO_OUT /testbench/empty +add wave -noupdate -expand -group FIFO -expand -group FIFO_OUT /testbench/data_ren +add wave -noupdate -expand -group FIFO -expand -group FIFO_OUT /testbench/data_out +add wave -noupdate -radix hexadecimal /testbench/data_out_obs +add wave -noupdate /testbench/pointer_read +add wave -noupdate /testbench/pointer_write +add wave -noupdate /testbench/error_now +add wave -noupdate /testbench/error_new +add wave -noupdate /testbench/read_stop +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {56085000 ps} 0} +configure wave -namecolwidth 510 +configure wave -valuecolwidth 172 +configure wave -justifyvalue left +configure wave -signalnamewidth 0 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits ns +update +WaveRestoreZoom {0 ps} {105131250 ps} diff --git a/lib/lpp/lpp_waveform/lpp_waveform_fifo_headreg.vhd b/lib/lpp/lpp_waveform/lpp_waveform_fifo_headreg.vhd --- a/lib/lpp/lpp_waveform/lpp_waveform_fifo_headreg.vhd +++ b/lib/lpp/lpp_waveform/lpp_waveform_fifo_headreg.vhd @@ -73,6 +73,7 @@ BEGIN -- DATA_REN_FIFO ----------------------------------------------------------------------------- i_data_ren <= s_ren; + PROCESS (clk, rstn) BEGIN IF rstn = '0' THEN @@ -88,17 +89,17 @@ BEGIN s_ren(0) <= o_data_ren(0) WHEN one_ren_and_notEmpty = '1' ELSE NOT ((NOT i_empty(0)) AND (NOT reg_full(0))); - s_ren(1) <= o_data_ren(1) WHEN one_ren_and_notEmpty = '1' ELSE - '1' WHEN s_ren(0) = '0' ELSE + s_ren(1) <= '1' WHEN s_ren(0) = '0' ELSE + o_data_ren(1) WHEN one_ren_and_notEmpty = '1' ELSE NOT ((NOT i_empty(1)) AND (NOT reg_full(1))); - s_ren(2) <= o_data_ren(2) WHEN one_ren_and_notEmpty = '1' ELSE - '1' WHEN s_ren(0) = '0' ELSE + s_ren(2) <= '1' WHEN s_ren(0) = '0' ELSE '1' WHEN s_ren(1) = '0' ELSE + o_data_ren(2) WHEN one_ren_and_notEmpty = '1' ELSE NOT ((NOT i_empty(2)) AND (NOT reg_full(2))); - s_ren(3) <= o_data_ren(3) WHEN one_ren_and_notEmpty = '1' ELSE - '1' WHEN s_ren(0) = '0' ELSE + s_ren(3) <= '1' WHEN s_ren(0) = '0' ELSE '1' WHEN s_ren(1) = '0' ELSE '1' WHEN s_ren(2) = '0' ELSE + o_data_ren(3) WHEN one_ren_and_notEmpty = '1' ELSE NOT ((NOT i_empty(3)) AND (NOT reg_full(3))); ----------------------------------------------------------------------------- all_ren : FOR I IN 3 DOWNTO 0 GENERATE @@ -128,10 +129,10 @@ BEGIN IF s_ren_reg(2) = '0' THEN s_rdata_2 <= i_rdata; END IF; IF s_ren_reg(3) = '0' THEN s_rdata_3 <= i_rdata; END IF; ELSE - s_rdata_0 <= (OTHERS => '0'); - s_rdata_1 <= (OTHERS => '0'); - s_rdata_2 <= (OTHERS => '0'); - s_rdata_3 <= (OTHERS => '0'); + s_rdata_0 <= (OTHERS => '0'); + s_rdata_1 <= (OTHERS => '0'); + s_rdata_2 <= (OTHERS => '0'); + s_rdata_3 <= (OTHERS => '0'); END IF; END IF; END PROCESS;