HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib Commit - r59:7a2c75e9a56c

Modification UART (VHDL)...

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LPP_drivers/exemples/BenchUART/bin/Release/UART_Driver.exe created 644 binary 0 0

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LPP_drivers/exemples/BenchUART/main.c created 644 +19 0

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	1	#include <stdio.h>
	2	#include "lpp_apb_functions.h"
	3	#include "apb_uart_Driver.h"
	4
	5
	6	int main()
	7	{
	8	printf("Debut Main\n\n");
	9	UART_Device* dev = openUART(0);
	10	printf("addr: %x\n",(unsigned int)dev);
	11	printf("cfg: %x\n",dev->ConfigReg);
	12	char* a = "hello world\n";
	13	uartputs(dev,a);
	14	printf("Try #1 done\n");
	15	uartputs(dev,"salut monde\n");
	16	printf("Try #2 done\n");
	17	return 0;
	18	}
	19

LPP_drivers/includes/apb_dac_Driver.h created 644 +60 0

@@ -0,0 +1,60
	1	/*------------------------------------------------------------------------------
	2	-- This file is a part of the LPP VHDL IP LIBRARY
	3	-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
	4	--
	5	-- This program is free software; you can redistribute it and/or modify
	6	-- it under the terms of the GNU General Public License as published by
	7	-- the Free Software Foundation; either version 3 of the License, or
	8	-- (at your option) any later version.
	9	--
	10	-- This program is distributed in the hope that it will be useful,
	11	-- but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	-- GNU General Public License for more details.
	14	--
	15	-- You should have received a copy of the GNU General Public License
	16	-- along with this program; if not, write to the Free Software
	17	-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	18	-------------------------------------------------------------------------------
	19	-- Author : Martin Morlot
	20	-- Mail : martin.morlot@lpp.polytechnique.fr
	21	-----------------------------------------------------------------------------*/
	22	#ifndef APB_CNA_DRIVER_H
	23	#define APB_CNA_DRIVER_H
	24
	25	#define DAC_ready 3
	26	#define DAC_enable 1
	27	#define DAC_disable 0
	28
	29
	30	/*===================================================
	31	T Y P E S D E F
	32	====================================================*/
	33
	34	/** Structure repr�sentant le registre du CNA */
	35	struct DAC_Driver
	36	{
	37	int configReg; /*< Registre de configuration: Flag Ready [1] ; Flag Enable [0] /
	38	int dataReg; /*< Registre de donn�e sur 16 bits /
	39	};
	40
	41	typedef struct DAC_Driver DAC_Device;
	42
	43	/*===================================================
	44	F U N C T I O N S
	45	====================================================*/
	46
	47	/** Ouvre l'acc� au CNA */
	48	DAC_Device* DacOpen(int count);
	49
	50	//DAC_Device* DacClose(int count);
	51
	52	/** Les donn�es sont lus a partir d'un tableau pour obtenir le signal de CAL (10Khz + 625hz) */
	53	int DacTable();
	54
	55	/** Les donn�es sont entr�e par l'utilisateur, la conversion se fait a chaque nouvelle donn�e */
	56	int DacConst();
	57
	58
	59
	60	#endif

LPP_drivers/libsrc/UART/apb_uart_Driver.c created 644 +60 0

@@ -0,0 +1,60
	1	/*------------------------------------------------------------------------------
	2	-- This file is a part of the LPP VHDL IP LIBRARY
	3	-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
	4	--
	5	-- This program is free software; you can redistribute it and/or modify
	6	-- it under the terms of the GNU General Public License as published by
	7	-- the Free Software Foundation; either version 3 of the License, or
	8	-- (at your option) any later version.
	9	--
	10	-- This program is distributed in the hope that it will be useful,
	11	-- but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	-- GNU General Public License for more details.
	14	--
	15	-- You should have received a copy of the GNU General Public License
	16	-- along with this program; if not, write to the Free Software
	17	-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	18	-------------------------------------------------------------------------------
	19	-- Author : Martin Morlot
	20	-- Mail : martin.morlot@lpp.polytechnique.fr
	21	-----------------------------------------------------------------------------*/
	22	#include "apb_uart_Driver.h"
	23	#include "lpp_apb_functions.h"
	24	#include <stdio.h>
	25
	26
	27	UART_Device* openUART(int count)
	28	{
	29	UART_Device* uart0;
	30	uart0 = (UART_Device*) apbgetdevice(LPP_UART_CTRLR,VENDOR_LPP,count);
	31	uart0->ConfigReg = BaudGenOnDuty;
	32	return uart0;
	33	}
	34
	35
	36	void uartputc(UART_Device* dev,char c)
	37	{
	38	//while (!(dev->ConfigReg & (1<<5)));
	39	while (!((dev->ConfigReg & DataSended) == DataSended));
	40	dev->DataWReg = c;
	41	printf(" ");
	42	}
	43
	44	void uartputs(UART_Device* dev,char* s)
	45	{
	46	while (s) uartputc(dev,(s++));
	47	}
	48
	49	char uartgetc(UART_Device* dev)
	50	{
	51	//while (!((dev->ConfigReg & (1<<2))));
	52	while (!((dev->ConfigReg & NewData) == NewData));
	53	return dev->DataRReg;
	54	}
	55
	56	void uartgets(UART_Device* dev,char* s)
	57	{
	58	while (s && (s!=0xd)) *s++ = uartgetc(dev);
	59	}
	60

LPP_drivers/libsrc/UART/apb_uart_Driver.h created 644 +56 0

@@ -0,0 +1,56
	1	/*------------------------------------------------------------------------------
	2	-- This file is a part of the LPP VHDL IP LIBRARY
	3	-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
	4	--
	5	-- This program is free software; you can redistribute it and/or modify
	6	-- it under the terms of the GNU General Public License as published by
	7	-- the Free Software Foundation; either version 3 of the License, or
	8	-- (at your option) any later version.
	9	--
	10	-- This program is distributed in the hope that it will be useful,
	11	-- but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	-- GNU General Public License for more details.
	14	--
	15	-- You should have received a copy of the GNU General Public License
	16	-- along with this program; if not, write to the Free Software
	17	-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	18	-------------------------------------------------------------------------------
	19	-- Author : Martin Morlot
	20	-- Mail : martin.morlot@lpp.polytechnique.fr
	21	-----------------------------------------------------------------------------*/
	22	#ifndef APB_UART_DRIVER_H
	23	#define APB_UART_DRIVER_H
	24
	25
	26	#define BaudGenOnDuty 0
	27	#define DataSended 0x10
	28	#define NewData 0x100
	29
	30	/*===================================================
	31	T Y P E S D E F
	32	====================================================*/
	33
	34	struct UART_Driver
	35	{
	36	int ConfigReg;
	37	int DataWReg;
	38	int DataRReg;
	39	};
	40
	41	typedef struct UART_Driver UART_Device;
	42
	43
	44	/*===================================================
	45	F U N C T I O N S
	46	====================================================*/
	47
	48
	49	UART_Device* openUART(int count);
	50	void uartputc(UART_Device* dev,char c);
	51	void uartputs(UART_Device* dev,char* s);
	52	char uartgetc(UART_Device* dev);
	53	void uartgets(UART_Device* dev,char* s);
	54
	55
	56	#endif

LPP_drivers/exemples/Makefile +1 0

             #------------------------------------------------------------------------------
             #--  This file is a part of the LPP VHDL IP LIBRARY
             #--  Copyright (C) 2010, Laboratory of Plasmas Physic - CNRS
             #--
             #--  This program is free software; you can redistribute it and/or modify
             #--  it under the terms of the GNU General Public License as published by
             #--  the Free Software Foundation; either version 3 of the License, or
             #--  (at your option) any later version.
             #--
             #--  This program is distributed in the hope that it will be useful,
             #--  but WITHOUT ANY WARRANTY; without even the implied warranty of
             #--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
             #--  GNU General Public License for more details.
             #--
             #--  You should have received a copy of the GNU General Public License
             #--  along with this program; if not, write to the Free Software
             #--  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
             #------------------------------------------------------------------------------
             all:
             	make all -C ScanAPB
             	make all -C APB_lcd_ctrlr
             	make all -C BenchFIFO
+            	make all -C BenchUART

LPP_drivers/libsrc/Makefile +2 0

             #------------------------------------------------------------------------------
             #--  This file is a part of the LPP VHDL IP LIBRARY
             #--  Copyright (C) 2010, Laboratory of Plasmas Physic - CNRS
             #--
             #--  This program is free software; you can redistribute it and/or modify
             #--  it under the terms of the GNU General Public License as published by
             #--  the Free Software Foundation; either version 3 of the License, or
             #--  (at your option) any later version.
             #--
             #--  This program is distributed in the hope that it will be useful,
             #--  but WITHOUT ANY WARRANTY; without even the implied warranty of
             #--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
             #--  GNU General Public License for more details.
             #--
             #--  You should have received a copy of the GNU General Public License
             #--  along with this program; if not, write to the Free Software
             #--  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
             #------------------------------------------------------------------------------
             include ../rules.mk
             all:
             	make all -C AMBA
             	make all -C LCD
             	make all -C DAC
             	make all -C FIFO
+            	make all -C UART
             cleanall:
             	make clean -C AMBA
             	make clean -C LCD
             	make clean -C DAC
             	make clean -C FIFO
+            	make clean -C UART

lib/lpp/lpp_uart/Shift_REG.vhd +3 -3

             ------------------------------------------------------------------------------
             --  This file is a part of the LPP VHDL IP LIBRARY
             --  Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
             --
             --  This program is free software; you can redistribute it and/or modify
             --  it under the terms of the GNU General Public License as published by
             --  the Free Software Foundation; either version 3 of the License, or
             --  (at your option) any later version.
             --
             --  This program is distributed in the hope that it will be useful,
             --  but WITHOUT ANY WARRANTY; without even the implied warranty of
             --  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
             --  GNU General Public License for more details.
             --
             --  You should have received a copy of the GNU General Public License
             --  along with this program; if not, write to the Free Software
             --  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
             -------------------------------------------------------------------------------
             --                    Author : Alexis Jeandet
             --                     Mail : alexis.jeandet@lpp.polytechnique.fr
             ----------------------------------------------------------------------------
             library IEEE;
             use IEEE.numeric_std.all;
             use IEEE.std_logic_1164.all;
             --! Gestion Reception/Transmission
             entity Shift_REG is
             generic(Data_sz     :   integer :=  10);
             port(
                 clk         :   in  std_logic;
                 Sclk        :   in  std_logic;
                 reset       :   in  std_logic;
                 SIN         :   in  std_logic;
                 SOUT        :   out std_logic;
                 Serialize   :   in  std_logic;
                 Serialized  :   out std_logic;
                 D           :   in  std_logic_vector(Data_sz-1 downto 0);
                 Q           :   out std_logic_vector(Data_sz-1 downto 0)
             );
             end entity;
             architecture ar_Shift_REG of Shift_REG is
             signal   REG                :   std_logic_vector(Data_sz-1 downto 0);
             signal   Serialized_int     :   std_logic;
             signal   Serialize_reg      :   std_logic;
             signal   Serial_reg         :   std_logic;
             signal   CptBits            :   std_logic_vector(Data_sz-1 downto 0);
             constant CptBits_trig       :   std_logic_vector(Data_sz-1 downto 0) := (others => '1');
             signal   CptBits_flag       :   std_logic;
             signal   CptBits_flag_reg   :   std_logic;
             begin
             Serialized          <=  Serialized_int;
             CptBits_flag        <=  '1' when CptBits = CptBits_trig else '0';
             process(reset,clk)
             begin
                 if reset = '0' then
                     Serialized_int  <=  '1';
                     CptBits_flag_reg    <=  '0';
                     Serial_reg    <=   '0';
                     Q               <=  (others => '0');
                 elsif clk'event and clk = '1' then
                     CptBits_flag_reg    <=  CptBits_flag;
                     Serial_reg   <=    Serialize;
                     if CptBits_flag = '1' and CptBits_flag_reg = '0' then
                         Serialized_int  <=  '1';
                         Q               <=  REG;
                     elsif(Serial_reg='0' and Serialize='1')then
                         Serialized_int  <=  '0';
                     end if;
                 end if;
             end process;
             process(reset,Sclk)
             begin
                 if reset = '0' then
                     CptBits <=  (others =>  '0');
                     REG     <=  (others =>  '0');
                     SOUT    <=  '1';
                     Serialize_reg  <=  '0';
                 elsif Sclk'event and Sclk = '1' then
                     Serialize_reg       <=  Serialized_int;
                     if (Serialized_int = '0' and Serialize_reg ='1') then
                         REG          <=  SIN & D(Data_sz-1 downto 1);
                         SOUT         <=  D(0);
-                    elsif CptBits_flag ='1' then
+            --        elsif CptBits_flag ='1' then
-                        REG          <=  SIN & D(Data_sz-1 downto 1);
+            --            REG          <=  SIN & D(Data_sz-1 downto 1);
-                        SOUT         <=  D(0);
+            --            SOUT         <=  D(0);
                     elsif Serialized_int = '0' then
                         REG          <=  SIN & REG(Data_sz-1 downto 1);
                         SOUT         <=  REG(0);
                     else
                         SOUT         <=  '1';
                     end if;
                     if Serialized_int = '0' then
                         if CptBits_flag = '1' then
                             CptBits <=  (others =>  '0');
                         else
                             CptBits <=  '1' & CptBits(Data_sz-1 downto 1);
                         end if;
                     else
                         CptBits <=  (others =>  '0');
                     end if;
                 end if;
             end process;
             end ar_Shift_REG;

lib/lpp/lpp_uart/UART.vhd +3 -3

             ------------------------------------------------------------------------------
             --  This file is a part of the LPP VHDL IP LIBRARY
             --  Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
             --
             --  This program is free software; you can redistribute it and/or modify
             --  it under the terms of the GNU General Public License as published by
             --  the Free Software Foundation; either version 3 of the License, or
             --  (at your option) any later version.
             --
             --  This program is distributed in the hope that it will be useful,
             --  but WITHOUT ANY WARRANTY; without even the implied warranty of
             --  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
             --  GNU General Public License for more details.
             --
             --  You should have received a copy of the GNU General Public License
             --  along with this program; if not, write to the Free Software
             --  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
             -------------------------------------------------------------------------------
             --                    Author : Alexis Jeandet
             --                     Mail : alexis.jeandet@lpp.polytechnique.fr
             ----------------------------------------------------------------------------
             library IEEE;
             use IEEE.numeric_std.all;
             use IEEE.std_logic_1164.all;
             library lpp;
             use lpp.lpp_uart.all;
             --! Programme qui va gerer toute la communication entre le PC et le FPGA
             entity UART is
             generic(Data_sz     :   integer :=  8);            --! Constante de taille pour un mot de donnee
             port(
                 clk         :   in  std_logic;                              --! Horloge a 25Mhz du systeme
                 reset       :   in  std_logic;                              --! Reset du systeme
                 TXD         :   out std_logic;                              --! Transmission, cote PC
                 RXD         :   in  std_logic;                              --! Reception, cote PC
                 Capture     :   in  std_logic;                              --! "Reset" cible pour le generateur de bauds, ici indissocie du reset global
                 NwDat       :   out std_logic;                              --! Flag, Nouvelle donnee presente
                 ACK         :   in  std_logic;                              --! Flag, Reponse au flag precedent
                 Send        :   in  std_logic;                              --! Flag, Demande d'envoi sur le bus
                 Sended      :   out std_logic;                              --! Flag, Envoi termine
                 BTrigger    :   out std_logic_vector(11 downto 0);          --! Registre contenant la valeur du diviseur de frequence pour la transmission
                 RDATA       :   out std_logic_vector(Data_sz-1 downto 0);   --! Mot de donnee en provenance de l'utilisateur
                 WDATA       :   in  std_logic_vector(Data_sz-1 downto 0)    --! Mot de donnee a transmettre a l'utilisateur
             );
             end entity;
             --! @details Gestion de la Reception/Transmission donc de la Vectorisation/Serialisation
             --! ainsi que la detection et le reglage de le frequence de transmission optimale sur le bus (Generateur de Bauds)
             architecture ar_UART of UART is
             signal  Bclk    :   std_logic;
             signal  RDATA_int       :   std_logic_vector(Data_sz+1 downto 0);
             signal  WDATA_int       :   std_logic_vector(Data_sz+1 downto 0);
             signal  TXD_Dummy       :   std_logic;
             signal  NwDat_int       :   std_logic;
             signal  NwDat_int_reg   :   std_logic;
             signal  receive         :   std_logic;
             constant zeroVect       :   std_logic_vector(Data_sz+1 downto 0) := (others => '0');
             begin
             WDATA_int   <=  '1' & WDATA & '0';
-            BaudGenerator : BaudGen
+            BaudGenerator : entity work.BaudGen
                 port map(clk,reset,Capture,Bclk,RXD,BTrigger);
-            RX_REG  : Shift_REG
+            RX_REG  : entity work.Shift_REG
                 generic map(Data_sz+2)
                 port map(clk,Bclk,reset,RXD,TXD_Dummy,receive,NwDat_int,zeroVect,RDATA_int);
-            TX_REG  : Shift_REG
+            TX_REG  : entity work.Shift_REG
                 generic map(Data_sz+2)
                 port map(clk,Bclk,reset,'1',TXD,Send,Sended,WDATA_int);
             process(clk,reset)
             begin
                 if reset = '0' then
                     NwDat   <=  '0';
                 elsif clk'event and clk = '1' then
                     NwDat_int_reg   <=  NwDat_int;
                     if RXD = '1' and NwDat_int = '1' then
                         receive <=  '0';
                     elsif RXD = '0' then
                         receive <=  '1';
                     end if;
                     if NwDat_int_reg = '0' and NwDat_int = '1' then
                         NwDat   <=  '1';
             				RDATA   <=  RDATA_int(8 downto 1);
                     elsif ack = '1' then
                         NwDat   <=  '0';
                     end if;
                 end if;
             end process;
             end ar_UART;

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