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------------------------------------------------------------------------------
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-- This file is a part of the LPP VHDL IP LIBRARY
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-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-------------------------------------------------------------------------------
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-- Author : Alexis Jeandet
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-- Mail : alexis.jeandet@lpp.polytechnique.fr
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----------------------------------------------------------------------------
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library IEEE;
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use IEEE.numeric_std.all;
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use IEEE.std_logic_1164.all;
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library lpp;
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use lpp.lpp_uart.all;
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--! Programme qui va gerer toute la communication entre le PC et le FPGA
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entity UART is
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generic(Data_sz : integer := 8); --! Constante de taille pour un mot de donnee
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port(
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clk : in std_logic; --! Horloge a 25Mhz du systeme
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reset : in std_logic; --! Reset du systeme
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TXD : out std_logic; --! Transmission, cote PC
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RXD : in std_logic; --! Reception, cote PC
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Capture : in std_logic; --! "Reset" cible pour le generateur de bauds, ici indissocie du reset global
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NwDat : out std_logic; --! Flag, Nouvelle donnee presente
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ACK : in std_logic; --! Flag, Reponse au flag precedent
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Send : in std_logic; --! Flag, Demande d'envoi sur le bus
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Sended : out std_logic; --! Flag, Envoi termine
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BTrigger : out std_logic_vector(11 downto 0); --! Registre contenant la valeur du diviseur de frequence pour la transmission
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RDATA : out std_logic_vector(Data_sz-1 downto 0); --! Mot de donnee en provenance de l'utilisateur
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WDATA : in std_logic_vector(Data_sz-1 downto 0) --! Mot de donnee a transmettre a l'utilisateur
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);
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end entity;
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--! @details Gestion de la Reception/Transmission donc de la Vectorisation/Serialisation
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--! ainsi que la detection et le reglage de le frequence de transmission optimale sur le bus (Generateur de Bauds)
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architecture ar_UART of UART is
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signal Bclk : std_logic;
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signal RDATA_int : std_logic_vector(Data_sz+1 downto 0);
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signal WDATA_int : std_logic_vector(Data_sz+1 downto 0);
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signal TXD_Dummy : std_logic;
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signal NwDat_int : std_logic;
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signal NwDat_int_reg : std_logic;
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signal receive : std_logic;
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constant zeroVect : std_logic_vector(Data_sz+1 downto 0) := (others => '0');
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begin
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WDATA_int <= '1' & WDATA & '0';
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BaudGenerator : entity work.BaudGen
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port map(clk,reset,Capture,Bclk,RXD,BTrigger);
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RX_REG : entity work.Shift_REG
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generic map(Data_sz+2)
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port map(clk,Bclk,reset,RXD,TXD_Dummy,receive,NwDat_int,zeroVect,RDATA_int);
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TX_REG : entity work.Shift_REG
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generic map(Data_sz+2)
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port map(clk,Bclk,reset,'1',TXD,Send,Sended,WDATA_int);
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process(clk,reset)
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begin
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if reset = '0' then
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NwDat <= '0';
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elsif clk'event and clk = '1' then
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NwDat_int_reg <= NwDat_int;
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if RXD = '1' and NwDat_int = '1' then
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receive <= '0';
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elsif RXD = '0' then
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receive <= '1';
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end if;
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if NwDat_int_reg = '0' and NwDat_int = '1' then
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NwDat <= '1';
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RDATA <= RDATA_int(8 downto 1);
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elsif ack = '1' then
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NwDat <= '0';
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end if;
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end if;
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end process;
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end ar_UART;
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