HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib Commit - r544:7527baf4377d

add automatic tb for SpectralMatrix

pellion -

r544:7527baf4377d JC

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r544:7527baf4377d

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designs/Validation_MS_auto/Makefile created 644 +54 0

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		1	#GRLIB=../..
		2	VHDLIB=../..
		3	SCRIPTSDIR=$(VHDLIB)/scripts/
		4	GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh)
		5	TOP=leon3mp
		6	BOARD=em-LeonLPP-A3PE3kL-v3-core1
		7	include $(GRLIB)/boards/$(BOARD)/Makefile.inc
		8	DEVICE=$(PART)-$(PACKAGE)$(SPEED)
		9	UCF=$(GRLIB)/boards/$(BOARD)/$(TOP).ucf
		10	QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf
		11	EFFORT=high
		12	XSTOPT=
		13	SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0"
		14	#VHDLSYNFILES=config.vhd ahbrom.vhd leon3mp.vhd
		15	VHDLSYNFILES=
		16	VHDLSIMFILES= data_read.vhd data_write.vhd data_read_with_timer.vhd data_write_with_burstCounter.vhd tb.vhd
		17	SIMTOP=testbench
		18	#SDCFILE=$(GRLIB)/boards/$(BOARD)/synplify.sdc
		19	#SDC=$(GRLIB)/boards/$(BOARD)/leon3mp.sdc
		20	PDC=$(GRLIB)/boards/$(BOARD)/em-LeonLPP-A3PE3kL.pdc
		21	BITGEN=$(GRLIB)/boards/$(BOARD)/default.ut
		22	CLEAN=soft-clean
		23
		24	TECHLIBS = proasic3e
		25
		26	LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
		27	tmtc openchip hynix ihp gleichmann micron usbhc
		28
		29	DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \
		30	pci grusbhc haps slink ascs pwm coremp7 spi ac97 \
		31	./amba_lcd_16x2_ctrlr \
		32	./general_purpose/lpp_AMR \
		33	./general_purpose/lpp_balise \
		34	./general_purpose/lpp_delay \
		35	./lpp_bootloader \
		36	./lpp_cna \
		37	./lpp_uart \
		38	./lpp_usb \
		39	./dsp/lpp_fft_rtax \
		40	./lpp_sim/CY7C1061DV33 \
		41
		42	FILESKIP = i2cmst.vhd \
		43	APB_MULTI_DIODE.vhd \
		44	APB_MULTI_DIODE.vhd \
		45	Top_MatrixSpec.vhd \
		46	APB_FFT.vhd \
		47	CoreFFT_simu.vhd \
		48	lpp_lfr_apbreg_simu.vhd
		49
		50	include $(GRLIB)/bin/Makefile
		51	include $(GRLIB)/software/leon3/Makefile
		52
		53	################## project specific targets ##########################
		54

designs/Validation_MS_auto/data_file/test/test_gen_data.py created 644 +79 0

			@@ -0,0 +1,79
		1	import math as m
		2	import numpy as np
		3
		4	def int2hex(n,nbits):
		5	if (nbits % 4) != 0 :
		6	return 'ERROR 1!'
		7	spec='0'+str(nbits/4)+'x'
		8	if n >= (-2(nbits-1)) and n <= (2(nbits-1)-1) :
		9	return format(n, spec) if n>=0 else format(2**nbits+n, spec)
		10	else :
		11	return 'ERROR 2!'
		12
		13
		14
		15	nb_point = 256
		16	t = np.arange(nb_point)
		17
		18	## f0
		19	ampl_f0_0 = pow(2,14)
		20	freq_f0_0 = float(16)/256
		21	phi_f0_0 = 0
		22
		23	ampl_f0_1 = pow(2,13)
		24	freq_f0_1 = float(16)/256
		25	phi_f0_1 = 0
		26
		27	ampl_f0_2 = pow(2,12)
		28	freq_f0_2 = float(16)/256
		29	phi_f0_2 = 0
		30
		31	ampl_f0_3 = pow(2,11)
		32	freq_f0_3 = float(16)/256
		33	phi_f0_3 = 0
		34
		35	ampl_f0_4 = pow(2,10)
		36	freq_f0_4 = float(16)/256
		37	phi_f0_4 = 0
		38
		39	x_f0 = [ampl_f0_0 * np.cos(2 * m.pi * freq_f0_0 * t + phi_f0_0 * m.pi / 180 ) ,
		40	ampl_f0_1 * np.cos(2 * m.pi * freq_f0_1 * t + phi_f0_1 * m.pi / 180 ) ,
		41	ampl_f0_2 * np.cos(2 * m.pi * freq_f0_2 * t + phi_f0_2 * m.pi / 180 ) ,
		42	ampl_f0_3 * np.cos(2 * m.pi * freq_f0_3 * t + phi_f0_3 * m.pi / 180 ) ,
		43	ampl_f0_4 * np.cos(2 * m.pi * freq_f0_4 * t + phi_f0_4 * m.pi / 180 ) ]
		44
		45	# x_f0 = [ampl_f0_0 * np.cos(2 * m.pi * freq_f0_0 * t + phi_f0_0 * m.pi / 180 ) ,
		46	# np.zeros(nb_point,dtype=np.int16) + 10 ,
		47	# np.zeros(nb_point,dtype=np.int16) - 10 ,
		48	# ampl_f0_3 * np.cos(2 * m.pi * freq_f0_3 * t + phi_f0_3 * m.pi / 180 ) ,
		49	# ampl_f0_4 * np.cos(2 * m.pi * freq_f0_4 * t + phi_f0_4 * m.pi / 180 ) ]
		50
		51
		52	x_f0_int16 = [np.zeros(nb_point,dtype=np.int16),
		53	np.zeros(nb_point,dtype=np.int16),
		54	np.zeros(nb_point,dtype=np.int16),
		55	np.zeros(nb_point,dtype=np.int16),
		56	np.zeros(nb_point,dtype=np.int16)]
		57
		58	for j in xrange(5) :
		59	for i in xrange(nb_point) :
		60	x_f0_int16[j][i] = int(round(x_f0[j][i]))
		61
		62	f = open("data_f0.txt", 'w')
		63	for i in xrange(nb_point) :
		64	for j in xrange(5) :
		65	f.write(int2hex(x_f0_int16[j][i],16))
		66	f.write('\n')
		67	f.close
		68
		69	f = open("data_f1.txt", 'w')
		70	for i in xrange(1) :
		71	for j in xrange(5) :
		72	f.write(int2hex(0,16))
		73	f.close
		74
		75	f = open("data_f2.txt", 'w')
		76	for i in xrange(1) :
		77	for j in xrange(5) :
		78	f.write(int2hex(0,16))
		79	f.close

designs/Validation_MS_auto/data_read.vhd created 644 +84 0

			@@ -0,0 +1,84
		1
		2	LIBRARY ieee;
		3	USE ieee.std_logic_1164.ALL;
		4	USE IEEE.MATH_REAL.ALL;
		5	USE ieee.numeric_std.ALL;
		6
		7	LIBRARY std;
		8	use std.textio.all;
		9
		10	ENTITY data_read IS
		11	GENERIC (
		12	input_file_name : STRING := "input_data_2.txt";
		13	NB_CHAR_PER_DATA : INTEGER := 4
		14	);
		15	PORT (
		16	clk : IN STD_LOGIC;
		17	read_new_data : IN STD_LOGIC;
		18
		19	end_of_file : OUT STD_LOGIC;
		20
		21	data_out_val : OUT STD_LOGIC;
		22	data_out : OUT STD_LOGIC_VECTOR(NB_CHAR_PER_DATA * 4 - 1 DOWNTO 0)
		23	);
		24	END;
		25
		26	ARCHITECTURE beh OF data_read IS
		27
		28	BEGIN -- beh
		29
		30	PROCESS
		31	FILE file_pointer : TEXT;
		32	VARIABLE line_read : LINE;
		33	VARIABLE line_content : STRING(1 TO NB_CHAR_PER_DATA);
		34	VARIABLE char_read : CHARACTER;
		35	VARIABLE data_read : STD_LOGIC_VECTOR(NB_CHAR_PER_DATA * 4 - 1 DOWNTO 0);
		36	VARIABLE signal_part : STD_LOGIC_VECTOR(3 DOWNTO 0);
		37	BEGIN -- PROCESS
		38	end_of_file <= '0';
		39	data_out_val <= '0';
		40	data_out <= (OTHERS => '0');
		41
		42	WAIT UNTIL clk = '1';
		43
		44	file_open(file_pointer,input_file_name,READ_MODE);
		45	WHILE NOT endfile(file_pointer) LOOP
		46	readline(file_pointer, line_read);
		47	read(line_read,line_content);
		48	FOR i IN 1 TO NB_CHAR_PER_DATA LOOP
		49	char_read := line_content(NB_CHAR_PER_DATA+1-i);
		50	CASE char_read IS
		51	WHEN '0' => data_read(4i-1 DOWNTO 4(i-1)) := "0000";
		52	WHEN '1' => data_read(4i-1 DOWNTO 4(i-1)) := "0001";
		53	WHEN '2' => data_read(4i-1 DOWNTO 4(i-1)) := "0010";
		54	WHEN '3' => data_read(4i-1 DOWNTO 4(i-1)) := "0011";
		55	WHEN '4' => data_read(4i-1 DOWNTO 4(i-1)) := "0100";
		56	WHEN '5' => data_read(4i-1 DOWNTO 4(i-1)) := "0101";
		57	WHEN '6' => data_read(4i-1 DOWNTO 4(i-1)) := "0110";
		58	WHEN '7' => data_read(4i-1 DOWNTO 4(i-1)) := "0111";
		59	WHEN '8' => data_read(4i-1 DOWNTO 4(i-1)) := "1000";
		60	WHEN '9' => data_read(4i-1 DOWNTO 4(i-1)) := "1001";
		61	WHEN 'a' => data_read(4i-1 DOWNTO 4(i-1)) := "1010";
		62	WHEN 'b' => data_read(4i-1 DOWNTO 4(i-1)) := "1011";
		63	WHEN 'c' => data_read(4i-1 DOWNTO 4(i-1)) := "1100";
		64	WHEN 'd' => data_read(4i-1 DOWNTO 4(i-1)) := "1101";
		65	WHEN 'e' => data_read(4i-1 DOWNTO 4(i-1)) := "1110";
		66	WHEN 'f' => data_read(4i-1 DOWNTO 4(i-1)) := "1111";
		67	WHEN OTHERS => NULL;
		68	END CASE;
		69	END LOOP;
		70	WAIT UNTIL read_new_data = '1';
		71	WAIT UNTIL clk = '1';
		72	data_out <= data_read;
		73	data_out_val <= '1';
		74	WAIT UNTIL clk = '1';
		75	data_out_val <= '0';
		76	END LOOP;
		77	file_close(file_pointer);
		78	end_of_file <= '1';
		79	data_out_val <= '0';
		80	WAIT;
		81
		82	END PROCESS;
		83
		84	END beh;

designs/Validation_MS_auto/data_read_with_timer.vhd created 644 +74 0

			@@ -0,0 +1,74
		1
		2	LIBRARY ieee;
		3	USE ieee.std_logic_1164.ALL;
		4	USE IEEE.MATH_REAL.ALL;
		5	USE ieee.numeric_std.ALL;
		6
		7	LIBRARY std;
		8	use std.textio.all;
		9
		10	ENTITY data_read_with_timer IS
		11	GENERIC (
		12	input_file_name : STRING := "input_data_2.txt";
		13	NB_CHAR_PER_DATA : INTEGER := 4;
		14	NB_CYCLE_TIMER : INTEGER := 1024
		15	);
		16	PORT (
		17	clk : IN STD_LOGIC;
		18	rstn : IN STD_LOGIC;
		19
		20	end_of_file : OUT STD_LOGIC;
		21
		22	data_out_val : OUT STD_LOGIC;
		23	data_out : OUT STD_LOGIC_VECTOR(NB_CHAR_PER_DATA * 4 - 1 DOWNTO 0)
		24	);
		25	END;
		26
		27	ARCHITECTURE beh OF data_read_with_timer IS
		28
		29	COMPONENT data_read
		30	GENERIC (
		31	input_file_name : STRING;
		32	NB_CHAR_PER_DATA : INTEGER);
		33	PORT (
		34	clk : IN STD_LOGIC;
		35	read_new_data : IN STD_LOGIC;
		36	end_of_file : OUT STD_LOGIC;
		37	data_out_val : OUT STD_LOGIC;
		38	data_out : OUT STD_LOGIC_VECTOR(NB_CHAR_PER_DATA * 4 - 1 DOWNTO 0));
		39	END COMPONENT;
		40
		41	SIGNAL nb_cycle_counter : INTEGER;
		42	SIGNAL read_new_data : STD_LOGIC;
		43
		44	BEGIN -- beh
		45
		46	PROCESS (clk, rstn)
		47	BEGIN -- PROCESS
		48	IF rstn = '0' THEN -- asynchronous reset (active low)
		49	nb_cycle_counter <= 0;
		50	read_new_data <= '0';
		51	ELSIF clk'event AND clk = '1' THEN -- rising clock edge
		52	IF nb_cycle_counter < NB_CYCLE_TIMER-1 THEN
		53	nb_cycle_counter <= nb_cycle_counter + 1;
		54	read_new_data <= '0';
		55	ELSE
		56	nb_cycle_counter <= 0;
		57	read_new_data <= '1';
		58	END IF;
		59	END IF;
		60	END PROCESS;
		61
		62
		63	data_read_1: data_read
		64	GENERIC MAP (
		65	input_file_name => input_file_name,
		66	NB_CHAR_PER_DATA => NB_CHAR_PER_DATA)
		67	PORT MAP (
		68	clk => clk,
		69	read_new_data => read_new_data,
		70	end_of_file => end_of_file,
		71	data_out_val => data_out_val,
		72	data_out => data_out);
		73
		74	END beh;

designs/Validation_MS_auto/data_write.vhd created 644 +77 0

			@@ -0,0 +1,77
		1
		2	LIBRARY ieee;
		3	USE ieee.std_logic_1164.ALL;
		4	USE IEEE.MATH_REAL.ALL;
		5	USE ieee.numeric_std.ALL;
		6
		7	LIBRARY std;
		8	use std.textio.all;
		9
		10	ENTITY data_write IS
		11	GENERIC (
		12	OUTPUT_FILE_NAME : STRING := "output_data_2.txt";
		13	NB_CHAR_PER_DATA : INTEGER := 4
		14	);
		15	PORT (
		16	clk : IN STD_LOGIC;
		17	data_in_val : IN STD_LOGIC;
		18	data : IN STD_LOGIC_VECTOR(NB_CHAR_PER_DATA * 4 - 1 DOWNTO 0);
		19	close_file : IN STD_LOGIC
		20	);
		21	END;
		22
		23	ARCHITECTURE beh OF data_write IS
		24
		25
		26	BEGIN -- beh
		27
		28	PROCESS
		29	FILE file_pointer : TEXT;
		30	VARIABLE line_read : LINE;
		31	VARIABLE line_content : STRING(1 TO 4);
		32	VARIABLE line_write : LINE;
		33	VARIABLE line_content_write : STRING(1 TO NB_CHAR_PER_DATA);
		34	VARIABLE line_content_write_inv : STRING(1 TO NB_CHAR_PER_DATA);
		35	VARIABLE char_read : CHARACTER;
		36	VARIABLE data_read : STD_LOGIC_VECTOR(15 DOWNTO 0);
		37	VARIABLE signal_part : STD_LOGIC_VECTOR(3 DOWNTO 0);
		38
		39	BEGIN -- PROCESS
		40
		41	WAIT UNTIL clk = '1';
		42
		43	file_open(file_pointer , OUTPUT_FILE_NAME , WRITE_MODE);
		44	WHILE close_file = '0' LOOP
		45	IF data_in_val = '1' THEN
		46	FOR i IN 1 TO NB_CHAR_PER_DATA LOOP
		47	signal_part := data(i4-1 DOWNTO (i-1)4);
		48	CASE signal_part IS
		49	WHEN "0000" => line_content_write(NB_CHAR_PER_DATA+1-i) := '0';
		50	WHEN "0001" => line_content_write(NB_CHAR_PER_DATA+1-i) := '1';
		51	WHEN "0010" => line_content_write(NB_CHAR_PER_DATA+1-i) := '2';
		52	WHEN "0011" => line_content_write(NB_CHAR_PER_DATA+1-i) := '3';
		53	WHEN "0100" => line_content_write(NB_CHAR_PER_DATA+1-i) := '4';
		54	WHEN "0101" => line_content_write(NB_CHAR_PER_DATA+1-i) := '5';
		55	WHEN "0110" => line_content_write(NB_CHAR_PER_DATA+1-i) := '6';
		56	WHEN "0111" => line_content_write(NB_CHAR_PER_DATA+1-i) := '7';
		57	WHEN "1000" => line_content_write(NB_CHAR_PER_DATA+1-i) := '8';
		58	WHEN "1001" => line_content_write(NB_CHAR_PER_DATA+1-i) := '9';
		59	WHEN "1010" => line_content_write(NB_CHAR_PER_DATA+1-i) := 'a';
		60	WHEN "1011" => line_content_write(NB_CHAR_PER_DATA+1-i) := 'b';
		61	WHEN "1100" => line_content_write(NB_CHAR_PER_DATA+1-i) := 'c';
		62	WHEN "1101" => line_content_write(NB_CHAR_PER_DATA+1-i) := 'd';
		63	WHEN "1110" => line_content_write(NB_CHAR_PER_DATA+1-i) := 'e';
		64	WHEN "1111" => line_content_write(NB_CHAR_PER_DATA+1-i) := 'f';
		65	WHEN OTHERS => NULL;
		66	END CASE;
		67	END LOOP; -- i
		68	write(line_write,line_content_write);
		69	writeline(file_pointer,line_write);
		70	END IF;
		71	WAIT UNTIL clk = '1';
		72	END LOOP;
		73	file_close(file_pointer);
		74	WAIT;
		75	END PROCESS;
		76
		77	END beh;

designs/Validation_MS_auto/data_write_with_burstCounter.vhd created 644 +81 0

			@@ -0,0 +1,81
		1
		2	LIBRARY ieee;
		3	USE ieee.std_logic_1164.ALL;
		4	USE IEEE.MATH_REAL.ALL;
		5	USE ieee.numeric_std.ALL;
		6
		7	LIBRARY std;
		8	use std.textio.all;
		9
		10	ENTITY data_write_with_burstCounter IS
		11	GENERIC (
		12	OUTPUT_FILE_NAME : STRING := "output_data_2.txt";
		13	NB_CHAR_PER_DATA : INTEGER := 4;
		14	BASE_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0)
		15	);
		16	PORT (
		17	clk : IN STD_LOGIC;
		18	rstn : IN STD_LOGIC;
		19
		20	burst_valid : IN STD_LOGIC;
		21	burst_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
		22	data_ren : OUT STD_LOGIC;
		23
		24	data : IN STD_LOGIC_VECTOR(NB_CHAR_PER_DATA * 4 - 1 DOWNTO 0);
		25	close_file : IN STD_LOGIC
		26	);
		27	END;
		28
		29	ARCHITECTURE beh OF data_write_with_burstCounter IS
		30
		31	COMPONENT data_write
		32	GENERIC (
		33	OUTPUT_FILE_NAME : STRING;
		34	NB_CHAR_PER_DATA : INTEGER );
		35	PORT (
		36	clk : IN STD_LOGIC;
		37	data_in_val : IN STD_LOGIC;
		38	data : IN STD_LOGIC_VECTOR(NB_CHAR_PER_DATA * 4 - 1 DOWNTO 0);
		39	close_file : IN STD_LOGIC);
		40	END COMPONENT;
		41
		42	SIGNAL ren_counter : INTEGER;
		43	SIGNAL data_ren_s : STD_LOGIC;
		44	SIGNAL data_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
		45	SIGNAL data_in_val : STD_LOGIC;
		46
		47	BEGIN
		48
		49	PROCESS (clk, rstn)
		50	BEGIN -- PROCESS
		51	IF rstn = '0' THEN -- asynchronous reset (active low)
		52	ren_counter <= 0;
		53	data_ren_s <= '1';
		54	data_s <= (OTHERS => '0');
		55	ELSIF clk'event AND clk = '1' THEN -- rising clock edge
		56	data_s <= data;
		57	data_ren_s <= '1';
		58	IF ren_counter = 0 AND burst_valid = '1' AND burst_addr = BASE_ADDR THEN
		59	ren_counter <= 16;
		60	END IF;
		61	IF ren_counter > 0 THEN
		62	ren_counter <= ren_counter - 1;
		63	data_ren_s <= '0';
		64	END IF;
		65	END IF;
		66	END PROCESS;
		67
		68	data_in_val <= NOT data_ren_s;
		69	data_ren <= data_ren_s;
		70
		71	data_write_1: data_write
		72	GENERIC MAP (
		73	OUTPUT_FILE_NAME => OUTPUT_FILE_NAME,
		74	NB_CHAR_PER_DATA => NB_CHAR_PER_DATA)
		75	PORT MAP (
		76	clk => clk,
		77	data_in_val => data_in_val,
		78	data => data_s,
		79	close_file => close_file);
		80
		81	END beh;

designs/Validation_MS_auto/run.do created 644 +13 0

			@@ -0,0 +1,13
		1	vcom -quiet -93 -work work data_read.vhd
		2	vcom -quiet -93 -work work data_write.vhd
		3	vcom -quiet -93 -work work data_read_with_timer.vhd
		4	vcom -quiet -93 -work work data_write_with_burstCounter.vhd
		5	vcom -quiet -93 -work work tb.vhd
		6
		7	vsim work.testbench
		8
		9	log -r *
		10
		11	do wave.do
		12
		13	run -all

designs/Validation_MS_auto/run_nowindow.do created 644 +56 0

			@@ -0,0 +1,56
		1	#vsim -c -do "run_nowindow.do" -goutput_file_name="output_data.txt" -ginput_file_name="input_data.txt"
		2
		3	quietly set args [ split $argv {\ } ]
		4	set argc [ llength $args ]
		5
		6	set outputfile_f0 "output\_data\_f0\.txt"
		7	set inputfile_f0 "input\_data\_f0\.txt"
		8	set outputfile_f1 "output\_data\_f1\.txt"
		9	set inputfile_f1 "input\_data\_f1\.txt"
		10	set outputfile_f2 "output\_data\_f2\.txt"
		11	set inputfile_f2 "input\_data\_f2\.txt"
		12
		13	#puts "there are $argc arguments to this script"
		14	#puts "The name of this script is $argv0"
		15
		16	#foreach arg $::argv {puts $arg}
		17
		18	#puts [ lindex $args 4 ]
		19
		20	for { set i 0 } { $i < $argc } { incr i 1 } {
		21	puts "$i : [ lindex $args $i ]"
		22
		23	if { [ string match -goutput_file_name_f0=* [ lindex $args $i ] ] } {
		24	set outputfile_f0 [ lindex [ split [ lindex $args $i ] {=} ] 1 ]
		25	puts "OUTPUT_FILE_f0 : $outputfile_f0"
		26	}
		27	if { [ string match -goutput_file_name_f1=* [ lindex $args $i ] ] } {
		28	set outputfile_f1 [ lindex [ split [ lindex $args $i ] {=} ] 1 ]
		29	puts "OUTPUT_FILE_f1 : $outputfile_f1"
		30	}
		31	if { [ string match -goutput_file_name_f2=* [ lindex $args $i ] ] } {
		32	set outputfile_f2 [ lindex [ split [ lindex $args $i ] {=} ] 1 ]
		33	puts "OUTPUT_FILE_f2 : $outputfile_f2"
		34	}
		35
		36	if { [ string match -ginput_file_name_f0=* [ lindex $args $i ] ] } {
		37	set inputfile_f0 [ lindex [ split [ lindex $args $i ] {=} ] 1 ]
		38	puts "INPUT_FILE_F0 : $inputfile_f0"
		39	}
		40	if { [ string match -ginput_file_name_f1=* [ lindex $args $i ] ] } {
		41	set inputfile_f1 [ lindex [ split [ lindex $args $i ] {=} ] 1 ]
		42	puts "INPUT_FILE_F1 : $inputfile_f1"
		43	}
		44	if { [ string match -ginput_file_name_f2=* [ lindex $args $i ] ] } {
		45	set inputfile_f2 [ lindex [ split [ lindex $args $i ] {=} ] 1 ]
		46	puts "INPUT_FILE_F2 : $inputfile_f2"
		47	}
		48	}
		49
		50	vsim work.testbench \
		51	-goutput_file_name_f0=$outputfile_f0 -ginput_file_name_f0=$inputfile_f0 \
		52	-goutput_file_name_f1=$outputfile_f1 -ginput_file_name_f1=$inputfile_f1 \
		53	-goutput_file_name_f2=$outputfile_f2 -ginput_file_name_f2=$inputfile_f2
		54	when -label end_of_simulation {end_of_sim == '1'} {echo "End of simulation"; exit ;}
		55	run -all
		56	exit

designs/Validation_MS_auto/script_run.sh created 644 +29 0

			@@ -0,0 +1,29
		1	#!/bin/sh
		2
		3	for FILE_NAME in "$@"
		4	do
		5	vsim -c -do "run_nowindow.do" \
		6	-goutput_file_name_f0=$FILE_NAME"_f0_output.txt" -ginput_file_name_f0=$FILE_NAME"_f0.txt" \
		7	-goutput_file_name_f1=$FILE_NAME"_f1_output.txt" -ginput_file_name_f1=$FILE_NAME"_f1.txt" \
		8	-goutput_file_name_f2=$FILE_NAME"_f2_output.txt" -ginput_file_name_f2=$FILE_NAME"_f2.txt"
		9
		10	PATH_FILE=`pwd`
		11
		12	BASE_NAME_FILE=`basename ${FILE_NAME}_f0.txt`
		13	echo -e "input_0="$BASE_NAME_FILE > $FILE_NAME.conf
		14	BASE_NAME_FILE=`basename ${FILE_NAME}_f1.txt`
		15	echo -e "input_1="$BASE_NAME_FILE >> $FILE_NAME.conf
		16	BASE_NAME_FILE=`basename ${FILE_NAME}_f2.txt`
		17	echo -e "input_2="$BASE_NAME_FILE >> $FILE_NAME.conf
		18
		19	BASE_NAME_FILE=`basename ${FILE_NAME}_f0_output.txt`
		20	echo -e "output_0="$BASE_NAME_FILE >> $FILE_NAME.conf
		21	BASE_NAME_FILE=`basename ${FILE_NAME}_f1_output.txt`
		22	echo -e "output_1="$BASE_NAME_FILE >> $FILE_NAME.conf
		23	BASE_NAME_FILE=`basename ${FILE_NAME}_f2_output.txt`
		24	echo -e "output_2="$BASE_NAME_FILE >> $FILE_NAME.conf
		25	done
		26
		27
		28
		29

designs/Validation_MS_auto/tb.vhd created 644 +438 0

			@@ -0,0 +1,438
		1
		2	LIBRARY ieee;
		3	USE ieee.std_logic_1164.ALL;
		4	USE IEEE.MATH_REAL.ALL;
		5	USE ieee.numeric_std.ALL;
		6
		7	LIBRARY std;
		8	USE std.textio.ALL;
		9
		10	LIBRARY lpp;
		11	USE lpp.cic_pkg.ALL;
		12	USE lpp.chirp_pkg.ALL;
		13	USE lpp.lpp_fft.ALL;
		14	USE lpp.lpp_lfr_pkg.ALL;
		15	USE lpp.iir_filter.ALL;
		16
		17	ENTITY testbench IS
		18	GENERIC (
		19	input_file_name_f0 : STRING := "input_data_f0.txt";
		20	input_file_name_f1 : STRING := "input_data_f1.txt";
		21	input_file_name_f2 : STRING := "input_data_f2.txt";
		22	output_file_name_f0 : STRING := "output_data_f0.txt";
		23	output_file_name_f1 : STRING := "output_data_f1.txt";
		24	output_file_name_f2 : STRING := "output_data_f2.txt");
		25	END;
		26
		27	ARCHITECTURE behav OF testbench IS
		28
		29	COMPONENT data_read_with_timer
		30	GENERIC (
		31	input_file_name : STRING;
		32	NB_CHAR_PER_DATA : INTEGER;
		33	NB_CYCLE_TIMER : INTEGER);
		34	PORT (
		35	clk : IN STD_LOGIC;
		36	rstn : IN STD_LOGIC;
		37	end_of_file : OUT STD_LOGIC;
		38	data_out_val : OUT STD_LOGIC;
		39	data_out : OUT STD_LOGIC_VECTOR(NB_CHAR_PER_DATA * 4 - 1 DOWNTO 0));
		40	END COMPONENT;
		41
		42	COMPONENT data_write_with_burstCounter
		43	GENERIC (
		44	OUTPUT_FILE_NAME : STRING;
		45	NB_CHAR_PER_DATA : INTEGER;
		46	BASE_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0));
		47	PORT (
		48	clk : IN STD_LOGIC;
		49	rstn : IN STD_LOGIC;
		50	burst_valid : IN STD_LOGIC;
		51	burst_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
		52	data_ren : OUT STD_LOGIC;
		53	data : IN STD_LOGIC_VECTOR(NB_CHAR_PER_DATA * 4 - 1 DOWNTO 0);
		54	close_file : IN STD_LOGIC);
		55	END COMPONENT;
		56
		57	SIGNAL clk : STD_LOGIC := '0';
		58	SIGNAL rstn : STD_LOGIC;
		59
		60	SIGNAL start : STD_LOGIC;
		61
		62	-- IN
		63	SIGNAL sample_valid : STD_LOGIC;
		64	SIGNAL fft_read : STD_LOGIC;
		65	SIGNAL sample_data : STD_LOGIC_VECTOR(15 DOWNTO 0);
		66	SIGNAL sample_load : STD_LOGIC;
		67	-- OUT
		68	SIGNAL fft_pong : STD_LOGIC;
		69	SIGNAL fft_data_im : STD_LOGIC_VECTOR(15 DOWNTO 0);
		70	SIGNAL fft_data_re : STD_LOGIC_VECTOR(15 DOWNTO 0);
		71	SIGNAL fft_data_valid : STD_LOGIC;
		72	SIGNAL fft_ready : STD_LOGIC;
		73	SIGNAL fft_component_number : INTEGER;
		74
		75	SIGNAL end_of_sim : STD_LOGIC := '0';
		76
		77	-----------------------------------------------------------------------------
		78	-- DATA GEN
		79	-----------------------------------------------------------------------------
		80	CONSTANT NB_CYCLE_f0 : INTEGER := 1017; -- 25MHz / 24576Hz
		81	CONSTANT NB_CYCLE_f1 : INTEGER := 6103; -- 25MHz / 4096Hz
		82	CONSTANT NB_CYCLE_f2 : INTEGER := 97656; -- 25MHz / 256Hz
		83
		84	SIGNAL data_counter_f0 : INTEGER;
		85	SIGNAL data_counter_f1 : INTEGER;
		86	SIGNAL data_counter_f2 : INTEGER;
		87
		88	SIGNAL sample_f0_wen : STD_LOGIC;
		89	SIGNAL sample_f1_wen : STD_LOGIC;
		90	SIGNAL sample_f2_wen : STD_LOGIC;
		91
		92	SIGNAL sample_f0_wen_v : STD_LOGIC_VECTOR(4 DOWNTO 0);
		93	SIGNAL sample_f1_wen_v : STD_LOGIC_VECTOR(4 DOWNTO 0);
		94	SIGNAL sample_f2_wen_v : STD_LOGIC_VECTOR(4 DOWNTO 0);
		95
		96	SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
		97	SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
		98	SIGNAL sample_f2_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
		99
		100	-----------------------------------------------------------------------------
		101	-- TIME
		102	-----------------------------------------------------------------------------
		103	SIGNAL start_date : STD_LOGIC_VECTOR(30 DOWNTO 0);
		104	SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
		105	SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
		106	SIGNAL time_counter : INTEGER;
		107
		108	SIGNAL new_fine_time : STD_LOGIC := '0';
		109	SIGNAL new_fine_time_reg : STD_LOGIC := '0';
		110
		111	-----------------------------------------------------------------------------
		112	--
		113	-----------------------------------------------------------------------------
		114	SIGNAL end_of_file : STD_LOGIC_VECTOR(2 DOWNTO 0);
		115	SIGNAL data_out_val : STD_LOGIC_VECTOR(2 DOWNTO 0);
		116
		117	-----------------------------------------------------------------------------
		118	-----------------------------------------------------------------------------
		119	SIGNAL dma_fifo_burst_valid : STD_LOGIC; --TODO
		120	SIGNAL dma_fifo_data : STD_LOGIC_VECTOR(31 DOWNTO 0); --TODO
		121	SIGNAL dma_fifo_ren : STD_LOGIC; --TODO
		122	SIGNAL dma_fifo_ren_f0 : STD_LOGIC; --TODO
		123	SIGNAL dma_fifo_ren_f1 : STD_LOGIC; --TODO
		124	SIGNAL dma_fifo_ren_f2 : STD_LOGIC; --TODO
		125	SIGNAL dma_buffer_new : STD_LOGIC; --TODOx
		126	SIGNAL dma_buffer_addr : STD_LOGIC_VECTOR(31 DOWNTO 0); --TODO
		127	SIGNAL dma_buffer_length : STD_LOGIC_VECTOR(25 DOWNTO 0); --TODO
		128	SIGNAL dma_buffer_full : STD_LOGIC; --TODO
		129	SIGNAL dma_buffer_full_err : STD_LOGIC; --TODO
		130	SIGNAL ready_matrix_f0 : STD_LOGIC; -- TODO
		131	SIGNAL ready_matrix_f1 : STD_LOGIC; -- TODO
		132	SIGNAL ready_matrix_f2 : STD_LOGIC; -- TODO
		133	SIGNAL status_ready_matrix_f0 : STD_LOGIC; -- TODO
		134	SIGNAL status_ready_matrix_f1 : STD_LOGIC; -- TODO
		135	SIGNAL status_ready_matrix_f2 : STD_LOGIC; -- TODO
		136	SIGNAL addr_matrix_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO
		137	SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO
		138	SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO
		139	SIGNAL length_matrix_f0 : STD_LOGIC_VECTOR(25 DOWNTO 0); -- TODO
		140	SIGNAL length_matrix_f1 : STD_LOGIC_VECTOR(25 DOWNTO 0); -- TODO
		141	SIGNAL length_matrix_f2 : STD_LOGIC_VECTOR(25 DOWNTO 0); -- TODO
		142	SIGNAL matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0); -- TODO
		143	SIGNAL matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0); -- TODO
		144	SIGNAL matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0); -- TODO
		145	-----------------------------------------------------------------------------
		146	SIGNAL dma_ren_counter : INTEGER;
		147	SIGNAL dma_output_counter : INTEGER;
		148	-----------------------------------------------------------------------------
		149	CONSTANT BASE_ADDR_F0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"01000000";
		150	CONSTANT BASE_ADDR_F1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"10000000";
		151	CONSTANT BASE_ADDR_F2 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"11000000";
		152	-----------------------------------------------------------------------------
		153	SIGNAL close_file : STD_LOGIC := '0';
		154
		155	BEGIN
		156
		157	-----------------------------------------------------------------------------
		158
		159	clk <= NOT clk AFTER 20 ns;
		160	new_fine_time <= NOT new_fine_time AFTER 15258 ns;
		161
		162	PROCESS
		163	BEGIN -- PROCESS
		164	WAIT UNTIL clk = '1';
		165	close_file <= '0';
		166	rstn <= '0';
		167	start <= '0';
		168	WAIT UNTIL clk = '1';
		169	rstn <= '1';
		170	WAIT UNTIL clk = '1';
		171	WAIT UNTIL clk = '1';
		172	WAIT UNTIL clk = '1';
		173	WAIT UNTIL clk = '1';
		174	start <= '1';
		175	WHILE NOT (end_of_file = "111") LOOP
		176	WAIT UNTIL clk = '1';
		177	END LOOP;
		178	REPORT "* END READ FILE *";-- SEVERITY failure;
		179	WAIT FOR 3 ms;
		180	close_file <= '1';
		181	WAIT UNTIL clk = '1';
		182	WAIT UNTIL clk = '1';
		183	WAIT UNTIL clk = '1';
		184	end_of_sim <= '1';
		185	WAIT FOR 100 ns;
		186	REPORT "* END SIMULATION *" SEVERITY failure;
		187	WAIT;
		188	END PROCESS;
		189
		190	-----------------------------------------------------------------------------
		191	-- TIME
		192	-----------------------------------------------------------------------------
		193	PROCESS (clk, rstn)
		194	BEGIN -- PROCESS
		195	IF rstn = '0' THEN -- asynchronous reset (active low)
		196	start_date <= X"0000000" & "001";
		197	coarse_time <= (OTHERS => '0');
		198	fine_time <= (OTHERS => '0');
		199	time_counter <= 0;
		200	new_fine_time_reg <= '0';
		201	ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
		202	new_fine_time_reg <= new_fine_time;
		203	IF start = '1' THEN
		204	IF coarse_time(30 downto 0) = X"0000000" & "000" THEN
		205	coarse_time(30 downto 0) <= start_date;
		206	ELSE
		207	IF new_fine_time = NOT new_fine_time_reg THEN
		208	IF fine_time = X"FFFF" THEN
		209	coarse_time <= STD_LOGIC_VECTOR(UNSIGNED(coarse_time) + 1);
		210	fine_time <= (OTHERS => '0');
		211	ELSE
		212	fine_time <= STD_LOGIC_VECTOR(UNSIGNED(fine_time) + 1);
		213	END IF;
		214	END IF;
		215	END IF;
		216	END IF;
		217	END IF;
		218	END PROCESS;
		219
		220	-----------------------------------------------------------------------------
		221	-- DATA IN
		222	-----------------------------------------------------------------------------
		223	data_read_with_timer_f0 : data_read_with_timer
		224	GENERIC MAP (input_file_name_f0, 4*5, NB_CYCLE_f0)
		225	PORT MAP (clk, rstn, end_of_file(0), data_out_val(0), sample_f0_wdata(16*5-1 downto 0));
		226	sample_f0_wen <= NOT data_out_val(0);
		227
		228	data_read_with_timer_f1 : data_read_with_timer
		229	GENERIC MAP (input_file_name_f1, 4*5, NB_CYCLE_f1)
		230	PORT MAP (clk, rstn, end_of_file(1), data_out_val(1), sample_f1_wdata(16*5-1 downto 0));
		231	sample_f1_wen <= NOT data_out_val(1);
		232
		233	data_read_with_timer_f2 : data_read_with_timer
		234	GENERIC MAP (input_file_name_f2, 4*5, NB_CYCLE_f2)
		235	PORT MAP (clk, rstn, end_of_file(2), data_out_val(2), sample_f2_wdata(16*5-1 downto 0));
		236	sample_f2_wen <= NOT data_out_val(2);
		237
		238	-----------------------------------------------------------------------------
		239	-- DATA OUT
		240	-----------------------------------------------------------------------------
		241	--dma_fifo_burst_valid -- in
		242	--dma_fifo_data -- in
		243	--dma_fifo_ren -- OUT
		244	--dma_fifo_ren <= '0';
		245
		246	--PROCESS (clk, rstn)
		247	--BEGIN -- PROCESS
		248	-- IF rstn = '0' THEN -- asynchronous reset (active low)
		249	-- dma_ren_counter <= 0;
		250	-- dma_fifo_ren <= '1';
		251	-- ELSIF clk'event AND clk = '1' THEN -- rising clock edge
		252	-- dma_fifo_ren <= '1';
		253	-- IF dma_ren_counter = 0 AND dma_fifo_burst_valid = '1' THEN
		254	-- dma_ren_counter <= 16;
		255	-- END IF;
		256	-- IF dma_ren_counter > 0 THEN
		257	-- dma_ren_counter <= dma_ren_counter - 1;
		258	-- dma_fifo_ren <= '0';
		259	-- END IF;
		260
		261	-- END IF;
		262	--END PROCESS;
		263
		264	data_write_with_burstCounter_0: data_write_with_burstCounter
		265	GENERIC MAP (
		266	OUTPUT_FILE_NAME => output_file_name_f0,
		267	NB_CHAR_PER_DATA => 32/4,
		268	BASE_ADDR => BASE_ADDR_F0)
		269	PORT MAP (
		270	clk => clk,
		271	rstn => rstn,
		272	burst_addr => dma_buffer_addr,
		273	burst_valid => dma_fifo_burst_valid,
		274	data_ren => dma_fifo_ren_f0,
		275	data => dma_fifo_data,
		276	close_file => close_file);
		277
		278	data_write_with_burstCounter_1: data_write_with_burstCounter
		279	GENERIC MAP (
		280	OUTPUT_FILE_NAME => output_file_name_f1,
		281	NB_CHAR_PER_DATA => 32/4,
		282	BASE_ADDR => BASE_ADDR_F1)
		283	PORT MAP (
		284	clk => clk,
		285	rstn => rstn,
		286	burst_addr => dma_buffer_addr,
		287	burst_valid => dma_fifo_burst_valid,
		288	data_ren => dma_fifo_ren_f1,
		289	data => dma_fifo_data,
		290	close_file => close_file);
		291
		292	data_write_with_burstCounter_2: data_write_with_burstCounter
		293	GENERIC MAP (
		294	OUTPUT_FILE_NAME => output_file_name_f2,
		295	NB_CHAR_PER_DATA => 32/4,
		296	BASE_ADDR => BASE_ADDR_F2)
		297	PORT MAP (
		298	clk => clk,
		299	rstn => rstn,
		300	burst_addr => dma_buffer_addr,
		301	burst_valid => dma_fifo_burst_valid,
		302	data_ren => dma_fifo_ren_f2,
		303	data => dma_fifo_data,
		304	close_file => close_file);
		305
		306	dma_fifo_ren <= dma_fifo_ren_f0 AND dma_fifo_ren_f1 AND dma_fifo_ren_f2;
		307
		308
		309	PROCESS (clk, rstn)
		310	BEGIN -- PROCESS
		311	IF rstn = '0' THEN -- asynchronous reset (active low)
		312	dma_buffer_full <= '0';
		313	dma_buffer_full_err <= '0';
		314	dma_output_counter <= 0;
		315	ELSIF clk'event AND clk = '1' THEN -- rising clock edge
		316	dma_buffer_full <= '0';
		317
		318	IF dma_buffer_new = '1' THEN
		319	dma_output_counter <= to_integer(UNSIGNED(dma_buffer_length));
		320	END IF;
		321
		322	IF dma_fifo_ren = '0' THEN
		323	IF dma_output_counter = 1 THEN
		324	dma_buffer_full <= '1';
		325	dma_output_counter <= 0;
		326	ELSE
		327	dma_output_counter <= dma_output_counter - 1;
		328	END IF;
		329	END IF;
		330
		331	END IF;
		332	END PROCESS;
		333
		334	--dma_buffer_new -- in
		335	--dma_buffer_addr -- in
		336	--dma_buffer_length -- in
		337	--dma_buffer_full -- out
		338	--dma_buffer_full_err -- OUT
		339	-- dma_buffer_full <= '0';
		340	-- dma_buffer_full_err <= '0';
		341
		342	-----------------------------------------------------------------------------
		343	-- BUFFER CONFIGURATION and INFORMATION
		344	-----------------------------------------------------------------------------
		345	PROCESS (clk, rstn)
		346	BEGIN -- PROCESS
		347	IF rstn = '0' THEN -- asynchronous reset (active low)
		348	status_ready_matrix_f0 <= '0';
		349	status_ready_matrix_f1 <= '0';
		350	status_ready_matrix_f2 <= '0';
		351	ELSIF clk'event AND clk = '1' THEN -- rising clock edge
		352	status_ready_matrix_f0 <= ready_matrix_f0;
		353	status_ready_matrix_f1 <= ready_matrix_f1;
		354	status_ready_matrix_f2 <= ready_matrix_f2;
		355	END IF;
		356	END PROCESS;
		357
		358	addr_matrix_f0 <= BASE_ADDR_F0;
		359	addr_matrix_f1 <= BASE_ADDR_F1;
		360	addr_matrix_f2 <= BASE_ADDR_F2;
		361
		362	length_matrix_f0 <= "00" & X"000C80";
		363	length_matrix_f1 <= "00" & X"000C80";
		364	length_matrix_f2 <= "00" & X"000C80";
		365
		366	sample_f0_wen_v <= sample_f0_wen & sample_f0_wen & sample_f0_wen & sample_f0_wen & sample_f0_wen;
		367	sample_f1_wen_v <= sample_f1_wen & sample_f1_wen & sample_f1_wen & sample_f1_wen & sample_f1_wen;
		368	sample_f2_wen_v <= sample_f2_wen & sample_f2_wen & sample_f2_wen & sample_f2_wen & sample_f2_wen;
		369
		370	-----------------------------------------------------------------------------
		371	-- DUT
		372	-----------------------------------------------------------------------------
		373	lpp_lfr_ms_1 : lpp_lfr_ms
		374	GENERIC MAP (
		375	Mem_use => use_RAM)
		376	PORT MAP (
		377	clk => clk,
		378	rstn => rstn,
		379	run => '1',
		380
		381	-----------------------------------------------------------------------------
		382	-- TIME
		383	-----------------------------------------------------------------------------
		384	start_date => start_date,
		385	coarse_time => coarse_time,
		386	fine_time => fine_time,
		387
		388	-------------------------------------------------------------------------
		389	-- DATA IN
		390	-------------------------------------------------------------------------
		391	sample_f0_wen => sample_f0_wen_v, --
		392	sample_f0_wdata => sample_f0_wdata,
		393	sample_f1_wen => sample_f1_wen_v,
		394	sample_f1_wdata => sample_f1_wdata,
		395	sample_f2_wen => sample_f2_wen_v,
		396	sample_f2_wdata => sample_f2_wdata,
		397
		398	-------------------------------------------------------------------------
		399	-- DMA OUT
		400	-------------------------------------------------------------------------
		401	dma_fifo_burst_valid => dma_fifo_burst_valid, --out
		402	dma_fifo_data => dma_fifo_data, --out
		403	dma_fifo_ren => dma_fifo_ren, --in
		404	dma_buffer_new => dma_buffer_new, --out
		405	dma_buffer_addr => dma_buffer_addr, --out
		406	dma_buffer_length => dma_buffer_length, --out
		407	dma_buffer_full => dma_buffer_full, --in
		408	dma_buffer_full_err => dma_buffer_full_err, --in
		409
		410	-------------------------------------------------------------------------
		411	-- BUFFER CONFIGURATION and INFORMATION
		412	-------------------------------------------------------------------------
		413	ready_matrix_f0 => ready_matrix_f0, --out
		414	ready_matrix_f1 => ready_matrix_f1, --out
		415	ready_matrix_f2 => ready_matrix_f2, --out
		416
		417	error_buffer_full => OPEN,
		418	error_input_fifo_write => OPEN,
		419
		420	status_ready_matrix_f0 => status_ready_matrix_f0, --in
		421	status_ready_matrix_f1 => status_ready_matrix_f1, --in
		422	status_ready_matrix_f2 => status_ready_matrix_f2, --in
		423
		424	addr_matrix_f0 => addr_matrix_f0, --in
		425	addr_matrix_f1 => addr_matrix_f1, --in
		426	addr_matrix_f2 => addr_matrix_f2, --in
		427
		428	length_matrix_f0 => length_matrix_f0, --in
		429	length_matrix_f1 => length_matrix_f1, --in
		430	length_matrix_f2 => length_matrix_f2, --in
		431
		432	matrix_time_f0 => matrix_time_f0, --out
		433	matrix_time_f1 => matrix_time_f1, --out
		434	matrix_time_f2 => matrix_time_f2, --out
		435
		436	debug_vector => OPEN);
		437
		438	END;

designs/Validation_MS_auto/wave.do created 644 +39 0

			@@ -0,0 +1,39
		1	onerror {resume}
		2	quietly WaveActivateNextPane {} 0
		3	add wave -noupdate -expand -group DATA_GEN_F0 /testbench/data_read_with_timer_f0/data_out_val
		4	add wave -noupdate -expand -group DATA_GEN_F0 /testbench/data_read_with_timer_f0/end_of_file
		5	add wave -noupdate -expand -group DATA_GEN_F0 /testbench/data_read_with_timer_f0/data_out
		6	add wave -noupdate -expand -group DATA_GEN_F1 /testbench/data_read_with_timer_f1/data_out_val
		7	add wave -noupdate -expand -group DATA_GEN_F1 /testbench/data_read_with_timer_f1/end_of_file
		8	add wave -noupdate -expand -group DATA_GEN_F1 /testbench/data_read_with_timer_f1/data_out
		9	add wave -noupdate -expand -group DATA_GEN_F2 /testbench/data_read_with_timer_f2/data_out_val
		10	add wave -noupdate -expand -group DATA_GEN_F2 /testbench/data_read_with_timer_f2/end_of_file
		11	add wave -noupdate -expand -group DATA_GEN_F2 /testbench/data_read_with_timer_f2/data_out
		12	add wave -noupdate -expand -group DMA_interface /testbench/lpp_lfr_ms_1/dma_buffer_addr
		13	add wave -noupdate -expand -group DMA_interface /testbench/lpp_lfr_ms_1/dma_buffer_full
		14	add wave -noupdate -expand -group DMA_interface /testbench/lpp_lfr_ms_1/dma_buffer_full_err
		15	add wave -noupdate -expand -group DMA_interface /testbench/lpp_lfr_ms_1/dma_buffer_length
		16	add wave -noupdate -expand -group DMA_interface /testbench/lpp_lfr_ms_1/dma_buffer_new
		17	add wave -noupdate -expand -group DMA_interface /testbench/lpp_lfr_ms_1/dma_fifo_burst_valid
		18	add wave -noupdate -expand -group DMA_interface /testbench/lpp_lfr_ms_1/dma_fifo_data
		19	add wave -noupdate -expand -group DMA_interface /testbench/lpp_lfr_ms_1/dma_fifo_ren
		20	add wave -noupdate /testbench/dma_ren_counter
		21	add wave -noupdate /testbench/dma_output_counter
		22	TreeUpdate [SetDefaultTree]
		23	WaveRestoreCursors {{Cursor 1} {10933060000 ps} 0}
		24	quietly wave cursor active 1
		25	configure wave -namecolwidth 339
		26	configure wave -valuecolwidth 100
		27	configure wave -justifyvalue left
		28	configure wave -signalnamewidth 0
		29	configure wave -snapdistance 10
		30	configure wave -datasetprefix 0
		31	configure wave -rowmargin 4
		32	configure wave -childrowmargin 2
		33	configure wave -gridoffset 0
		34	configure wave -gridperiod 1
		35	configure wave -griddelta 40
		36	configure wave -timeline 0
		37	configure wave -timelineunits ns
		38	update
		39	WaveRestoreZoom {0 ps} {42718685333 ps}

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