diff --git a/designs/Validation_MS_auto/Makefile b/designs/Validation_MS_auto/Makefile new file mode 100644 --- /dev/null +++ b/designs/Validation_MS_auto/Makefile @@ -0,0 +1,54 @@ +#GRLIB=../.. +VHDLIB=../.. +SCRIPTSDIR=$(VHDLIB)/scripts/ +GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh) +TOP=leon3mp +BOARD=em-LeonLPP-A3PE3kL-v3-core1 +include $(GRLIB)/boards/$(BOARD)/Makefile.inc +DEVICE=$(PART)-$(PACKAGE)$(SPEED) +UCF=$(GRLIB)/boards/$(BOARD)/$(TOP).ucf +QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf +EFFORT=high +XSTOPT= +SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0" +#VHDLSYNFILES=config.vhd ahbrom.vhd leon3mp.vhd +VHDLSYNFILES= +VHDLSIMFILES= data_read.vhd data_write.vhd data_read_with_timer.vhd data_write_with_burstCounter.vhd tb.vhd +SIMTOP=testbench +#SDCFILE=$(GRLIB)/boards/$(BOARD)/synplify.sdc +#SDC=$(GRLIB)/boards/$(BOARD)/leon3mp.sdc +PDC=$(GRLIB)/boards/$(BOARD)/em-LeonLPP-A3PE3kL.pdc +BITGEN=$(GRLIB)/boards/$(BOARD)/default.ut +CLEAN=soft-clean + +TECHLIBS = proasic3e + +LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \ + tmtc openchip hynix ihp gleichmann micron usbhc + +DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \ + pci grusbhc haps slink ascs pwm coremp7 spi ac97 \ + ./amba_lcd_16x2_ctrlr \ + ./general_purpose/lpp_AMR \ + ./general_purpose/lpp_balise \ + ./general_purpose/lpp_delay \ + ./lpp_bootloader \ + ./lpp_cna \ + ./lpp_uart \ + ./lpp_usb \ + ./dsp/lpp_fft_rtax \ + ./lpp_sim/CY7C1061DV33 \ + +FILESKIP = i2cmst.vhd \ + APB_MULTI_DIODE.vhd \ + APB_MULTI_DIODE.vhd \ + Top_MatrixSpec.vhd \ + APB_FFT.vhd \ + CoreFFT_simu.vhd \ + lpp_lfr_apbreg_simu.vhd + +include $(GRLIB)/bin/Makefile +include $(GRLIB)/software/leon3/Makefile + +################## project specific targets ########################## + diff --git a/designs/Validation_MS_auto/data_file/test/test_gen_data.py b/designs/Validation_MS_auto/data_file/test/test_gen_data.py new file mode 100644 --- /dev/null +++ b/designs/Validation_MS_auto/data_file/test/test_gen_data.py @@ -0,0 +1,79 @@ +import math as m +import numpy as np + +def int2hex(n,nbits): + if (nbits % 4) != 0 : + return 'ERROR 1!' + spec='0'+str(nbits/4)+'x' + if n >= (-2**(nbits-1)) and n <= (2**(nbits-1)-1) : + return format(n, spec) if n>=0 else format(2**nbits+n, spec) + else : + return 'ERROR 2!' + + + +nb_point = 256 +t = np.arange(nb_point) + +## f0 +ampl_f0_0 = pow(2,14) +freq_f0_0 = float(16)/256 +phi_f0_0 = 0 + +ampl_f0_1 = pow(2,13) +freq_f0_1 = float(16)/256 +phi_f0_1 = 0 + +ampl_f0_2 = pow(2,12) +freq_f0_2 = float(16)/256 +phi_f0_2 = 0 + +ampl_f0_3 = pow(2,11) +freq_f0_3 = float(16)/256 +phi_f0_3 = 0 + +ampl_f0_4 = pow(2,10) +freq_f0_4 = float(16)/256 +phi_f0_4 = 0 + +x_f0 = [ampl_f0_0 * np.cos(2 * m.pi * freq_f0_0 * t + phi_f0_0 * m.pi / 180 ) , + ampl_f0_1 * np.cos(2 * m.pi * freq_f0_1 * t + phi_f0_1 * m.pi / 180 ) , + ampl_f0_2 * np.cos(2 * m.pi * freq_f0_2 * t + phi_f0_2 * m.pi / 180 ) , + ampl_f0_3 * np.cos(2 * m.pi * freq_f0_3 * t + phi_f0_3 * m.pi / 180 ) , + ampl_f0_4 * np.cos(2 * m.pi * freq_f0_4 * t + phi_f0_4 * m.pi / 180 ) ] + +# x_f0 = [ampl_f0_0 * np.cos(2 * m.pi * freq_f0_0 * t + phi_f0_0 * m.pi / 180 ) , +# np.zeros(nb_point,dtype=np.int16) + 10 , +# np.zeros(nb_point,dtype=np.int16) - 10 , +# ampl_f0_3 * np.cos(2 * m.pi * freq_f0_3 * t + phi_f0_3 * m.pi / 180 ) , +# ampl_f0_4 * np.cos(2 * m.pi * freq_f0_4 * t + phi_f0_4 * m.pi / 180 ) ] + + +x_f0_int16 = [np.zeros(nb_point,dtype=np.int16), + np.zeros(nb_point,dtype=np.int16), + np.zeros(nb_point,dtype=np.int16), + np.zeros(nb_point,dtype=np.int16), + np.zeros(nb_point,dtype=np.int16)] + +for j in xrange(5) : + for i in xrange(nb_point) : + x_f0_int16[j][i] = int(round(x_f0[j][i])) + +f = open("data_f0.txt", 'w') +for i in xrange(nb_point) : + for j in xrange(5) : + f.write(int2hex(x_f0_int16[j][i],16)) + f.write('\n') +f.close + +f = open("data_f1.txt", 'w') +for i in xrange(1) : + for j in xrange(5) : + f.write(int2hex(0,16)) +f.close + +f = open("data_f2.txt", 'w') +for i in xrange(1) : + for j in xrange(5) : + f.write(int2hex(0,16)) +f.close diff --git a/designs/Validation_MS_auto/data_read.vhd b/designs/Validation_MS_auto/data_read.vhd new file mode 100644 --- /dev/null +++ b/designs/Validation_MS_auto/data_read.vhd @@ -0,0 +1,84 @@ + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE IEEE.MATH_REAL.ALL; +USE ieee.numeric_std.ALL; + +LIBRARY std; +use std.textio.all; + +ENTITY data_read IS + GENERIC ( + input_file_name : STRING := "input_data_2.txt"; + NB_CHAR_PER_DATA : INTEGER := 4 + ); + PORT ( + clk : IN STD_LOGIC; + read_new_data : IN STD_LOGIC; + + end_of_file : OUT STD_LOGIC; + + data_out_val : OUT STD_LOGIC; + data_out : OUT STD_LOGIC_VECTOR(NB_CHAR_PER_DATA * 4 - 1 DOWNTO 0) + ); +END; + +ARCHITECTURE beh OF data_read IS + +BEGIN -- beh + + PROCESS + FILE file_pointer : TEXT; + VARIABLE line_read : LINE; + VARIABLE line_content : STRING(1 TO NB_CHAR_PER_DATA); + VARIABLE char_read : CHARACTER; + VARIABLE data_read : STD_LOGIC_VECTOR(NB_CHAR_PER_DATA * 4 - 1 DOWNTO 0); + VARIABLE signal_part : STD_LOGIC_VECTOR(3 DOWNTO 0); + BEGIN -- PROCESS + end_of_file <= '0'; + data_out_val <= '0'; + data_out <= (OTHERS => '0'); + + WAIT UNTIL clk = '1'; + + file_open(file_pointer,input_file_name,READ_MODE); + WHILE NOT endfile(file_pointer) LOOP + readline(file_pointer, line_read); + read(line_read,line_content); + FOR i IN 1 TO NB_CHAR_PER_DATA LOOP + char_read := line_content(NB_CHAR_PER_DATA+1-i); + CASE char_read IS + WHEN '0' => data_read(4*i-1 DOWNTO 4*(i-1)) := "0000"; + WHEN '1' => data_read(4*i-1 DOWNTO 4*(i-1)) := "0001"; + WHEN '2' => data_read(4*i-1 DOWNTO 4*(i-1)) := "0010"; + WHEN '3' => data_read(4*i-1 DOWNTO 4*(i-1)) := "0011"; + WHEN '4' => data_read(4*i-1 DOWNTO 4*(i-1)) := "0100"; + WHEN '5' => data_read(4*i-1 DOWNTO 4*(i-1)) := "0101"; + WHEN '6' => data_read(4*i-1 DOWNTO 4*(i-1)) := "0110"; + WHEN '7' => data_read(4*i-1 DOWNTO 4*(i-1)) := "0111"; + WHEN '8' => data_read(4*i-1 DOWNTO 4*(i-1)) := "1000"; + WHEN '9' => data_read(4*i-1 DOWNTO 4*(i-1)) := "1001"; + WHEN 'a' => data_read(4*i-1 DOWNTO 4*(i-1)) := "1010"; + WHEN 'b' => data_read(4*i-1 DOWNTO 4*(i-1)) := "1011"; + WHEN 'c' => data_read(4*i-1 DOWNTO 4*(i-1)) := "1100"; + WHEN 'd' => data_read(4*i-1 DOWNTO 4*(i-1)) := "1101"; + WHEN 'e' => data_read(4*i-1 DOWNTO 4*(i-1)) := "1110"; + WHEN 'f' => data_read(4*i-1 DOWNTO 4*(i-1)) := "1111"; + WHEN OTHERS => NULL; + END CASE; + END LOOP; + WAIT UNTIL read_new_data = '1'; + WAIT UNTIL clk = '1'; + data_out <= data_read; + data_out_val <= '1'; + WAIT UNTIL clk = '1'; + data_out_val <= '0'; + END LOOP; + file_close(file_pointer); + end_of_file <= '1'; + data_out_val <= '0'; + WAIT; + + END PROCESS; + +END beh; diff --git a/designs/Validation_MS_auto/data_read_with_timer.vhd b/designs/Validation_MS_auto/data_read_with_timer.vhd new file mode 100644 --- /dev/null +++ b/designs/Validation_MS_auto/data_read_with_timer.vhd @@ -0,0 +1,74 @@ + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE IEEE.MATH_REAL.ALL; +USE ieee.numeric_std.ALL; + +LIBRARY std; +use std.textio.all; + +ENTITY data_read_with_timer IS + GENERIC ( + input_file_name : STRING := "input_data_2.txt"; + NB_CHAR_PER_DATA : INTEGER := 4; + NB_CYCLE_TIMER : INTEGER := 1024 + ); + PORT ( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + + end_of_file : OUT STD_LOGIC; + + data_out_val : OUT STD_LOGIC; + data_out : OUT STD_LOGIC_VECTOR(NB_CHAR_PER_DATA * 4 - 1 DOWNTO 0) + ); +END; + +ARCHITECTURE beh OF data_read_with_timer IS + + COMPONENT data_read + GENERIC ( + input_file_name : STRING; + NB_CHAR_PER_DATA : INTEGER); + PORT ( + clk : IN STD_LOGIC; + read_new_data : IN STD_LOGIC; + end_of_file : OUT STD_LOGIC; + data_out_val : OUT STD_LOGIC; + data_out : OUT STD_LOGIC_VECTOR(NB_CHAR_PER_DATA * 4 - 1 DOWNTO 0)); + END COMPONENT; + + SIGNAL nb_cycle_counter : INTEGER; + SIGNAL read_new_data : STD_LOGIC; + +BEGIN -- beh + + PROCESS (clk, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + nb_cycle_counter <= 0; + read_new_data <= '0'; + ELSIF clk'event AND clk = '1' THEN -- rising clock edge + IF nb_cycle_counter < NB_CYCLE_TIMER-1 THEN + nb_cycle_counter <= nb_cycle_counter + 1; + read_new_data <= '0'; + ELSE + nb_cycle_counter <= 0; + read_new_data <= '1'; + END IF; + END IF; + END PROCESS; + + + data_read_1: data_read + GENERIC MAP ( + input_file_name => input_file_name, + NB_CHAR_PER_DATA => NB_CHAR_PER_DATA) + PORT MAP ( + clk => clk, + read_new_data => read_new_data, + end_of_file => end_of_file, + data_out_val => data_out_val, + data_out => data_out); + +END beh; diff --git a/designs/Validation_MS_auto/data_write.vhd b/designs/Validation_MS_auto/data_write.vhd new file mode 100644 --- /dev/null +++ b/designs/Validation_MS_auto/data_write.vhd @@ -0,0 +1,77 @@ + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE IEEE.MATH_REAL.ALL; +USE ieee.numeric_std.ALL; + +LIBRARY std; +use std.textio.all; + +ENTITY data_write IS + GENERIC ( + OUTPUT_FILE_NAME : STRING := "output_data_2.txt"; + NB_CHAR_PER_DATA : INTEGER := 4 + ); + PORT ( + clk : IN STD_LOGIC; + data_in_val : IN STD_LOGIC; + data : IN STD_LOGIC_VECTOR(NB_CHAR_PER_DATA * 4 - 1 DOWNTO 0); + close_file : IN STD_LOGIC + ); +END; + +ARCHITECTURE beh OF data_write IS + + +BEGIN -- beh + + PROCESS + FILE file_pointer : TEXT; + VARIABLE line_read : LINE; + VARIABLE line_content : STRING(1 TO 4); + VARIABLE line_write : LINE; + VARIABLE line_content_write : STRING(1 TO NB_CHAR_PER_DATA); + VARIABLE line_content_write_inv : STRING(1 TO NB_CHAR_PER_DATA); + VARIABLE char_read : CHARACTER; + VARIABLE data_read : STD_LOGIC_VECTOR(15 DOWNTO 0); + VARIABLE signal_part : STD_LOGIC_VECTOR(3 DOWNTO 0); + + BEGIN -- PROCESS + + WAIT UNTIL clk = '1'; + + file_open(file_pointer , OUTPUT_FILE_NAME , WRITE_MODE); + WHILE close_file = '0' LOOP + IF data_in_val = '1' THEN + FOR i IN 1 TO NB_CHAR_PER_DATA LOOP + signal_part := data(i*4-1 DOWNTO (i-1)*4); + CASE signal_part IS + WHEN "0000" => line_content_write(NB_CHAR_PER_DATA+1-i) := '0'; + WHEN "0001" => line_content_write(NB_CHAR_PER_DATA+1-i) := '1'; + WHEN "0010" => line_content_write(NB_CHAR_PER_DATA+1-i) := '2'; + WHEN "0011" => line_content_write(NB_CHAR_PER_DATA+1-i) := '3'; + WHEN "0100" => line_content_write(NB_CHAR_PER_DATA+1-i) := '4'; + WHEN "0101" => line_content_write(NB_CHAR_PER_DATA+1-i) := '5'; + WHEN "0110" => line_content_write(NB_CHAR_PER_DATA+1-i) := '6'; + WHEN "0111" => line_content_write(NB_CHAR_PER_DATA+1-i) := '7'; + WHEN "1000" => line_content_write(NB_CHAR_PER_DATA+1-i) := '8'; + WHEN "1001" => line_content_write(NB_CHAR_PER_DATA+1-i) := '9'; + WHEN "1010" => line_content_write(NB_CHAR_PER_DATA+1-i) := 'a'; + WHEN "1011" => line_content_write(NB_CHAR_PER_DATA+1-i) := 'b'; + WHEN "1100" => line_content_write(NB_CHAR_PER_DATA+1-i) := 'c'; + WHEN "1101" => line_content_write(NB_CHAR_PER_DATA+1-i) := 'd'; + WHEN "1110" => line_content_write(NB_CHAR_PER_DATA+1-i) := 'e'; + WHEN "1111" => line_content_write(NB_CHAR_PER_DATA+1-i) := 'f'; + WHEN OTHERS => NULL; + END CASE; + END LOOP; -- i + write(line_write,line_content_write); + writeline(file_pointer,line_write); + END IF; + WAIT UNTIL clk = '1'; + END LOOP; + file_close(file_pointer); + WAIT; + END PROCESS; + +END beh; diff --git a/designs/Validation_MS_auto/data_write_with_burstCounter.vhd b/designs/Validation_MS_auto/data_write_with_burstCounter.vhd new file mode 100644 --- /dev/null +++ b/designs/Validation_MS_auto/data_write_with_burstCounter.vhd @@ -0,0 +1,81 @@ + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE IEEE.MATH_REAL.ALL; +USE ieee.numeric_std.ALL; + +LIBRARY std; +use std.textio.all; + +ENTITY data_write_with_burstCounter IS + GENERIC ( + OUTPUT_FILE_NAME : STRING := "output_data_2.txt"; + NB_CHAR_PER_DATA : INTEGER := 4; + BASE_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) + ); + PORT ( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + + burst_valid : IN STD_LOGIC; + burst_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + data_ren : OUT STD_LOGIC; + + data : IN STD_LOGIC_VECTOR(NB_CHAR_PER_DATA * 4 - 1 DOWNTO 0); + close_file : IN STD_LOGIC + ); +END; + +ARCHITECTURE beh OF data_write_with_burstCounter IS + + COMPONENT data_write + GENERIC ( + OUTPUT_FILE_NAME : STRING; + NB_CHAR_PER_DATA : INTEGER ); + PORT ( + clk : IN STD_LOGIC; + data_in_val : IN STD_LOGIC; + data : IN STD_LOGIC_VECTOR(NB_CHAR_PER_DATA * 4 - 1 DOWNTO 0); + close_file : IN STD_LOGIC); + END COMPONENT; + + SIGNAL ren_counter : INTEGER; + SIGNAL data_ren_s : STD_LOGIC; + SIGNAL data_s : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL data_in_val : STD_LOGIC; + +BEGIN + + PROCESS (clk, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + ren_counter <= 0; + data_ren_s <= '1'; + data_s <= (OTHERS => '0'); + ELSIF clk'event AND clk = '1' THEN -- rising clock edge + data_s <= data; + data_ren_s <= '1'; + IF ren_counter = 0 AND burst_valid = '1' AND burst_addr = BASE_ADDR THEN + ren_counter <= 16; + END IF; + IF ren_counter > 0 THEN + ren_counter <= ren_counter - 1; + data_ren_s <= '0'; + END IF; + END IF; + END PROCESS; + + data_in_val <= NOT data_ren_s; + data_ren <= data_ren_s; + + data_write_1: data_write + GENERIC MAP ( + OUTPUT_FILE_NAME => OUTPUT_FILE_NAME, + NB_CHAR_PER_DATA => NB_CHAR_PER_DATA) + PORT MAP ( + clk => clk, + data_in_val => data_in_val, + data => data_s, + close_file => close_file); + +END beh; diff --git a/designs/Validation_MS_auto/run.do b/designs/Validation_MS_auto/run.do new file mode 100644 --- /dev/null +++ b/designs/Validation_MS_auto/run.do @@ -0,0 +1,13 @@ +vcom -quiet -93 -work work data_read.vhd +vcom -quiet -93 -work work data_write.vhd +vcom -quiet -93 -work work data_read_with_timer.vhd +vcom -quiet -93 -work work data_write_with_burstCounter.vhd +vcom -quiet -93 -work work tb.vhd + +vsim work.testbench + +log -r * + +do wave.do + +run -all diff --git a/designs/Validation_MS_auto/run_nowindow.do b/designs/Validation_MS_auto/run_nowindow.do new file mode 100644 --- /dev/null +++ b/designs/Validation_MS_auto/run_nowindow.do @@ -0,0 +1,56 @@ +#vsim -c -do "run_nowindow.do" -goutput_file_name="output_data.txt" -ginput_file_name="input_data.txt" + +quietly set args [ split $argv {\ } ] +set argc [ llength $args ] + +set outputfile_f0 "output\_data\_f0\.txt" +set inputfile_f0 "input\_data\_f0\.txt" +set outputfile_f1 "output\_data\_f1\.txt" +set inputfile_f1 "input\_data\_f1\.txt" +set outputfile_f2 "output\_data\_f2\.txt" +set inputfile_f2 "input\_data\_f2\.txt" + +#puts "there are $argc arguments to this script" +#puts "The name of this script is $argv0" + +#foreach arg $::argv {puts $arg} + +#puts [ lindex $args 4 ] + +for { set i 0 } { $i < $argc } { incr i 1 } { + puts "$i : [ lindex $args $i ]" + + if { [ string match -goutput_file_name_f0=* [ lindex $args $i ] ] } { + set outputfile_f0 [ lindex [ split [ lindex $args $i ] {=} ] 1 ] + puts "OUTPUT_FILE_f0 : $outputfile_f0" + } + if { [ string match -goutput_file_name_f1=* [ lindex $args $i ] ] } { + set outputfile_f1 [ lindex [ split [ lindex $args $i ] {=} ] 1 ] + puts "OUTPUT_FILE_f1 : $outputfile_f1" + } + if { [ string match -goutput_file_name_f2=* [ lindex $args $i ] ] } { + set outputfile_f2 [ lindex [ split [ lindex $args $i ] {=} ] 1 ] + puts "OUTPUT_FILE_f2 : $outputfile_f2" + } + + if { [ string match -ginput_file_name_f0=* [ lindex $args $i ] ] } { + set inputfile_f0 [ lindex [ split [ lindex $args $i ] {=} ] 1 ] + puts "INPUT_FILE_F0 : $inputfile_f0" + } + if { [ string match -ginput_file_name_f1=* [ lindex $args $i ] ] } { + set inputfile_f1 [ lindex [ split [ lindex $args $i ] {=} ] 1 ] + puts "INPUT_FILE_F1 : $inputfile_f1" + } + if { [ string match -ginput_file_name_f2=* [ lindex $args $i ] ] } { + set inputfile_f2 [ lindex [ split [ lindex $args $i ] {=} ] 1 ] + puts "INPUT_FILE_F2 : $inputfile_f2" + } +} + +vsim work.testbench \ +-goutput_file_name_f0=$outputfile_f0 -ginput_file_name_f0=$inputfile_f0 \ +-goutput_file_name_f1=$outputfile_f1 -ginput_file_name_f1=$inputfile_f1 \ +-goutput_file_name_f2=$outputfile_f2 -ginput_file_name_f2=$inputfile_f2 +when -label end_of_simulation {end_of_sim == '1'} {echo "End of simulation"; exit ;} +run -all +exit diff --git a/designs/Validation_MS_auto/script_run.sh b/designs/Validation_MS_auto/script_run.sh new file mode 100644 --- /dev/null +++ b/designs/Validation_MS_auto/script_run.sh @@ -0,0 +1,29 @@ +#!/bin/sh + +for FILE_NAME in "$@" +do + vsim -c -do "run_nowindow.do" \ + -goutput_file_name_f0=$FILE_NAME"_f0_output.txt" -ginput_file_name_f0=$FILE_NAME"_f0.txt" \ + -goutput_file_name_f1=$FILE_NAME"_f1_output.txt" -ginput_file_name_f1=$FILE_NAME"_f1.txt" \ + -goutput_file_name_f2=$FILE_NAME"_f2_output.txt" -ginput_file_name_f2=$FILE_NAME"_f2.txt" + + PATH_FILE=`pwd` + + BASE_NAME_FILE=`basename ${FILE_NAME}_f0.txt` + echo -e "input_0="$BASE_NAME_FILE > $FILE_NAME.conf + BASE_NAME_FILE=`basename ${FILE_NAME}_f1.txt` + echo -e "input_1="$BASE_NAME_FILE >> $FILE_NAME.conf + BASE_NAME_FILE=`basename ${FILE_NAME}_f2.txt` + echo -e "input_2="$BASE_NAME_FILE >> $FILE_NAME.conf + + BASE_NAME_FILE=`basename ${FILE_NAME}_f0_output.txt` + echo -e "output_0="$BASE_NAME_FILE >> $FILE_NAME.conf + BASE_NAME_FILE=`basename ${FILE_NAME}_f1_output.txt` + echo -e "output_1="$BASE_NAME_FILE >> $FILE_NAME.conf + BASE_NAME_FILE=`basename ${FILE_NAME}_f2_output.txt` + echo -e "output_2="$BASE_NAME_FILE >> $FILE_NAME.conf +done + + + + diff --git a/designs/Validation_MS_auto/tb.vhd b/designs/Validation_MS_auto/tb.vhd new file mode 100644 --- /dev/null +++ b/designs/Validation_MS_auto/tb.vhd @@ -0,0 +1,438 @@ + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE IEEE.MATH_REAL.ALL; +USE ieee.numeric_std.ALL; + +LIBRARY std; +USE std.textio.ALL; + +LIBRARY lpp; +USE lpp.cic_pkg.ALL; +USE lpp.chirp_pkg.ALL; +USE lpp.lpp_fft.ALL; +USE lpp.lpp_lfr_pkg.ALL; +USE lpp.iir_filter.ALL; + +ENTITY testbench IS + GENERIC ( + input_file_name_f0 : STRING := "input_data_f0.txt"; + input_file_name_f1 : STRING := "input_data_f1.txt"; + input_file_name_f2 : STRING := "input_data_f2.txt"; + output_file_name_f0 : STRING := "output_data_f0.txt"; + output_file_name_f1 : STRING := "output_data_f1.txt"; + output_file_name_f2 : STRING := "output_data_f2.txt"); +END; + +ARCHITECTURE behav OF testbench IS + + COMPONENT data_read_with_timer + GENERIC ( + input_file_name : STRING; + NB_CHAR_PER_DATA : INTEGER; + NB_CYCLE_TIMER : INTEGER); + PORT ( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + end_of_file : OUT STD_LOGIC; + data_out_val : OUT STD_LOGIC; + data_out : OUT STD_LOGIC_VECTOR(NB_CHAR_PER_DATA * 4 - 1 DOWNTO 0)); + END COMPONENT; + + COMPONENT data_write_with_burstCounter + GENERIC ( + OUTPUT_FILE_NAME : STRING; + NB_CHAR_PER_DATA : INTEGER; + BASE_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0)); + PORT ( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + burst_valid : IN STD_LOGIC; + burst_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + data_ren : OUT STD_LOGIC; + data : IN STD_LOGIC_VECTOR(NB_CHAR_PER_DATA * 4 - 1 DOWNTO 0); + close_file : IN STD_LOGIC); + END COMPONENT; + + SIGNAL clk : STD_LOGIC := '0'; + SIGNAL rstn : STD_LOGIC; + + SIGNAL start : STD_LOGIC; + + -- IN + SIGNAL sample_valid : STD_LOGIC; + SIGNAL fft_read : STD_LOGIC; + SIGNAL sample_data : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL sample_load : STD_LOGIC; + -- OUT + SIGNAL fft_pong : STD_LOGIC; + SIGNAL fft_data_im : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL fft_data_re : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL fft_data_valid : STD_LOGIC; + SIGNAL fft_ready : STD_LOGIC; + SIGNAL fft_component_number : INTEGER; + + SIGNAL end_of_sim : STD_LOGIC := '0'; + + ----------------------------------------------------------------------------- + -- DATA GEN + ----------------------------------------------------------------------------- + CONSTANT NB_CYCLE_f0 : INTEGER := 1017; -- 25MHz / 24576Hz + CONSTANT NB_CYCLE_f1 : INTEGER := 6103; -- 25MHz / 4096Hz + CONSTANT NB_CYCLE_f2 : INTEGER := 97656; -- 25MHz / 256Hz + + SIGNAL data_counter_f0 : INTEGER; + SIGNAL data_counter_f1 : INTEGER; + SIGNAL data_counter_f2 : INTEGER; + + SIGNAL sample_f0_wen : STD_LOGIC; + SIGNAL sample_f1_wen : STD_LOGIC; + SIGNAL sample_f2_wen : STD_LOGIC; + + SIGNAL sample_f0_wen_v : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL sample_f1_wen_v : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL sample_f2_wen_v : STD_LOGIC_VECTOR(4 DOWNTO 0); + + SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); + SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); + SIGNAL sample_f2_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); + + ----------------------------------------------------------------------------- + -- TIME + ----------------------------------------------------------------------------- + SIGNAL start_date : STD_LOGIC_VECTOR(30 DOWNTO 0); + SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL time_counter : INTEGER; + + SIGNAL new_fine_time : STD_LOGIC := '0'; + SIGNAL new_fine_time_reg : STD_LOGIC := '0'; + + ----------------------------------------------------------------------------- + -- + ----------------------------------------------------------------------------- + SIGNAL end_of_file : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL data_out_val : STD_LOGIC_VECTOR(2 DOWNTO 0); + + ----------------------------------------------------------------------------- + ----------------------------------------------------------------------------- + SIGNAL dma_fifo_burst_valid : STD_LOGIC; --TODO + SIGNAL dma_fifo_data : STD_LOGIC_VECTOR(31 DOWNTO 0); --TODO + SIGNAL dma_fifo_ren : STD_LOGIC; --TODO + SIGNAL dma_fifo_ren_f0 : STD_LOGIC; --TODO + SIGNAL dma_fifo_ren_f1 : STD_LOGIC; --TODO + SIGNAL dma_fifo_ren_f2 : STD_LOGIC; --TODO + SIGNAL dma_buffer_new : STD_LOGIC; --TODOx + SIGNAL dma_buffer_addr : STD_LOGIC_VECTOR(31 DOWNTO 0); --TODO + SIGNAL dma_buffer_length : STD_LOGIC_VECTOR(25 DOWNTO 0); --TODO + SIGNAL dma_buffer_full : STD_LOGIC; --TODO + SIGNAL dma_buffer_full_err : STD_LOGIC; --TODO + SIGNAL ready_matrix_f0 : STD_LOGIC; -- TODO + SIGNAL ready_matrix_f1 : STD_LOGIC; -- TODO + SIGNAL ready_matrix_f2 : STD_LOGIC; -- TODO + SIGNAL status_ready_matrix_f0 : STD_LOGIC; -- TODO + SIGNAL status_ready_matrix_f1 : STD_LOGIC; -- TODO + SIGNAL status_ready_matrix_f2 : STD_LOGIC; -- TODO + SIGNAL addr_matrix_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO + SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO + SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO + SIGNAL length_matrix_f0 : STD_LOGIC_VECTOR(25 DOWNTO 0); -- TODO + SIGNAL length_matrix_f1 : STD_LOGIC_VECTOR(25 DOWNTO 0); -- TODO + SIGNAL length_matrix_f2 : STD_LOGIC_VECTOR(25 DOWNTO 0); -- TODO + SIGNAL matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0); -- TODO + SIGNAL matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0); -- TODO + SIGNAL matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0); -- TODO + ----------------------------------------------------------------------------- + SIGNAL dma_ren_counter : INTEGER; + SIGNAL dma_output_counter : INTEGER; + ----------------------------------------------------------------------------- + CONSTANT BASE_ADDR_F0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"01000000"; + CONSTANT BASE_ADDR_F1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"10000000"; + CONSTANT BASE_ADDR_F2 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"11000000"; + ----------------------------------------------------------------------------- + SIGNAL close_file : STD_LOGIC := '0'; + +BEGIN + + ----------------------------------------------------------------------------- + + clk <= NOT clk AFTER 20 ns; + new_fine_time <= NOT new_fine_time AFTER 15258 ns; + + PROCESS + BEGIN -- PROCESS + WAIT UNTIL clk = '1'; + close_file <= '0'; + rstn <= '0'; + start <= '0'; + WAIT UNTIL clk = '1'; + rstn <= '1'; + WAIT UNTIL clk = '1'; + WAIT UNTIL clk = '1'; + WAIT UNTIL clk = '1'; + WAIT UNTIL clk = '1'; + start <= '1'; + WHILE NOT (end_of_file = "111") LOOP + WAIT UNTIL clk = '1'; + END LOOP; + REPORT "*** END READ FILE ***";-- SEVERITY failure; + WAIT FOR 3 ms; + close_file <= '1'; + WAIT UNTIL clk = '1'; + WAIT UNTIL clk = '1'; + WAIT UNTIL clk = '1'; + end_of_sim <= '1'; + WAIT FOR 100 ns; + REPORT "*** END SIMULATION ***" SEVERITY failure; + WAIT; + END PROCESS; + + ----------------------------------------------------------------------------- + -- TIME + ----------------------------------------------------------------------------- + PROCESS (clk, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + start_date <= X"0000000" & "001"; + coarse_time <= (OTHERS => '0'); + fine_time <= (OTHERS => '0'); + time_counter <= 0; + new_fine_time_reg <= '0'; + ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge + new_fine_time_reg <= new_fine_time; + IF start = '1' THEN + IF coarse_time(30 downto 0) = X"0000000" & "000" THEN + coarse_time(30 downto 0) <= start_date; + ELSE + IF new_fine_time = NOT new_fine_time_reg THEN + IF fine_time = X"FFFF" THEN + coarse_time <= STD_LOGIC_VECTOR(UNSIGNED(coarse_time) + 1); + fine_time <= (OTHERS => '0'); + ELSE + fine_time <= STD_LOGIC_VECTOR(UNSIGNED(fine_time) + 1); + END IF; + END IF; + END IF; + END IF; + END IF; + END PROCESS; + + ----------------------------------------------------------------------------- + -- DATA IN + ----------------------------------------------------------------------------- + data_read_with_timer_f0 : data_read_with_timer + GENERIC MAP (input_file_name_f0, 4*5, NB_CYCLE_f0) + PORT MAP (clk, rstn, end_of_file(0), data_out_val(0), sample_f0_wdata(16*5-1 downto 0)); + sample_f0_wen <= NOT data_out_val(0); + + data_read_with_timer_f1 : data_read_with_timer + GENERIC MAP (input_file_name_f1, 4*5, NB_CYCLE_f1) + PORT MAP (clk, rstn, end_of_file(1), data_out_val(1), sample_f1_wdata(16*5-1 downto 0)); + sample_f1_wen <= NOT data_out_val(1); + + data_read_with_timer_f2 : data_read_with_timer + GENERIC MAP (input_file_name_f2, 4*5, NB_CYCLE_f2) + PORT MAP (clk, rstn, end_of_file(2), data_out_val(2), sample_f2_wdata(16*5-1 downto 0)); + sample_f2_wen <= NOT data_out_val(2); + + ----------------------------------------------------------------------------- + -- DATA OUT + ----------------------------------------------------------------------------- + --dma_fifo_burst_valid -- in + --dma_fifo_data -- in + --dma_fifo_ren -- OUT + --dma_fifo_ren <= '0'; + + --PROCESS (clk, rstn) + --BEGIN -- PROCESS + -- IF rstn = '0' THEN -- asynchronous reset (active low) + -- dma_ren_counter <= 0; + -- dma_fifo_ren <= '1'; + -- ELSIF clk'event AND clk = '1' THEN -- rising clock edge + -- dma_fifo_ren <= '1'; + -- IF dma_ren_counter = 0 AND dma_fifo_burst_valid = '1' THEN + -- dma_ren_counter <= 16; + -- END IF; + -- IF dma_ren_counter > 0 THEN + -- dma_ren_counter <= dma_ren_counter - 1; + -- dma_fifo_ren <= '0'; + -- END IF; + + -- END IF; + --END PROCESS; + + data_write_with_burstCounter_0: data_write_with_burstCounter + GENERIC MAP ( + OUTPUT_FILE_NAME => output_file_name_f0, + NB_CHAR_PER_DATA => 32/4, + BASE_ADDR => BASE_ADDR_F0) + PORT MAP ( + clk => clk, + rstn => rstn, + burst_addr => dma_buffer_addr, + burst_valid => dma_fifo_burst_valid, + data_ren => dma_fifo_ren_f0, + data => dma_fifo_data, + close_file => close_file); + + data_write_with_burstCounter_1: data_write_with_burstCounter + GENERIC MAP ( + OUTPUT_FILE_NAME => output_file_name_f1, + NB_CHAR_PER_DATA => 32/4, + BASE_ADDR => BASE_ADDR_F1) + PORT MAP ( + clk => clk, + rstn => rstn, + burst_addr => dma_buffer_addr, + burst_valid => dma_fifo_burst_valid, + data_ren => dma_fifo_ren_f1, + data => dma_fifo_data, + close_file => close_file); + + data_write_with_burstCounter_2: data_write_with_burstCounter + GENERIC MAP ( + OUTPUT_FILE_NAME => output_file_name_f2, + NB_CHAR_PER_DATA => 32/4, + BASE_ADDR => BASE_ADDR_F2) + PORT MAP ( + clk => clk, + rstn => rstn, + burst_addr => dma_buffer_addr, + burst_valid => dma_fifo_burst_valid, + data_ren => dma_fifo_ren_f2, + data => dma_fifo_data, + close_file => close_file); + + dma_fifo_ren <= dma_fifo_ren_f0 AND dma_fifo_ren_f1 AND dma_fifo_ren_f2; + + + PROCESS (clk, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + dma_buffer_full <= '0'; + dma_buffer_full_err <= '0'; + dma_output_counter <= 0; + ELSIF clk'event AND clk = '1' THEN -- rising clock edge + dma_buffer_full <= '0'; + + IF dma_buffer_new = '1' THEN + dma_output_counter <= to_integer(UNSIGNED(dma_buffer_length)); + END IF; + + IF dma_fifo_ren = '0' THEN + IF dma_output_counter = 1 THEN + dma_buffer_full <= '1'; + dma_output_counter <= 0; + ELSE + dma_output_counter <= dma_output_counter - 1; + END IF; + END IF; + + END IF; + END PROCESS; + + --dma_buffer_new -- in + --dma_buffer_addr -- in + --dma_buffer_length -- in + --dma_buffer_full -- out + --dma_buffer_full_err -- OUT +-- dma_buffer_full <= '0'; +-- dma_buffer_full_err <= '0'; + + ----------------------------------------------------------------------------- + -- BUFFER CONFIGURATION and INFORMATION + ----------------------------------------------------------------------------- + PROCESS (clk, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + status_ready_matrix_f0 <= '0'; + status_ready_matrix_f1 <= '0'; + status_ready_matrix_f2 <= '0'; + ELSIF clk'event AND clk = '1' THEN -- rising clock edge + status_ready_matrix_f0 <= ready_matrix_f0; + status_ready_matrix_f1 <= ready_matrix_f1; + status_ready_matrix_f2 <= ready_matrix_f2; + END IF; + END PROCESS; + + addr_matrix_f0 <= BASE_ADDR_F0; + addr_matrix_f1 <= BASE_ADDR_F1; + addr_matrix_f2 <= BASE_ADDR_F2; + + length_matrix_f0 <= "00" & X"000C80"; + length_matrix_f1 <= "00" & X"000C80"; + length_matrix_f2 <= "00" & X"000C80"; + + sample_f0_wen_v <= sample_f0_wen & sample_f0_wen & sample_f0_wen & sample_f0_wen & sample_f0_wen; + sample_f1_wen_v <= sample_f1_wen & sample_f1_wen & sample_f1_wen & sample_f1_wen & sample_f1_wen; + sample_f2_wen_v <= sample_f2_wen & sample_f2_wen & sample_f2_wen & sample_f2_wen & sample_f2_wen; + + ----------------------------------------------------------------------------- + -- DUT + ----------------------------------------------------------------------------- + lpp_lfr_ms_1 : lpp_lfr_ms + GENERIC MAP ( + Mem_use => use_RAM) + PORT MAP ( + clk => clk, + rstn => rstn, + run => '1', + + ----------------------------------------------------------------------------- + -- TIME + ----------------------------------------------------------------------------- + start_date => start_date, + coarse_time => coarse_time, + fine_time => fine_time, + + ------------------------------------------------------------------------- + -- DATA IN + ------------------------------------------------------------------------- + sample_f0_wen => sample_f0_wen_v, -- + sample_f0_wdata => sample_f0_wdata, + sample_f1_wen => sample_f1_wen_v, + sample_f1_wdata => sample_f1_wdata, + sample_f2_wen => sample_f2_wen_v, + sample_f2_wdata => sample_f2_wdata, + + ------------------------------------------------------------------------- + -- DMA OUT + ------------------------------------------------------------------------- + dma_fifo_burst_valid => dma_fifo_burst_valid, --out + dma_fifo_data => dma_fifo_data, --out + dma_fifo_ren => dma_fifo_ren, --in + dma_buffer_new => dma_buffer_new, --out + dma_buffer_addr => dma_buffer_addr, --out + dma_buffer_length => dma_buffer_length, --out + dma_buffer_full => dma_buffer_full, --in + dma_buffer_full_err => dma_buffer_full_err, --in + + ------------------------------------------------------------------------- + -- BUFFER CONFIGURATION and INFORMATION + ------------------------------------------------------------------------- + ready_matrix_f0 => ready_matrix_f0, --out + ready_matrix_f1 => ready_matrix_f1, --out + ready_matrix_f2 => ready_matrix_f2, --out + + error_buffer_full => OPEN, + error_input_fifo_write => OPEN, + + status_ready_matrix_f0 => status_ready_matrix_f0, --in + status_ready_matrix_f1 => status_ready_matrix_f1, --in + status_ready_matrix_f2 => status_ready_matrix_f2, --in + + addr_matrix_f0 => addr_matrix_f0, --in + addr_matrix_f1 => addr_matrix_f1, --in + addr_matrix_f2 => addr_matrix_f2, --in + + length_matrix_f0 => length_matrix_f0, --in + length_matrix_f1 => length_matrix_f1, --in + length_matrix_f2 => length_matrix_f2, --in + + matrix_time_f0 => matrix_time_f0, --out + matrix_time_f1 => matrix_time_f1, --out + matrix_time_f2 => matrix_time_f2, --out + + debug_vector => OPEN); + +END; diff --git a/designs/Validation_MS_auto/wave.do b/designs/Validation_MS_auto/wave.do new file mode 100644 --- /dev/null +++ b/designs/Validation_MS_auto/wave.do @@ -0,0 +1,39 @@ +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate -expand -group DATA_GEN_F0 /testbench/data_read_with_timer_f0/data_out_val +add wave -noupdate -expand -group DATA_GEN_F0 /testbench/data_read_with_timer_f0/end_of_file +add wave -noupdate -expand -group DATA_GEN_F0 /testbench/data_read_with_timer_f0/data_out +add wave -noupdate -expand -group DATA_GEN_F1 /testbench/data_read_with_timer_f1/data_out_val +add wave -noupdate -expand -group DATA_GEN_F1 /testbench/data_read_with_timer_f1/end_of_file +add wave -noupdate -expand -group DATA_GEN_F1 /testbench/data_read_with_timer_f1/data_out +add wave -noupdate -expand -group DATA_GEN_F2 /testbench/data_read_with_timer_f2/data_out_val +add wave -noupdate -expand -group DATA_GEN_F2 /testbench/data_read_with_timer_f2/end_of_file +add wave -noupdate -expand -group DATA_GEN_F2 /testbench/data_read_with_timer_f2/data_out +add wave -noupdate -expand -group DMA_interface /testbench/lpp_lfr_ms_1/dma_buffer_addr +add wave -noupdate -expand -group DMA_interface /testbench/lpp_lfr_ms_1/dma_buffer_full +add wave -noupdate -expand -group DMA_interface /testbench/lpp_lfr_ms_1/dma_buffer_full_err +add wave -noupdate -expand -group DMA_interface /testbench/lpp_lfr_ms_1/dma_buffer_length +add wave -noupdate -expand -group DMA_interface /testbench/lpp_lfr_ms_1/dma_buffer_new +add wave -noupdate -expand -group DMA_interface /testbench/lpp_lfr_ms_1/dma_fifo_burst_valid +add wave -noupdate -expand -group DMA_interface /testbench/lpp_lfr_ms_1/dma_fifo_data +add wave -noupdate -expand -group DMA_interface /testbench/lpp_lfr_ms_1/dma_fifo_ren +add wave -noupdate /testbench/dma_ren_counter +add wave -noupdate /testbench/dma_output_counter +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {10933060000 ps} 0} +quietly wave cursor active 1 +configure wave -namecolwidth 339 +configure wave -valuecolwidth 100 +configure wave -justifyvalue left +configure wave -signalnamewidth 0 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits ns +update +WaveRestoreZoom {0 ps} {42718685333 ps}