HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib Commit - r163:74b59a804717

lib/lpp/lpp_matrix/ReUse_CTRLR.vhd created 644 +80 0

@@ -0,0 +1,80
	1	------------------------------------------------------------------------------
	2	-- This file is a part of the LPP VHDL IP LIBRARY
	3	-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
	4	--
	5	-- This program is free software; you can redistribute it and/or modify
	6	-- it under the terms of the GNU General Public License as published by
	7	-- the Free Software Foundation; either version 3 of the License, or
	8	-- (at your option) any later version.
	9	--
	10	-- This program is distributed in the hope that it will be useful,
	11	-- but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	-- GNU General Public License for more details.
	14	--
	15	-- You should have received a copy of the GNU General Public License
	16	-- along with this program; if not, write to the Free Software
	17	-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	18	-------------------------------------------------------------------------------
	19	-- Author : Martin Morlot
	20	-- Mail : martin.morlot@lpp.polytechnique.fr
	21	-------------------------------------------------------------------------------
	22	library IEEE;
	23	use IEEE.numeric_std.all;
	24	use IEEE.std_logic_1164.all;
	25
	26	entity ReUse_CTRLR is
	27	port(
	28	clk : in std_logic;
	29	reset : in std_logic;
	30
	31	SetReUse : in std_logic_vector(4 downto 0);
	32	Statu : in std_logic_vector(3 downto 0);
	33
	34	ReUse : out std_logic_vector(4 downto 0)
	35	);
	36	end entity;
	37
	38
	39	architecture ar_ReUse_CTRLR of ReUse_CTRLR is
	40
	41	signal ResetReUse : std_logic_vector(4 downto 0);
	42	signal MatrixParam : integer;
	43	signal MatrixParam_Reg : integer;
	44
	45	begin
	46
	47
	48
	49	process (clk,reset)
	50	-- variable MatrixParam : integer;
	51	begin
	52	-- MatrixParam := to_integer(unsigned(Statu));
	53
	54	if(reset='0')then
	55	ResetReUse <= (others => '1');
	56	MatrixParam_Reg <= 0;
	57
	58
	59	elsif(clk' event and clk='1')then
	60	MatrixParam_Reg <= MatrixParam;
	61
	62	if(MatrixParam_Reg = 7 and MatrixParam = 8)then -- On videra FIFO(B1) a sa derni�re utilisation PARAM = 11
	63	ResetReUse(0) <= '0';
	64	elsif(MatrixParam_Reg = 8 and MatrixParam = 9)then -- On videra FIFO(B2) a sa derni�re utilisation PARAM = 12
	65	ResetReUse(1) <= '0';
	66	elsif(MatrixParam_Reg = 9 and MatrixParam = 10)then -- On videra FIFO(B3) a sa derni�re utilisation PARAM = 13
	67	ResetReUse(2) <= '0';
	68	elsif(MatrixParam_Reg = 10 and MatrixParam = 11)then -- On videra FIFO(E1) a sa derni�re utilisation PARAM = 14
	69	ResetReUse(3) <= '0';
	70	elsif(MatrixParam_Reg = 14 and MatrixParam = 15)then -- On videra FIFO(E2) a sa derni�re utilisation PARAM = 15
	71	ResetReUse(4) <= '0';
	72	end if;
	73
	74	end if;
	75	end process;
	76
	77	MatrixParam <= to_integer(unsigned(Statu));
	78	ReUse <= SetReUse and ResetReUse;
	79
	80	end architecture; No newline at end of file

lib/lpp/general_purpose/Adder.vhd 0 -4

             LIBRARY IEEE;
             USE IEEE.numeric_std.ALL;
             USE IEEE.std_logic_1164.ALL;
-            LIBRARY lpp;
-            USE lpp.general_purpose.ALL;
             ENTITY Adder IS
               GENERIC(

lib/lpp/general_purpose/MAC_CONTROLER.vhd 0 -3

             library IEEE;
             use IEEE.numeric_std.all;
             use IEEE.std_logic_1164.all;
-            library lpp;
-            use lpp.general_purpose.all;
             --IDLE =00 MAC =01 MULT =10 ADD =11

lib/lpp/general_purpose/MAC_MUX.vhd 0 -4

             library IEEE;
             use IEEE.numeric_std.all;
             use IEEE.std_logic_1164.all;
-            library lpp;
-            use lpp.general_purpose.all;
             entity MAC_MUX is
             generic(

lib/lpp/general_purpose/MAC_MUX2.vhd 0 -3

             library IEEE;
             use IEEE.numeric_std.all;
             use IEEE.std_logic_1164.all;
-            library lpp;
-            use lpp.general_purpose.all;
             entity MAC_MUX2 is

lib/lpp/general_purpose/MAC_REG.vhd 0 -4

             library IEEE;
             use IEEE.numeric_std.all;
             use IEEE.std_logic_1164.all;
-            library lpp;
-            use lpp.general_purpose.all;
             entity MAC_REG is
             generic(size    :   integer := 16);

lib/lpp/general_purpose/Multiplier.vhd 0 -5

             use IEEE.numeric_std.all;
             use IEEE.std_logic_1164.all;
-            library lpp;
-            use lpp.general_purpose.all;
             entity Multiplier is
             generic(
                 Input_SZ_A     :   integer := 16;

lib/lpp/lpp_matrix/ALU_Driver.vhd 0 -1

             library IEEE;
             use IEEE.numeric_std.all;
             use IEEE.std_logic_1164.all;
-            library lpp;
             use lpp.general_purpose.all;
             --! Driver de l'ALU

lib/lpp/lpp_matrix/MatriceSpectrale.vhd +15 -7

             library IEEE;
             use IEEE.std_logic_1164.all;
             use IEEE.numeric_std.all;
-            library lpp;
+            --library lpp;
-            use lpp.lpp_matrix.all;
+            --use lpp.lpp_matrix.all;
             entity MatriceSpectrale is
               generic(
                     rstn            : in std_logic;
                     FifoIN_Full     : in std_logic_vector(4 downto 0);
+                    SetReUse        : in std_logic_vector(4 downto 0);
                     FifoOUT_Full    : in std_logic_vector(1 downto 0);
-                    Data_IN         : in std_logic_vector(79 downto 0);
+                    Data_IN         : in std_logic_vector((5*Input_SZ)-1 downto 0);
                     ACQ             : in std_logic;
                     FlagError       : out std_logic;
                     Pong            : out std_logic;
+                    Statu           : out std_logic_vector(3 downto 0);
                     Write           : out std_logic_vector(1 downto 0);
                     Read            : out std_logic_vector(4 downto 0);
-                    Data_OUT        : out std_logic_vector(63 downto 0)
+                    ReUse           : out std_logic_vector(4 downto 0);
+                    Data_OUT        : out std_logic_vector((2*Result_SZ)-1 downto 0)
                     );
             end entity;
             begin
-                TopSM : TopSpecMatrix
+                CTRL0 : entity work.ReUse_CTRLR
+                    port map(clkm,rstn,SetReUse,TopSM_Statu,ReUse);
+                TopSM : entity work.TopSpecMatrix
                     generic map (Input_SZ)
                     port map(clkm,rstn,Matrix_Write,Matrix_Read,FifoIN_Full,Data_IN,TopSM_Start,Read,TopSM_Statu,TopSM_Data1,TopSM_Data2);
-                SM : SpectralMatrix
+                SM : entity work.SpectralMatrix
                     generic map (Input_SZ,Result_SZ)
                     port map(clkm,rstn,TopSM_Start,TopSM_Data1,TopSM_Data2,TopSM_Statu,Matrix_Read,Matrix_Write,Matrix_Result);
-                DISP : Dispatch
+                DISP : entity work.Dispatch
                     generic map(Result_SZ)
                     port map(clkm,rstn,ACQ,Matrix_Result,Matrix_Write,FifoOUT_Full,Data_OUT,Write,Pong,FlagError);
+            Statu <= TopSM_Statu;
             end architecture;

lib/lpp/lpp_matrix/lpp_matrix.vhd +15 -2

                     rstn            : in std_logic;
                     FifoIN_Full     : in std_logic_vector(4 downto 0);
+                    SetReUse        : in std_logic_vector(4 downto 0);
                     FifoOUT_Full    : in std_logic_vector(1 downto 0);
-                    Data_IN         : in std_logic_vector(79 downto 0);
+                    Data_IN         : in std_logic_vector((5*Input_SZ)-1 downto 0);
                     ACQ             : in std_logic;
                     FlagError       : out std_logic;
                     Pong            : out std_logic;
+                    Statu           : out std_logic_vector(3 downto 0);
                     Write           : out std_logic_vector(1 downto 0);
                     Read            : out std_logic_vector(4 downto 0);
-                    Data_OUT        : out std_logic_vector(63 downto 0)
+                    ReUse           : out std_logic_vector(4 downto 0);
+                    Data_OUT        : out std_logic_vector((2*Result_SZ)-1 downto 0)
                     );
             end component;
             );
             end component;
+            component ReUse_CTRLR is
+                port(
+                    clk         : in std_logic;
+                    reset       : in std_logic;
+                    SetReUse    : in std_logic_vector(4 downto 0);
+                    Statu       : in std_logic_vector(3 downto 0);
+                    ReUse       : out std_logic_vector(4 downto 0)
+                );
+            end component;
             end;

lib/lpp/lpp_top_lfr/lpp_top_acq.vhd +1 -1

               IIR_CEL_CTRLR_v2_1 : IIR_CEL_CTRLR_v2
                 GENERIC MAP (
                   tech         => 0,
-                  Mem_use      => use_CEL,
+                  Mem_use      => use_RAM,
                   Sample_SZ    => 18,
                   Coef_SZ      => Coef_SZ,
                   Coef_Nb      => 25,               -- TODO

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