# HG changeset patch # User martin # Date 2013-04-30 12:57:42 # Node ID 74b59a804717449910eed9466e8b8a859fb2cb1d # Parent c0ff37e0fab543eb83b834963687ee41f8cef53d Chaine de donnée ok De ADC a Matrice ! diff --git a/lib/lpp/general_purpose/Adder.vhd b/lib/lpp/general_purpose/Adder.vhd --- a/lib/lpp/general_purpose/Adder.vhd +++ b/lib/lpp/general_purpose/Adder.vhd @@ -22,10 +22,6 @@ LIBRARY IEEE; USE IEEE.numeric_std.ALL; USE IEEE.std_logic_1164.ALL; -LIBRARY lpp; -USE lpp.general_purpose.ALL; - - ENTITY Adder IS GENERIC( diff --git a/lib/lpp/general_purpose/MAC_CONTROLER.vhd b/lib/lpp/general_purpose/MAC_CONTROLER.vhd --- a/lib/lpp/general_purpose/MAC_CONTROLER.vhd +++ b/lib/lpp/general_purpose/MAC_CONTROLER.vhd @@ -22,9 +22,6 @@ library IEEE; use IEEE.numeric_std.all; use IEEE.std_logic_1164.all; -library lpp; -use lpp.general_purpose.all; - --IDLE =00 MAC =01 MULT =10 ADD =11 diff --git a/lib/lpp/general_purpose/MAC_MUX.vhd b/lib/lpp/general_purpose/MAC_MUX.vhd --- a/lib/lpp/general_purpose/MAC_MUX.vhd +++ b/lib/lpp/general_purpose/MAC_MUX.vhd @@ -22,10 +22,6 @@ library IEEE; use IEEE.numeric_std.all; use IEEE.std_logic_1164.all; -library lpp; -use lpp.general_purpose.all; - - entity MAC_MUX is generic( diff --git a/lib/lpp/general_purpose/MAC_MUX2.vhd b/lib/lpp/general_purpose/MAC_MUX2.vhd --- a/lib/lpp/general_purpose/MAC_MUX2.vhd +++ b/lib/lpp/general_purpose/MAC_MUX2.vhd @@ -22,9 +22,6 @@ library IEEE; use IEEE.numeric_std.all; use IEEE.std_logic_1164.all; -library lpp; -use lpp.general_purpose.all; - entity MAC_MUX2 is diff --git a/lib/lpp/general_purpose/MAC_REG.vhd b/lib/lpp/general_purpose/MAC_REG.vhd --- a/lib/lpp/general_purpose/MAC_REG.vhd +++ b/lib/lpp/general_purpose/MAC_REG.vhd @@ -22,10 +22,6 @@ library IEEE; use IEEE.numeric_std.all; use IEEE.std_logic_1164.all; -library lpp; -use lpp.general_purpose.all; - - entity MAC_REG is generic(size : integer := 16); diff --git a/lib/lpp/general_purpose/Multiplier.vhd b/lib/lpp/general_purpose/Multiplier.vhd --- a/lib/lpp/general_purpose/Multiplier.vhd +++ b/lib/lpp/general_purpose/Multiplier.vhd @@ -23,11 +23,6 @@ library IEEE; use IEEE.numeric_std.all; use IEEE.std_logic_1164.all; -library lpp; -use lpp.general_purpose.all; - - - entity Multiplier is generic( Input_SZ_A : integer := 16; diff --git a/lib/lpp/lpp_matrix/ALU_Driver.vhd b/lib/lpp/lpp_matrix/ALU_Driver.vhd --- a/lib/lpp/lpp_matrix/ALU_Driver.vhd +++ b/lib/lpp/lpp_matrix/ALU_Driver.vhd @@ -22,7 +22,6 @@ library IEEE; use IEEE.numeric_std.all; use IEEE.std_logic_1164.all; -library lpp; use lpp.general_purpose.all; --! Driver de l'ALU diff --git a/lib/lpp/lpp_matrix/MatriceSpectrale.vhd b/lib/lpp/lpp_matrix/MatriceSpectrale.vhd --- a/lib/lpp/lpp_matrix/MatriceSpectrale.vhd +++ b/lib/lpp/lpp_matrix/MatriceSpectrale.vhd @@ -22,8 +22,8 @@ library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; -library lpp; -use lpp.lpp_matrix.all; +--library lpp; +--use lpp.lpp_matrix.all; entity MatriceSpectrale is generic( @@ -34,14 +34,17 @@ entity MatriceSpectrale is rstn : in std_logic; FifoIN_Full : in std_logic_vector(4 downto 0); + SetReUse : in std_logic_vector(4 downto 0); FifoOUT_Full : in std_logic_vector(1 downto 0); - Data_IN : in std_logic_vector(79 downto 0); + Data_IN : in std_logic_vector((5*Input_SZ)-1 downto 0); ACQ : in std_logic; FlagError : out std_logic; Pong : out std_logic; + Statu : out std_logic_vector(3 downto 0); Write : out std_logic_vector(1 downto 0); Read : out std_logic_vector(4 downto 0); - Data_OUT : out std_logic_vector(63 downto 0) + ReUse : out std_logic_vector(4 downto 0); + Data_OUT : out std_logic_vector((2*Result_SZ)-1 downto 0) ); end entity; @@ -59,18 +62,23 @@ signal TopSM_Data2 : std_logic_vect begin - TopSM : TopSpecMatrix + CTRL0 : entity work.ReUse_CTRLR + port map(clkm,rstn,SetReUse,TopSM_Statu,ReUse); + + + TopSM : entity work.TopSpecMatrix generic map (Input_SZ) port map(clkm,rstn,Matrix_Write,Matrix_Read,FifoIN_Full,Data_IN,TopSM_Start,Read,TopSM_Statu,TopSM_Data1,TopSM_Data2); - SM : SpectralMatrix + SM : entity work.SpectralMatrix generic map (Input_SZ,Result_SZ) port map(clkm,rstn,TopSM_Start,TopSM_Data1,TopSM_Data2,TopSM_Statu,Matrix_Read,Matrix_Write,Matrix_Result); - DISP : Dispatch + DISP : entity work.Dispatch generic map(Result_SZ) port map(clkm,rstn,ACQ,Matrix_Result,Matrix_Write,FifoOUT_Full,Data_OUT,Write,Pong,FlagError); +Statu <= TopSM_Statu; end architecture; diff --git a/lib/lpp/lpp_matrix/ReUse_CTRLR.vhd b/lib/lpp/lpp_matrix/ReUse_CTRLR.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/lpp_matrix/ReUse_CTRLR.vhd @@ -0,0 +1,80 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Martin Morlot +-- Mail : martin.morlot@lpp.polytechnique.fr +------------------------------------------------------------------------------- +library IEEE; +use IEEE.numeric_std.all; +use IEEE.std_logic_1164.all; + +entity ReUse_CTRLR is + port( + clk : in std_logic; + reset : in std_logic; + + SetReUse : in std_logic_vector(4 downto 0); + Statu : in std_logic_vector(3 downto 0); + + ReUse : out std_logic_vector(4 downto 0) + ); +end entity; + + +architecture ar_ReUse_CTRLR of ReUse_CTRLR is + +signal ResetReUse : std_logic_vector(4 downto 0); +signal MatrixParam : integer; +signal MatrixParam_Reg : integer; + +begin + + + + process (clk,reset) +-- variable MatrixParam : integer; + begin +-- MatrixParam := to_integer(unsigned(Statu)); + + if(reset='0')then + ResetReUse <= (others => '1'); + MatrixParam_Reg <= 0; + + + elsif(clk' event and clk='1')then + MatrixParam_Reg <= MatrixParam; + + if(MatrixParam_Reg = 7 and MatrixParam = 8)then -- On videra FIFO(B1) a sa derni�re utilisation PARAM = 11 + ResetReUse(0) <= '0'; + elsif(MatrixParam_Reg = 8 and MatrixParam = 9)then -- On videra FIFO(B2) a sa derni�re utilisation PARAM = 12 + ResetReUse(1) <= '0'; + elsif(MatrixParam_Reg = 9 and MatrixParam = 10)then -- On videra FIFO(B3) a sa derni�re utilisation PARAM = 13 + ResetReUse(2) <= '0'; + elsif(MatrixParam_Reg = 10 and MatrixParam = 11)then -- On videra FIFO(E1) a sa derni�re utilisation PARAM = 14 + ResetReUse(3) <= '0'; + elsif(MatrixParam_Reg = 14 and MatrixParam = 15)then -- On videra FIFO(E2) a sa derni�re utilisation PARAM = 15 + ResetReUse(4) <= '0'; + end if; + + end if; + end process; + + MatrixParam <= to_integer(unsigned(Statu)); + ReUse <= SetReUse and ResetReUse; + +end architecture; \ No newline at end of file diff --git a/lib/lpp/lpp_matrix/lpp_matrix.vhd b/lib/lpp/lpp_matrix/lpp_matrix.vhd --- a/lib/lpp/lpp_matrix/lpp_matrix.vhd +++ b/lib/lpp/lpp_matrix/lpp_matrix.vhd @@ -65,14 +65,17 @@ component MatriceSpectrale is rstn : in std_logic; FifoIN_Full : in std_logic_vector(4 downto 0); + SetReUse : in std_logic_vector(4 downto 0); FifoOUT_Full : in std_logic_vector(1 downto 0); - Data_IN : in std_logic_vector(79 downto 0); + Data_IN : in std_logic_vector((5*Input_SZ)-1 downto 0); ACQ : in std_logic; FlagError : out std_logic; Pong : out std_logic; + Statu : out std_logic_vector(3 downto 0); Write : out std_logic_vector(1 downto 0); Read : out std_logic_vector(4 downto 0); - Data_OUT : out std_logic_vector(63 downto 0) + ReUse : out std_logic_vector(4 downto 0); + Data_OUT : out std_logic_vector((2*Result_SZ)-1 downto 0) ); end component; @@ -250,4 +253,14 @@ component ALU_Driver is ); end component; +component ReUse_CTRLR is + port( + clk : in std_logic; + reset : in std_logic; + SetReUse : in std_logic_vector(4 downto 0); + Statu : in std_logic_vector(3 downto 0); + ReUse : out std_logic_vector(4 downto 0) + ); +end component; + end; \ No newline at end of file diff --git a/lib/lpp/lpp_top_lfr/lpp_top_acq.vhd b/lib/lpp/lpp_top_lfr/lpp_top_acq.vhd --- a/lib/lpp/lpp_top_lfr/lpp_top_acq.vhd +++ b/lib/lpp/lpp_top_lfr/lpp_top_acq.vhd @@ -143,7 +143,7 @@ BEGIN IIR_CEL_CTRLR_v2_1 : IIR_CEL_CTRLR_v2 GENERIC MAP ( tech => 0, - Mem_use => use_CEL, + Mem_use => use_RAM, Sample_SZ => 18, Coef_SZ => Coef_SZ, Coef_Nb => 25, -- TODO