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IIR Filter Ready for tests, New version of APB_FIFO under developpement.
jeandet@PC-DE-JEANDET.lpp.polytechnique.fr -
r92:74ac16764d41 alexis
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
22 library ieee;
23 use ieee.std_logic_1164.all;
24 library grlib;
25 use grlib.amba.all;
26 use grlib.stdlib.all;
27 use grlib.devices.all;
28 library lpp;
29 use lpp.lpp_amba.all;
30 use lpp.apb_devices_list.all;
31
32 --! Driver APB "G�n�rique" qui va faire le lien entre le bus Amba et la FIFO
33
34 entity ApbFifoDriverV is
35 generic (
36 pindex : integer := 0;
37 paddr : integer := 0;
38 pmask : integer := 16#fff#;
39 pirq : integer := 0;
40 abits : integer := 8;
41 LPP_DEVICE : integer;
42 FifoCnt : integer := 1;
43 Data_sz : integer := 16;
44 Addr_sz : integer := 8;
45 addr_max_int : integer := 256);
46 port (
47 clk : in std_logic; --! Horloge du composant
48 rst : in std_logic; --! Reset general du composant
49 ReadEnable : out std_logic_vector(FifoCnt-1 downto 0); --! Instruction de lecture en m�moire
50 WriteEnable : out std_logic_vector(FifoCnt-1 downto 0); --! Instruction d'�criture en m�moire
51 FlagEmpty : in std_logic_vector(FifoCnt-1 downto 0); --! Flag, M�moire vide
52 FlagFull : in std_logic_vector(FifoCnt-1 downto 0); --! Flag, M�moire pleine
53 ReUse : out std_logic_vector(FifoCnt-1 downto 0); --! Flag, Permet de relire la m�moire du d�but
54 Lock : out std_logic_vector(FifoCnt-1 downto 0); --! Flag, Permet de bloquer l'�criture dans la m�moire
55 DataIn : out std_logic_vector((FifoCnt*Data_sz)-1 downto 0); --! Registre de donn�es en entr�e
56 DataOut : in std_logic_vector((FifoCnt*Data_sz)-1 downto 0); --! Registre de donn�es en sortie
57 AddrIn : in std_logic_vector((FifoCnt*Addr_sz)-1 downto 0); --! Registre d'addresse (�criture)
58 AddrOut : in std_logic_vector((FifoCnt*Addr_sz)-1 downto 0); --! Registre d'addresse (lecture)
59 apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus
60 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
61 );
62 end ApbFifoDriverV;
63
64 --! @details Utilisable avec n'importe quelle IP VHDL de type FIFO
65
66 architecture ar_ApbFifoDriverV of ApbFifoDriverV is
67
68 constant REVISION : integer := 1;
69
70 constant pconfig : apb_config_type := (
71 0 => ahb_device_reg (VENDOR_LPP, LPP_DEVICE, 0, REVISION, 0),
72 1 => apb_iobar(paddr, pmask));
73
74 type DEVICE_ctrlr_Reg is record
75 DEVICE_Cfg : std_logic_vector(5 downto 0);
76 DEVICE_DataW : std_logic_vector(Data_sz-1 downto 0);
77 DEVICE_DataR : std_logic_vector(Data_sz-1 downto 0);
78 DEVICE_AddrW : std_logic_vector(Addr_sz-1 downto 0);
79 DEVICE_AddrR : std_logic_vector(Addr_sz-1 downto 0);
80 end record;
81
82 type DEVICE_ctrlr_RegV is array(FifoCnt-1 downto 0) of DEVICE_ctrlr_Reg;
83
84 signal Rec : DEVICE_ctrlr_RegV;
85 signal Rdata : std_logic_vector(31 downto 0);
86
87 signal FlagRE : std_logic;
88 signal FlagWR : std_logic;
89
90 begin
91
92 fifoflags: for i in 0 to FifoCnt-1 generate:
93
94 Rec(i).DEVICE_Cfg(0) <= FlagRE(i);
95 Rec(i).DEVICE_Cfg(1) <= FlagWR(i);
96 Rec(i).DEVICE_Cfg(2) <= FlagEmpty(i);
97 Rec(i).DEVICE_Cfg(3) <= FlagFull(i);
98
99 ReUse(i) <= Rec(i).DEVICE_Cfg(4);
100 Lock(i) <= Rec(i).DEVICE_Cfg(5);
101
102 DataIn(i*(Data_sz-1 downto 0)) <= Rec(i).DEVICE_DataW;
103
104 Rec(i).DEVICE_DataR <= DataOut(i*(Data_sz-1 downto 0));
105 Rec(i).DEVICE_AddrW <= AddrIn(i*(Addr_sz-1 downto 0));
106 Rec(i).DEVICE_AddrR <= AddrOut(i*(Addr_sz-1 downto 0));
107
108 WriteEnable(i) <= FlagWR(i);
109 ReadEnable(i) <= FlagRE(i);
110
111 end generate;
112
113
114 process(rst,clk)
115 begin
116 if(rst='0')then
117 Rec.DEVICE_DataW <= (others => '0');
118 FlagWR <= '0';
119 FlagRE <= '0';
120 Rec.DEVICE_Cfg(4) <= '0';
121 Rec.DEVICE_Cfg(5) <= '0';
122
123 elsif(clk'event and clk='1')then
124
125 --APB Write OP
126 if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
127 case apbi.paddr(abits-1 downto 2) is
128 when "000000" =>
129 FlagWR <= '1';
130 Rec.DEVICE_DataW <= apbi.pwdata(Data_sz-1 downto 0);
131 when "000010" =>
132 Rec.DEVICE_Cfg(4) <= apbi.pwdata(16);
133 Rec.DEVICE_Cfg(5) <= apbi.pwdata(20);
134 when others =>
135 null;
136 end case;
137 else
138 FlagWR <= (others => '0');
139 end if;
140
141 --APB Read OP
142 if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
143 case apbi.paddr(abits-1 downto 2) is
144 for i in 0 to FifoCnt-1 loop
145 if conv_integer(apbi.paddr(7 downto 3)) = i then
146 case apbi.paddr(2 downto 2) is
147 when "0" =>
148 CoefsReg.numCoefs(i)(0) <= (apbi.pwdata(Coef_SZ-1 downto 0));
149 when "1" =>
150 CoefsReg.numCoefs(i)(1) <= (apbi.pwdata(Coef_SZ-1 downto 0));
151 when others =>
152 end case;
153 end if;
154 end loop;
155 when "000000" =>
156 FlagRE <= '1';
157 Rdata(Data_sz-1 downto 0) <= Rec.DEVICE_DataR;
158 when "000001" =>
159 Rdata(31 downto 8) <= X"AAAAAA";
160 Rdata(7 downto 0) <= Rec.DEVICE_AddrR;
161 when "000101" =>
162 Rdata(31 downto 8) <= X"AAAAAA";
163 Rdata(7 downto 0) <= Rec.DEVICE_AddrW;
164 when "000010" =>
165 Rdata(3 downto 0) <= "000" & Rec.DEVICE_Cfg(0);
166 Rdata(7 downto 4) <= "000" & Rec.DEVICE_Cfg(1);
167 Rdata(11 downto 8) <= "000" & Rec.DEVICE_Cfg(2);
168 Rdata(15 downto 12) <= "000" & Rec.DEVICE_Cfg(3);
169 Rdata(19 downto 16) <= "000" & Rec.DEVICE_Cfg(4);
170 Rdata(23 downto 20) <= "000" & Rec.DEVICE_Cfg(5);
171 Rdata(31 downto 24) <= X"CC";
172 when others =>
173 Rdata <= (others => '0');
174 end case;
175 else
176 FlagRE <= (others => '0');
177 end if;
178
179 end if;
180 apbo.pconfig <= pconfig;
181 end process;
182
183 apbo.prdata <= Rdata when apbi.penable = '1';
184
185
186 end ar_ApbFifoDriverV; No newline at end of file
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
22 library IEEE;
23 use IEEE.std_logic_1164.all;
24 use IEEE.numeric_std.all;
25 library lpp;
26 use lpp.lpp_memory.all;
27
28 entity lpp_fifo is
29 generic(
30 tech : integer := 0;
31 DataSz : integer range 1 to 32 := 8;
32 abits : integer range 2 to 12 := 8
33 );
34 port(
35 rstn : in std_logic;
36 rclk : in std_logic;
37 ren : in std_logic;
38 rdata : out std_logic_vector(DataSz-1 downto 0);
39 empty : out std_logic;
40 raddr : out std_logic_vector(abits-1 downto 0);
41 wclk : in std_logic;
42 wen : in std_logic;
43 wdata : in std_logic_vector(DataSz-1 downto 0);
44 full : out std_logic;
45 waddr : out std_logic_vector(abits-1 downto 0)
46 );
47 end entity;
48
49
50 architecture ar_lpp_fifo of lpp_fifo is
51
52 signal sFull : std_logic:='0';
53 signal sEmpty : std_logic:='1';
54 signal sREN : std_logic:='0';
55 signal sWEN : std_logic:='0';
56
57 signal Waddr_vect_d : std_logic_vector(abits-1 downto 0):=(others =>'0');
58 signal Raddr_vect_d : std_logic_vector(abits-1 downto 0);
59 signal Waddr_vect : std_logic_vector(abits-1 downto 0):=(others =>'0');
60 signal Raddr_vect : std_logic_vector(abits-1 downto 0):=(others =>'0');
61
62 type etat is (e0,e1,e2);
63 signal rect : etat;
64 signal wect : etat;
65
66 begin
67
68 SRAM : syncram_2p
69 generic map(tech,abits,DataSz)
70 port map(RCLK,sREN,Raddr_vect,rdata,WCLK,sWEN,Waddr_vect,wdata);
71
72 --RAM0: entity work.RAM_CEL
73 -- generic map(abits, DataSz)
74 -- port map(wdata, rdata, sWEN, sREN, Waddr_vect, Raddr_vect, RCLK, WCLK, rstn);
75
76 --=============================
77 -- Read section
78 --=============================
79 sREN <= not REN when (rect=e0) else '0';
80 process (rclk,rstn)
81 begin
82 if(rstn='0')then
83 rect <= e2;
84 sempty <= '1';
85 Raddr_vect <= (others =>'0');
86 Raddr_vect_d <= (others =>'1');
87
88 elsif(rclk'event and rclk='1')then
89 if(sREN='1') then
90 Raddr_vect <= std_logic_vector(unsigned(Raddr_vect) + 1);
91 Raddr_vect_d <= Raddr_vect;
92 end if;
93
94 case rect is
95 when e0 =>
96 sempty <= '0';
97 if(Raddr_vect=Waddr_vect_d)then
98 rect <= e1;
99 sempty <= '1';
100 end if;
101
102 when e1 =>
103 if(Waddr_vect_d=Raddr_vect_d)then
104 rect <= e2;
105 else
106 rect <= e0;
107 end if;
108
109 when e2 =>
110 if(Waddr_vect_d/=Raddr_vect_d)then
111 rect <= e0;
112 end if;
113
114 end case;
115 end if;
116 end process;
117
118
119 --=============================
120 -- Write section
121 --=============================
122 sWEN <= not WEN when (wect=e0) else '0';
123 process (wclk,rstn)
124 begin
125 if(rstn='0')then
126 wect <= e0;
127 sfull <= '0';
128 Waddr_vect <= (others =>'0');
129 Waddr_vect_d <= (others =>'1');
130
131 elsif(wclk'event and wclk='1')then
132 if(sWEN='1') then
133 Waddr_vect <= std_logic_vector(unsigned(Waddr_vect) +1);
134 Waddr_vect_d <= Waddr_vect;
135 end if;
136
137 case wect is
138 when e0 =>
139 sfull <= '0';
140 if(Waddr_vect=Raddr_vect_d)then
141 wect <= e1;
142 sfull <= '1';
143 end if;
144
145 when e1 =>
146 if(Waddr_vect_d=Raddr_vect_d)then
147 wect <= e2;
148 else
149 wect <= e0;
150 end if;
151
152 when e2 =>
153 if(Waddr_vect_d/=Raddr_vect_d)then
154 wect <= e0;
155 end if;
156
157 end case;
158 end if;
159 end process;
160
161
162 full <= sFull;
163 empty <= sEmpty;
164 waddr <= Waddr_vect;
165 raddr <= Raddr_vect;
166
167 end architecture;
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1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
21 -------------------------------------------------------------------------------
22 library ieee;
22 library ieee;
23 use ieee.std_logic_1164.all;
23 use ieee.std_logic_1164.all;
24 use ieee.numeric_std.all;
24 use ieee.numeric_std.all;
25 library grlib;
25 library grlib;
26 use grlib.amba.all;
26 use grlib.amba.all;
27 use grlib.stdlib.all;
27 use grlib.stdlib.all;
28 use grlib.devices.all;
28 use grlib.devices.all;
29 library lpp;
29 library lpp;
30 use lpp.iir_filter.all;
30 use lpp.iir_filter.all;
31 use lpp.general_purpose.all;
31 use lpp.general_purpose.all;
32 use lpp.lpp_amba.all;
32 use lpp.lpp_amba.all;
33 use lpp.apb_devices_list.all;
33 use lpp.apb_devices_list.all;
34
34
35 entity APB_IIR_CEL is
35 entity APB_IIR_CEL is
36 generic (
36 generic (
37 tech : integer := 0;
37 pindex : integer := 0;
38 pindex : integer := 0;
38 paddr : integer := 0;
39 paddr : integer := 0;
39 pmask : integer := 16#fff#;
40 pmask : integer := 16#fff#;
40 pirq : integer := 0;
41 pirq : integer := 0;
41 abits : integer := 8;
42 abits : integer := 8;
42 Sample_SZ : integer := 16;
43 Sample_SZ : integer := 16;
43 ChanelsCount : integer := 1;
44 ChanelsCount : integer := 1;
44 Coef_SZ : integer := 9;
45 Coef_SZ : integer := 9;
45 CoefCntPerCel: integer := 3;
46 CoefCntPerCel: integer := 3;
46 Cels_count : integer := 5;
47 Cels_count : integer := 5;
47 virgPos : integer := 3;
48 virgPos : integer := 3;
48 Mem_use : integer := use_RAM
49 Mem_use : integer := use_RAM
49 );
50 );
50 port (
51 port (
51 rst : in std_logic;
52 rst : in std_logic;
52 clk : in std_logic;
53 clk : in std_logic;
53 apbi : in apb_slv_in_type;
54 apbi : in apb_slv_in_type;
54 apbo : out apb_slv_out_type;
55 apbo : out apb_slv_out_type;
55 sample_clk : in std_logic;
56 sample_clk : in std_logic;
56 sample_clk_out : out std_logic;
57 sample_clk_out : out std_logic;
57 sample_in : in samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0);
58 sample_in : in samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0);
58 sample_out : out samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0)
59 sample_out : out samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0)
59 );
60 );
60 end;
61 end;
61
62
62
63
63 architecture AR_APB_IIR_CEL of APB_IIR_CEL is
64 architecture AR_APB_IIR_CEL of APB_IIR_CEL is
64
65
65 constant REVISION : integer := 1;
66 constant REVISION : integer := 1;
66
67
67 constant pconfig : apb_config_type := (
68 constant pconfig : apb_config_type := (
68 0 => ahb_device_reg (VENDOR_LPP, LPP_IIR_CEL_FILTER, 0, REVISION, 0),
69 0 => ahb_device_reg (VENDOR_LPP, LPP_IIR_CEL_FILTER, 0, REVISION, 0),
69 1 => apb_iobar(paddr, pmask));
70 1 => apb_iobar(paddr, pmask));
70
71
71
72
72
73
73 type FILTERreg is record
74 type FILTERreg is record
74 regin : in_IIR_CEL_reg;
75 regin : in_IIR_CEL_reg;
75 regout : out_IIR_CEL_reg;
76 regout : out_IIR_CEL_reg;
76 end record;
77 end record;
77
78
78 signal Rdata : std_logic_vector(31 downto 0);
79 signal Rdata : std_logic_vector(31 downto 0);
79 signal r : FILTERreg;
80 signal r : FILTERreg;
80 signal filter_reset : std_logic:='0';
81 signal filter_reset : std_logic:='0';
81 signal smp_cnt : integer :=0;
82 signal smp_cnt : integer :=0;
82 signal sample_clk_out_R : std_logic;
83 signal sample_clk_out_R : std_logic;
83
84 signal RawCoefs : std_logic_vector(Coef_SZ*CoefCntPerCel*Cels_count-1 downto 0);
84
85
85 type CoefCelT is array(CoefCntPerCel-1 downto 0) of std_logic_vector(Coef_SZ-1 downto 0);
86 type CoefCelT is array(CoefCntPerCel-1 downto 0) of std_logic_vector(Coef_SZ-1 downto 0);
86 type CoefTblT is array(Cels_count-1 downto 0) of CoefCelT;
87 type CoefTblT is array(Cels_count-1 downto 0) of CoefCelT;
87
88
88 type CoefsRegT is record
89 type CoefsRegT is record
89 numCoefs : CoefTblT;
90 numCoefs : CoefTblT;
90 denCoefs : CoefTblT;
91 denCoefs : CoefTblT;
91 end record;
92 end record;
92
93
93 signal CoefsReg : CoefsRegT;
94 signal CoefsReg : CoefsRegT;
94
95
95 begin
96 begin
96
97
97 filter_reset <= rst and r.regin.config(0);
98 filter_reset <= rst and r.regin.config(0);
98 sample_clk_out <= sample_clk_out_R;
99 sample_clk_out <= sample_clk_out_R;
99
100
100 filter : IIR_CEL_FILTER
101 filter : IIR_CEL_FILTER
101 generic map(Sample_SZ,ChanelsCount,Coef_SZ,CoefCntPerCel,Cels_count,Mem_use)
102 generic map(tech,Sample_SZ,ChanelsCount,Coef_SZ,CoefCntPerCel,Cels_count,Mem_use)
102 port map(
103 port map(
103 reset => filter_reset,
104 reset => filter_reset,
104 clk => clk,
105 clk => clk,
105 sample_clk => sample_clk,
106 sample_clk => sample_clk,
106 regs_in => r.regin,
107 regs_in => r.regin,
107 regs_out => r.regout,
108 regs_out => r.regout,
108 sample_in => sample_in,
109 sample_in => sample_in,
109 sample_out => sample_out
110 sample_out => sample_out,
111 coefs => RawCoefs
110 );
112 );
111
113
112 process(rst,sample_clk)
114 process(rst,sample_clk)
113 begin
115 begin
114 if rst = '0' then
116 if rst = '0' then
115 smp_cnt <= 0;
117 smp_cnt <= 0;
116 sample_clk_out_R <= '0';
118 sample_clk_out_R <= '0';
117 elsif sample_clk'event and sample_clk = '1' then
119 elsif sample_clk'event and sample_clk = '1' then
118 if smp_cnt = 1 then
120 if smp_cnt = 1 then
119 smp_cnt <= 0;
121 smp_cnt <= 0;
120 sample_clk_out_R <= not sample_clk_out_R;
122 sample_clk_out_R <= not sample_clk_out_R;
121 else
123 else
122 smp_cnt <= smp_cnt +1;
124 smp_cnt <= smp_cnt +1;
123 end if;
125 end if;
124 end if;
126 end if;
125 end process;
127 end process;
126
128
127
129
130 coefsConnectL0: for z in 0 to Cels_count-1 generate
131 coefsConnectL1: for y in 0 to (CoefCntPerCel/2)-1 generate
132 coefsConnectL2: for x in 0 to Coef_SZ-1 generate
133 RawCoefs(x + ((2*y))*Coef_SZ + z*Coef_SZ*CoefCntPerCel) <= CoefsReg.numCoefs(z)(y)(x);
134 RawCoefs(x + ((2*y)+1)*Coef_SZ + z*Coef_SZ*CoefCntPerCel) <= CoefsReg.denCoefs(z)(y)(x);
135 end generate;
136 end generate;
137 end generate;
138
128 process(rst,clk)
139 process(rst,clk)
129 begin
140 begin
130 if rst = '0' then
141 if rst = '0' then
131 r.regin.virgPos <= std_logic_vector(to_unsigned(virgPos,5));
142 r.regin.virgPos <= std_logic_vector(to_unsigned(virgPos,5));
132
143
133 elsif clk'event and clk = '1' then
144 elsif clk'event and clk = '1' then
134
145
135
146
136 --APB Write OP
147 --APB Write OP
137 if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
148 if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
138 case apbi.paddr(7 downto 2) is
149 case apbi.paddr(7 downto 2) is
139 when "000000" =>
150 when "000000" =>
140 r.regin.config(0) <= apbi.pwdata(0);
151 r.regin.config(0) <= apbi.pwdata(0);
141 when "000001" =>
152 when "000001" =>
142 r.regin.virgPos <= apbi.pwdata(4 downto 0);
153 r.regin.virgPos <= apbi.pwdata(4 downto 0);
143 when others =>
154 when others =>
144 for i in 0 to Cels_count-1 loop
155 for i in 0 to Cels_count-1 loop
145 if conv_integer(apbi.paddr(7 downto 5)) = i+1 then
156 if conv_integer(apbi.paddr(7 downto 5)) = i+1 then
146 case apbi.paddr(4 downto 2) is
157 case apbi.paddr(4 downto 2) is
147 when "000" =>
158 when "000" =>
148 CoefsReg.numCoefs(i)(0) <= (apbi.pwdata(Coef_SZ-1 downto 0));
159 CoefsReg.numCoefs(i)(0) <= (apbi.pwdata(Coef_SZ-1 downto 0));
149 when "001" =>
160 when "001" =>
150 CoefsReg.numCoefs(i)(1) <= (apbi.pwdata(Coef_SZ-1 downto 0));
161 CoefsReg.numCoefs(i)(1) <= (apbi.pwdata(Coef_SZ-1 downto 0));
151 when "010" =>
162 when "010" =>
152 CoefsReg.numCoefs(i)(2) <= (apbi.pwdata(Coef_SZ-1 downto 0));
163 CoefsReg.numCoefs(i)(2) <= (apbi.pwdata(Coef_SZ-1 downto 0));
153 when "011" =>
164 when "011" =>
154 CoefsReg.denCoefs(i)(0) <= (apbi.pwdata(Coef_SZ-1 downto 0));
165 CoefsReg.denCoefs(i)(0) <= (apbi.pwdata(Coef_SZ-1 downto 0));
155 when "100" =>
166 when "100" =>
156 CoefsReg.denCoefs(i)(1) <= (apbi.pwdata(Coef_SZ-1 downto 0));
167 CoefsReg.denCoefs(i)(1) <= (apbi.pwdata(Coef_SZ-1 downto 0));
157 when "101" =>
168 when "101" =>
158 CoefsReg.denCoefs(i)(2) <= (apbi.pwdata(Coef_SZ-1 downto 0));
169 CoefsReg.denCoefs(i)(2) <= (apbi.pwdata(Coef_SZ-1 downto 0));
159 when others =>
170 when others =>
160 end case;
171 end case;
161 end if;
172 end if;
162 end loop;
173 end loop;
163 end case;
174 end case;
164 end if;
175 end if;
165
176
166 --APB READ OP
177 --APB READ OP
167 if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
178 if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
168 case apbi.paddr(7 downto 2) is
179 case apbi.paddr(7 downto 2) is
169 when "000000" =>
180 when "000000" =>
170
181
171 when "000001" =>
182 when "000001" =>
172 Rdata(4 downto 0) <= r.regin.virgPos;
183 Rdata(4 downto 0) <= r.regin.virgPos;
173 when others =>
184 when others =>
174 for i in 0 to Cels_count-1 loop
185 for i in 0 to Cels_count-1 loop
175 if conv_integer(apbi.paddr(7 downto 5)) = i+1 then
186 if conv_integer(apbi.paddr(7 downto 5)) = i+1 then
176 case apbi.paddr(4 downto 2) is
187 case apbi.paddr(4 downto 2) is
177 when "000" =>
188 when "000" =>
178 Rdata(Coef_SZ-1 downto 0) <= std_logic_vector(CoefsReg.numCoefs(i)(0));
189 Rdata(Coef_SZ-1 downto 0) <= std_logic_vector(CoefsReg.numCoefs(i)(0));
179 when "001" =>
190 when "001" =>
180 Rdata(Coef_SZ-1 downto 0) <= std_logic_vector(CoefsReg.numCoefs(i)(1));
191 Rdata(Coef_SZ-1 downto 0) <= std_logic_vector(CoefsReg.numCoefs(i)(1));
181 when "010" =>
192 when "010" =>
182 Rdata(Coef_SZ-1 downto 0) <= std_logic_vector(CoefsReg.numCoefs(i)(2));
193 Rdata(Coef_SZ-1 downto 0) <= std_logic_vector(CoefsReg.numCoefs(i)(2));
183 when "011" =>
194 when "011" =>
184 Rdata(Coef_SZ-1 downto 0) <= std_logic_vector(CoefsReg.denCoefs(i)(0));
195 Rdata(Coef_SZ-1 downto 0) <= std_logic_vector(CoefsReg.denCoefs(i)(0));
185 when "100" =>
196 when "100" =>
186 Rdata(Coef_SZ-1 downto 0) <= std_logic_vector(CoefsReg.denCoefs(i)(1));
197 Rdata(Coef_SZ-1 downto 0) <= std_logic_vector(CoefsReg.denCoefs(i)(1));
187 when "101" =>
198 when "101" =>
188 Rdata(Coef_SZ-1 downto 0) <= std_logic_vector(CoefsReg.denCoefs(i)(2));
199 Rdata(Coef_SZ-1 downto 0) <= std_logic_vector(CoefsReg.denCoefs(i)(2));
189 when others =>
200 when others =>
190 end case;
201 end case;
191 end if;
202 end if;
192 end loop;
203 end loop;
193 end case;
204 end case;
194 end if;
205 end if;
195
206
196 end if;
207 end if;
197 apbo.pconfig <= pconfig;
208 apbo.pconfig <= pconfig;
198 end process;
209 end process;
199
210
200 apbo.prdata <= Rdata when apbi.penable = '1' ;
211 apbo.prdata <= Rdata when apbi.penable = '1' ;
201
212
202 -- pragma translate_off
213 -- pragma translate_off
203 bootmsg : report_version
214 bootmsg : report_version
204 generic map ("apbuart" & tost(pindex) &
215 generic map ("apbuart" & tost(pindex) &
205 ": Generic UART rev " & tost(REVISION) & ", fifo " & tost(fifosize) &
216 ": Generic UART rev " & tost(REVISION) & ", fifo " & tost(fifosize) &
206 ", irq " & tost(pirq));
217 ", irq " & tost(pirq));
207 -- pragma translate_on
218 -- pragma translate_on
208
219
209
220
210
221
211 end ar_APB_IIR_CEL;
222 end ar_APB_IIR_CEL;
212
223
Show file before | Show file after | Hide comments
@@ -1,326 +1,329
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
21 -------------------------------------------------------------------------------
22
22
23 library IEEE;
23 library IEEE;
24 use IEEE.numeric_std.all;
24 use IEEE.numeric_std.all;
25 use IEEE.std_logic_1164.all;
25 use IEEE.std_logic_1164.all;
26 library lpp;
26 library lpp;
27 use lpp.iir_filter.all;
27 use lpp.iir_filter.all;
28 use lpp.general_purpose.all;
28 use lpp.general_purpose.all;
29
29
30 --TODO amliorer la gestion de la RAM et de la flexibilit du filtre
30 --TODO amliorer la gestion de la RAM et de la flexibilit du filtre
31
31
32 entity IIR_CEL_CTRLR is
32 entity IIR_CEL_CTRLR is
33 generic(Sample_SZ : integer := 16;
33 generic(
34 tech : integer := 0;
35 Sample_SZ : integer := 16;
34 ChanelsCount : integer := 1;
36 ChanelsCount : integer := 1;
35 Coef_SZ : integer := 9;
37 Coef_SZ : integer := 9;
36 CoefCntPerCel: integer := 3;
38 CoefCntPerCel: integer := 3;
37 Cels_count : integer := 5;
39 Cels_count : integer := 5;
38 Mem_use : integer := use_RAM
40 Mem_use : integer := use_RAM
39 );
41 );
40 port(
42 port(
41 reset : in std_logic;
43 reset : in std_logic;
42 clk : in std_logic;
44 clk : in std_logic;
43 sample_clk : in std_logic;
45 sample_clk : in std_logic;
44 sample_in : in samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0);
46 sample_in : in samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0);
45 sample_out : out samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0);
47 sample_out : out samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0);
46 virg_pos : in integer;
48 virg_pos : in integer;
47 coefs : in std_logic_vector(Coef_SZ*CoefCntPerCel*Cels_count-1 downto 0)
49 coefs : in std_logic_vector(Coef_SZ*CoefCntPerCel*Cels_count-1 downto 0)
48 );
50 );
49 end IIR_CEL_CTRLR;
51 end IIR_CEL_CTRLR;
50
52
51
53
52
54
53
55
54 architecture ar_IIR_CEL_CTRLR of IIR_CEL_CTRLR is
56 architecture ar_IIR_CEL_CTRLR of IIR_CEL_CTRLR is
55
57
56 subtype sampleVect is std_logic_vector(Sample_SZ-1 downto 0);
58 subtype sampleVect is std_logic_vector(Sample_SZ-1 downto 0);
57
59
58 signal smpl_clk_old : std_logic := '0';
60 signal smpl_clk_old : std_logic := '0';
59 signal WD_sel : std_logic := '0';
61 signal WD_sel : std_logic := '0';
60 signal Read : std_logic := '0';
62 signal Read : std_logic := '0';
61 signal SVG_ADDR : std_logic := '0';
63 signal SVG_ADDR : std_logic := '0';
62 signal count : std_logic := '0';
64 signal count : std_logic := '0';
63 signal Write : std_logic := '0';
65 signal Write : std_logic := '0';
64 signal WADDR_sel : std_logic := '0';
66 signal WADDR_sel : std_logic := '0';
65 signal GO_0 : std_logic := '0';
67 signal GO_0 : std_logic := '0';
66
68
67 signal RAM_sample_in : sampleVect;
69 signal RAM_sample_in : sampleVect;
68 signal RAM_sample_in_bk: sampleVect;
70 signal RAM_sample_in_bk: sampleVect;
69 signal RAM_sample_out : sampleVect;
71 signal RAM_sample_out : sampleVect;
70 signal ALU_ctrl : std_logic_vector(3 downto 0);
72 signal ALU_ctrl : std_logic_vector(3 downto 0);
71 signal ALU_sample_in : sampleVect;
73 signal ALU_sample_in : sampleVect;
72 signal ALU_Coef_in : std_logic_vector(Coef_SZ-1 downto 0);
74 signal ALU_Coef_in : std_logic_vector(Coef_SZ-1 downto 0);
73 signal ALU_out : std_logic_vector(Sample_SZ+Coef_SZ-1 downto 0);
75 signal ALU_out : std_logic_vector(Sample_SZ+Coef_SZ-1 downto 0);
74 signal curentCel : integer range 0 to Cels_count-1 := 0;
76 signal curentCel : integer range 0 to Cels_count-1 := 0;
75 signal curentChan : integer range 0 to ChanelsCount-1 := 0;
77 signal curentChan : integer range 0 to ChanelsCount-1 := 0;
76
78
77
79
78 type sampleBuffT is array(ChanelsCount-1 downto 0) of sampleVect;
80 type sampleBuffT is array(ChanelsCount-1 downto 0) of sampleVect;
79
81
80 signal sample_in_BUFF : sampleBuffT;
82 signal sample_in_BUFF : sampleBuffT;
81 signal sample_out_BUFF : sampleBuffT;
83 signal sample_out_BUFF : sampleBuffT;
82
84
83 type CoefCelT is array(CoefCntPerCel-1 downto 0) of std_logic_vector(Coef_SZ-1 downto 0);
85 type CoefCelT is array(CoefCntPerCel-1 downto 0) of std_logic_vector(Coef_SZ-1 downto 0);
84 type CoefTblT is array(Cels_count-1 downto 0) of CoefCelT;
86 type CoefTblT is array(Cels_count-1 downto 0) of CoefCelT;
85
87
86 type CoefsRegT is record
88 type CoefsRegT is record
87 numCoefs : CoefTblT;
89 numCoefs : CoefTblT;
88 denCoefs : CoefTblT;
90 denCoefs : CoefTblT;
89 end record;
91 end record;
90
92
91 signal CoefsReg : CoefsRegT;
93 signal CoefsReg : CoefsRegT;
92
94
93 type fsmIIR_CEL_T is (waiting,pipe1,computeb1,computeb2,computea1,computea2,next_cel,pipe2,pipe3,next_chan);
95 type fsmIIR_CEL_T is (waiting,pipe1,computeb1,computeb2,computea1,computea2,next_cel,pipe2,pipe3,next_chan);
94
96
95 signal IIR_CEL_STATE : fsmIIR_CEL_T;
97 signal IIR_CEL_STATE : fsmIIR_CEL_T;
96
98
97 begin
99 begin
98
100
99
101
100 coefsConnectL0: for z in 0 to Cels_count-1 generate
102 coefsConnectL0: for z in 0 to Cels_count-1 generate
101 coefsConnectL1: for y in 0 to CoefCntPerCel-1 generate
103 coefsConnectL1: for y in 0 to (CoefCntPerCel/2)-1 generate
102 coefsConnectL2: for x in 0 to Coef_SZ-1 generate
104 coefsConnectL2: for x in 0 to Coef_SZ-1 generate
103 CoefsReg.numCoefs(z)(y)(x) <= coefs(x + y*Coef_SZ + z*Coef_SZ*CoefCntPerCel);
105 CoefsReg.numCoefs(z)(y)(x) <= coefs(x + ((2*y))*Coef_SZ + z*Coef_SZ*CoefCntPerCel);
104 CoefsReg.denCoefs(z)(y)(x) <= coefs(x + y*Coef_SZ + z*Coef_SZ*CoefCntPerCel);
106 CoefsReg.denCoefs(z)(y)(x) <= coefs(x + ((2*y)+1)*Coef_SZ + z*Coef_SZ*CoefCntPerCel);
105 end generate;
107 end generate;
106 end generate;
108 end generate;
107 end generate;
109 end generate;
108
110
109
111
112
110 RAM_CTRLR2inst : RAM_CTRLR2
113 RAM_CTRLR2inst : RAM_CTRLR2
111 generic map(Sample_SZ,Mem_use)
114 generic map(tech,Sample_SZ,Mem_use)
112 port map(
115 port map(
113 reset => reset,
116 reset => reset,
114 clk => clk,
117 clk => clk,
115 WD_sel => WD_sel,
118 WD_sel => WD_sel,
116 Read => Read,
119 Read => Read,
117 WADDR_sel => WADDR_sel,
120 WADDR_sel => WADDR_sel,
118 count => count,
121 count => count,
119 SVG_ADDR => SVG_ADDR,
122 SVG_ADDR => SVG_ADDR,
120 Write => Write,
123 Write => Write,
121 GO_0 => GO_0,
124 GO_0 => GO_0,
122 sample_in => RAM_sample_in,
125 sample_in => RAM_sample_in,
123 sample_out => RAM_sample_out
126 sample_out => RAM_sample_out
124 );
127 );
125
128
126
129
127
130
128 ALU_inst :ALU
131 ALU_inst :ALU
129 generic map(Logic_en => 0,Input_SZ_1 => Sample_SZ, Input_SZ_2 => Coef_SZ)
132 generic map(Logic_en => 0,Input_SZ_1 => Sample_SZ, Input_SZ_2 => Coef_SZ)
130 port map(
133 port map(
131 clk => clk,
134 clk => clk,
132 reset => reset,
135 reset => reset,
133 ctrl => ALU_ctrl,
136 ctrl => ALU_ctrl,
134 OP1 => ALU_sample_in,
137 OP1 => ALU_sample_in,
135 OP2 => ALU_coef_in,
138 OP2 => ALU_coef_in,
136 RES => ALU_out
139 RES => ALU_out
137 );
140 );
138
141
139
142
140
143
141
144
142
145
143
146
144 WD_sel <= '0' when (IIR_CEL_STATE = waiting or IIR_CEL_STATE = pipe1 or IIR_CEL_STATE = computeb2) else '1';
147 WD_sel <= '0' when (IIR_CEL_STATE = waiting or IIR_CEL_STATE = pipe1 or IIR_CEL_STATE = computeb2) else '1';
145 Read <= '1' when (IIR_CEL_STATE = pipe1 or IIR_CEL_STATE = computeb1 or IIR_CEL_STATE = computeb2 or IIR_CEL_STATE = computea1 or IIR_CEL_STATE = computea2) else '0';
148 Read <= '1' when (IIR_CEL_STATE = pipe1 or IIR_CEL_STATE = computeb1 or IIR_CEL_STATE = computeb2 or IIR_CEL_STATE = computea1 or IIR_CEL_STATE = computea2) else '0';
146 WADDR_sel <= '1' when IIR_CEL_STATE = computea1 else '0';
149 WADDR_sel <= '1' when IIR_CEL_STATE = computea1 else '0';
147 count <= '1' when (IIR_CEL_STATE = pipe1 or IIR_CEL_STATE = computeb1 or IIR_CEL_STATE = computeb2 or IIR_CEL_STATE = computea1) else '0';
150 count <= '1' when (IIR_CEL_STATE = pipe1 or IIR_CEL_STATE = computeb1 or IIR_CEL_STATE = computeb2 or IIR_CEL_STATE = computea1) else '0';
148 SVG_ADDR <= '1' when IIR_CEL_STATE = computeb2 else '0';
151 SVG_ADDR <= '1' when IIR_CEL_STATE = computeb2 else '0';
149 --Write <= '1' when (IIR_CEL_STATE = computeb1 or IIR_CEL_STATE = computeb2 or (IIR_CEL_STATE = computea1 and not(curentChan = 0 and curentCel = 0)) or IIR_CEL_STATE = computea2) else '0';
152 --Write <= '1' when (IIR_CEL_STATE = computeb1 or IIR_CEL_STATE = computeb2 or (IIR_CEL_STATE = computea1 and not(curentChan = 0 and curentCel = 0)) or IIR_CEL_STATE = computea2) else '0';
150 Write <= '1' when (IIR_CEL_STATE = computeb1 or IIR_CEL_STATE = computeb2 or IIR_CEL_STATE = computea1 or IIR_CEL_STATE = computea2) else '0';
153 Write <= '1' when (IIR_CEL_STATE = computeb1 or IIR_CEL_STATE = computeb2 or IIR_CEL_STATE = computea1 or IIR_CEL_STATE = computea2) else '0';
151
154
152 GO_0 <= '1' when IIR_CEL_STATE = waiting else '0';
155 GO_0 <= '1' when IIR_CEL_STATE = waiting else '0';
153
156
154
157
155
158
156
159
157
160
158
161
159
162
160 process(clk,reset)
163 process(clk,reset)
161 variable result : std_logic_vector(Sample_SZ-1 downto 0);
164 variable result : std_logic_vector(Sample_SZ-1 downto 0);
162
165
163 begin
166 begin
164
167
165 if reset = '0' then
168 if reset = '0' then
166
169
167 smpl_clk_old <= '0';
170 smpl_clk_old <= '0';
168 RAM_sample_in <= (others=> '0');
171 RAM_sample_in <= (others=> '0');
169 ALU_ctrl <= IDLE;
172 ALU_ctrl <= IDLE;
170 ALU_sample_in <= (others=> '0');
173 ALU_sample_in <= (others=> '0');
171 ALU_Coef_in <= (others=> '0');
174 ALU_Coef_in <= (others=> '0');
172 RAM_sample_in_bk<= (others=> '0');
175 RAM_sample_in_bk<= (others=> '0');
173 curentCel <= 0;
176 curentCel <= 0;
174 curentChan <= 0;
177 curentChan <= 0;
175 IIR_CEL_STATE <= waiting;
178 IIR_CEL_STATE <= waiting;
176 resetL0 : for i in 0 to ChanelsCount-1 loop
179 resetL0 : for i in 0 to ChanelsCount-1 loop
177 sample_in_BUFF(i) <= (others => '0');
180 sample_in_BUFF(i) <= (others => '0');
178 sample_out_BUFF(i) <= (others => '0');
181 sample_out_BUFF(i) <= (others => '0');
179 resetL1: for j in 0 to Sample_SZ-1 loop
182 resetL1: for j in 0 to Sample_SZ-1 loop
180 sample_out(i,j) <= '0';
183 sample_out(i,j) <= '0';
181 end loop;
184 end loop;
182 end loop;
185 end loop;
183
186
184 elsif clk'event and clk = '1' then
187 elsif clk'event and clk = '1' then
185
188
186 smpl_clk_old <= sample_clk;
189 smpl_clk_old <= sample_clk;
187
190
188 case IIR_CEL_STATE is
191 case IIR_CEL_STATE is
189
192
190 when waiting =>
193 when waiting =>
191 if sample_clk = '1' and smpl_clk_old = '0' then
194 if sample_clk = '1' and smpl_clk_old = '0' then
192 IIR_CEL_STATE <= pipe1;
195 IIR_CEL_STATE <= pipe1;
193 RAM_sample_in <= std_logic_vector(sample_in_BUFF(0));
196 RAM_sample_in <= std_logic_vector(sample_in_BUFF(0));
194 ALU_sample_in <= std_logic_vector(sample_in_BUFF(0));
197 ALU_sample_in <= std_logic_vector(sample_in_BUFF(0));
195
198
196 else
199 else
197 ALU_ctrl <= IDLE;
200 ALU_ctrl <= IDLE;
198 smplConnectL0: for i in 0 to ChanelsCount-1 loop
201 smplConnectL0: for i in 0 to ChanelsCount-1 loop
199 smplConnectL1: for j in 0 to Sample_SZ-1 loop
202 smplConnectL1: for j in 0 to Sample_SZ-1 loop
200 sample_in_BUFF(i)(j) <= sample_in(i,j);
203 sample_in_BUFF(i)(j) <= sample_in(i,j);
201 sample_out(i,j) <= sample_out_BUFF(i)(j);
204 sample_out(i,j) <= sample_out_BUFF(i)(j);
202 end loop;
205 end loop;
203 end loop;
206 end loop;
204 end if;
207 end if;
205 curentCel <= 0;
208 curentCel <= 0;
206 curentChan <= 0;
209 curentChan <= 0;
207
210
208 when pipe1 =>
211 when pipe1 =>
209 IIR_CEL_STATE <= computeb1;
212 IIR_CEL_STATE <= computeb1;
210 ALU_ctrl <= MAC_op;
213 ALU_ctrl <= MAC_op;
211 ALU_Coef_in <= std_logic_vector(CoefsReg.NumCoefs(curentCel)(0));
214 ALU_Coef_in <= std_logic_vector(CoefsReg.NumCoefs(curentCel)(0));
212
215
213 when computeb1 =>
216 when computeb1 =>
214
217
215 ALU_ctrl <= MAC_op;
218 ALU_ctrl <= MAC_op;
216 ALU_sample_in <= RAM_sample_out;
219 ALU_sample_in <= RAM_sample_out;
217 ALU_Coef_in <= std_logic_vector(CoefsReg.NumCoefs(curentCel)(1));
220 ALU_Coef_in <= std_logic_vector(CoefsReg.NumCoefs(curentCel)(1));
218 IIR_CEL_STATE <= computeb2;
221 IIR_CEL_STATE <= computeb2;
219 RAM_sample_in <= RAM_sample_in_bk;
222 RAM_sample_in <= RAM_sample_in_bk;
220 when computeb2 =>
223 when computeb2 =>
221 ALU_sample_in <= RAM_sample_out;
224 ALU_sample_in <= RAM_sample_out;
222 ALU_Coef_in <= std_logic_vector(CoefsReg.NumCoefs(curentCel)(2));
225 ALU_Coef_in <= std_logic_vector(CoefsReg.NumCoefs(curentCel)(2));
223 IIR_CEL_STATE <= computea1;
226 IIR_CEL_STATE <= computea1;
224
227
225
228
226 when computea1 =>
229 when computea1 =>
227 ALU_sample_in <= RAM_sample_out;
230 ALU_sample_in <= RAM_sample_out;
228 ALU_Coef_in <= std_logic_vector(CoefsReg.DenCoefs(curentCel)(1));
231 ALU_Coef_in <= std_logic_vector(CoefsReg.DenCoefs(curentCel)(1));
229 IIR_CEL_STATE <= computea2;
232 IIR_CEL_STATE <= computea2;
230
233
231
234
232 when computea2 =>
235 when computea2 =>
233 ALU_sample_in <= RAM_sample_out;
236 ALU_sample_in <= RAM_sample_out;
234 ALU_Coef_in <= std_logic_vector(CoefsReg.DenCoefs(curentCel)(2));
237 ALU_Coef_in <= std_logic_vector(CoefsReg.DenCoefs(curentCel)(2));
235 IIR_CEL_STATE <= next_cel;
238 IIR_CEL_STATE <= next_cel;
236
239
237
240
238 when next_cel =>
241 when next_cel =>
239 ALU_ctrl <= clr_mac;
242 ALU_ctrl <= clr_mac;
240 IIR_CEL_STATE <= pipe2;
243 IIR_CEL_STATE <= pipe2;
241
244
242 when pipe2 =>
245 when pipe2 =>
243 IIR_CEL_STATE <= pipe3;
246 IIR_CEL_STATE <= pipe3;
244
247
245
248
246 when pipe3 =>
249 when pipe3 =>
247
250
248 result := ALU_out(Sample_SZ+virg_pos-1 downto virg_pos);
251 result := ALU_out(Sample_SZ+virg_pos-1 downto virg_pos);
249
252
250 sample_out_BUFF(0) <= result;
253 sample_out_BUFF(0) <= result;
251 RAM_sample_in_bk <= result;
254 RAM_sample_in_bk <= result;
252 RAM_sample_in <= result;
255 RAM_sample_in <= result;
253 if curentCel = Cels_count-1 then
256 if curentCel = Cels_count-1 then
254 IIR_CEL_STATE <= next_chan;
257 IIR_CEL_STATE <= next_chan;
255 curentCel <= 0;
258 curentCel <= 0;
256 else
259 else
257 curentCel <= curentCel + 1;
260 curentCel <= curentCel + 1;
258 IIR_CEL_STATE <= pipe1;
261 IIR_CEL_STATE <= pipe1;
259 ALU_sample_in <= result;
262 ALU_sample_in <= result;
260 end if;
263 end if;
261 when next_chan =>
264 when next_chan =>
262
265
263 rotate : for i in 1 to ChanelsCount-1 loop
266 rotate : for i in 1 to ChanelsCount-1 loop
264 sample_in_BUFF(i-1) <= sample_in_BUFF(i);
267 sample_in_BUFF(i-1) <= sample_in_BUFF(i);
265 sample_out_BUFF(i-1) <= sample_out_BUFF(i);
268 sample_out_BUFF(i-1) <= sample_out_BUFF(i);
266 end loop;
269 end loop;
267 sample_in_BUFF(ChanelsCount-1) <= sample_in_BUFF(0);
270 sample_in_BUFF(ChanelsCount-1) <= sample_in_BUFF(0);
268 sample_out_BUFF(ChanelsCount-1)<= sample_out_BUFF(0);
271 sample_out_BUFF(ChanelsCount-1)<= sample_out_BUFF(0);
269
272
270 if curentChan = (ChanelsCount-1) then
273 if curentChan = (ChanelsCount-1) then
271 IIR_CEL_STATE <= waiting;
274 IIR_CEL_STATE <= waiting;
272 ALU_ctrl <= clr_mac;
275 ALU_ctrl <= clr_mac;
273 elsif ChanelsCount>1 then
276 elsif ChanelsCount>1 then
274 curentChan <= curentChan + 1;
277 curentChan <= curentChan + 1;
275 IIR_CEL_STATE <= pipe1;
278 IIR_CEL_STATE <= pipe1;
276 ALU_sample_in <= sample_in_BUFF(1);
279 ALU_sample_in <= sample_in_BUFF(1);
277 RAM_sample_in <= sample_in_BUFF(1);
280 RAM_sample_in <= sample_in_BUFF(1);
278 end if;
281 end if;
279 end case;
282 end case;
280
283
281 end if;
284 end if;
282 end process;
285 end process;
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289 end ar_IIR_CEL_CTRLR;
292 end ar_IIR_CEL_CTRLR;
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1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
21 -------------------------------------------------------------------------------
22 library IEEE;
22 library IEEE;
23 use IEEE.numeric_std.all;
23 use IEEE.numeric_std.all;
24 use IEEE.std_logic_1164.all;
24 use IEEE.std_logic_1164.all;
25 library lpp;
25 library lpp;
26 use lpp.iir_filter.all;
26 use lpp.iir_filter.all;
27 use lpp.general_purpose.all;
27 use lpp.general_purpose.all;
28
28
29 --TODO amliorer la gestion de la RAM et de la flexibilit du filtre
29 --TODO amliorer la gestion de la RAM et de la flexibilit du filtre
30
30
31 entity IIR_CEL_FILTER is
31 entity IIR_CEL_FILTER is
32 generic(Sample_SZ : integer := 16;
32 generic(
33 tech : integer := 0;
34 Sample_SZ : integer := 16;
33 ChanelsCount : integer := 1;
35 ChanelsCount : integer := 1;
34 Coef_SZ : integer := 9;
36 Coef_SZ : integer := 9;
35 CoefCntPerCel: integer := 3;
37 CoefCntPerCel: integer := 3;
36 Cels_count : integer := 5;
38 Cels_count : integer := 5;
37 Mem_use : integer := use_RAM);
39 Mem_use : integer := use_RAM);
38 port(
40 port(
39 reset : in std_logic;
41 reset : in std_logic;
40 clk : in std_logic;
42 clk : in std_logic;
41 sample_clk : in std_logic;
43 sample_clk : in std_logic;
42 regs_in : in in_IIR_CEL_reg;
44 regs_in : in in_IIR_CEL_reg;
43 regs_out : in out_IIR_CEL_reg;
45 regs_out : in out_IIR_CEL_reg;
44 sample_in : in samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0);
46 sample_in : in samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0);
45 sample_out : out samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0);
47 sample_out : out samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0);
46 coefs : in std_logic_vector(Coef_SZ*CoefCntPerCel*Cels_count-1 downto 0)
48 coefs : in std_logic_vector(Coef_SZ*CoefCntPerCel*Cels_count-1 downto 0)
47
49
48 );
50 );
49 end IIR_CEL_FILTER;
51 end IIR_CEL_FILTER;
50
52
51
53
52
54
53
55
54 architecture ar_IIR_CEL_FILTER of IIR_CEL_FILTER is
56 architecture ar_IIR_CEL_FILTER of IIR_CEL_FILTER is
55
57
56 signal virg_pos : integer;
58 signal virg_pos : integer;
57 begin
59 begin
58
60
59 virg_pos <= to_integer(unsigned(regs_in.virgPos));
61 virg_pos <= to_integer(unsigned(regs_in.virgPos));
60
62
61 CTRLR : IIR_CEL_CTRLR
63 CTRLR : IIR_CEL_CTRLR
62 generic map (Sample_SZ,ChanelsCount,Coef_SZ,CoefCntPerCel,Cels_count,Mem_use)
64 generic map (tech,Sample_SZ,ChanelsCount,Coef_SZ,CoefCntPerCel,Cels_count,Mem_use)
63 port map(
65 port map(
64 reset => reset,
66 reset => reset,
65 clk => clk,
67 clk => clk,
66 sample_clk => sample_clk,
68 sample_clk => sample_clk,
67 sample_in => sample_in,
69 sample_in => sample_in,
68 sample_out => sample_out,
70 sample_out => sample_out,
69 virg_pos => virg_pos,
71 virg_pos => virg_pos,
70 coefs => coefs
72 coefs => coefs
71 );
73 );
72
74
73
75
74
76
75
77
76
78
77 end ar_IIR_CEL_FILTER;
79 end ar_IIR_CEL_FILTER;
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1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 ----------------------------------------------------------------------------
21 ----------------------------------------------------------------------------
22 library IEEE;
22 library IEEE;
23 use IEEE.numeric_std.all;
23 use IEEE.numeric_std.all;
24 use IEEE.std_logic_1164.all;
24 use IEEE.std_logic_1164.all;
25 library lpp;
25 library lpp;
26 use lpp.iir_filter.all;
26 use lpp.iir_filter.all;
27 use lpp.FILTERcfg.all;
27 use lpp.FILTERcfg.all;
28 use lpp.general_purpose.all;
28 use lpp.general_purpose.all;
29 library techmap;
30 use techmap.gencomp.all;
29
31
30 --TODO amliorer la flexibilit de la config de la RAM.
32 --TODO amliorer la flexibilit de la config de la RAM.
31
33
32 entity RAM_CTRLR2 is
34 entity RAM_CTRLR2 is
33 generic(
35 generic(
36 tech : integer := 0;
34 Input_SZ_1 : integer := 16;
37 Input_SZ_1 : integer := 16;
35 Mem_use : integer := use_RAM
38 Mem_use : integer := use_RAM
39
36 );
40 );
37 port(
41 port(
38 reset : in std_logic;
42 reset : in std_logic;
39 clk : in std_logic;
43 clk : in std_logic;
40 WD_sel : in std_logic;
44 WD_sel : in std_logic;
41 Read : in std_logic;
45 Read : in std_logic;
42 WADDR_sel : in std_logic;
46 WADDR_sel : in std_logic;
43 count : in std_logic;
47 count : in std_logic;
44 SVG_ADDR : in std_logic;
48 SVG_ADDR : in std_logic;
45 Write : in std_logic;
49 Write : in std_logic;
46 GO_0 : in std_logic;
50 GO_0 : in std_logic;
47 sample_in : in std_logic_vector(Input_SZ_1-1 downto 0);
51 sample_in : in std_logic_vector(Input_SZ_1-1 downto 0);
48 sample_out : out std_logic_vector(Input_SZ_1-1 downto 0)
52 sample_out : out std_logic_vector(Input_SZ_1-1 downto 0)
49 );
53 );
50 end RAM_CTRLR2;
54 end RAM_CTRLR2;
51
55
52
56
53 architecture ar_RAM_CTRLR2 of RAM_CTRLR2 is
57 architecture ar_RAM_CTRLR2 of RAM_CTRLR2 is
54
58
55 signal WD : std_logic_vector(35 downto 0);
59 signal WD : std_logic_vector(Input_SZ_1-1 downto 0);
56 signal WD_D : std_logic_vector(35 downto 0);
60 signal WD_D : std_logic_vector(Input_SZ_1-1 downto 0);
57 signal RD : std_logic_vector(35 downto 0);
61 signal RD : std_logic_vector(Input_SZ_1-1 downto 0);
58 signal WEN, REN : std_logic;
62 signal WEN, REN : std_logic;
59 signal WADDR_back : std_logic_vector(7 downto 0);
63 signal WADDR_back : std_logic_vector(7 downto 0);
60 signal WADDR_back_D: std_logic_vector(7 downto 0);
64 signal WADDR_back_D: std_logic_vector(7 downto 0);
61 signal RADDR : std_logic_vector(7 downto 0);
65 signal RADDR : std_logic_vector(7 downto 0);
62 signal WADDR : std_logic_vector(7 downto 0);
66 signal WADDR : std_logic_vector(7 downto 0);
63 signal WADDR_D : std_logic_vector(7 downto 0);
67 signal WADDR_D : std_logic_vector(7 downto 0);
64
68
65
69
66
70
67 begin
71 begin
68
72
69 sample_out <= RD(Input_SZ_1-1 downto 0);
73 sample_out <= RD(Input_SZ_1-1 downto 0);
70
74
71
75
72 WEN <= not Write;
76 WEN <= not Write;
73 REN <= not read;
77 REN <= not read;
74
78
75
79
76 --==============================================================
80 --==============================================================
77 --=========================R A M================================
81 --=========================R A M================================
78 --==============================================================
82 --==============================================================
79 memRAM : if Mem_use = use_RAM generate
83 --memRAM : if Mem_use = use_RAM generate
80 RAMblk :RAM
84 --RAMblk :RAM
81 port map(
85 -- port map(
82 WD => WD_D,
86 -- WD => WD_D,
83 RD => RD,
87 -- RD => RD,
84 WEN => WEN,
88 -- WEN => WEN,
85 REN => REN,
89 -- REN => REN,
86 WADDR => WADDR,
90 -- WADDR => WADDR,
87 RADDR => RADDR,
91 -- RADDR => RADDR,
88 RWCLK => clk,
92 -- RWCLK => clk,
89 RESET => reset
93 -- RESET => reset
90 ) ;
94 -- ) ;
91 end generate;
95 --end generate;
92
96
93 memCEL : if Mem_use = use_CEL generate
97 --memCEL : if Mem_use = use_CEL generate
94 RAMblk :RAM_CEL
98 --RAMblk :RAM_CEL
95 port map(
99 -- port map(
96 WD => WD_D,
100 -- WD => WD_D,
97 RD => RD,
101 -- RD => RD,
98 WEN => WEN,
102 -- WEN => WEN,
99 REN => REN,
103 -- REN => REN,
100 WADDR => WADDR,
104 -- WADDR => WADDR,
101 RADDR => RADDR,
105 -- RADDR => RADDR,
102 RWCLK => clk,
106 -- RWCLK => clk,
103 RESET => reset
107 -- RESET => reset
104 ) ;
108 -- ) ;
105 end generate;
109 --end generate;
110
111 SRAM : syncram_2p
112 generic map(tech,8,Input_SZ_1)
113 port map(clk,not REN,RADDR,RD,clk,not WEN,WADDR,WD_D);
106 --==============================================================
114 --==============================================================
107 --==============================================================
115 --==============================================================
108
116
109
117
110 ADDRcntr_inst : ADDRcntr
118 ADDRcntr_inst : ADDRcntr
111 port map(
119 port map(
112 clk => clk,
120 clk => clk,
113 reset => reset,
121 reset => reset,
114 count => count,
122 count => count,
115 clr => GO_0,
123 clr => GO_0,
116 Q => RADDR
124 Q => RADDR
117 );
125 );
118
126
119
127
120
128
121 MUX2_inst1 :MUX2
129 MUX2_inst1 :MUX2
122 generic map(Input_SZ => Input_SZ_1)
130 generic map(Input_SZ => Input_SZ_1)
123 port map(
131 port map(
124 sel => WD_sel,
132 sel => WD_sel,
125 IN1 => sample_in,
133 IN1 => sample_in,
126 IN2 => RD(Input_SZ_1-1 downto 0),
134 IN2 => RD(Input_SZ_1-1 downto 0),
127 RES => WD(Input_SZ_1-1 downto 0)
135 RES => WD(Input_SZ_1-1 downto 0)
128 );
136 );
129
137
130
138
131 MUX2_inst2 :MUX2
139 MUX2_inst2 :MUX2
132 generic map(Input_SZ => 8)
140 generic map(Input_SZ => 8)
133 port map(
141 port map(
134 sel => WADDR_sel,
142 sel => WADDR_sel,
135 IN1 => WADDR_D,
143 IN1 => WADDR_D,
136 IN2 => WADDR_back_D,
144 IN2 => WADDR_back_D,
137 RES => WADDR
145 RES => WADDR
138 );
146 );
139
147
140
148
141
149
142
150
143 WADDR_backreg :REG
151 WADDR_backreg :REG
144 generic map(size => 8,initial_VALUE =>ChanelsCNT*Cels_count*4-2)
152 generic map(size => 8,initial_VALUE =>ChanelsCNT*Cels_count*4-2)
145 port map(
153 port map(
146 reset => reset,
154 reset => reset,
147 clk => SVG_ADDR,
155 clk => SVG_ADDR,
148 D => RADDR,
156 D => RADDR,
149 Q => WADDR_back
157 Q => WADDR_back
150 );
158 );
151
159
152 WADDR_backreg2 :REG
160 WADDR_backreg2 :REG
153 generic map(size => 8)
161 generic map(size => 8)
154 port map(
162 port map(
155 reset => reset,
163 reset => reset,
156 clk => SVG_ADDR,
164 clk => SVG_ADDR,
157 D => WADDR_back,
165 D => WADDR_back,
158 Q => WADDR_back_D
166 Q => WADDR_back_D
159 );
167 );
160
168
161 WDRreg :REG
169 WDRreg :REG
162 generic map(size => Input_SZ_1)
170 generic map(size => Input_SZ_1)
163 port map(
171 port map(
164 reset => reset,
172 reset => reset,
165 clk => clk,
173 clk => clk,
166 D => WD(Input_SZ_1-1 downto 0),
174 D => WD(Input_SZ_1-1 downto 0),
167 Q => WD_D(Input_SZ_1-1 downto 0)
175 Q => WD_D(Input_SZ_1-1 downto 0)
168 );
176 );
169
177
170
178
171
179
172
180
173 ADDRreg :REG
181 ADDRreg :REG
174 generic map(size => 8)
182 generic map(size => 8)
175 port map(
183 port map(
176 reset => reset,
184 reset => reset,
177 clk => clk,
185 clk => clk,
178 D => RADDR,
186 D => RADDR,
179 Q => WADDR_D
187 Q => WADDR_D
180 );
188 );
181
189
182
190
183
191
184 end ar_RAM_CTRLR2;
192 end ar_RAM_CTRLR2;
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@@ -1,225 +1,231
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 ----------------------------------------------------------------------------
21 ----------------------------------------------------------------------------
22 library ieee;
22 library ieee;
23 use ieee.std_logic_1164.all;
23 use ieee.std_logic_1164.all;
24 library grlib;
24 library grlib;
25 use grlib.amba.all;
25 use grlib.amba.all;
26 use grlib.stdlib.all;
26 use grlib.stdlib.all;
27 use grlib.devices.all;
27 use grlib.devices.all;
28 library lpp;
28 library lpp;
29
29
30
30
31
31
32
32
33 package iir_filter is
33 package iir_filter is
34
34
35
35
36 --===========================================================|
36 --===========================================================|
37 --================A L U C O N T R O L======================|
37 --================A L U C O N T R O L======================|
38 --===========================================================|
38 --===========================================================|
39 constant IDLE : std_logic_vector(3 downto 0) := "0000";
39 constant IDLE : std_logic_vector(3 downto 0) := "0000";
40 constant MAC_op : std_logic_vector(3 downto 0) := "0001";
40 constant MAC_op : std_logic_vector(3 downto 0) := "0001";
41 constant MULT : std_logic_vector(3 downto 0) := "0010";
41 constant MULT : std_logic_vector(3 downto 0) := "0010";
42 constant ADD : std_logic_vector(3 downto 0) := "0011";
42 constant ADD : std_logic_vector(3 downto 0) := "0011";
43 constant clr_mac : std_logic_vector(3 downto 0) := "0100";
43 constant clr_mac : std_logic_vector(3 downto 0) := "0100";
44
44
45 --____
45 --____
46 --RAM |
46 --RAM |
47 --____|
47 --____|
48 constant use_RAM : integer := 1;
48 constant use_RAM : integer := 1;
49 constant use_CEL : integer := 0;
49 constant use_CEL : integer := 0;
50
50
51
51
52 --===========================================================|
52 --===========================================================|
53 --=============C O E F S ====================================|
53 --=============C O E F S ====================================|
54 --===========================================================|
54 --===========================================================|
55 -- create a specific type of data for coefs to avoid errors |
55 -- create a specific type of data for coefs to avoid errors |
56 --===========================================================|
56 --===========================================================|
57
57
58 type scaleValT is array(natural range <>) of integer;
58 type scaleValT is array(natural range <>) of integer;
59
59
60 type samplT is array(natural range <>,natural range <>) of std_logic;
60 type samplT is array(natural range <>,natural range <>) of std_logic;
61
61
62 type in_IIR_CEL_reg is record
62 type in_IIR_CEL_reg is record
63 config : std_logic_vector(31 downto 0);
63 config : std_logic_vector(31 downto 0);
64 virgPos : std_logic_vector(4 downto 0);
64 virgPos : std_logic_vector(4 downto 0);
65 end record;
65 end record;
66
66
67 type out_IIR_CEL_reg is record
67 type out_IIR_CEL_reg is record
68 config : std_logic_vector(31 downto 0);
68 config : std_logic_vector(31 downto 0);
69 status : std_logic_vector(31 downto 0);
69 status : std_logic_vector(31 downto 0);
70 end record;
70 end record;
71
71
72
72
73
73
74 component APB_IIR_CEL is
74 component APB_IIR_CEL is
75 generic (
75 generic (
76 tech : integer := 0;
76 pindex : integer := 0;
77 pindex : integer := 0;
77 paddr : integer := 0;
78 paddr : integer := 0;
78 pmask : integer := 16#fff#;
79 pmask : integer := 16#fff#;
79 pirq : integer := 0;
80 pirq : integer := 0;
80 abits : integer := 8;
81 abits : integer := 8;
81 Sample_SZ : integer := 16;
82 Sample_SZ : integer := 16;
82 ChanelsCount : integer := 1;
83 ChanelsCount : integer := 1;
83 Coef_SZ : integer := 9;
84 Coef_SZ : integer := 9;
84 CoefCntPerCel: integer := 3;
85 CoefCntPerCel: integer := 3;
85 Cels_count : integer := 5;
86 Cels_count : integer := 5;
86 virgPos : integer := 3;
87 virgPos : integer := 3;
87 Mem_use : integer := use_RAM
88 Mem_use : integer := use_RAM
88 );
89 );
89 port (
90 port (
90 rst : in std_logic;
91 rst : in std_logic;
91 clk : in std_logic;
92 clk : in std_logic;
92 apbi : in apb_slv_in_type;
93 apbi : in apb_slv_in_type;
93 apbo : out apb_slv_out_type;
94 apbo : out apb_slv_out_type;
94 sample_clk : in std_logic;
95 sample_clk : in std_logic;
95 sample_clk_out : out std_logic;
96 sample_clk_out : out std_logic;
96 sample_in : in samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0);
97 sample_in : in samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0);
97 sample_out : out samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0)
98 sample_out : out samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0)
98 );
99 );
99 end component;
100 end component;
100
101
101
102
102 --component FILTER is
103 --component FILTER is
103 --generic(Smpl_SZ : integer := 16;
104 --generic(Smpl_SZ : integer := 16;
104 -- ChanelsCNT : integer := 3
105 -- ChanelsCNT : integer := 3
105 --);
106 --);
106 --port(
107 --port(
107 --
108 --
108 -- reset : in std_logic;
109 -- reset : in std_logic;
109 -- clk : in std_logic;
110 -- clk : in std_logic;
110 -- sample_clk : in std_logic;
111 -- sample_clk : in std_logic;
111 -- Sample_IN : in std_logic_vector(Smpl_SZ*ChanelsCNT-1 downto 0);
112 -- Sample_IN : in std_logic_vector(Smpl_SZ*ChanelsCNT-1 downto 0);
112 -- Sample_OUT : out std_logic_vector(Smpl_SZ*ChanelsCNT-1 downto 0)
113 -- Sample_OUT : out std_logic_vector(Smpl_SZ*ChanelsCNT-1 downto 0)
113 --);
114 --);
114 --end component;
115 --end component;
115
116
116
117
117
118
118 --component FilterCTRLR is
119 --component FilterCTRLR is
119 --port(
120 --port(
120 -- reset : in std_logic;
121 -- reset : in std_logic;
121 -- clk : in std_logic;
122 -- clk : in std_logic;
122 -- sample_clk : in std_logic;
123 -- sample_clk : in std_logic;
123 -- ALU_Ctrl : out std_logic_vector(3 downto 0);
124 -- ALU_Ctrl : out std_logic_vector(3 downto 0);
124 -- sample_in : in samplT;
125 -- sample_in : in samplT;
125 -- coef : out std_logic_vector(Coef_SZ-1 downto 0);
126 -- coef : out std_logic_vector(Coef_SZ-1 downto 0);
126 -- sample : out std_logic_vector(Smpl_SZ-1 downto 0)
127 -- sample : out std_logic_vector(Smpl_SZ-1 downto 0)
127 --);
128 --);
128 --end component;
129 --end component;
129
130
130
131
131 --component FILTER_RAM_CTRLR is
132 --component FILTER_RAM_CTRLR is
132 --port(
133 --port(
133 -- reset : in std_logic;
134 -- reset : in std_logic;
134 -- clk : in std_logic;
135 -- clk : in std_logic;
135 -- run : in std_logic;
136 -- run : in std_logic;
136 -- GO_0 : in std_logic;
137 -- GO_0 : in std_logic;
137 -- B_A : in std_logic;
138 -- B_A : in std_logic;
138 -- writeForce : in std_logic;
139 -- writeForce : in std_logic;
139 -- next_blk : in std_logic;
140 -- next_blk : in std_logic;
140 -- sample_in : in std_logic_vector(Smpl_SZ-1 downto 0);
141 -- sample_in : in std_logic_vector(Smpl_SZ-1 downto 0);
141 -- sample_out : out std_logic_vector(Smpl_SZ-1 downto 0)
142 -- sample_out : out std_logic_vector(Smpl_SZ-1 downto 0)
142 --);
143 --);
143 --end component;
144 --end component;
144
145
145
146
146 component IIR_CEL_CTRLR is
147 component IIR_CEL_CTRLR is
147 generic(Sample_SZ : integer := 16;
148 generic(
149 tech : integer := 0;
150 Sample_SZ : integer := 16;
148 ChanelsCount : integer := 1;
151 ChanelsCount : integer := 1;
149 Coef_SZ : integer := 9;
152 Coef_SZ : integer := 9;
150 CoefCntPerCel: integer := 3;
153 CoefCntPerCel: integer := 3;
151 Cels_count : integer := 5;
154 Cels_count : integer := 5;
152 Mem_use : integer := use_RAM
155 Mem_use : integer := use_RAM
153 );
156 );
154 port(
157 port(
155 reset : in std_logic;
158 reset : in std_logic;
156 clk : in std_logic;
159 clk : in std_logic;
157 sample_clk : in std_logic;
160 sample_clk : in std_logic;
158 sample_in : in samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0);
161 sample_in : in samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0);
159 sample_out : out samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0);
162 sample_out : out samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0);
160 virg_pos : in integer;
163 virg_pos : in integer;
161 coefs : in std_logic_vector(Coef_SZ*CoefCntPerCel*Cels_count-1 downto 0)
164 coefs : in std_logic_vector(Coef_SZ*CoefCntPerCel*Cels_count-1 downto 0)
162 );
165 );
163 end component;
166 end component;
164
167
165
168
166 component RAM is
169 component RAM is
167 port( WD : in std_logic_vector(35 downto 0); RD : out
170 port( WD : in std_logic_vector(35 downto 0); RD : out
168 std_logic_vector(35 downto 0);WEN, REN : in std_logic;
171 std_logic_vector(35 downto 0);WEN, REN : in std_logic;
169 WADDR : in std_logic_vector(7 downto 0); RADDR : in
172 WADDR : in std_logic_vector(7 downto 0); RADDR : in
170 std_logic_vector(7 downto 0);RWCLK, RESET : in std_logic
173 std_logic_vector(7 downto 0);RWCLK, RESET : in std_logic
171 ) ;
174 ) ;
172 end component;
175 end component;
173
176
174
177
175 component RAM_CEL is
178 component RAM_CEL is
176 port( WD : in std_logic_vector(35 downto 0); RD : out
179 port( WD : in std_logic_vector(35 downto 0); RD : out
177 std_logic_vector(35 downto 0);WEN, REN : in std_logic;
180 std_logic_vector(35 downto 0);WEN, REN : in std_logic;
178 WADDR : in std_logic_vector(7 downto 0); RADDR : in
181 WADDR : in std_logic_vector(7 downto 0); RADDR : in
179 std_logic_vector(7 downto 0);RWCLK, RESET : in std_logic
182 std_logic_vector(7 downto 0);RWCLK, RESET : in std_logic
180 ) ;
183 ) ;
181 end component;
184 end component;
182
185
183 component IIR_CEL_FILTER is
186 component IIR_CEL_FILTER is
184 generic(Sample_SZ : integer := 16;
187 generic(
188 tech : integer := 0;
189 Sample_SZ : integer := 16;
185 ChanelsCount : integer := 1;
190 ChanelsCount : integer := 1;
186 Coef_SZ : integer := 9;
191 Coef_SZ : integer := 9;
187 CoefCntPerCel: integer := 3;
192 CoefCntPerCel: integer := 3;
188 Cels_count : integer := 5;
193 Cels_count : integer := 5;
189 Mem_use : integer := use_RAM);
194 Mem_use : integer := use_RAM);
190 port(
195 port(
191 reset : in std_logic;
196 reset : in std_logic;
192 clk : in std_logic;
197 clk : in std_logic;
193 sample_clk : in std_logic;
198 sample_clk : in std_logic;
194 regs_in : in in_IIR_CEL_reg;
199 regs_in : in in_IIR_CEL_reg;
195 regs_out : in out_IIR_CEL_reg;
200 regs_out : in out_IIR_CEL_reg;
196 sample_in : in samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0);
201 sample_in : in samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0);
197 sample_out : out samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0);
202 sample_out : out samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0);
198 coefs : in std_logic_vector(Coef_SZ*CoefCntPerCel*Cels_count-1 downto 0)
203 coefs : in std_logic_vector(Coef_SZ*CoefCntPerCel*Cels_count-1 downto 0)
199
204
200 );
205 );
201 end component;
206 end component;
202
207
203
208
204 component RAM_CTRLR2 is
209 component RAM_CTRLR2 is
205 generic(
210 generic(
211 tech : integer := 0;
206 Input_SZ_1 : integer := 16;
212 Input_SZ_1 : integer := 16;
207 Mem_use : integer := use_RAM
213 Mem_use : integer := use_RAM
208 );
214 );
209 port(
215 port(
210 reset : in std_logic;
216 reset : in std_logic;
211 clk : in std_logic;
217 clk : in std_logic;
212 WD_sel : in std_logic;
218 WD_sel : in std_logic;
213 Read : in std_logic;
219 Read : in std_logic;
214 WADDR_sel : in std_logic;
220 WADDR_sel : in std_logic;
215 count : in std_logic;
221 count : in std_logic;
216 SVG_ADDR : in std_logic;
222 SVG_ADDR : in std_logic;
217 Write : in std_logic;
223 Write : in std_logic;
218 GO_0 : in std_logic;
224 GO_0 : in std_logic;
219 sample_in : in std_logic_vector(Input_SZ_1-1 downto 0);
225 sample_in : in std_logic_vector(Input_SZ_1-1 downto 0);
220 sample_out : out std_logic_vector(Input_SZ_1-1 downto 0)
226 sample_out : out std_logic_vector(Input_SZ_1-1 downto 0)
221 );
227 );
222 end component;
228 end component;
223
229
224
230
225 end;
231 end;
Show file before | Show file after | Hide comments
@@ -1,278 +1,83
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
21 ------------------------------------------------------------------------------
22 library ieee;
22 library ieee;
23 use ieee.std_logic_1164.all;
23 use ieee.std_logic_1164.all;
24 library grlib;
24 library grlib;
25 use grlib.amba.all;
25 use grlib.amba.all;
26 use std.textio.all;
26 use std.textio.all;
27 library lpp;
27 library lpp;
28 use lpp.lpp_amba.all;
28 use lpp.lpp_amba.all;
29 library gaisler;
29 library gaisler;
30 use gaisler.misc.all;
30 use gaisler.misc.all;
31 use gaisler.memctrl.all;
31 use gaisler.memctrl.all;
32
32
33 --! Package contenant tous les programmes qui forment le composant int�gr� dans le l�on
33 --! Package contenant tous les programmes qui forment le composant int�gr� dans le l�on
34
34
35 package lpp_memory is
35 package lpp_memory is
36
36
37 --===========================================================|
37 component lpp_fifo is
38 --=================== FIFO Compl�te =========================|
38 generic(
39 --===========================================================|
39 tech : integer := 0;
40
40 DataSz : integer range 1 to 32 := 8;
41 component APB_FIFO is
41 abits : integer range 2 to 12 := 8
42 generic (
43 pindex : integer := 0;
44 paddr : integer := 0;
45 pmask : integer := 16#fff#;
46 pirq : integer := 0;
47 abits : integer := 8;
48 Data_sz : integer := 16;
49 Addr_sz : integer := 8;
50 addr_max_int : integer := 256);
51 port (
52 clk : in std_logic;
53 rst : in std_logic;
54 apbi : in apb_slv_in_type;
55 Full : out std_logic;
56 Empty : out std_logic;
57 WR : out std_logic;
58 RE : out std_logic;
59 apbo : out apb_slv_out_type
60 );
61 end component;
62
63
64 component ApbDriver is
65 generic (
66 pindex : integer := 0;
67 paddr : integer := 0;
68 pmask : integer := 16#fff#;
69 pirq : integer := 0;
70 abits : integer := 8;
71 LPP_DEVICE : integer;
72 Data_sz : integer := 16;
73 Addr_sz : integer := 8;
74 addr_max_int : integer := 256);
75 port (
76 clk : in std_logic;
77 rst : in std_logic;
78 ReadEnable : out std_logic;
79 WriteEnable : out std_logic;
80 FlagEmpty : in std_logic;
81 FlagFull : in std_logic;
82 ReUse : out std_logic;
83 Lock : out std_logic;
84 DataIn : out std_logic_vector(Data_sz-1 downto 0);
85 DataOut : in std_logic_vector(Data_sz-1 downto 0);
86 AddrIn : in std_logic_vector(Addr_sz-1 downto 0);
87 AddrOut : in std_logic_vector(Addr_sz-1 downto 0);
88 apbi : in apb_slv_in_type;
89 apbo : out apb_slv_out_type
90 );
42 );
91 end component;
43 port(
92
44 rstn : in std_logic;
93
45 rclk : in std_logic;
94 component Top_FIFO is
46 ren : in std_logic;
95 generic(
47 rdata : out std_logic_vector(DataSz-1 downto 0);
96 Data_sz : integer := 16;
48 empty : out std_logic;
97 Addr_sz : integer := 8;
49 raddr : out std_logic_vector(abits-1 downto 0);
98 addr_max_int : integer := 256
50 wclk : in std_logic;
99 );
51 wen : in std_logic;
100 port(
52 wdata : in std_logic_vector(DataSz-1 downto 0);
101 clk,raz : in std_logic;
53 full : out std_logic;
102 flag_RE : in std_logic;
54 waddr : out std_logic_vector(abits-1 downto 0)
103 flag_WR : in std_logic;
55 );
104 ReUse : in std_logic;
105 Lock : in std_logic;
106 Data_in : in std_logic_vector(Data_sz-1 downto 0);
107 Addr_RE : out std_logic_vector(addr_sz-1 downto 0);
108 Addr_WR : out std_logic_vector(addr_sz-1 downto 0);
109 full : out std_logic;
110 empty : out std_logic;
111 Data_out : out std_logic_vector(Data_sz-1 downto 0)
112 );
113 end component;
114
115
116 component Fifo_Read is
117 generic(
118 Addr_sz : integer := 8;
119 addr_max_int : integer := 256);
120 port(
121 clk : in std_logic;
122 raz : in std_logic;
123 flag_RE : in std_logic;
124 ReUse : in std_logic;
125 Waddr : in std_logic_vector(addr_sz-1 downto 0);
126 empty : out std_logic;
127 Raddr : out std_logic_vector(addr_sz-1 downto 0)
128 );
129 end component;
130
131
132 component Fifo_Write is
133 generic(
134 Addr_sz : integer := 8;
135 addr_max_int : integer := 256);
136 port(
137 clk : in std_logic;
138 raz : in std_logic;
139 flag_WR : in std_logic;
140 Raddr : in std_logic_vector(addr_sz-1 downto 0);
141 full : out std_logic;
142 Waddr : out std_logic_vector(addr_sz-1 downto 0)
143 );
144 end component;
56 end component;
145
57
146
147 component Link_Reg is
148 generic(Data_sz : integer := 16);
149 port(
150 clk,raz : in std_logic;
151 Data_one : in std_logic_vector(Data_sz-1 downto 0);
152 Data_two : in std_logic_vector(Data_sz-1 downto 0);
153 ReUse : in std_logic;
154 flag_RE : in std_logic;
155 flag_WR : in std_logic;
156 empty : in std_logic;
157 Data_out : out std_logic_vector(Data_sz-1 downto 0)
158 );
159 end component;
160
161 --===========================================================|
162 --================= Demi FIFO Ecriture ======================|
163 --===========================================================|
164
165 component APB_FifoWrite is
166 generic (
167 pindex : integer := 0;
168 paddr : integer := 0;
169 pmask : integer := 16#fff#;
170 pirq : integer := 0;
171 abits : integer := 8;
172 Data_sz : integer := 16;
173 Addr_sz : integer := 8;
174 addr_max_int : integer := 256);
175 port (
176 clk : in std_logic;
177 rst : in std_logic;
178 apbi : in apb_slv_in_type;
179 ReadEnable : in std_logic;
180 Empty : out std_logic;
181 Full : out std_logic;
182 DATA : out std_logic_vector(Data_sz-1 downto 0);
183 apbo : out apb_slv_out_type
184 );
185 end component;
186
187
188 --component Top_FifoWrite is
189 -- generic(
190 -- Data_sz : integer := 16;
191 -- Addr_sz : integer := 8;
192 -- addr_max_int : integer := 256);
193 -- port(
194 -- clk : in std_logic;
195 -- raz : in std_logic;
196 -- flag_RE : in std_logic;
197 -- flag_WR : in std_logic;
198 -- Data_in : in std_logic_vector(Data_sz-1 downto 0);
199 -- Raddr : in std_logic_vector(addr_sz-1 downto 0);
200 -- full : out std_logic;
201 -- empty : out std_logic;
202 -- Waddr : out std_logic_vector(addr_sz-1 downto 0);
203 -- Data_out : out std_logic_vector(Data_sz-1 downto 0)
204 -- );
205 --end component;
206
207 --===========================================================|
208 --================== Demi FIFO Lecture ======================|
209 --===========================================================|
210
211 component APB_FifoRead is
212 generic (
213 pindex : integer := 0;
214 paddr : integer := 0;
215 pmask : integer := 16#fff#;
216 pirq : integer := 0;
217 abits : integer := 8;
218 Data_sz : integer := 16;
219 Addr_sz : integer := 8;
220 addr_max_int : integer := 256);
221 port (
222 clk : in std_logic;
223 rst : in std_logic;
224 apbi : in apb_slv_in_type;
225 WriteEnable : in std_logic;
226 Full : out std_logic;
227 Empty : out std_logic;
228 DATA : in std_logic_vector(Data_sz-1 downto 0);
229 apbo : out apb_slv_out_type
230 );
231 end component;
232
233
234 --component Top_FifoRead is
235 -- generic(
236 -- Data_sz : integer := 16;
237 -- Addr_sz : integer := 8;
238 -- addr_max_int : integer := 256);
239 -- port(
240 -- clk : in std_logic;
241 -- raz : in std_logic;
242 -- flag_RE : in std_logic;
243 -- flag_WR : in std_logic;
244 -- Data_in : in std_logic_vector(Data_sz-1 downto 0);
245 -- Waddr : in std_logic_vector(addr_sz-1 downto 0);
246 -- full : out std_logic;
247 -- empty : out std_logic;
248 -- Raddr : out std_logic_vector(addr_sz-1 downto 0);
249 -- Data_out : out std_logic_vector(Data_sz-1 downto 0)
250 -- );
251 --end component;
252
253 component ssram_plugin is
58 component ssram_plugin is
254 generic (tech : integer := 0);
59 generic (tech : integer := 0);
255 port
60 port
256 (
61 (
257 clk : in std_logic;
62 clk : in std_logic;
258 mem_ctrlr_o : in memory_out_type;
63 mem_ctrlr_o : in memory_out_type;
259 SSRAM_CLK : out std_logic;
64 SSRAM_CLK : out std_logic;
260 nBWa : out std_logic;
65 nBWa : out std_logic;
261 nBWb : out std_logic;
66 nBWb : out std_logic;
262 nBWc : out std_logic;
67 nBWc : out std_logic;
263 nBWd : out std_logic;
68 nBWd : out std_logic;
264 nBWE : out std_logic;
69 nBWE : out std_logic;
265 nADSC : out std_logic;
70 nADSC : out std_logic;
266 nADSP : out std_logic;
71 nADSP : out std_logic;
267 nADV : out std_logic;
72 nADV : out std_logic;
268 nGW : out std_logic;
73 nGW : out std_logic;
269 nCE1 : out std_logic;
74 nCE1 : out std_logic;
270 CE2 : out std_logic;
75 CE2 : out std_logic;
271 nCE3 : out std_logic;
76 nCE3 : out std_logic;
272 nOE : out std_logic;
77 nOE : out std_logic;
273 MODE : out std_logic;
78 MODE : out std_logic;
274 ZZ : out std_logic
79 ZZ : out std_logic
275 );
80 );
276 end component;
81 end component;
277
82
278 end;
83 end;
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1 NO CONTENT: file was removed
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