diff --git a/lib/lpp/dsp/iir_filter/APB_IIR_CEL.vhd b/lib/lpp/dsp/iir_filter/APB_IIR_CEL.vhd --- a/lib/lpp/dsp/iir_filter/APB_IIR_CEL.vhd +++ b/lib/lpp/dsp/iir_filter/APB_IIR_CEL.vhd @@ -34,6 +34,7 @@ use lpp.apb_devices_list.all; entity APB_IIR_CEL is generic ( + tech : integer := 0; pindex : integer := 0; paddr : integer := 0; pmask : integer := 16#fff#; @@ -80,7 +81,7 @@ signal r : FILTERreg; signal filter_reset : std_logic:='0'; signal smp_cnt : integer :=0; signal sample_clk_out_R : std_logic; - +signal RawCoefs : std_logic_vector(Coef_SZ*CoefCntPerCel*Cels_count-1 downto 0); type CoefCelT is array(CoefCntPerCel-1 downto 0) of std_logic_vector(Coef_SZ-1 downto 0); type CoefTblT is array(Cels_count-1 downto 0) of CoefCelT; @@ -98,7 +99,7 @@ filter_reset <= rst and r.regin.conf sample_clk_out <= sample_clk_out_R; filter : IIR_CEL_FILTER -generic map(Sample_SZ,ChanelsCount,Coef_SZ,CoefCntPerCel,Cels_count,Mem_use) +generic map(tech,Sample_SZ,ChanelsCount,Coef_SZ,CoefCntPerCel,Cels_count,Mem_use) port map( reset => filter_reset, clk => clk, @@ -106,7 +107,8 @@ port map( regs_in => r.regin, regs_out => r.regout, sample_in => sample_in, - sample_out => sample_out + sample_out => sample_out, + coefs => RawCoefs ); process(rst,sample_clk) @@ -125,6 +127,15 @@ end if; end process; +coefsConnectL0: for z in 0 to Cels_count-1 generate + coefsConnectL1: for y in 0 to (CoefCntPerCel/2)-1 generate + coefsConnectL2: for x in 0 to Coef_SZ-1 generate + RawCoefs(x + ((2*y))*Coef_SZ + z*Coef_SZ*CoefCntPerCel) <= CoefsReg.numCoefs(z)(y)(x); + RawCoefs(x + ((2*y)+1)*Coef_SZ + z*Coef_SZ*CoefCntPerCel) <= CoefsReg.denCoefs(z)(y)(x); + end generate; + end generate; +end generate; + process(rst,clk) begin if rst = '0' then diff --git a/lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR.vhd b/lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR.vhd --- a/lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR.vhd +++ b/lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR.vhd @@ -30,7 +30,9 @@ use lpp.general_purpose.all; --TODO amliorer la gestion de la RAM et de la flexibilit du filtre entity IIR_CEL_CTRLR is -generic(Sample_SZ : integer := 16; +generic( + tech : integer := 0; + Sample_SZ : integer := 16; ChanelsCount : integer := 1; Coef_SZ : integer := 9; CoefCntPerCel: integer := 3; @@ -98,17 +100,18 @@ begin coefsConnectL0: for z in 0 to Cels_count-1 generate - coefsConnectL1: for y in 0 to CoefCntPerCel-1 generate + coefsConnectL1: for y in 0 to (CoefCntPerCel/2)-1 generate coefsConnectL2: for x in 0 to Coef_SZ-1 generate - CoefsReg.numCoefs(z)(y)(x) <= coefs(x + y*Coef_SZ + z*Coef_SZ*CoefCntPerCel); - CoefsReg.denCoefs(z)(y)(x) <= coefs(x + y*Coef_SZ + z*Coef_SZ*CoefCntPerCel); + CoefsReg.numCoefs(z)(y)(x) <= coefs(x + ((2*y))*Coef_SZ + z*Coef_SZ*CoefCntPerCel); + CoefsReg.denCoefs(z)(y)(x) <= coefs(x + ((2*y)+1)*Coef_SZ + z*Coef_SZ*CoefCntPerCel); end generate; end generate; end generate; + RAM_CTRLR2inst : RAM_CTRLR2 -generic map(Sample_SZ,Mem_use) +generic map(tech,Sample_SZ,Mem_use) port map( reset => reset, clk => clk, diff --git a/lib/lpp/dsp/iir_filter/IIR_CEL_FILTER.vhd b/lib/lpp/dsp/iir_filter/IIR_CEL_FILTER.vhd --- a/lib/lpp/dsp/iir_filter/IIR_CEL_FILTER.vhd +++ b/lib/lpp/dsp/iir_filter/IIR_CEL_FILTER.vhd @@ -29,7 +29,9 @@ use lpp.general_purpose.all; --TODO amliorer la gestion de la RAM et de la flexibilit du filtre entity IIR_CEL_FILTER is -generic(Sample_SZ : integer := 16; +generic( + tech : integer := 0; + Sample_SZ : integer := 16; ChanelsCount : integer := 1; Coef_SZ : integer := 9; CoefCntPerCel: integer := 3; @@ -43,7 +45,7 @@ port( regs_out : in out_IIR_CEL_reg; sample_in : in samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0); sample_out : out samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0); - coefs : in std_logic_vector(Coef_SZ*CoefCntPerCel*Cels_count-1 downto 0) + coefs : in std_logic_vector(Coef_SZ*CoefCntPerCel*Cels_count-1 downto 0) ); end IIR_CEL_FILTER; @@ -59,7 +61,7 @@ begin virg_pos <= to_integer(unsigned(regs_in.virgPos)); CTRLR : IIR_CEL_CTRLR -generic map (Sample_SZ,ChanelsCount,Coef_SZ,CoefCntPerCel,Cels_count,Mem_use) +generic map (tech,Sample_SZ,ChanelsCount,Coef_SZ,CoefCntPerCel,Cels_count,Mem_use) port map( reset => reset, clk => clk, diff --git a/lib/lpp/dsp/iir_filter/RAM_CTRLR2.vhd b/lib/lpp/dsp/iir_filter/RAM_CTRLR2.vhd --- a/lib/lpp/dsp/iir_filter/RAM_CTRLR2.vhd +++ b/lib/lpp/dsp/iir_filter/RAM_CTRLR2.vhd @@ -26,13 +26,17 @@ library lpp; use lpp.iir_filter.all; use lpp.FILTERcfg.all; use lpp.general_purpose.all; +library techmap; +use techmap.gencomp.all; --TODO amliorer la flexibilit de la config de la RAM. entity RAM_CTRLR2 is generic( + tech : integer := 0; Input_SZ_1 : integer := 16; Mem_use : integer := use_RAM + ); port( reset : in std_logic; @@ -52,9 +56,9 @@ end RAM_CTRLR2; architecture ar_RAM_CTRLR2 of RAM_CTRLR2 is -signal WD : std_logic_vector(35 downto 0); -signal WD_D : std_logic_vector(35 downto 0); -signal RD : std_logic_vector(35 downto 0); +signal WD : std_logic_vector(Input_SZ_1-1 downto 0); +signal WD_D : std_logic_vector(Input_SZ_1-1 downto 0); +signal RD : std_logic_vector(Input_SZ_1-1 downto 0); signal WEN, REN : std_logic; signal WADDR_back : std_logic_vector(7 downto 0); signal WADDR_back_D: std_logic_vector(7 downto 0); @@ -76,33 +80,37 @@ REN <= not read; --============================================================== --=========================R A M================================ --============================================================== -memRAM : if Mem_use = use_RAM generate -RAMblk :RAM - port map( - WD => WD_D, - RD => RD, - WEN => WEN, - REN => REN, - WADDR => WADDR, - RADDR => RADDR, - RWCLK => clk, - RESET => reset - ) ; -end generate; +--memRAM : if Mem_use = use_RAM generate +--RAMblk :RAM +-- port map( +-- WD => WD_D, +-- RD => RD, +-- WEN => WEN, +-- REN => REN, +-- WADDR => WADDR, +-- RADDR => RADDR, +-- RWCLK => clk, +-- RESET => reset +-- ) ; +--end generate; -memCEL : if Mem_use = use_CEL generate -RAMblk :RAM_CEL - port map( - WD => WD_D, - RD => RD, - WEN => WEN, - REN => REN, - WADDR => WADDR, - RADDR => RADDR, - RWCLK => clk, - RESET => reset - ) ; -end generate; +--memCEL : if Mem_use = use_CEL generate +--RAMblk :RAM_CEL +-- port map( +-- WD => WD_D, +-- RD => RD, +-- WEN => WEN, +-- REN => REN, +-- WADDR => WADDR, +-- RADDR => RADDR, +-- RWCLK => clk, +-- RESET => reset +-- ) ; +--end generate; + + SRAM : syncram_2p + generic map(tech,8,Input_SZ_1) + port map(clk,not REN,RADDR,RD,clk,not WEN,WADDR,WD_D); --============================================================== --============================================================== diff --git a/lib/lpp/dsp/iir_filter/iir_filter.vhd b/lib/lpp/dsp/iir_filter/iir_filter.vhd --- a/lib/lpp/dsp/iir_filter/iir_filter.vhd +++ b/lib/lpp/dsp/iir_filter/iir_filter.vhd @@ -73,6 +73,7 @@ end record; component APB_IIR_CEL is generic ( + tech : integer := 0; pindex : integer := 0; paddr : integer := 0; pmask : integer := 16#fff#; @@ -144,7 +145,9 @@ end component; component IIR_CEL_CTRLR is -generic(Sample_SZ : integer := 16; +generic( + tech : integer := 0; + Sample_SZ : integer := 16; ChanelsCount : integer := 1; Coef_SZ : integer := 9; CoefCntPerCel: integer := 3; @@ -181,7 +184,9 @@ component RAM_CEL is end component; component IIR_CEL_FILTER is -generic(Sample_SZ : integer := 16; +generic( + tech : integer := 0; + Sample_SZ : integer := 16; ChanelsCount : integer := 1; Coef_SZ : integer := 9; CoefCntPerCel: integer := 3; @@ -203,6 +208,7 @@ end component; component RAM_CTRLR2 is generic( + tech : integer := 0; Input_SZ_1 : integer := 16; Mem_use : integer := use_RAM ); diff --git a/lib/lpp/lpp_memory/APB_FIFO.vhd b/lib/lpp/lpp_memory/APB_FIFO.vhd deleted file mode 100644 --- a/lib/lpp/lpp_memory/APB_FIFO.vhd +++ /dev/null @@ -1,87 +0,0 @@ ------------------------------------------------------------------------------- --- This file is a part of the LPP VHDL IP LIBRARY --- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program; if not, write to the Free Software --- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ------------------------------------------------------------------------------- --- Author : Martin Morlot --- Mail : martin.morlot@lpp.polytechnique.fr ------------------------------------------------------------------------------- -library ieee; -use ieee.std_logic_1164.all; -library grlib; -use grlib.amba.all; -use grlib.stdlib.all; -use grlib.devices.all; -library lpp; -use lpp.lpp_amba.all; -use lpp.apb_devices_list.all; -use lpp.lpp_memory.all; - ---! Driver APB, va faire le lien entre l'IP VHDL de la FIFO et le bus Amba - -entity APB_FIFO is - generic ( - pindex : integer := 0; - paddr : integer := 0; - pmask : integer := 16#fff#; - pirq : integer := 0; - abits : integer := 8; - Data_sz : integer := 16; - Addr_sz : integer := 8; - addr_max_int : integer := 256); - port ( - clk : in std_logic; --! Horloge du composant - rst : in std_logic; --! Reset general du composant - apbi : in apb_slv_in_type; --! Registre de gestion des entrées du bus - Full : out std_logic; - Empty : out std_logic; - WR : out std_logic; - RE : out std_logic; - apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus - ); -end APB_FIFO; - - -architecture ar_APB_FIFO of APB_FIFO is - -signal ReadEnable : std_logic; -signal WriteEnable : std_logic; -signal FlagEmpty : std_logic; -signal FlagFull : std_logic; -signal ReUse : std_logic; -signal Lock : std_logic; -signal DataIn : std_logic_vector(Data_sz-1 downto 0); -signal DataOut : std_logic_vector(Data_sz-1 downto 0); -signal AddrIn : std_logic_vector(Addr_sz-1 downto 0); -signal AddrOut : std_logic_vector(Addr_sz-1 downto 0); - -begin - - APB : ApbDriver - generic map(pindex,paddr,pmask,pirq,abits,LPP_FIFO,Data_sz,Addr_sz,addr_max_int) - port map(clk,rst,ReadEnable,WriteEnable,FlagEmpty,FlagFull,ReUse,Lock,DataIn,DataOut,AddrIn,AddrOut,apbi,apbo); - - - DEVICE : Top_FIFO - generic map(Data_sz,Addr_sz,addr_max_int) - port map(clk,rst,ReadEnable,WriteEnable,ReUse,Lock,DataIn,AddrOut,AddrIn,FlagFull,FlagEmpty,DataOut); - -Empty <= FlagEmpty; -Full <= FlagFull; -WR <= WriteEnable; -RE <= ReadEnable; - -end ar_APB_FIFO; \ No newline at end of file diff --git a/lib/lpp/lpp_memory/APB_FifoRead.vhd b/lib/lpp/lpp_memory/APB_FifoRead.vhd deleted file mode 100644 --- a/lib/lpp/lpp_memory/APB_FifoRead.vhd +++ /dev/null @@ -1,86 +0,0 @@ ------------------------------------------------------------------------------- --- This file is a part of the LPP VHDL IP LIBRARY --- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program; if not, write to the Free Software --- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ------------------------------------------------------------------------------- --- Author : Martin Morlot --- Mail : martin.morlot@lpp.polytechnique.fr ------------------------------------------------------------------------------- -library ieee; -use ieee.std_logic_1164.all; -library grlib; -use grlib.amba.all; -use grlib.stdlib.all; -use grlib.devices.all; -library lpp; -use lpp.lpp_amba.all; -use lpp.apb_devices_list.all; -use lpp.lpp_memory.all; - ---! Driver APB, va faire le lien entre l'IP VHDL de la FIFO et le bus Amba - -entity APB_FifoRead is - generic ( - pindex : integer := 0; - paddr : integer := 0; - pmask : integer := 16#fff#; - pirq : integer := 0; - abits : integer := 8; - Data_sz : integer := 16; - Addr_sz : integer := 8; - addr_max_int : integer := 256); - port ( - clk : in std_logic; --! Horloge du composant - rst : in std_logic; --! Reset general du composant - apbi : in apb_slv_in_type; --! Registre de gestion des entrées du bus - WriteEnable : in std_logic; --! Demande d'écriture dans la mémoire, géré hors de l'IP - Full : out std_logic; --! Flag, Memoire pleine - Empty : out std_logic; --! Flag, Memoire vide - DATA : in std_logic_vector(Data_sz-1 downto 0); --! Données en entrée de la mémoire - apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus - ); -end APB_FifoRead; - ---! @details Gestion de la FIFO, écriture via le bus APB, lecture interne au FPGA - -architecture ar_APB_FifoRead of APB_FifoRead is - -signal Low : std_logic:='0'; -signal ReadEnable : std_logic; -signal FlagEmpty : std_logic; -signal FlagFull : std_logic; -signal ReUse : std_logic; -signal Lock : std_logic; -signal DataIn : std_logic_vector(Data_sz-1 downto 0); -signal DataOut : std_logic_vector(Data_sz-1 downto 0); -signal AddrIn : std_logic_vector(Addr_sz-1 downto 0); -signal AddrOut : std_logic_vector(Addr_sz-1 downto 0); - -begin - - APB : ApbDriver - generic map(pindex,paddr,pmask,pirq,abits,LPP_FIFO,Data_sz,Addr_sz,addr_max_int) - port map(clk,rst,ReadEnable,Low,FlagEmpty,FlagFull,ReUse,Lock,DataIn,DataOut,AddrIn,AddrOut,apbi,apbo); - - - FIFO : Top_FIFO - generic map(Data_sz,Addr_sz,addr_max_int) - port map(clk,rst,ReadEnable,WriteEnable,ReUse,Lock,DATA,AddrOut,AddrIn,FlagFull,FlagEmpty,DataOut); - -Empty <= FlagEmpty; -Full <= FlagFull; - -end ar_APB_FifoRead; \ No newline at end of file diff --git a/lib/lpp/lpp_memory/APB_FifoWrite.vhd b/lib/lpp/lpp_memory/APB_FifoWrite.vhd deleted file mode 100644 --- a/lib/lpp/lpp_memory/APB_FifoWrite.vhd +++ /dev/null @@ -1,87 +0,0 @@ ------------------------------------------------------------------------------- --- This file is a part of the LPP VHDL IP LIBRARY --- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program; if not, write to the Free Software --- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ------------------------------------------------------------------------------- --- Author : Martin Morlot --- Mail : martin.morlot@lpp.polytechnique.fr ------------------------------------------------------------------------------- -library ieee; -use ieee.std_logic_1164.all; -library grlib; -use grlib.amba.all; -use grlib.stdlib.all; -use grlib.devices.all; -library lpp; -use lpp.lpp_amba.all; -use lpp.apb_devices_list.all; -use lpp.lpp_memory.all; - ---! Driver APB, va faire le lien entre l'IP VHDL de la FIFO et le bus Amba - -entity APB_FifoWrite is - generic ( - pindex : integer := 0; - paddr : integer := 0; - pmask : integer := 16#fff#; - pirq : integer := 0; - abits : integer := 8; - Data_sz : integer := 16; - Addr_sz : integer := 8; - addr_max_int : integer := 256); - port ( - clk : in std_logic; --! Horloge du composant - rst : in std_logic; --! Reset general du composant - apbi : in apb_slv_in_type; --! Registre de gestion des entrées du bus - ReadEnable : in std_logic; --! Demande de lecture de la mémoire, géré hors de l'IP - Empty : out std_logic; --! Flag, Memoire vide - Full : out std_logic; --! Flag, Memoire pleine - DATA : out std_logic_vector(Data_sz-1 downto 0); --! Données en sortie de la mémoire - apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus - ); -end APB_FifoWrite; - ---! @details Gestion de la FIFO, écriture via le bus APB, lecture interne au FPGA - -architecture ar_APB_FifoWrite of APB_FifoWrite is - -signal Low : std_logic:='0'; -signal WriteEnable : std_logic; -signal FlagEmpty : std_logic; -signal FlagFull : std_logic; -signal ReUse : std_logic; -signal Lock : std_logic; -signal DataIn : std_logic_vector(Data_sz-1 downto 0); -signal DataOut : std_logic_vector(Data_sz-1 downto 0); -signal AddrIn : std_logic_vector(Addr_sz-1 downto 0); -signal AddrOut : std_logic_vector(Addr_sz-1 downto 0); - -begin - - APB : ApbDriver - generic map(pindex,paddr,pmask,pirq,abits,LPP_FIFO,Data_sz,Addr_sz,addr_max_int) - port map(clk,rst,Low,WriteEnable,FlagEmpty,FlagFull,ReUse,Lock,DataIn,DataOut,AddrIn,AddrOut,apbi,apbo); - - - FIFO : Top_FIFO - generic map(Data_sz,Addr_sz,addr_max_int) - port map(clk,rst,ReadEnable,WriteEnable,ReUse,Lock,DataIn,AddrOut,AddrIn,FlagFull,FlagEmpty,DataOut); - -DATA <= DataOut; -Empty <= FlagEmpty; -Full <= FlagFull; - -end ar_APB_FifoWrite; \ No newline at end of file diff --git a/lib/lpp/lpp_memory/ApbDriver.vhd b/lib/lpp/lpp_memory/ApbDriver.vhd deleted file mode 100644 --- a/lib/lpp/lpp_memory/ApbDriver.vhd +++ /dev/null @@ -1,165 +0,0 @@ ------------------------------------------------------------------------------- --- This file is a part of the LPP VHDL IP LIBRARY --- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program; if not, write to the Free Software --- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ------------------------------------------------------------------------------- --- Author : Martin Morlot --- Mail : martin.morlot@lpp.polytechnique.fr ------------------------------------------------------------------------------- -library ieee; -use ieee.std_logic_1164.all; -library grlib; -use grlib.amba.all; -use grlib.stdlib.all; -use grlib.devices.all; -library lpp; -use lpp.lpp_amba.all; -use lpp.apb_devices_list.all; - ---! Driver APB "Générique" qui va faire le lien entre le bus Amba et la FIFO - -entity ApbDriver is - generic ( - pindex : integer := 0; - paddr : integer := 0; - pmask : integer := 16#fff#; - pirq : integer := 0; - abits : integer := 8; - LPP_DEVICE : integer; - Data_sz : integer := 16; - Addr_sz : integer := 8; - addr_max_int : integer := 256); - port ( - clk : in std_logic; --! Horloge du composant - rst : in std_logic; --! Reset general du composant - ReadEnable : out std_logic; --! Instruction de lecture en mémoire - WriteEnable : out std_logic; --! Instruction d'écriture en mémoire - FlagEmpty : in std_logic; --! Flag, Mémoire vide - FlagFull : in std_logic; --! Flag, Mémoire pleine - ReUse : out std_logic; --! Flag, Permet de relire la mémoire du début - Lock : out std_logic; --! Flag, Permet de bloquer l'écriture dans la mémoire - DataIn : out std_logic_vector(Data_sz-1 downto 0); --! Registre de données en entrée - DataOut : in std_logic_vector(Data_sz-1 downto 0); --! Registre de données en sortie - AddrIn : in std_logic_vector(Addr_sz-1 downto 0); --! Registre d'addresse (écriture) - AddrOut : in std_logic_vector(Addr_sz-1 downto 0); --! Registre d'addresse (lecture) - apbi : in apb_slv_in_type; --! Registre de gestion des entrées du bus - apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus - ); -end ApbDriver; - ---! @details Utilisable avec n'importe quelle IP VHDL de type FIFO - -architecture ar_ApbDriver of ApbDriver is - -constant REVISION : integer := 1; - -constant pconfig : apb_config_type := ( - 0 => ahb_device_reg (VENDOR_LPP, LPP_DEVICE, 0, REVISION, 0), - 1 => apb_iobar(paddr, pmask)); - -type DEVICE_ctrlr_Reg is record - DEVICE_Cfg : std_logic_vector(5 downto 0); - DEVICE_DataW : std_logic_vector(Data_sz-1 downto 0); - DEVICE_DataR : std_logic_vector(Data_sz-1 downto 0); - DEVICE_AddrW : std_logic_vector(Addr_sz-1 downto 0); - DEVICE_AddrR : std_logic_vector(Addr_sz-1 downto 0); -end record; - -signal Rec : DEVICE_ctrlr_Reg; -signal Rdata : std_logic_vector(31 downto 0); - -signal FlagRE : std_logic; -signal FlagWR : std_logic; - -begin - -Rec.DEVICE_Cfg(0) <= FlagRE; -Rec.DEVICE_Cfg(1) <= FlagWR; -Rec.DEVICE_Cfg(2) <= FlagEmpty; -Rec.DEVICE_Cfg(3) <= FlagFull; -ReUse <= Rec.DEVICE_Cfg(4); -Lock <= Rec.DEVICE_Cfg(5); - -DataIn <= Rec.DEVICE_DataW; -Rec.DEVICE_DataR <= DataOut; -Rec.DEVICE_AddrW <= AddrIn; -Rec.DEVICE_AddrR <= AddrOut; - - - - process(rst,clk) - begin - if(rst='0')then - Rec.DEVICE_DataW <= (others => '0'); - FlagWR <= '0'; - FlagRE <= '0'; - Rec.DEVICE_Cfg(4) <= '0'; - Rec.DEVICE_Cfg(5) <= '0'; - - elsif(clk'event and clk='1')then - - --APB Write OP - if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then - case apbi.paddr(abits-1 downto 2) is - when "000000" => - FlagWR <= '1'; - Rec.DEVICE_DataW <= apbi.pwdata(Data_sz-1 downto 0); - when "000010" => - Rec.DEVICE_Cfg(4) <= apbi.pwdata(16); - Rec.DEVICE_Cfg(5) <= apbi.pwdata(20); - when others => - null; - end case; - else - FlagWR <= '0'; - end if; - - --APB Read OP - if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then - case apbi.paddr(abits-1 downto 2) is - when "000000" => - FlagRE <= '1'; - Rdata(Data_sz-1 downto 0) <= Rec.DEVICE_DataR; - when "000001" => - Rdata(31 downto 8) <= X"AAAAAA"; - Rdata(7 downto 0) <= Rec.DEVICE_AddrR; - when "000101" => - Rdata(31 downto 8) <= X"AAAAAA"; - Rdata(7 downto 0) <= Rec.DEVICE_AddrW; - when "000010" => - Rdata(3 downto 0) <= "000" & Rec.DEVICE_Cfg(0); - Rdata(7 downto 4) <= "000" & Rec.DEVICE_Cfg(1); - Rdata(11 downto 8) <= "000" & Rec.DEVICE_Cfg(2); - Rdata(15 downto 12) <= "000" & Rec.DEVICE_Cfg(3); - Rdata(19 downto 16) <= "000" & Rec.DEVICE_Cfg(4); - Rdata(23 downto 20) <= "000" & Rec.DEVICE_Cfg(5); - Rdata(31 downto 24) <= X"CC"; - when others => - Rdata <= (others => '0'); - end case; - else - FlagRE <= '0'; - end if; - - end if; - apbo.pconfig <= pconfig; - end process; - -apbo.prdata <= Rdata when apbi.penable = '1'; -WriteEnable <= FlagWR; -ReadEnable <= FlagRE; - -end ar_ApbDriver; \ No newline at end of file diff --git a/lib/lpp/lpp_memory/ApbFifoDriverV.vhd b/lib/lpp/lpp_memory/ApbFifoDriverV.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/lpp_memory/ApbFifoDriverV.vhd @@ -0,0 +1,186 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------ +-- Author : Alexis Jeandet +-- Mail : alexis.jeandet@lpp.polytechnique.fr +------------------------------------------------------------------------------ +library ieee; +use ieee.std_logic_1164.all; +library grlib; +use grlib.amba.all; +use grlib.stdlib.all; +use grlib.devices.all; +library lpp; +use lpp.lpp_amba.all; +use lpp.apb_devices_list.all; + +--! Driver APB "Générique" qui va faire le lien entre le bus Amba et la FIFO + +entity ApbFifoDriverV is + generic ( + pindex : integer := 0; + paddr : integer := 0; + pmask : integer := 16#fff#; + pirq : integer := 0; + abits : integer := 8; + LPP_DEVICE : integer; + FifoCnt : integer := 1; + Data_sz : integer := 16; + Addr_sz : integer := 8; + addr_max_int : integer := 256); + port ( + clk : in std_logic; --! Horloge du composant + rst : in std_logic; --! Reset general du composant + ReadEnable : out std_logic_vector(FifoCnt-1 downto 0); --! Instruction de lecture en mémoire + WriteEnable : out std_logic_vector(FifoCnt-1 downto 0); --! Instruction d'écriture en mémoire + FlagEmpty : in std_logic_vector(FifoCnt-1 downto 0); --! Flag, Mémoire vide + FlagFull : in std_logic_vector(FifoCnt-1 downto 0); --! Flag, Mémoire pleine + ReUse : out std_logic_vector(FifoCnt-1 downto 0); --! Flag, Permet de relire la mémoire du début + Lock : out std_logic_vector(FifoCnt-1 downto 0); --! Flag, Permet de bloquer l'écriture dans la mémoire + DataIn : out std_logic_vector((FifoCnt*Data_sz)-1 downto 0); --! Registre de données en entrée + DataOut : in std_logic_vector((FifoCnt*Data_sz)-1 downto 0); --! Registre de données en sortie + AddrIn : in std_logic_vector((FifoCnt*Addr_sz)-1 downto 0); --! Registre d'addresse (écriture) + AddrOut : in std_logic_vector((FifoCnt*Addr_sz)-1 downto 0); --! Registre d'addresse (lecture) + apbi : in apb_slv_in_type; --! Registre de gestion des entrées du bus + apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus + ); +end ApbFifoDriverV; + +--! @details Utilisable avec n'importe quelle IP VHDL de type FIFO + +architecture ar_ApbFifoDriverV of ApbFifoDriverV is + +constant REVISION : integer := 1; + +constant pconfig : apb_config_type := ( + 0 => ahb_device_reg (VENDOR_LPP, LPP_DEVICE, 0, REVISION, 0), + 1 => apb_iobar(paddr, pmask)); + +type DEVICE_ctrlr_Reg is record + DEVICE_Cfg : std_logic_vector(5 downto 0); + DEVICE_DataW : std_logic_vector(Data_sz-1 downto 0); + DEVICE_DataR : std_logic_vector(Data_sz-1 downto 0); + DEVICE_AddrW : std_logic_vector(Addr_sz-1 downto 0); + DEVICE_AddrR : std_logic_vector(Addr_sz-1 downto 0); +end record; + +type DEVICE_ctrlr_RegV is array(FifoCnt-1 downto 0) of DEVICE_ctrlr_Reg; + +signal Rec : DEVICE_ctrlr_RegV; +signal Rdata : std_logic_vector(31 downto 0); + +signal FlagRE : std_logic; +signal FlagWR : std_logic; + +begin + +fifoflags: for i in 0 to FifoCnt-1 generate: + + Rec(i).DEVICE_Cfg(0) <= FlagRE(i); + Rec(i).DEVICE_Cfg(1) <= FlagWR(i); + Rec(i).DEVICE_Cfg(2) <= FlagEmpty(i); + Rec(i).DEVICE_Cfg(3) <= FlagFull(i); + + ReUse(i) <= Rec(i).DEVICE_Cfg(4); + Lock(i) <= Rec(i).DEVICE_Cfg(5); + + DataIn(i*(Data_sz-1 downto 0)) <= Rec(i).DEVICE_DataW; + + Rec(i).DEVICE_DataR <= DataOut(i*(Data_sz-1 downto 0)); + Rec(i).DEVICE_AddrW <= AddrIn(i*(Addr_sz-1 downto 0)); + Rec(i).DEVICE_AddrR <= AddrOut(i*(Addr_sz-1 downto 0)); + + WriteEnable(i) <= FlagWR(i); + ReadEnable(i) <= FlagRE(i); + +end generate; + + + process(rst,clk) + begin + if(rst='0')then + Rec.DEVICE_DataW <= (others => '0'); + FlagWR <= '0'; + FlagRE <= '0'; + Rec.DEVICE_Cfg(4) <= '0'; + Rec.DEVICE_Cfg(5) <= '0'; + + elsif(clk'event and clk='1')then + + --APB Write OP + if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then + case apbi.paddr(abits-1 downto 2) is + when "000000" => + FlagWR <= '1'; + Rec.DEVICE_DataW <= apbi.pwdata(Data_sz-1 downto 0); + when "000010" => + Rec.DEVICE_Cfg(4) <= apbi.pwdata(16); + Rec.DEVICE_Cfg(5) <= apbi.pwdata(20); + when others => + null; + end case; + else + FlagWR <= (others => '0'); + end if; + + --APB Read OP + if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then + case apbi.paddr(abits-1 downto 2) is + for i in 0 to FifoCnt-1 loop + if conv_integer(apbi.paddr(7 downto 3)) = i then + case apbi.paddr(2 downto 2) is + when "0" => + CoefsReg.numCoefs(i)(0) <= (apbi.pwdata(Coef_SZ-1 downto 0)); + when "1" => + CoefsReg.numCoefs(i)(1) <= (apbi.pwdata(Coef_SZ-1 downto 0)); + when others => + end case; + end if; + end loop; + when "000000" => + FlagRE <= '1'; + Rdata(Data_sz-1 downto 0) <= Rec.DEVICE_DataR; + when "000001" => + Rdata(31 downto 8) <= X"AAAAAA"; + Rdata(7 downto 0) <= Rec.DEVICE_AddrR; + when "000101" => + Rdata(31 downto 8) <= X"AAAAAA"; + Rdata(7 downto 0) <= Rec.DEVICE_AddrW; + when "000010" => + Rdata(3 downto 0) <= "000" & Rec.DEVICE_Cfg(0); + Rdata(7 downto 4) <= "000" & Rec.DEVICE_Cfg(1); + Rdata(11 downto 8) <= "000" & Rec.DEVICE_Cfg(2); + Rdata(15 downto 12) <= "000" & Rec.DEVICE_Cfg(3); + Rdata(19 downto 16) <= "000" & Rec.DEVICE_Cfg(4); + Rdata(23 downto 20) <= "000" & Rec.DEVICE_Cfg(5); + Rdata(31 downto 24) <= X"CC"; + when others => + Rdata <= (others => '0'); + end case; + else + FlagRE <= (others => '0'); + end if; + + end if; + apbo.pconfig <= pconfig; + end process; + +apbo.prdata <= Rdata when apbi.penable = '1'; + + +end ar_ApbFifoDriverV; \ No newline at end of file diff --git a/lib/lpp/lpp_memory/Fifo_Read.vhd b/lib/lpp/lpp_memory/Fifo_Read.vhd deleted file mode 100644 --- a/lib/lpp/lpp_memory/Fifo_Read.vhd +++ /dev/null @@ -1,93 +0,0 @@ ------------------------------------------------------------------------------- --- This file is a part of the LPP VHDL IP LIBRARY --- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program; if not, write to the Free Software --- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ------------------------------------------------------------------------------- --- Author : Martin Morlot --- Mail : martin.morlot@lpp.polytechnique.fr ------------------------------------------------------------------------------- -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - ---! Programme de la FIFO de lecture - -entity Fifo_Read is -generic( - Addr_sz : integer := 8; - addr_max_int : integer := 256); -port( - clk,raz : in std_logic; --! Horloge et reset general du composant - flag_RE : in std_logic; --! Flag, Demande la lecture de la mémoire - ReUse : in std_logic; --! Flag, Permet de relire la mémoire du début - Waddr : in std_logic_vector(addr_sz-1 downto 0); --! Adresse du registre d'écriture dans la mémoire - empty : out std_logic; --! Flag, Mémoire vide - Raddr : out std_logic_vector(addr_sz-1 downto 0) --! Adresse du registre de lecture de la mémoire - ); -end Fifo_Read; - ---! @details En aval de la SRAM Gaisler - -architecture ar_Fifo_Read of Fifo_Read is - -signal Rad_int : integer range 0 to addr_max_int; -signal Rad_int_reg : integer range 0 to addr_max_int; -signal Wad_int : integer range 0 to addr_max_int; -signal Wad_int_reg : integer range 0 to addr_max_int; -signal flag_reg : std_logic; - -begin - process (clk,raz) - begin - if(raz='0')then - Rad_int <= 0; - empty <= '1'; - - elsif(clk' event and clk='1')then - Wad_int_reg <= Wad_int; - Rad_int_reg <= Rad_int; - flag_reg <= flag_RE; - - - if(flag_reg ='0' and flag_RE='1')then - if(Rad_int=addr_max_int-1)then - Rad_int <= 0; - else - Rad_int <= Rad_int+1; - end if; - end if; - - if(ReUse='1')then - empty <= '0'; - else - if(Rad_int_reg /= Rad_int)then - if(Rad_int=Wad_int)then - empty <= '1'; - else - empty <= '0'; - end if; - elsif(Wad_int_reg /= Wad_int)then - empty <= '0'; - end if; - end if; - - end if; - end process; - -Wad_int <= to_integer(unsigned(Waddr)); -Raddr <= std_logic_vector(to_unsigned(Rad_int,addr_sz)); - -end ar_Fifo_Read; \ No newline at end of file diff --git a/lib/lpp/lpp_memory/Fifo_Write.vhd b/lib/lpp/lpp_memory/Fifo_Write.vhd deleted file mode 100644 --- a/lib/lpp/lpp_memory/Fifo_Write.vhd +++ /dev/null @@ -1,86 +0,0 @@ ------------------------------------------------------------------------------- --- This file is a part of the LPP VHDL IP LIBRARY --- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program; if not, write to the Free Software --- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ------------------------------------------------------------------------------- --- Author : Martin Morlot --- Mail : martin.morlot@lpp.polytechnique.fr ------------------------------------------------------------------------------- -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - ---! Programme de la FIFO d'écriture - -entity Fifo_Write is -generic( - Addr_sz : integer := 8; - addr_max_int : integer := 256); -port( - clk,raz : in std_logic; --! Horloge et reset general du composant - flag_WR : in std_logic; --! Flag, Demande l'écriture dans la mémoire - Raddr : in std_logic_vector(addr_sz-1 downto 0); --! Adresse du registre de lecture de la mémoire - full : out std_logic; --! Flag, Mémoire pleine - Waddr : out std_logic_vector(addr_sz-1 downto 0) --! Adresse du registre d'écriture dans la mémoire - ); -end Fifo_Write; - ---! @details En amont de la SRAM Gaisler - -architecture ar_Fifo_Write of Fifo_Write is - -signal Wad_int : integer range 0 to addr_max_int; -signal Wad_int_reg : integer range 0 to addr_max_int; -signal Rad_int : integer range 0 to addr_max_int; -signal Rad_int_reg : integer range 0 to addr_max_int; - -begin - process (clk,raz) - begin - if(raz='0')then - Wad_int <= 0; - full <= '0'; - - elsif(clk' event and clk='1')then - Wad_int_reg <= Wad_int; - Rad_int_reg <= Rad_int; - - - if(flag_WR='1')then - if(Wad_int=addr_max_int-1)then - Wad_int <= 0; - else - Wad_int <= Wad_int+1; - end if; - end if; - - if(Wad_int_reg /= Wad_int)then - if(Wad_int=Rad_int)then - full <= '1'; - else - full <= '0'; - end if; - elsif(Rad_int_reg /= Rad_int)then - full <= '0'; - end if; - - end if; - end process; - -Rad_int <= to_integer(unsigned(Raddr)); -Waddr <= std_logic_vector(to_unsigned(Wad_int,addr_sz)); - -end ar_Fifo_Write; \ No newline at end of file diff --git a/lib/lpp/lpp_memory/Link_Reg.vhd b/lib/lpp/lpp_memory/Link_Reg.vhd deleted file mode 100644 --- a/lib/lpp/lpp_memory/Link_Reg.vhd +++ /dev/null @@ -1,106 +0,0 @@ ------------------------------------------------------------------------------- --- This file is a part of the LPP VHDL IP LIBRARY --- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program; if not, write to the Free Software --- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ------------------------------------------------------------------------------- --- Author : Martin Morlot --- Mail : martin.morlot@lpp.polytechnique.fr ------------------------------------------------------------------------------- -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; -use work.FIFO_Config.all; - ---! Programme qui va permettre de "pipeliner" la FIFO, donnée disponible en sortie dé son écriture en entrée de la FIFO - -entity Link_Reg is -generic(Data_sz : integer := 16); -port( - clk,raz : in std_logic; --! Horloge et reset general du composant - Data_one : in std_logic_vector(Data_sz-1 downto 0); --! Donnée en entrée de la FIFO, coté écriture - Data_two : in std_logic_vector(Data_sz-1 downto 0); --! Donnée en sortie de la FIFO, coté lecture - ReUse : in std_logic; --! Flag, Permet de relire la mémoire du début - flag_RE : in std_logic; --! Flag, Demande la lecture de la mémoire - flag_WR : in std_logic; --! Flag, Demande l'écriture dans la mémoire - empty : in std_logic; --! Flag, Mémoire vide - Data_out : out std_logic_vector(Data_sz-1 downto 0) --! Donnée en sortie, pipelinée - ); -end Link_Reg; - -architecture ar_Link_Reg of Link_Reg is - -type etat is (e0,e1,e2,e3); -signal ect : etat; - -begin - process (clk,raz) - begin - if(raz='0')then - Data_out <= (others => 'X'); - ect <= e0; - - elsif(clk' event and clk='1')then - case ect is - when e0 => - if(flag_WR='1')then - Data_out <= Data_one; - ect <= e1; - elsif(ReUse='1')then - ect <= e1; - end if; - - when e1 => - if(flag_RE='1')then - Data_out <= Data_two; - ect <= e2; - end if; - - when e2 => - if(empty='1')then - ect <= e3; - else - Data_out <= Data_two; - ect <= e2; - end if; - - when e3 => - Data_out <= Data_two; - ect <= e0; - - end case; - end if; - end process; - -end ar_Link_Reg; - - - - - - - - - - - - - - - - - - - diff --git a/lib/lpp/lpp_memory/Top_FIFO.vhd b/lib/lpp/lpp_memory/Top_FIFO.vhd deleted file mode 100644 --- a/lib/lpp/lpp_memory/Top_FIFO.vhd +++ /dev/null @@ -1,135 +0,0 @@ ------------------------------------------------------------------------------- --- This file is a part of the LPP VHDL IP LIBRARY --- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program; if not, write to the Free Software --- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ------------------------------------------------------------------------------- --- Author : Martin Morlot --- Mail : martin.morlot@lpp.polytechnique.fr ------------------------------------------------------------------------------- -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; -library techmap; -use techmap.gencomp.all; -use work.config.all; -use lpp.lpp_memory.all; - ---! Programme de la FIFO - -entity Top_FIFO is - generic( - Data_sz : integer := 16; - Addr_sz : integer := 8; - addr_max_int : integer := 256 - ); - port( - clk,raz : in std_logic; --! Horloge et reset general du composant - flag_RE : in std_logic; --! Flag, Demande la lecture de la mémoire - flag_WR : in std_logic; --! Flag, Demande l'écriture dans la mémoire - ReUse : in std_logic; --! Flag, Permet de relire la mémoire du début - Lock : in std_logic; --! Permet de bloquer l'écriture dans la mémoire - Data_in : in std_logic_vector(Data_sz-1 downto 0); --! Data en entrée du composant - Addr_RE : out std_logic_vector(addr_sz-1 downto 0); --! Adresse d'écriture - Addr_WR : out std_logic_vector(addr_sz-1 downto 0); --! Adresse de lecture - full : out std_logic; --! Flag, Mémoire pleine - empty : out std_logic; --! Flag, Mémoire vide - Data_out : out std_logic_vector(Data_sz-1 downto 0) --! Data en sortie du composant - ); -end Top_FIFO; - ---! @details Une mémoire SRAM de chez Gaisler est utilisée, ---! associée a deux Drivers, un pour écrire l'autre pour lire cette mémoire - -architecture ar_Top_FIFO of Top_FIFO is - -component syncram_2p - generic (tech : integer := 0; abits : integer := 6; dbits : integer := 8; sepclk : integer := 0); - port ( - rclk : in std_ulogic; - renable : in std_ulogic; - raddress : in std_logic_vector((abits -1) downto 0); - dataout : out std_logic_vector((dbits -1) downto 0); - wclk : in std_ulogic; - write : in std_ulogic; - waddress : in std_logic_vector((abits -1) downto 0); - datain : in std_logic_vector((dbits -1) downto 0)); -end component; - -signal Raddr : std_logic_vector(addr_sz-1 downto 0); -signal Waddr : std_logic_vector(addr_sz-1 downto 0); ---signal Data_int : std_logic_vector(Data_sz-1 downto 0); -signal s_empty : std_logic; -signal s_full : std_logic; -signal s_full2 : std_logic; -signal s_flag_RE : std_logic; -signal s_flag_WR : std_logic; - -begin - - WR : Fifo_Write - generic map(Addr_sz,addr_max_int) - port map(clk,raz,s_flag_WR,Raddr,s_full,Waddr); - - - SRAM : syncram_2p - generic map(CFG_MEMTECH,Addr_sz,Data_sz) - port map(clk,s_flag_RE,Raddr,Data_out,clk,s_flag_WR,Waddr,Data_in); - - --- link : Link_Reg --- generic map(Data_sz) --- port map(clk,raz,Data_in,Data_int,ReUse,s_flag_RE,s_flag_WR,s_empty,Data_out); - - - RE : Fifo_Read - generic map(Addr_sz,addr_max_int) - port map(clk,raz,s_flag_RE,ReUse,Waddr,s_empty,Raddr); - - process(clk,raz) - begin - if(raz='0')then - s_flag_RE <= '0'; - s_flag_WR <= '0'; - s_full2 <= s_full; - - elsif(clk'event and clk='1')then - if(s_full2='0')then - s_flag_WR <= Flag_WR; - else - s_flag_WR <= '0'; - end if; - - if(s_empty='0')then - s_flag_RE <= Flag_RE; - else - s_flag_RE <= '0'; - end if; - - if(Lock='1')then - s_full2 <= '1'; - else - s_full2 <= s_full; - end if; - - end if; - end process; - -full <= s_full2; -empty <= s_empty; -Addr_RE <= Raddr; -Addr_WR <= Waddr; - -end ar_Top_FIFO; \ No newline at end of file diff --git a/lib/lpp/lpp_memory/lpp_FIFO.vhd b/lib/lpp/lpp_memory/lpp_FIFO.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/lpp_memory/lpp_FIFO.vhd @@ -0,0 +1,193 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------ +-- Author : Martin Morlot +-- Mail : martin.morlot@lpp.polytechnique.fr +------------------------------------------------------------------------------ +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +library lpp; +use lpp.lpp_memory.all; + +entity lpp_fifo is +generic( + tech : integer := 0; + DataSz : integer range 1 to 32 := 8; + abits : integer range 2 to 12 := 8 + ); +port( + rstn : in std_logic; + rclk : in std_logic; + ren : in std_logic; + rdata : out std_logic_vector(DataSz-1 downto 0); + empty : out std_logic; + raddr : out std_logic_vector(abits-1 downto 0); + wclk : in std_logic; + wen : in std_logic; + wdata : in std_logic_vector(DataSz-1 downto 0); + full : out std_logic; + waddr : out std_logic_vector(abits-1 downto 0) +); +end entity; + + +architecture ar_lpp_fifo of lpp_fifo is + +signal sFull : std_logic:='0'; +signal sEmpty : std_logic:='1'; +signal sREN : std_logic:='0'; +signal sWEN : std_logic:='0'; + +signal Waddr_vect_d : std_logic_vector(abits-1 downto 0):=(others =>'0'); +signal Raddr_vect_d : std_logic_vector(abits-1 downto 0); +signal Waddr_vect : std_logic_vector(abits-1 downto 0):=(others =>'0'); +signal Raddr_vect : std_logic_vector(abits-1 downto 0):=(others =>'0'); + +type etat is (e0,e1,e2); +signal rect : etat; +signal wect : etat; + +begin + +SRAM : syncram_2p +generic map(tech,abits,DataSz) +port map(RCLK,sREN,Raddr_vect,rdata,WCLK,sWEN,Waddr_vect,wdata); + +--RAM0: entity work.RAM_CEL +-- generic map(abits, DataSz) +-- port map(wdata, rdata, sWEN, sREN, Waddr_vect, Raddr_vect, RCLK, WCLK, rstn); + +--============================= +-- Read section +--============================= +sREN <= not REN when (rect=e0) else '0'; +process (rclk,rstn) +begin + if(rstn='0')then + rect <= e2; + sempty <= '1'; + Raddr_vect <= (others =>'0'); + Raddr_vect_d <= (others =>'1'); + + elsif(rclk'event and rclk='1')then + if(sREN='1') then + Raddr_vect <= std_logic_vector(unsigned(Raddr_vect) + 1); + Raddr_vect_d <= Raddr_vect; + end if; + + case rect is + when e0 => + sempty <= '0'; + if(Raddr_vect=Waddr_vect_d)then + rect <= e1; + sempty <= '1'; + end if; + + when e1 => + if(Waddr_vect_d=Raddr_vect_d)then + rect <= e2; + else + rect <= e0; + end if; + + when e2 => + if(Waddr_vect_d/=Raddr_vect_d)then + rect <= e0; + end if; + + end case; + end if; +end process; + + +--============================= +-- Write section +--============================= +sWEN <= not WEN when (wect=e0) else '0'; +process (wclk,rstn) +begin + if(rstn='0')then + wect <= e0; + sfull <= '0'; + Waddr_vect <= (others =>'0'); + Waddr_vect_d <= (others =>'1'); + + elsif(wclk'event and wclk='1')then + if(sWEN='1') then + Waddr_vect <= std_logic_vector(unsigned(Waddr_vect) +1); + Waddr_vect_d <= Waddr_vect; + end if; + + case wect is + when e0 => + sfull <= '0'; + if(Waddr_vect=Raddr_vect_d)then + wect <= e1; + sfull <= '1'; + end if; + + when e1 => + if(Waddr_vect_d=Raddr_vect_d)then + wect <= e2; + else + wect <= e0; + end if; + + when e2 => + if(Waddr_vect_d/=Raddr_vect_d)then + wect <= e0; + end if; + + end case; + end if; +end process; + + +full <= sFull; +empty <= sEmpty; +waddr <= Waddr_vect; +raddr <= Raddr_vect; + +end architecture; + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/lib/lpp/lpp_memory/lpp_memory.vhd b/lib/lpp/lpp_memory/lpp_memory.vhd --- a/lib/lpp/lpp_memory/lpp_memory.vhd +++ b/lib/lpp/lpp_memory/lpp_memory.vhd @@ -34,222 +34,27 @@ use gaisler.memctrl.all; package lpp_memory is ---===========================================================| ---=================== FIFO Complète =========================| ---===========================================================| - -component APB_FIFO is - generic ( - pindex : integer := 0; - paddr : integer := 0; - pmask : integer := 16#fff#; - pirq : integer := 0; - abits : integer := 8; - Data_sz : integer := 16; - Addr_sz : integer := 8; - addr_max_int : integer := 256); - port ( - clk : in std_logic; - rst : in std_logic; - apbi : in apb_slv_in_type; - Full : out std_logic; - Empty : out std_logic; - WR : out std_logic; - RE : out std_logic; - apbo : out apb_slv_out_type - ); -end component; - - -component ApbDriver is - generic ( - pindex : integer := 0; - paddr : integer := 0; - pmask : integer := 16#fff#; - pirq : integer := 0; - abits : integer := 8; - LPP_DEVICE : integer; - Data_sz : integer := 16; - Addr_sz : integer := 8; - addr_max_int : integer := 256); - port ( - clk : in std_logic; - rst : in std_logic; - ReadEnable : out std_logic; - WriteEnable : out std_logic; - FlagEmpty : in std_logic; - FlagFull : in std_logic; - ReUse : out std_logic; - Lock : out std_logic; - DataIn : out std_logic_vector(Data_sz-1 downto 0); - DataOut : in std_logic_vector(Data_sz-1 downto 0); - AddrIn : in std_logic_vector(Addr_sz-1 downto 0); - AddrOut : in std_logic_vector(Addr_sz-1 downto 0); - apbi : in apb_slv_in_type; - apbo : out apb_slv_out_type +component lpp_fifo is +generic( + tech : integer := 0; + DataSz : integer range 1 to 32 := 8; + abits : integer range 2 to 12 := 8 ); -end component; - - -component Top_FIFO is - generic( - Data_sz : integer := 16; - Addr_sz : integer := 8; - addr_max_int : integer := 256 - ); - port( - clk,raz : in std_logic; - flag_RE : in std_logic; - flag_WR : in std_logic; - ReUse : in std_logic; - Lock : in std_logic; - Data_in : in std_logic_vector(Data_sz-1 downto 0); - Addr_RE : out std_logic_vector(addr_sz-1 downto 0); - Addr_WR : out std_logic_vector(addr_sz-1 downto 0); - full : out std_logic; - empty : out std_logic; - Data_out : out std_logic_vector(Data_sz-1 downto 0) - ); -end component; - - -component Fifo_Read is - generic( - Addr_sz : integer := 8; - addr_max_int : integer := 256); - port( - clk : in std_logic; - raz : in std_logic; - flag_RE : in std_logic; - ReUse : in std_logic; - Waddr : in std_logic_vector(addr_sz-1 downto 0); - empty : out std_logic; - Raddr : out std_logic_vector(addr_sz-1 downto 0) - ); -end component; - - -component Fifo_Write is - generic( - Addr_sz : integer := 8; - addr_max_int : integer := 256); - port( - clk : in std_logic; - raz : in std_logic; - flag_WR : in std_logic; - Raddr : in std_logic_vector(addr_sz-1 downto 0); - full : out std_logic; - Waddr : out std_logic_vector(addr_sz-1 downto 0) - ); +port( + rstn : in std_logic; + rclk : in std_logic; + ren : in std_logic; + rdata : out std_logic_vector(DataSz-1 downto 0); + empty : out std_logic; + raddr : out std_logic_vector(abits-1 downto 0); + wclk : in std_logic; + wen : in std_logic; + wdata : in std_logic_vector(DataSz-1 downto 0); + full : out std_logic; + waddr : out std_logic_vector(abits-1 downto 0) +); end component; - -component Link_Reg is - generic(Data_sz : integer := 16); - port( - clk,raz : in std_logic; - Data_one : in std_logic_vector(Data_sz-1 downto 0); - Data_two : in std_logic_vector(Data_sz-1 downto 0); - ReUse : in std_logic; - flag_RE : in std_logic; - flag_WR : in std_logic; - empty : in std_logic; - Data_out : out std_logic_vector(Data_sz-1 downto 0) - ); -end component; - ---===========================================================| ---================= Demi FIFO Ecriture ======================| ---===========================================================| - -component APB_FifoWrite is - generic ( - pindex : integer := 0; - paddr : integer := 0; - pmask : integer := 16#fff#; - pirq : integer := 0; - abits : integer := 8; - Data_sz : integer := 16; - Addr_sz : integer := 8; - addr_max_int : integer := 256); - port ( - clk : in std_logic; - rst : in std_logic; - apbi : in apb_slv_in_type; - ReadEnable : in std_logic; - Empty : out std_logic; - Full : out std_logic; - DATA : out std_logic_vector(Data_sz-1 downto 0); - apbo : out apb_slv_out_type - ); -end component; - - ---component Top_FifoWrite is --- generic( --- Data_sz : integer := 16; --- Addr_sz : integer := 8; --- addr_max_int : integer := 256); --- port( --- clk : in std_logic; --- raz : in std_logic; --- flag_RE : in std_logic; --- flag_WR : in std_logic; --- Data_in : in std_logic_vector(Data_sz-1 downto 0); --- Raddr : in std_logic_vector(addr_sz-1 downto 0); --- full : out std_logic; --- empty : out std_logic; --- Waddr : out std_logic_vector(addr_sz-1 downto 0); --- Data_out : out std_logic_vector(Data_sz-1 downto 0) --- ); ---end component; - ---===========================================================| ---================== Demi FIFO Lecture ======================| ---===========================================================| - -component APB_FifoRead is - generic ( - pindex : integer := 0; - paddr : integer := 0; - pmask : integer := 16#fff#; - pirq : integer := 0; - abits : integer := 8; - Data_sz : integer := 16; - Addr_sz : integer := 8; - addr_max_int : integer := 256); - port ( - clk : in std_logic; - rst : in std_logic; - apbi : in apb_slv_in_type; - WriteEnable : in std_logic; - Full : out std_logic; - Empty : out std_logic; - DATA : in std_logic_vector(Data_sz-1 downto 0); - apbo : out apb_slv_out_type - ); -end component; - - ---component Top_FifoRead is --- generic( --- Data_sz : integer := 16; --- Addr_sz : integer := 8; --- addr_max_int : integer := 256); --- port( --- clk : in std_logic; --- raz : in std_logic; --- flag_RE : in std_logic; --- flag_WR : in std_logic; --- Data_in : in std_logic_vector(Data_sz-1 downto 0); --- Waddr : in std_logic_vector(addr_sz-1 downto 0); --- full : out std_logic; --- empty : out std_logic; --- Raddr : out std_logic_vector(addr_sz-1 downto 0); --- Data_out : out std_logic_vector(Data_sz-1 downto 0) --- ); ---end component; - component ssram_plugin is generic (tech : integer := 0); port