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IIR Filter Ready for tests, New version of APB_FIFO under developpement.
jeandet@PC-DE-JEANDET.lpp.polytechnique.fr -
r92:74ac16764d41 alexis
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
22 library ieee;
23 use ieee.std_logic_1164.all;
24 library grlib;
25 use grlib.amba.all;
26 use grlib.stdlib.all;
27 use grlib.devices.all;
28 library lpp;
29 use lpp.lpp_amba.all;
30 use lpp.apb_devices_list.all;
31
32 --! Driver APB "G�n�rique" qui va faire le lien entre le bus Amba et la FIFO
33
34 entity ApbFifoDriverV is
35 generic (
36 pindex : integer := 0;
37 paddr : integer := 0;
38 pmask : integer := 16#fff#;
39 pirq : integer := 0;
40 abits : integer := 8;
41 LPP_DEVICE : integer;
42 FifoCnt : integer := 1;
43 Data_sz : integer := 16;
44 Addr_sz : integer := 8;
45 addr_max_int : integer := 256);
46 port (
47 clk : in std_logic; --! Horloge du composant
48 rst : in std_logic; --! Reset general du composant
49 ReadEnable : out std_logic_vector(FifoCnt-1 downto 0); --! Instruction de lecture en m�moire
50 WriteEnable : out std_logic_vector(FifoCnt-1 downto 0); --! Instruction d'�criture en m�moire
51 FlagEmpty : in std_logic_vector(FifoCnt-1 downto 0); --! Flag, M�moire vide
52 FlagFull : in std_logic_vector(FifoCnt-1 downto 0); --! Flag, M�moire pleine
53 ReUse : out std_logic_vector(FifoCnt-1 downto 0); --! Flag, Permet de relire la m�moire du d�but
54 Lock : out std_logic_vector(FifoCnt-1 downto 0); --! Flag, Permet de bloquer l'�criture dans la m�moire
55 DataIn : out std_logic_vector((FifoCnt*Data_sz)-1 downto 0); --! Registre de donn�es en entr�e
56 DataOut : in std_logic_vector((FifoCnt*Data_sz)-1 downto 0); --! Registre de donn�es en sortie
57 AddrIn : in std_logic_vector((FifoCnt*Addr_sz)-1 downto 0); --! Registre d'addresse (�criture)
58 AddrOut : in std_logic_vector((FifoCnt*Addr_sz)-1 downto 0); --! Registre d'addresse (lecture)
59 apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus
60 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
61 );
62 end ApbFifoDriverV;
63
64 --! @details Utilisable avec n'importe quelle IP VHDL de type FIFO
65
66 architecture ar_ApbFifoDriverV of ApbFifoDriverV is
67
68 constant REVISION : integer := 1;
69
70 constant pconfig : apb_config_type := (
71 0 => ahb_device_reg (VENDOR_LPP, LPP_DEVICE, 0, REVISION, 0),
72 1 => apb_iobar(paddr, pmask));
73
74 type DEVICE_ctrlr_Reg is record
75 DEVICE_Cfg : std_logic_vector(5 downto 0);
76 DEVICE_DataW : std_logic_vector(Data_sz-1 downto 0);
77 DEVICE_DataR : std_logic_vector(Data_sz-1 downto 0);
78 DEVICE_AddrW : std_logic_vector(Addr_sz-1 downto 0);
79 DEVICE_AddrR : std_logic_vector(Addr_sz-1 downto 0);
80 end record;
81
82 type DEVICE_ctrlr_RegV is array(FifoCnt-1 downto 0) of DEVICE_ctrlr_Reg;
83
84 signal Rec : DEVICE_ctrlr_RegV;
85 signal Rdata : std_logic_vector(31 downto 0);
86
87 signal FlagRE : std_logic;
88 signal FlagWR : std_logic;
89
90 begin
91
92 fifoflags: for i in 0 to FifoCnt-1 generate:
93
94 Rec(i).DEVICE_Cfg(0) <= FlagRE(i);
95 Rec(i).DEVICE_Cfg(1) <= FlagWR(i);
96 Rec(i).DEVICE_Cfg(2) <= FlagEmpty(i);
97 Rec(i).DEVICE_Cfg(3) <= FlagFull(i);
98
99 ReUse(i) <= Rec(i).DEVICE_Cfg(4);
100 Lock(i) <= Rec(i).DEVICE_Cfg(5);
101
102 DataIn(i*(Data_sz-1 downto 0)) <= Rec(i).DEVICE_DataW;
103
104 Rec(i).DEVICE_DataR <= DataOut(i*(Data_sz-1 downto 0));
105 Rec(i).DEVICE_AddrW <= AddrIn(i*(Addr_sz-1 downto 0));
106 Rec(i).DEVICE_AddrR <= AddrOut(i*(Addr_sz-1 downto 0));
107
108 WriteEnable(i) <= FlagWR(i);
109 ReadEnable(i) <= FlagRE(i);
110
111 end generate;
112
113
114 process(rst,clk)
115 begin
116 if(rst='0')then
117 Rec.DEVICE_DataW <= (others => '0');
118 FlagWR <= '0';
119 FlagRE <= '0';
120 Rec.DEVICE_Cfg(4) <= '0';
121 Rec.DEVICE_Cfg(5) <= '0';
122
123 elsif(clk'event and clk='1')then
124
125 --APB Write OP
126 if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
127 case apbi.paddr(abits-1 downto 2) is
128 when "000000" =>
129 FlagWR <= '1';
130 Rec.DEVICE_DataW <= apbi.pwdata(Data_sz-1 downto 0);
131 when "000010" =>
132 Rec.DEVICE_Cfg(4) <= apbi.pwdata(16);
133 Rec.DEVICE_Cfg(5) <= apbi.pwdata(20);
134 when others =>
135 null;
136 end case;
137 else
138 FlagWR <= (others => '0');
139 end if;
140
141 --APB Read OP
142 if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
143 case apbi.paddr(abits-1 downto 2) is
144 for i in 0 to FifoCnt-1 loop
145 if conv_integer(apbi.paddr(7 downto 3)) = i then
146 case apbi.paddr(2 downto 2) is
147 when "0" =>
148 CoefsReg.numCoefs(i)(0) <= (apbi.pwdata(Coef_SZ-1 downto 0));
149 when "1" =>
150 CoefsReg.numCoefs(i)(1) <= (apbi.pwdata(Coef_SZ-1 downto 0));
151 when others =>
152 end case;
153 end if;
154 end loop;
155 when "000000" =>
156 FlagRE <= '1';
157 Rdata(Data_sz-1 downto 0) <= Rec.DEVICE_DataR;
158 when "000001" =>
159 Rdata(31 downto 8) <= X"AAAAAA";
160 Rdata(7 downto 0) <= Rec.DEVICE_AddrR;
161 when "000101" =>
162 Rdata(31 downto 8) <= X"AAAAAA";
163 Rdata(7 downto 0) <= Rec.DEVICE_AddrW;
164 when "000010" =>
165 Rdata(3 downto 0) <= "000" & Rec.DEVICE_Cfg(0);
166 Rdata(7 downto 4) <= "000" & Rec.DEVICE_Cfg(1);
167 Rdata(11 downto 8) <= "000" & Rec.DEVICE_Cfg(2);
168 Rdata(15 downto 12) <= "000" & Rec.DEVICE_Cfg(3);
169 Rdata(19 downto 16) <= "000" & Rec.DEVICE_Cfg(4);
170 Rdata(23 downto 20) <= "000" & Rec.DEVICE_Cfg(5);
171 Rdata(31 downto 24) <= X"CC";
172 when others =>
173 Rdata <= (others => '0');
174 end case;
175 else
176 FlagRE <= (others => '0');
177 end if;
178
179 end if;
180 apbo.pconfig <= pconfig;
181 end process;
182
183 apbo.prdata <= Rdata when apbi.penable = '1';
184
185
186 end ar_ApbFifoDriverV; No newline at end of file
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@@ -0,0 +1,193
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
22 library IEEE;
23 use IEEE.std_logic_1164.all;
24 use IEEE.numeric_std.all;
25 library lpp;
26 use lpp.lpp_memory.all;
27
28 entity lpp_fifo is
29 generic(
30 tech : integer := 0;
31 DataSz : integer range 1 to 32 := 8;
32 abits : integer range 2 to 12 := 8
33 );
34 port(
35 rstn : in std_logic;
36 rclk : in std_logic;
37 ren : in std_logic;
38 rdata : out std_logic_vector(DataSz-1 downto 0);
39 empty : out std_logic;
40 raddr : out std_logic_vector(abits-1 downto 0);
41 wclk : in std_logic;
42 wen : in std_logic;
43 wdata : in std_logic_vector(DataSz-1 downto 0);
44 full : out std_logic;
45 waddr : out std_logic_vector(abits-1 downto 0)
46 );
47 end entity;
48
49
50 architecture ar_lpp_fifo of lpp_fifo is
51
52 signal sFull : std_logic:='0';
53 signal sEmpty : std_logic:='1';
54 signal sREN : std_logic:='0';
55 signal sWEN : std_logic:='0';
56
57 signal Waddr_vect_d : std_logic_vector(abits-1 downto 0):=(others =>'0');
58 signal Raddr_vect_d : std_logic_vector(abits-1 downto 0);
59 signal Waddr_vect : std_logic_vector(abits-1 downto 0):=(others =>'0');
60 signal Raddr_vect : std_logic_vector(abits-1 downto 0):=(others =>'0');
61
62 type etat is (e0,e1,e2);
63 signal rect : etat;
64 signal wect : etat;
65
66 begin
67
68 SRAM : syncram_2p
69 generic map(tech,abits,DataSz)
70 port map(RCLK,sREN,Raddr_vect,rdata,WCLK,sWEN,Waddr_vect,wdata);
71
72 --RAM0: entity work.RAM_CEL
73 -- generic map(abits, DataSz)
74 -- port map(wdata, rdata, sWEN, sREN, Waddr_vect, Raddr_vect, RCLK, WCLK, rstn);
75
76 --=============================
77 -- Read section
78 --=============================
79 sREN <= not REN when (rect=e0) else '0';
80 process (rclk,rstn)
81 begin
82 if(rstn='0')then
83 rect <= e2;
84 sempty <= '1';
85 Raddr_vect <= (others =>'0');
86 Raddr_vect_d <= (others =>'1');
87
88 elsif(rclk'event and rclk='1')then
89 if(sREN='1') then
90 Raddr_vect <= std_logic_vector(unsigned(Raddr_vect) + 1);
91 Raddr_vect_d <= Raddr_vect;
92 end if;
93
94 case rect is
95 when e0 =>
96 sempty <= '0';
97 if(Raddr_vect=Waddr_vect_d)then
98 rect <= e1;
99 sempty <= '1';
100 end if;
101
102 when e1 =>
103 if(Waddr_vect_d=Raddr_vect_d)then
104 rect <= e2;
105 else
106 rect <= e0;
107 end if;
108
109 when e2 =>
110 if(Waddr_vect_d/=Raddr_vect_d)then
111 rect <= e0;
112 end if;
113
114 end case;
115 end if;
116 end process;
117
118
119 --=============================
120 -- Write section
121 --=============================
122 sWEN <= not WEN when (wect=e0) else '0';
123 process (wclk,rstn)
124 begin
125 if(rstn='0')then
126 wect <= e0;
127 sfull <= '0';
128 Waddr_vect <= (others =>'0');
129 Waddr_vect_d <= (others =>'1');
130
131 elsif(wclk'event and wclk='1')then
132 if(sWEN='1') then
133 Waddr_vect <= std_logic_vector(unsigned(Waddr_vect) +1);
134 Waddr_vect_d <= Waddr_vect;
135 end if;
136
137 case wect is
138 when e0 =>
139 sfull <= '0';
140 if(Waddr_vect=Raddr_vect_d)then
141 wect <= e1;
142 sfull <= '1';
143 end if;
144
145 when e1 =>
146 if(Waddr_vect_d=Raddr_vect_d)then
147 wect <= e2;
148 else
149 wect <= e0;
150 end if;
151
152 when e2 =>
153 if(Waddr_vect_d/=Raddr_vect_d)then
154 wect <= e0;
155 end if;
156
157 end case;
158 end if;
159 end process;
160
161
162 full <= sFull;
163 empty <= sEmpty;
164 waddr <= Waddr_vect;
165 raddr <= Raddr_vect;
166
167 end architecture;
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@@ -34,6 +34,7 use lpp.apb_devices_list.all;
34 34
35 35 entity APB_IIR_CEL is
36 36 generic (
37 tech : integer := 0;
37 38 pindex : integer := 0;
38 39 paddr : integer := 0;
39 40 pmask : integer := 16#fff#;
@@ -80,7 +81,7 signal r : FILTERreg;
80 81 signal filter_reset : std_logic:='0';
81 82 signal smp_cnt : integer :=0;
82 83 signal sample_clk_out_R : std_logic;
83
84 signal RawCoefs : std_logic_vector(Coef_SZ*CoefCntPerCel*Cels_count-1 downto 0);
84 85
85 86 type CoefCelT is array(CoefCntPerCel-1 downto 0) of std_logic_vector(Coef_SZ-1 downto 0);
86 87 type CoefTblT is array(Cels_count-1 downto 0) of CoefCelT;
@@ -98,7 +99,7 filter_reset <= rst and r.regin.conf
98 99 sample_clk_out <= sample_clk_out_R;
99 100
100 101 filter : IIR_CEL_FILTER
101 generic map(Sample_SZ,ChanelsCount,Coef_SZ,CoefCntPerCel,Cels_count,Mem_use)
102 generic map(tech,Sample_SZ,ChanelsCount,Coef_SZ,CoefCntPerCel,Cels_count,Mem_use)
102 103 port map(
103 104 reset => filter_reset,
104 105 clk => clk,
@@ -106,7 +107,8 port map(
106 107 regs_in => r.regin,
107 108 regs_out => r.regout,
108 109 sample_in => sample_in,
109 sample_out => sample_out
110 sample_out => sample_out,
111 coefs => RawCoefs
110 112 );
111 113
112 114 process(rst,sample_clk)
@@ -125,6 +127,15 end if;
125 127 end process;
126 128
127 129
130 coefsConnectL0: for z in 0 to Cels_count-1 generate
131 coefsConnectL1: for y in 0 to (CoefCntPerCel/2)-1 generate
132 coefsConnectL2: for x in 0 to Coef_SZ-1 generate
133 RawCoefs(x + ((2*y))*Coef_SZ + z*Coef_SZ*CoefCntPerCel) <= CoefsReg.numCoefs(z)(y)(x);
134 RawCoefs(x + ((2*y)+1)*Coef_SZ + z*Coef_SZ*CoefCntPerCel) <= CoefsReg.denCoefs(z)(y)(x);
135 end generate;
136 end generate;
137 end generate;
138
128 139 process(rst,clk)
129 140 begin
130 141 if rst = '0' then
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@@ -30,7 +30,9 use lpp.general_purpose.all;
30 30 --TODO amliorer la gestion de la RAM et de la flexibilit du filtre
31 31
32 32 entity IIR_CEL_CTRLR is
33 generic(Sample_SZ : integer := 16;
33 generic(
34 tech : integer := 0;
35 Sample_SZ : integer := 16;
34 36 ChanelsCount : integer := 1;
35 37 Coef_SZ : integer := 9;
36 38 CoefCntPerCel: integer := 3;
@@ -98,17 +100,18 begin
98 100
99 101
100 102 coefsConnectL0: for z in 0 to Cels_count-1 generate
101 coefsConnectL1: for y in 0 to CoefCntPerCel-1 generate
103 coefsConnectL1: for y in 0 to (CoefCntPerCel/2)-1 generate
102 104 coefsConnectL2: for x in 0 to Coef_SZ-1 generate
103 CoefsReg.numCoefs(z)(y)(x) <= coefs(x + y*Coef_SZ + z*Coef_SZ*CoefCntPerCel);
104 CoefsReg.denCoefs(z)(y)(x) <= coefs(x + y*Coef_SZ + z*Coef_SZ*CoefCntPerCel);
105 CoefsReg.numCoefs(z)(y)(x) <= coefs(x + ((2*y))*Coef_SZ + z*Coef_SZ*CoefCntPerCel);
106 CoefsReg.denCoefs(z)(y)(x) <= coefs(x + ((2*y)+1)*Coef_SZ + z*Coef_SZ*CoefCntPerCel);
105 107 end generate;
106 108 end generate;
107 109 end generate;
108 110
109 111
112
110 113 RAM_CTRLR2inst : RAM_CTRLR2
111 generic map(Sample_SZ,Mem_use)
114 generic map(tech,Sample_SZ,Mem_use)
112 115 port map(
113 116 reset => reset,
114 117 clk => clk,
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@@ -29,7 +29,9 use lpp.general_purpose.all;
29 29 --TODO amliorer la gestion de la RAM et de la flexibilit du filtre
30 30
31 31 entity IIR_CEL_FILTER is
32 generic(Sample_SZ : integer := 16;
32 generic(
33 tech : integer := 0;
34 Sample_SZ : integer := 16;
33 35 ChanelsCount : integer := 1;
34 36 Coef_SZ : integer := 9;
35 37 CoefCntPerCel: integer := 3;
@@ -43,7 +45,7 port(
43 45 regs_out : in out_IIR_CEL_reg;
44 46 sample_in : in samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0);
45 47 sample_out : out samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0);
46 coefs : in std_logic_vector(Coef_SZ*CoefCntPerCel*Cels_count-1 downto 0)
48 coefs : in std_logic_vector(Coef_SZ*CoefCntPerCel*Cels_count-1 downto 0)
47 49
48 50 );
49 51 end IIR_CEL_FILTER;
@@ -59,7 +61,7 begin
59 61 virg_pos <= to_integer(unsigned(regs_in.virgPos));
60 62
61 63 CTRLR : IIR_CEL_CTRLR
62 generic map (Sample_SZ,ChanelsCount,Coef_SZ,CoefCntPerCel,Cels_count,Mem_use)
64 generic map (tech,Sample_SZ,ChanelsCount,Coef_SZ,CoefCntPerCel,Cels_count,Mem_use)
63 65 port map(
64 66 reset => reset,
65 67 clk => clk,
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@@ -26,13 +26,17 library lpp;
26 26 use lpp.iir_filter.all;
27 27 use lpp.FILTERcfg.all;
28 28 use lpp.general_purpose.all;
29 library techmap;
30 use techmap.gencomp.all;
29 31
30 32 --TODO amliorer la flexibilit de la config de la RAM.
31 33
32 34 entity RAM_CTRLR2 is
33 35 generic(
36 tech : integer := 0;
34 37 Input_SZ_1 : integer := 16;
35 38 Mem_use : integer := use_RAM
39
36 40 );
37 41 port(
38 42 reset : in std_logic;
@@ -52,9 +56,9 end RAM_CTRLR2;
52 56
53 57 architecture ar_RAM_CTRLR2 of RAM_CTRLR2 is
54 58
55 signal WD : std_logic_vector(35 downto 0);
56 signal WD_D : std_logic_vector(35 downto 0);
57 signal RD : std_logic_vector(35 downto 0);
59 signal WD : std_logic_vector(Input_SZ_1-1 downto 0);
60 signal WD_D : std_logic_vector(Input_SZ_1-1 downto 0);
61 signal RD : std_logic_vector(Input_SZ_1-1 downto 0);
58 62 signal WEN, REN : std_logic;
59 63 signal WADDR_back : std_logic_vector(7 downto 0);
60 64 signal WADDR_back_D: std_logic_vector(7 downto 0);
@@ -76,33 +80,37 REN <= not read;
76 80 --==============================================================
77 81 --=========================R A M================================
78 82 --==============================================================
79 memRAM : if Mem_use = use_RAM generate
80 RAMblk :RAM
81 port map(
82 WD => WD_D,
83 RD => RD,
84 WEN => WEN,
85 REN => REN,
86 WADDR => WADDR,
87 RADDR => RADDR,
88 RWCLK => clk,
89 RESET => reset
90 ) ;
91 end generate;
83 --memRAM : if Mem_use = use_RAM generate
84 --RAMblk :RAM
85 -- port map(
86 -- WD => WD_D,
87 -- RD => RD,
88 -- WEN => WEN,
89 -- REN => REN,
90 -- WADDR => WADDR,
91 -- RADDR => RADDR,
92 -- RWCLK => clk,
93 -- RESET => reset
94 -- ) ;
95 --end generate;
92 96
93 memCEL : if Mem_use = use_CEL generate
94 RAMblk :RAM_CEL
95 port map(
96 WD => WD_D,
97 RD => RD,
98 WEN => WEN,
99 REN => REN,
100 WADDR => WADDR,
101 RADDR => RADDR,
102 RWCLK => clk,
103 RESET => reset
104 ) ;
105 end generate;
97 --memCEL : if Mem_use = use_CEL generate
98 --RAMblk :RAM_CEL
99 -- port map(
100 -- WD => WD_D,
101 -- RD => RD,
102 -- WEN => WEN,
103 -- REN => REN,
104 -- WADDR => WADDR,
105 -- RADDR => RADDR,
106 -- RWCLK => clk,
107 -- RESET => reset
108 -- ) ;
109 --end generate;
110
111 SRAM : syncram_2p
112 generic map(tech,8,Input_SZ_1)
113 port map(clk,not REN,RADDR,RD,clk,not WEN,WADDR,WD_D);
106 114 --==============================================================
107 115 --==============================================================
108 116
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@@ -73,6 +73,7 end record;
73 73
74 74 component APB_IIR_CEL is
75 75 generic (
76 tech : integer := 0;
76 77 pindex : integer := 0;
77 78 paddr : integer := 0;
78 79 pmask : integer := 16#fff#;
@@ -144,7 +145,9 end component;
144 145
145 146
146 147 component IIR_CEL_CTRLR is
147 generic(Sample_SZ : integer := 16;
148 generic(
149 tech : integer := 0;
150 Sample_SZ : integer := 16;
148 151 ChanelsCount : integer := 1;
149 152 Coef_SZ : integer := 9;
150 153 CoefCntPerCel: integer := 3;
@@ -181,7 +184,9 component RAM_CEL is
181 184 end component;
182 185
183 186 component IIR_CEL_FILTER is
184 generic(Sample_SZ : integer := 16;
187 generic(
188 tech : integer := 0;
189 Sample_SZ : integer := 16;
185 190 ChanelsCount : integer := 1;
186 191 Coef_SZ : integer := 9;
187 192 CoefCntPerCel: integer := 3;
@@ -203,6 +208,7 end component;
203 208
204 209 component RAM_CTRLR2 is
205 210 generic(
211 tech : integer := 0;
206 212 Input_SZ_1 : integer := 16;
207 213 Mem_use : integer := use_RAM
208 214 );
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@@ -34,222 +34,27 use gaisler.memctrl.all;
34 34
35 35 package lpp_memory is
36 36
37 --===========================================================|
38 --=================== FIFO Compl�te =========================|
39 --===========================================================|
40
41 component APB_FIFO is
42 generic (
43 pindex : integer := 0;
44 paddr : integer := 0;
45 pmask : integer := 16#fff#;
46 pirq : integer := 0;
47 abits : integer := 8;
48 Data_sz : integer := 16;
49 Addr_sz : integer := 8;
50 addr_max_int : integer := 256);
51 port (
52 clk : in std_logic;
53 rst : in std_logic;
54 apbi : in apb_slv_in_type;
55 Full : out std_logic;
56 Empty : out std_logic;
57 WR : out std_logic;
58 RE : out std_logic;
59 apbo : out apb_slv_out_type
60 );
61 end component;
62
63
64 component ApbDriver is
65 generic (
66 pindex : integer := 0;
67 paddr : integer := 0;
68 pmask : integer := 16#fff#;
69 pirq : integer := 0;
70 abits : integer := 8;
71 LPP_DEVICE : integer;
72 Data_sz : integer := 16;
73 Addr_sz : integer := 8;
74 addr_max_int : integer := 256);
75 port (
76 clk : in std_logic;
77 rst : in std_logic;
78 ReadEnable : out std_logic;
79 WriteEnable : out std_logic;
80 FlagEmpty : in std_logic;
81 FlagFull : in std_logic;
82 ReUse : out std_logic;
83 Lock : out std_logic;
84 DataIn : out std_logic_vector(Data_sz-1 downto 0);
85 DataOut : in std_logic_vector(Data_sz-1 downto 0);
86 AddrIn : in std_logic_vector(Addr_sz-1 downto 0);
87 AddrOut : in std_logic_vector(Addr_sz-1 downto 0);
88 apbi : in apb_slv_in_type;
89 apbo : out apb_slv_out_type
37 component lpp_fifo is
38 generic(
39 tech : integer := 0;
40 DataSz : integer range 1 to 32 := 8;
41 abits : integer range 2 to 12 := 8
90 42 );
91 end component;
92
93
94 component Top_FIFO is
95 generic(
96 Data_sz : integer := 16;
97 Addr_sz : integer := 8;
98 addr_max_int : integer := 256
99 );
100 port(
101 clk,raz : in std_logic;
102 flag_RE : in std_logic;
103 flag_WR : in std_logic;
104 ReUse : in std_logic;
105 Lock : in std_logic;
106 Data_in : in std_logic_vector(Data_sz-1 downto 0);
107 Addr_RE : out std_logic_vector(addr_sz-1 downto 0);
108 Addr_WR : out std_logic_vector(addr_sz-1 downto 0);
109 full : out std_logic;
110 empty : out std_logic;
111 Data_out : out std_logic_vector(Data_sz-1 downto 0)
112 );
113 end component;
114
115
116 component Fifo_Read is
117 generic(
118 Addr_sz : integer := 8;
119 addr_max_int : integer := 256);
120 port(
121 clk : in std_logic;
122 raz : in std_logic;
123 flag_RE : in std_logic;
124 ReUse : in std_logic;
125 Waddr : in std_logic_vector(addr_sz-1 downto 0);
126 empty : out std_logic;
127 Raddr : out std_logic_vector(addr_sz-1 downto 0)
128 );
129 end component;
130
131
132 component Fifo_Write is
133 generic(
134 Addr_sz : integer := 8;
135 addr_max_int : integer := 256);
136 port(
137 clk : in std_logic;
138 raz : in std_logic;
139 flag_WR : in std_logic;
140 Raddr : in std_logic_vector(addr_sz-1 downto 0);
141 full : out std_logic;
142 Waddr : out std_logic_vector(addr_sz-1 downto 0)
143 );
43 port(
44 rstn : in std_logic;
45 rclk : in std_logic;
46 ren : in std_logic;
47 rdata : out std_logic_vector(DataSz-1 downto 0);
48 empty : out std_logic;
49 raddr : out std_logic_vector(abits-1 downto 0);
50 wclk : in std_logic;
51 wen : in std_logic;
52 wdata : in std_logic_vector(DataSz-1 downto 0);
53 full : out std_logic;
54 waddr : out std_logic_vector(abits-1 downto 0)
55 );
144 56 end component;
145 57
146
147 component Link_Reg is
148 generic(Data_sz : integer := 16);
149 port(
150 clk,raz : in std_logic;
151 Data_one : in std_logic_vector(Data_sz-1 downto 0);
152 Data_two : in std_logic_vector(Data_sz-1 downto 0);
153 ReUse : in std_logic;
154 flag_RE : in std_logic;
155 flag_WR : in std_logic;
156 empty : in std_logic;
157 Data_out : out std_logic_vector(Data_sz-1 downto 0)
158 );
159 end component;
160
161 --===========================================================|
162 --================= Demi FIFO Ecriture ======================|
163 --===========================================================|
164
165 component APB_FifoWrite is
166 generic (
167 pindex : integer := 0;
168 paddr : integer := 0;
169 pmask : integer := 16#fff#;
170 pirq : integer := 0;
171 abits : integer := 8;
172 Data_sz : integer := 16;
173 Addr_sz : integer := 8;
174 addr_max_int : integer := 256);
175 port (
176 clk : in std_logic;
177 rst : in std_logic;
178 apbi : in apb_slv_in_type;
179 ReadEnable : in std_logic;
180 Empty : out std_logic;
181 Full : out std_logic;
182 DATA : out std_logic_vector(Data_sz-1 downto 0);
183 apbo : out apb_slv_out_type
184 );
185 end component;
186
187
188 --component Top_FifoWrite is
189 -- generic(
190 -- Data_sz : integer := 16;
191 -- Addr_sz : integer := 8;
192 -- addr_max_int : integer := 256);
193 -- port(
194 -- clk : in std_logic;
195 -- raz : in std_logic;
196 -- flag_RE : in std_logic;
197 -- flag_WR : in std_logic;
198 -- Data_in : in std_logic_vector(Data_sz-1 downto 0);
199 -- Raddr : in std_logic_vector(addr_sz-1 downto 0);
200 -- full : out std_logic;
201 -- empty : out std_logic;
202 -- Waddr : out std_logic_vector(addr_sz-1 downto 0);
203 -- Data_out : out std_logic_vector(Data_sz-1 downto 0)
204 -- );
205 --end component;
206
207 --===========================================================|
208 --================== Demi FIFO Lecture ======================|
209 --===========================================================|
210
211 component APB_FifoRead is
212 generic (
213 pindex : integer := 0;
214 paddr : integer := 0;
215 pmask : integer := 16#fff#;
216 pirq : integer := 0;
217 abits : integer := 8;
218 Data_sz : integer := 16;
219 Addr_sz : integer := 8;
220 addr_max_int : integer := 256);
221 port (
222 clk : in std_logic;
223 rst : in std_logic;
224 apbi : in apb_slv_in_type;
225 WriteEnable : in std_logic;
226 Full : out std_logic;
227 Empty : out std_logic;
228 DATA : in std_logic_vector(Data_sz-1 downto 0);
229 apbo : out apb_slv_out_type
230 );
231 end component;
232
233
234 --component Top_FifoRead is
235 -- generic(
236 -- Data_sz : integer := 16;
237 -- Addr_sz : integer := 8;
238 -- addr_max_int : integer := 256);
239 -- port(
240 -- clk : in std_logic;
241 -- raz : in std_logic;
242 -- flag_RE : in std_logic;
243 -- flag_WR : in std_logic;
244 -- Data_in : in std_logic_vector(Data_sz-1 downto 0);
245 -- Waddr : in std_logic_vector(addr_sz-1 downto 0);
246 -- full : out std_logic;
247 -- empty : out std_logic;
248 -- Raddr : out std_logic_vector(addr_sz-1 downto 0);
249 -- Data_out : out std_logic_vector(Data_sz-1 downto 0)
250 -- );
251 --end component;
252
253 58 component ssram_plugin is
254 59 generic (tech : integer := 0);
255 60 port
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