HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib Commit - r324:74232a5eafa5

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lib/staging/LPP/PLE/dsp/lpp_fft/BUTTERFLY_CTRL.vhd created 644 +209 0

@@ -0,0 +1,209
	1	------------------------------------------------------------------------------
	2	-- This file is a part of the LPP VHDL IP LIBRARY
	3	-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
	4	--
	5	-- This program is free software; you can redistribute it and/or modify
	6	-- it under the terms of the GNU General Public License as published by
	7	-- the Free Software Foundation; either version 3 of the License, or
	8	-- (at your option) any later version.
	9	--
	10	-- This program is distributed in the hope that it will be useful,
	11	-- but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	-- GNU General Public License for more Cdetails.
	14	--
	15	-- You should have received a copy of the GNU General Public License
	16	-- along with this program; if not, write to the Free Software
	17	-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	18	-------------------------------------------------------------------------------
	19	-- Author : Paul LEROY
	20	-- Mail : paul.leroy@lpp.polytechnique.fr
	21	-------------------------------------------------------------------------------
	22
	23	LIBRARY IEEE;
	24	USE IEEE.numeric_std.ALL;
	25	USE IEEE.std_logic_1164.ALL;
	26
	27	LIBRARY staging_lpp;
	28	--USE lpp.general_purpose.ALL;
	29	use staging_lpp.PLE_general_purpose.all;
	30	use staging_lpp.PLE_lpp_fft.all;
	31
	32	ENTITY BUTTERFLY_CTRL IS
	33	PORT (
	34	rstn : IN STD_LOGIC;
	35	clk : IN STD_LOGIC;
	36
	37	sample_in_val : IN STD_LOGIC;
	38	sample_out_val : OUT STD_LOGIC;
	39
	40	sel_op1 : OUT STD_LOGIC_VECTOR( 4 DOWNTO 0 ); -- Are Aim X Y Z
	41	sel_op2 : OUT STD_LOGIC_VECTOR( 4 DOWNTO 0 ); -- Bre Bim C_in cps_in cms_in
	42	sel_xyz : OUT STD_LOGIC_VECTOR( 2 DOWNTO 0 ); -- X Y Z
	43	sel_out : OUT STD_LOGIC_VECTOR( 4 DOWNTO 0 );
	44	alu_ctrl : OUT STD_LOGIC_VECTOR( 2 DOWNTO 0 );
	45	alu_comp : OUT STD_LOGIC_VECTOR( 1 DOWNTO 0 )
	46	);
	47	END BUTTERFLY_CTRL;
	48
	49	ARCHITECTURE ar_BUTTERFLY_CTRL OF BUTTERFLY_CTRL IS
	50
	51	TYPE fsm_BUTTERFLY_CTRL_T IS ( clearMAC,
	52	waiting,
	53	add1,
	54	add2,
	55	add3,
	56	add4,
	57	mult5,
	58	mac6,
	59	mac7,
	60	mult8,
	61	mac9,
	62	last10,
	63	last11);
	64	SIGNAL BUTTERFLY_CTRL_STATE : fsm_BUTTERFLY_CTRL_T;
	65
	66	BEGIN
	67
	68	PROCESS (clk, rstn)
	69
	70	BEGIN -- PROCESS
	71	IF rstn = '0' THEN -- asynchronous reset (active low)
	72	--REG -------------------------------------------------------------------
	73	sel_xyz <= (OTHERS => '0');
	74	sel_out <= (OTHERS => '0');
	75	--ALU -------------------------------------------------------------------
	76	sel_op1 <= (OTHERS => '0');
	77	sel_op2 <= (OTHERS => '0');
	78	alu_ctrl <= ctrl_IDLE;
	79	alu_comp <= (OTHERS => '0');
	80	--OUT
	81	sample_out_val <= '0';
	82
	83	BUTTERFLY_CTRL_STATE <= clearMAC;
	84
	85	ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
	86
	87	CASE BUTTERFLY_CTRL_STATE IS
	88
	89	WHEN clearMAC =>
	90	IF sample_in_val = '1' THEN
	91	alu_ctrl <= ctrl_CLRMAC;
	92	BUTTERFLY_CTRL_STATE <= waiting;
	93	END IF;
	94
	95	WHEN waiting =>
	96	sel_op1 <= "10000"; -- Are
	97	sel_op2 <= "10000"; -- Bre
	98	alu_comp <= "10";
	99	BUTTERFLY_CTRL_STATE <= add1;
	100
	101	WHEN add1 =>
	102	sample_out_val <= '0';
	103	sel_op1 <= "01000"; -- Aim
	104	sel_op2 <= "01000"; -- Bim
	105	alu_comp <= "10";
	106	alu_ctrl <= ctrl_ADD;
	107	sel_out <= "10000";
	108	BUTTERFLY_CTRL_STATE <= add2;
	109
	110	WHEN add2 =>
	111	sample_out_val <= '0';
	112	sel_op1 <= "10000"; -- Are
	113	sel_op2 <= "10000"; -- Bre
	114	alu_comp <= "00";
	115	alu_ctrl <= ctrl_ADD;
	116	sel_out <= "10000";
	117	BUTTERFLY_CTRL_STATE <= add3;
	118
	119	WHEN add3 =>
	120	sample_out_val <= '0';
	121	sel_op1 <= "01000"; -- Aim
	122	sel_op2 <= "01000"; -- Bim
	123	alu_comp <= "00";
	124	alu_ctrl <= ctrl_ADD;
	125	sel_out <= "10000";
	126	sel_xyz <= "100"; -- X
	127	BUTTERFLY_CTRL_STATE <= add4;
	128
	129	WHEN add4 =>
	130	sample_out_val <= '0';
	131	sel_op1 <= "00100"; -- X
	132	sel_op2 <= "00100"; -- c
	133	alu_comp <= "00";
	134	alu_ctrl <= ctrl_ADD;
	135	sel_out <= "00000";
	136	sel_xyz <= "010";
	137	BUTTERFLY_CTRL_STATE <= mult5;
	138
	139	WHEN mult5 =>
	140	sample_out_val <= '0';
	141	alu_ctrl <= ctrl_MULT;
	142	sel_op1 <= "00010"; -- Y
	143	sel_op2 <= "00100"; -- c
	144	alu_comp <= "10";
	145	sel_out <= "00100";
	146	BUTTERFLY_CTRL_STATE <= mac6;
	147
	148	WHEN mac6 =>
	149	sample_out_val <= '0';
	150	sel_op1 <= "00010"; -- Y
	151	sel_op2 <= "00001"; -- cms
	152	alu_comp <= "00";
	153	alu_ctrl <= ctrl_MAC;
	154	sel_out <= "10000";
	155	BUTTERFLY_CTRL_STATE <= mac7;
	156
	157	WHEN mac7 =>
	158	sample_out_val <= '0';
	159	sel_op1 <= "00100"; -- X
	160	sel_op2 <= "00010"; -- cps
	161	alu_ctrl <= ctrl_MAC;
	162	alu_comp <= "00";
	163	sel_out <= "10000";
	164	BUTTERFLY_CTRL_STATE <= mult8;
	165
	166	WHEN mult8 =>
	167	sample_out_val <= '0';
	168	alu_ctrl <= ctrl_MULT;
	169	sel_op1 <= "00000"; -- Z is taken directly from the output of the ALU
	170	sel_op2 <= "00000"; -- 1
	171	alu_comp <= "00";
	172	sel_out <= "10000";
	173	BUTTERFLY_CTRL_STATE <= mac9;
	174
	175	WHEN mac9 =>
	176	sample_out_val <= '0';
	177	sel_op1 <= "10000";
	178	sel_op2 <= "10000";
	179	alu_ctrl <= ctrl_MAC;
	180	alu_comp <= "10";
	181	sel_out <= "10000";
	182	BUTTERFLY_CTRL_STATE <= last10;
	183
	184	WHEN last10 =>
	185	sample_out_val <= '0';
	186	sel_op1 <= "10000";
	187	sel_op2 <= "10000";
	188	alu_ctrl <= ctrl_IDLE;
	189	alu_comp <= "10";
	190	sel_out <= "10000";
	191	BUTTERFLY_CTRL_STATE <= last11;
	192
	193	WHEN last11 =>
	194	sample_out_val <= '0';
	195	alu_ctrl <= ctrl_IDLE;
	196	alu_comp <= "10";
	197	sel_out <= "10000";
	198	BUTTERFLY_CTRL_STATE <= waiting;
	199
	200	WHEN OTHERS =>
	201	NULL;
	202
	203	END CASE;
	204
	205	END IF;
	206
	207	END PROCESS;
	208
	209	END ar_BUTTERFLY_CTRL; No newline at end of file

lib/staging/LPP/PLE/dsp/lpp_fft/BUTTERFLY_TOP.vhd created 644 +115 0

@@ -0,0 +1,115
	1	------------------------------------------------------------------------------
	2	-- This file is a part of the LPP VHDL IP LIBRARY
	3	-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
	4	--
	5	-- This program is free software; you can redistribute it and/or modify
	6	-- it under the terms of the GNU General Public License as published by
	7	-- the Free Software Foundation; either version 3 of the License, or
	8	-- (at your option) any later version.
	9	--
	10	-- This program is distributed in the hope that it will be useful,
	11	-- but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	-- GNU General Public License for more Cdetails.
	14	--
	15	-- You should have received a copy of the GNU General Public License
	16	-- along with this program; if not, write to the Free Software
	17	-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	18	-------------------------------------------------------------------------------
	19	-- Author : Paul LEROY
	20	-- Mail : paul.leroy@lpp.polytechnique.fr
	21	-------------------------------------------------------------------------------
	22
	23	LIBRARY IEEE;
	24	USE IEEE.numeric_std.ALL;
	25	USE IEEE.std_logic_1164.ALL;
	26
	27	LIBRARY staging_lpp;
	28	USE staging_lpp.PLE_general_purpose.ALL;
	29	use staging_lpp.PLE_lpp_fft.all;
	30
	31	ENTITY BUTTERFLY_TOP IS
	32	GENERIC (
	33	Sample_SZ : INTEGER := 16);
	34	PORT (
	35	rstn : IN STD_LOGIC;
	36	clk : IN STD_LOGIC;
	37
	38	sample_in_val : IN STD_LOGIC;
	39	sample_out_val : OUT STD_LOGIC;
	40
	41	Are : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0);
	42	Aim : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0);
	43	Bre : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0);
	44	Bim : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0);
	45	c_in : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0);
	46	cps_in : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0);
	47	cms_in : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0);
	48
	49	op1 : OUT STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0);
	50	op2 : OUT STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0);
	51	alu_ctrl : OUT STD_LOGIC_VECTOR( 2 DOWNTO 0 );
	52	alu_comp : OUT STD_LOGIC_VECTOR( 1 DOWNTO 0 );
	53
	54	butterfly_out : OUT STD_LOGIC_VECTOR ( 2*Sample_SZ-1 DOWNTO 0);
	55	sel_out : OUT STD_LOGIC_VECTOR ( 4 DOWNTO 0)
	56	);
	57	END BUTTERFLY_TOP;
	58
	59	ARCHITECTURE ar_BUTTERFLY_TOP OF BUTTERFLY_TOP IS
	60
	61	SIGNAL sel_op1 : STD_LOGIC_VECTOR( 4 DOWNTO 0 ); -- Are Aim X Y Z
	62	SIGNAL sel_op2 : STD_LOGIC_VECTOR( 4 DOWNTO 0 ); -- Bre Bim C_in cps_in cms_in
	63	SIGNAL sel_xyz : STD_LOGIC_VECTOR( 2 DOWNTO 0 ); -- X Y Z
	64	SIGNAL alu_ctrl_sig : STD_LOGIC_VECTOR( 2 DOWNTO 0 );
	65	SIGNAL alu_comp_sig : STD_LOGIC_VECTOR( 1 DOWNTO 0 );
	66
	67	BEGIN
	68
	69	alu_ctrl <= alu_ctrl_sig;
	70	alu_comp <= alu_comp_sig;
	71
	72	BUTTERFLY_DATAFLOW_1 : BUTTERFLY_DATAFLOW
	73	GENERIC MAP (
	74	Sample_SZ => 16)
	75	PORT MAP (
	76	rstn => rstn,
	77	clk => clk,
	78
	79	Are => Are,
	80	Aim => Aim,
	81	Bre => Bre,
	82	Bim => Bim,
	83	c_in => c_in,
	84	cps_in => cps_in,
	85	cms_in => cms_in,
	86
	87	op1 => op1,
	88	op2 => op2,
	89
	90	out_alu => butterfly_out,
	91
	92	sel_op1 => sel_op1,
	93	sel_op2 => sel_op2,
	94	sel_xyz => sel_xyz,
	95	alu_ctrl => alu_ctrl_sig,
	96	alu_comp => alu_comp_sig
	97	);
	98
	99	BUTTERFLY_CTRL_1 : BUTTERFLY_CTRL
	100	PORT MAP(
	101	rstn => rstn,
	102	clk => clk,
	103
	104	sample_in_val => sample_in_val,
	105	sample_out_val => sample_out_val,
	106
	107	sel_op1 => sel_op1,
	108	sel_op2 => sel_op2,
	109	sel_xyz => sel_xyz,
	110	sel_out => sel_out,
	111	alu_ctrl => alu_ctrl_sig,
	112	alu_comp => alu_comp_sig
	113	);
	114
	115	END ar_BUTTERFLY_TOP; No newline at end of file

lib/staging/LPP/PLE/dsp/lpp_fft/LPP_BUTTERFLY_DATAFLOW.vhd created 644 +129 0

@@ -0,0 +1,129
	1	------------------------------------------------------------------------------
	2	-- This file is a part of the LPP VHDL IP LIBRARY
	3	-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
	4	--
	5	-- This program is free software; you can redistribute it and/or modify
	6	-- it under the terms of the GNU General Public License as published by
	7	-- the Free Software Foundation; either version 3 of the License, or
	8	-- (at your option) any later version.
	9	--
	10	-- This program is distributed in the hope that it will be useful,
	11	-- but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	-- GNU General Public License for more Cdetails.
	14	--
	15	-- You should have received a copy of the GNU General Public License
	16	-- along with this program; if not, write to the Free Software
	17	-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	18	-------------------------------------------------------------------------------
	19	-- Author : Paul LEROY
	20	-- Mail : paul.leroy@lpp.polytechnique.fr
	21	-------------------------------------------------------------------------------
	22
	23	LIBRARY IEEE;
	24	USE IEEE.numeric_std.ALL;
	25	USE IEEE.std_logic_1164.ALL;
	26	LIBRARY staging_lpp;
	27	USE staging_lpp.PLE_general_purpose.ALL;
	28
	29	ENTITY BUTTERFLY_DATAFLOW IS
	30	GENERIC (
	31	Sample_SZ : INTEGER := 16
	32	);
	33	PORT (
	34	rstn : IN STD_LOGIC;
	35	clk : IN STD_LOGIC;
	36
	37	Are : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0);
	38	Aim : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0);
	39	Bre : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0);
	40	Bim : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0);
	41	c_in : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0);
	42	cps_in : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0);
	43	cms_in : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0);
	44
	45	op1 : OUT STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0);
	46	op2 : OUT STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0);
	47
	48	out_alu : OUT STD_LOGIC_VECTOR ( 2*Sample_SZ-1 DOWNTO 0);
	49
	50	sel_op1 : IN STD_LOGIC_VECTOR( 4 DOWNTO 0 ); -- Are Aim X Y Z
	51	sel_op2 : IN STD_LOGIC_VECTOR( 4 DOWNTO 0 ); -- Bre Bim C_in cps_in cms_in
	52	sel_xyz : IN STD_LOGIC_VECTOR( 2 DOWNTO 0 ); -- X Y Z
	53	alu_ctrl : IN STD_LOGIC_VECTOR( 2 DOWNTO 0 );
	54	alu_comp : IN STD_LOGIC_VECTOR( 1 DOWNTO 0 )
	55	);
	56	END BUTTERFLY_DATAFLOW;
	57
	58	ARCHITECTURE ar_BUTTERFLY_DATAFLOW OF BUTTERFLY_DATAFLOW IS
	59
	60	SIGNAL X : STD_LOGIC_VECTOR( Sample_SZ-1 DOWNTO 0 );
	61	SIGNAL Y : STD_LOGIC_VECTOR( Sample_SZ-1 DOWNTO 0 );
	62	SIGNAL Z : STD_LOGIC_VECTOR( Sample_SZ-1 DOWNTO 0 );
	63
	64	SIGNAL ALU_OP1 : STD_LOGIC_VECTOR( Sample_SZ-1 DOWNTO 0 );
	65	SIGNAL ALU_OP2 : STD_LOGIC_VECTOR( Sample_SZ-1 DOWNTO 0 );
	66
	67	SIGNAL OUT_ALU_SIG : STD_LOGIC_VECTOR ( 2*Sample_SZ-1 DOWNTO 0);
	68
	69	BEGIN
	70
	71	out_alu <= OUT_ALU_SIG;
	72
	73	PROCESS (clk, rstn)
	74
	75	BEGIN -- PROCESS
	76	IF rstn = '0' THEN -- asynchronous reset (active low)
	77	X <= (OTHERS => '0');
	78	Y <= (OTHERS => '0');
	79	Z <= (OTHERS => '0');
	80
	81	ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
	82
	83	if sel_xyz = "100" THEN
	84	X <= STD_LOGIC_VECTOR(resize(SIGNED(OUT_ALU_SIG), Sample_SZ));
	85	elsif sel_xyz = "010" THEN
	86	Y <= STD_LOGIC_VECTOR(resize(SIGNED(OUT_ALU_SIG), Sample_SZ));
	87	elsif sel_xyz = "001" THEN
	88	Z <= STD_LOGIC_VECTOR(resize(SIGNED(OUT_ALU_SIG), Sample_SZ));
	89	end if;
	90
	91	END IF;
	92
	93	END PROCESS;
	94
	95	op1 <= ALU_OP1;
	96	op2 <= ALU_OP2;
	97
	98	ALU_OP1 <= Are WHEN sel_op1 = "10000" ELSE
	99	Aim WHEN sel_op1 = "01000" ELSE
	100	X WHEN sel_op1 = "00100" ELSE
	101	Y WHEN sel_op1 = "00010" ELSE
	102	Z WHEN sel_op1 = "00001" ELSE
	103	STD_LOGIC_VECTOR(resize(SIGNED(OUT_ALU_SIG), Sample_SZ)) WHEN sel_op1 = "00000" ELSE
	104	(OTHERS => '0');
	105
	106	ALU_OP2 <= Bre WHEN sel_op2 = "10000" ELSE
	107	Bim WHEN sel_op2 = "01000" ELSE
	108	c_in WHEN sel_op2 = "00100" ELSE
	109	cps_in WHEN sel_op2 = "00010" ELSE
	110	cms_in WHEN sel_op2 = "00001" ELSE
	111	std_logic_vector(TO_SIGNED(1,Sample_SZ)) WHEN sel_op2 = "00000" ELSE
	112	(OTHERS => '0');
	113
	114	ALU_1: ALU
	115	GENERIC MAP (
	116	Arith_en => 1,
	117	Input_SZ_1 => Sample_SZ,
	118	Input_SZ_2 => Sample_SZ,
	119	COMP_EN => 0) -- comp is enable when COMP_EN is 0
	120	PORT MAP (
	121	clk => clk,
	122	reset => rstn,
	123	ctrl => alu_ctrl,
	124	comp => alu_comp,
	125	OP1 => ALU_OP1,
	126	OP2 => ALU_OP2,
	127	RES => OUT_ALU_SIG);
	128
	129	END ar_BUTTERFLY_DATAFLOW; No newline at end of file

lib/staging/LPP/PLE/dsp/lpp_fft/lpp_fft.vhd created 644 +102 0

@@ -0,0 +1,102
	1	------------------------------------------------------------------------------
	2	-- This file is a part of the LPP VHDL IP LIBRARY
	3	-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
	4	--
	5	-- This program is free software; you can redistribute it and/or modify
	6	-- it under the terms of the GNU General Public License as published by
	7	-- the Free Software Foundation; either version 3 of the License, or
	8	-- (at your option) any later version.
	9	--
	10	-- This program is distributed in the hope that it will be useful,
	11	-- but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	-- GNU General Public License for more details.
	14	--
	15	-- You should have received a copy of the GNU General Public License
	16	-- along with this program; if not, write to the Free Software
	17	-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	18	-------------------------------------------------------------------------------
	19	-- Author : Paul Leroy
	20	-- Mail : paul.leroy@lpp.polytechnique.fr
	21	----------------------------------------------------------------------------
	22
	23
	24	LIBRARY ieee;
	25	USE ieee.std_logic_1164.ALL;
	26
	27	PACKAGE PLE_lpp_fft IS
	28
	29	COMPONENT BUTTERFLY_DATAFLOW
	30	GENERIC (
	31	Sample_SZ : INTEGER := 16);
	32	PORT (
	33	rstn : IN STD_LOGIC;
	34	clk : IN STD_LOGIC;
	35
	36	Are : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0);
	37	Aim : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0);
	38	Bre : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0);
	39	Bim : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0);
	40	c_in : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0);
	41	cps_in : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0);
	42	cms_in : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0);
	43
	44	op1 : OUT STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0);
	45	op2 : OUT STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0);
	46
	47	out_alu : OUT STD_LOGIC_VECTOR ( 2*Sample_SZ-1 DOWNTO 0);
	48
	49	sel_op1 : IN STD_LOGIC_VECTOR( 4 DOWNTO 0 ); -- Are Aim X Y Z
	50	sel_op2 : IN STD_LOGIC_VECTOR( 4 DOWNTO 0 ); -- Bre Bim C_in cps_in cms_in
	51	sel_xyz : IN STD_LOGIC_VECTOR( 2 DOWNTO 0 ); -- X Y Z
	52	alu_ctrl : IN STD_LOGIC_VECTOR( 2 DOWNTO 0 );
	53	alu_comp : IN STD_LOGIC_VECTOR( 1 DOWNTO 0 )
	54	);
	55	END COMPONENT;
	56
	57	COMPONENT BUTTERFLY_CTRL
	58	PORT (
	59	rstn : IN STD_LOGIC;
	60	clk : IN STD_LOGIC;
	61
	62	sample_in_val : IN STD_LOGIC;
	63	sample_out_val : OUT STD_LOGIC;
	64
	65	sel_op1 : OUT STD_LOGIC_VECTOR( 4 DOWNTO 0 ); -- Are Aim X Y Z
	66	sel_op2 : OUT STD_LOGIC_VECTOR( 4 DOWNTO 0 ); -- Bre Bim C_in cps_in cms_in
	67	sel_xyz : OUT STD_LOGIC_VECTOR( 2 DOWNTO 0 ); -- X Y Z
	68	sel_out : OUT STD_LOGIC_VECTOR( 4 DOWNTO 0 );
	69	alu_ctrl : OUT STD_LOGIC_VECTOR( 2 DOWNTO 0 );
	70	alu_comp : OUT STD_LOGIC_VECTOR( 1 DOWNTO 0 )
	71	);
	72	END COMPONENT;
	73
	74	COMPONENT BUTTERFLY_TOP
	75	GENERIC (
	76	Sample_SZ : INTEGER := 16);
	77	PORT (
	78	rstn : IN STD_LOGIC;
	79	clk : IN STD_LOGIC;
	80
	81	sample_in_val : IN STD_LOGIC;
	82	sample_out_val : OUT STD_LOGIC;
	83
	84	Are : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0);
	85	Aim : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0);
	86	Bre : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0);
	87	Bim : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0);
	88	c_in : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0);
	89	cps_in : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0);
	90	cms_in : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0);
	91
	92	op1 : OUT STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0);
	93	op2 : OUT STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0);
	94	alu_ctrl : OUT STD_LOGIC_VECTOR( 2 DOWNTO 0 );
	95	alu_comp : OUT STD_LOGIC_VECTOR( 1 DOWNTO 0 );
	96
	97	butterfly_out : OUT STD_LOGIC_VECTOR ( 2*Sample_SZ-1 DOWNTO 0);
	98	sel_out : OUT STD_LOGIC_VECTOR ( 4 DOWNTO 0)
	99	);
	100	END COMPONENT;
	101
	102	END; No newline at end of file

lib/staging/LPP/PLE/dsp/lpp_fft/test/modelsim.ini created 644 +337 0

@@ -0,0 +1,337
	1	; Copyright 1991-2010 Mentor Graphics Corporation
	2	;
	3	; All Rights Reserved.
	4	;
	5	; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF
	6	; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
	7	;
	8
	9	[Library]
	10	others = $MODEL_TECH/../modelsim.ini
	11
	12	; Actel Primitive Libraries
	13	;
	14	; VHDL Section
	15	;
	16	;aact1 = $MODEL_TECH/../actel/vhdl/aact1
	17	;aact2 = $MODEL_TECH/../actel/vhdl/aact2
	18	;aact3 = $MODEL_TECH/../actel/vhdl/aact3
	19	;a3200dx = $MODEL_TECH/../actel/vhdl/a3200dx
	20	;a40mx = $MODEL_TECH/../actel/vhdl/a40mx
	21	;a42mx = $MODEL_TECH/../actel/vhdl/a42mx
	22	;a54sxa = $MODEL_TECH/../actel/vhdl/a54sxa
	23	;
	24	; Verilog Section
	25	;
	26	;act1 = $MODEL_TECH/../actel/verilog/act1
	27	;act2 = $MODEL_TECH/../actel/verilog/act2
	28	;act3 = $MODEL_TECH/../actel/verilog/act3
	29	;3200dx = $MODEL_TECH/../actel/verilog/3200dx
	30	;40mx = $MODEL_TECH/../actel/verilog/40mx
	31	;42mx = $MODEL_TECH/../actel/verilog/42mx
	32	;54sxa = $MODEL_TECH/../actel/verilog/54sxa
	33
	34	staging_lpp = staging_lpp
	35	[vcom]
	36	; VHDL93 variable selects language version as the default.
	37	; Default is VHDL-2002.
	38	; Value of 0 or 1987 for VHDL-1987.
	39	; Value of 1 or 1993 for VHDL-1993.
	40	; Default or value of 2 or 2002 for VHDL-2002.
	41	VHDL93 = 2002
	42
	43	; Show source line containing error. Default is off.
	44	; Show_source = 1
	45
	46	; Turn off unbound-component warnings. Default is on.
	47	; Show_Warning1 = 0
	48
	49	; Turn off process-without-a-wait-statement warnings. Default is on.
	50	; Show_Warning2 = 0
	51
	52	; Turn off null-range warnings. Default is on.
	53	; Show_Warning3 = 0
	54
	55	; Turn off no-space-in-time-literal warnings. Default is on.
	56	; Show_Warning4 = 0
	57
	58	; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on.
	59	; Show_Warning5 = 0
	60
	61	; Turn off optimization for IEEE std_logic_1164 package. Default is on.
	62	; Optimize_1164 = 0
	63
	64	; Turn on resolving of ambiguous function overloading in favor of the
	65	; "explicit" function declaration (not the one automatically created by
	66	; the compiler for each type declaration). Default is off.
	67	; The .ini file has Explicit enabled so that std_logic_signed/unsigned
	68	; will match the behavior of synthesis tools.
	69	Explicit = 1
	70
	71	; Turn off acceleration of the VITAL packages. Default is to accelerate.
	72	; NoVital = 1
	73
	74	; Turn off VITAL compliance checking. Default is checking on.
	75	; NoVitalCheck = 1
	76
	77	; Ignore VITAL compliance checking errors. Default is to not ignore.
	78	; IgnoreVitalErrors = 1
	79
	80	; Turn off VITAL compliance checking warnings. Default is to show warnings.
	81	; Show_VitalChecksWarnings = 0
	82
	83	; Keep silent about case statement static warnings.
	84	; Default is to give a warning.
	85	; NoCaseStaticError = 1
	86
	87	; Keep silent about warnings caused by aggregates that are not locally static.
	88	; Default is to give a warning.
	89	; NoOthersStaticError = 1
	90
	91	; Turn off inclusion of debugging info within design units.
	92	; Default is to include debugging info.
	93	; NoDebug = 1
	94
	95	; Turn off "Loading..." messages. Default is messages on.
	96	; Quiet = 1
	97
	98	; Turn on some limited synthesis rule compliance checking. Checks only:
	99	; -- signals used (read) by a process must be in the sensitivity list
	100	; CheckSynthesis = 1
	101
	102	; Activate optimizations on expressions that do not involve signals,
	103	; waits, or function/procedure/task invocations. Default is off.
	104	; ScalarOpts = 1
	105
	106	; Require the user to specify a configuration for all bindings,
	107	; and do not generate a compile time default binding for the
	108	; component. This will result in an elaboration error of
	109	; 'component not bound' if the user fails to do so. Avoids the rare
	110	; issue of a false dependency upon the unused default binding.
	111	; RequireConfigForAllDefaultBinding = 1
	112
	113	; Inhibit range checking on subscripts of arrays. Range checking on
	114	; scalars defined with subtypes is inhibited by default.
	115	; NoIndexCheck = 1
	116
	117	; Inhibit range checks on all (implicit and explicit) assignments to
	118	; scalar objects defined with subtypes.
	119	; NoRangeCheck = 1
	120
	121	[vlog]
	122
	123	; Turn off inclusion of debugging info within design units.
	124	; Default is to include debugging info.
	125	; NoDebug = 1
	126
	127	; Turn off "loading..." messages. Default is messages on.
	128	; Quiet = 1
	129
	130	; Turn on Verilog hazard checking (order-dependent accessing of global vars).
	131	; Default is off.
	132	; Hazard = 1
	133
	134	; Turn on converting regular Verilog identifiers to uppercase. Allows case
	135	; insensitivity for module names. Default is no conversion.
	136	; UpCase = 1
	137
	138	; Turn on incremental compilation of modules. Default is off.
	139	; Incremental = 1
	140
	141	; Turns on lint-style checking.
	142	; Show_Lint = 1
	143
	144	[vsim]
	145	; Simulator resolution
	146	; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100.
	147	Resolution = ps
	148
	149	; User time unit for run commands
	150	; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the
	151	; unit specified for Resolution. For example, if Resolution is 100ps,
	152	; then UserTimeUnit defaults to ps.
	153	; Should generally be set to default.
	154	UserTimeUnit = default
	155
	156	; Default run length
	157	RunLength = 100
	158
	159	; Maximum iterations that can be run without advancing simulation time
	160	IterationLimit = 5000
	161
	162	; Directive to license manager:
	163	; vhdl Immediately reserve a VHDL license
	164	; vlog Immediately reserve a Verilog license
	165	; plus Immediately reserve a VHDL and Verilog license
	166	; nomgc Do not look for Mentor Graphics Licenses
	167	; nomti Do not look for Model Technology Licenses
	168	; noqueue Do not wait in the license queue when a license isn't available
	169	; viewsim Try for viewer license but accept simulator license(s) instead
	170	; of queuing for viewer license
	171	; License = plus
	172
	173	; Stop the simulator after a VHDL/Verilog assertion message
	174	; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal
	175	BreakOnAssertion = 3
	176
	177	; Assertion Message Format
	178	; %S - Severity Level
	179	; %R - Report Message
	180	; %T - Time of assertion
	181	; %D - Delta
	182	; %I - Instance or Region pathname (if available)
	183	; %% - print '%' character
	184	; AssertionFormat = "** %S: %R\n Time: %T Iteration: %D%I\n"
	185
	186	; Assertion File - alternate file for storing VHDL/Verilog assertion messages
	187	; AssertFile = assert.log
	188
	189	; Default radix for all windows and commands...
	190	; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned
	191	DefaultRadix = symbolic
	192
	193	; VSIM Startup command
	194	; Startup = do startup.do
	195
	196	; File for saving command transcript
	197	TranscriptFile = transcript
	198
	199	; File for saving command history
	200	; CommandHistory = cmdhist.log
	201
	202	; Specify whether paths in simulator commands should be described
	203	; in VHDL or Verilog format.
	204	; For VHDL, PathSeparator = /
	205	; For Verilog, PathSeparator = .
	206	; Must not be the same character as DatasetSeparator.
	207	PathSeparator = /
	208
	209	; Specify the dataset separator for fully rooted contexts.
	210	; The default is ':'. For example, sim:/top
	211	; Must not be the same character as PathSeparator.
	212	DatasetSeparator = :
	213
	214	; Disable VHDL assertion messages
	215	; IgnoreNote = 1
	216	; IgnoreWarning = 1
	217	; IgnoreError = 1
	218	; IgnoreFailure = 1
	219
	220	; Default force kind. May be freeze, drive, deposit, or default
	221	; or in other terms, fixed, wired, or charged.
	222	; A value of "default" will use the signal kind to determine the
	223	; force kind, drive for resolved signals, freeze for unresolved signals
	224	; DefaultForceKind = freeze
	225
	226	; If zero, open files when elaborated; otherwise, open files on
	227	; first read or write. Default is 0.
	228	; DelayFileOpen = 1
	229
	230	; Control VHDL files opened for write.
	231	; 0 = Buffered, 1 = Unbuffered
	232	UnbufferedOutput = 0
	233
	234	; Control the number of VHDL files open concurrently.
	235	; This number should always be less than the current ulimit
	236	; setting for max file descriptors.
	237	; 0 = unlimited
	238	ConcurrentFileLimit = 40
	239
	240	; Control the number of hierarchical regions displayed as
	241	; part of a signal name shown in the Wave window.
	242	; A value of zero tells VSIM to display the full name.
	243	; The default is 0.
	244	; WaveSignalNameWidth = 0
	245
	246	; Turn off warnings from the std_logic_arith, std_logic_unsigned
	247	; and std_logic_signed packages.
	248	; StdArithNoWarnings = 1
	249
	250	; Turn off warnings from the IEEE numeric_std and numeric_bit packages.
	251	; NumericStdNoWarnings = 1
	252
	253	; Control the format of the (VHDL) FOR generate statement label
	254	; for each iteration. Do not quote it.
	255	; The format string here must contain the conversion codes %s and %d,
	256	; in that order, and no other conversion codes. The %s represents
	257	; the generate_label; the %d represents the generate parameter value
	258	; at a particular generate iteration (this is the position number if
	259	; the generate parameter is of an enumeration type). Embedded whitespace
	260	; is allowed (but discouraged); leading and trailing whitespace is ignored.
	261	; Application of the format must result in a unique scope name over all
	262	; such names in the design so that name lookup can function properly.
	263	; GenerateFormat = %s__%d
	264
	265	; Specify whether checkpoint files should be compressed.
	266	; The default is 1 (compressed).
	267	; CheckpointCompressMode = 0
	268
	269	; List of dynamically loaded objects for Verilog PLI applications
	270	; Veriuser = veriuser.sl
	271
	272	; Specify default options for the restart command. Options can be one
	273	; or more of: -force -nobreakpoint -nolist -nolog -nowave
	274	; DefaultRestartOptions = -force
	275
	276	; HP-UX 10.20 ONLY - Enable memory locking to speed up large designs
	277	; (> 500 megabyte memory footprint). Default is disabled.
	278	; Specify number of megabytes to lock.
	279	; LockedMemory = 1000
	280
	281	; Turn on (1) or off (0) WLF file compression.
	282	; The default is 1 (compress WLF file).
	283	; WLFCompress = 0
	284
	285	; Specify whether to save all design hierarchy (1) in the WLF file
	286	; or only regions containing logged signals (0).
	287	; The default is 0 (save only regions with logged signals).
	288	; WLFSaveAllRegions = 1
	289
	290	; WLF file time limit. Limit WLF file by time, as closely as possible,
	291	; to the specified amount of simulation time. When the limit is exceeded
	292	; the earliest times get truncated from the file.
	293	; If both time and size limits are specified the most restrictive is used.
	294	; UserTimeUnits are used if time units are not specified.
	295	; The default is 0 (no limit). Example: WLFTimeLimit = {100 ms}
	296	; WLFTimeLimit = 0
	297
	298	; WLF file size limit. Limit WLF file size, as closely as possible,
	299	; to the specified number of megabytes. If both time and size limits
	300	; are specified then the most restrictive is used.
	301	; The default is 0 (no limit).
	302	; WLFSizeLimit = 1000
	303
	304	; Specify whether or not a WLF file should be deleted when the
	305	; simulation ends. A value of 1 will cause the WLF file to be deleted.
	306	; The default is 0 (do not delete WLF file when simulation ends).
	307	; WLFDeleteOnQuit = 1
	308
	309	; Automatic SDF compilation
	310	; Disables automatic compilation of SDF files in flows that support it.
	311	; Default is on, uncomment to turn off.
	312	; NoAutoSDFCompile = 1
	313
	314	[lmc]
	315
	316	[msg_system]
	317	; Change a message severity or suppress a message.
	318	; The format is: <msg directive> = <msg number>[,<msg number>...]
	319	; Examples:
	320	; note = 3009
	321	; warning = 3033
	322	; error = 3010,3016
	323	; fatal = 3016,3033
	324	; suppress = 3009,3016,3043
	325	; The command verror <msg number> can be used to get the complete
	326	; description of a message.
	327
	328	; Control transcripting of elaboration/runtime messages.
	329	; The default is to have messages appear in the transcript and
	330	; recorded in the wlf file (messages that are recorded in the
	331	; wlf file can be viewed in the MsgViewer). The other settings
	332	; are to send messages only to the transcript or only to the
	333	; wlf file. The valid values are
	334	; both {default}
	335	; tran {transcript only}
	336	; wlf {wlf file only}
	337	; msgmode = both

lib/staging/LPP/PLE/dsp/lpp_fft/test/run.do created 644 +30 0

@@ -0,0 +1,30
	1	vlib staging_lpp
	2	vmap staging_lpp "staging_lpp"
	3
	4	vcom -93 -explicit -work staging_lpp "../../../general_purpose/general_purpose.vhd"
	5	vcom -93 -explicit -work staging_lpp "../../../general_purpose/MAC_CONTROLER.vhd"
	6	vcom -93 -explicit -work staging_lpp "../../../general_purpose/Multiplier.vhd"
	7	vcom -93 -explicit -work staging_lpp "../../../general_purpose/Adder.vhd"
	8	vcom -93 -explicit -work staging_lpp "../../../general_purpose/TwoComplementer.vhd"
	9	vcom -93 -explicit -work staging_lpp "../../../general_purpose/MAC_REG.vhd"
	10	vcom -93 -explicit -work staging_lpp "../../../general_purpose/MAC_MUX.vhd"
	11	vcom -93 -explicit -work staging_lpp "../../../general_purpose/MAC_MUX2.vhd"
	12	vcom -93 -explicit -work staging_lpp "../../../general_purpose/MAC.vhd"
	13	vcom -93 -explicit -work staging_lpp "../../../general_purpose/ALU.vhd"
	14
	15	vcom -93 -explicit -work staging_lpp "../lpp_fft.vhd"
	16	vcom -93 -explicit -work staging_lpp "../LPP_BUTTERFLY_DATAFLOW.vhd"
	17	vcom -93 -explicit -work staging_lpp "../BUTTERFLY_CTRL.vhd"
	18	vcom -93 -explicit -work staging_lpp "../BUTTERFLY_TOP.vhd"
	19	vcom -93 -explicit -work staging_lpp "testBench_BUTTERFLY_TOP.vhd"
	20
	21	vsim -L staging_lpp -t 1ps staging_lpp.TestBench_BUTTERFLY_TOP
	22
	23	do wave.do
	24
	25	log -R *
	26
	27	run 1 us
	28	# The following lines are commented because no testbench is associated with the project
	29	# add wave /testbench/*
	30	# run 1000ns

lib/staging/LPP/PLE/dsp/lpp_fft/test/staging_lpp/_info created 644 +436 0

@@ -0,0 +1,436
	1	m255
	2	K3
	3	13
	4	cModel Technology
	5	Z0 dC:\VHDL\VHD_Lib-next\lib\staging\LPP\PLE\dsp\lpp_fft\test
	6	Eadder
	7	Z1 w1367492167
	8	Z2 DPx4 ieee 14 std_logic_1164 0 22 GH1=`jDDBJ=`LM;:Ak`kf2
	9	Z3 DPx4 ieee 11 numeric_std 0 22 =NSdli^?T5OD8;4F<blj<3
	10	Z4 dC:\VHDL\VHD_Lib-next\lib\staging\LPP\PLE\dsp\lpp_fft\test
	11	Z5 8../../../general_purpose/Adder.vhd
	12	Z6 F../../../general_purpose/Adder.vhd
	13	l0
	14	L26
	15	VoFM@XeC8`dJE];FJ5EZS62
	16	Z7 OW;C;6.6d;45
	17	31
	18	Z8 o-93 -explicit -work staging_lpp -O0
	19	Z9 tExplicit 1
	20	!s100 HIfJMPNI[=_daW0bOn4B93
	21	Aar_adder
	22	R2
	23	R3
	24	DEx4 work 5 adder 0 22 oFM@XeC8`dJE];FJ5EZS62
	25	l52
	26	L47
	27	V76IAS<9VXz9KglW`AJ8Ld3
	28	R7
	29	31
	30	Z10 Mx2 4 ieee 11 numeric_std
	31	Z11 Mx1 4 ieee 14 std_logic_1164
	32	R8
	33	R9
	34	!s100 J=IZ]JXJGi7g8KE`DCYDk0
	35	Ealu
	36	Z12 w1387453255
	37	Z13 DPx11 staging_lpp 19 ple_general_purpose 0 22 GgYZoG1iL[;Q6W7i9@@LK1
	38	R2
	39	R3
	40	R4
	41	Z14 8../../../general_purpose/ALU.vhd
	42	Z15 F../../../general_purpose/ALU.vhd
	43	l0
	44	L30
	45	VmEg_D0fVB_ZV1@FBk@aFd2
	46	R7
	47	31
	48	R8
	49	R9
	50	!s100 1nho@1aIf]5_E]d?WEDL92
	51	Aar_alu
	52	R13
	53	R2
	54	R3
	55	DEx4 work 3 alu 0 22 mEg_D0fVB_ZV1@FBk@aFd2
	56	l57
	57	L55
	58	VWjUk_]b@Sk^TfG4X_9Oc;2
	59	R7
	60	31
	61	Z16 Mx3 4 ieee 11 numeric_std
	62	Z17 Mx2 4 ieee 14 std_logic_1164
	63	Z18 Mx1 11 staging_lpp 19 ple_general_purpose
	64	R8
	65	R9
	66	!s100 X]Y0>a4c6R:;@zlk5miIO2
	67	Ebutterfly_ctrl
	68	Z19 w1387452436
	69	Z20 DPx11 staging_lpp 11 ple_lpp_fft 0 22 f<h7ZP]5PX4>R89[BSncW2
	70	R13
	71	R2
	72	R3
	73	R4
	74	Z21 8../BUTTERFLY_CTRL.vhd
	75	Z22 F../BUTTERFLY_CTRL.vhd
	76	l0
	77	L32
	78	VkQ?Y4JTf@DHzClk;BN8m?2
	79	R7
	80	31
	81	R8
	82	R9
	83	!s100 OFBC17;8gEg8J^PPd26]^0
	84	Aar_butterfly_ctrl
	85	R20
	86	R13
	87	R2
	88	R3
	89	DEx4 work 14 butterfly_ctrl 0 22 kQ?Y4JTf@DHzClk;BN8m?2
	90	l66
	91	L49
	92	VUOBVXO?RLc>P4cLYnIOJK3
	93	R7
	94	31
	95	Z23 Mx4 4 ieee 11 numeric_std
	96	Z24 Mx3 4 ieee 14 std_logic_1164
	97	Z25 Mx2 11 staging_lpp 19 ple_general_purpose
	98	Z26 Mx1 11 staging_lpp 11 ple_lpp_fft
	99	R8
	100	R9
	101	!s100 6jJJ^<^7KVK9YiOCAmAfk1
	102	Ebutterfly_dataflow
	103	Z27 w1387454361
	104	R13
	105	R2
	106	R3
	107	R4
	108	Z28 8../LPP_BUTTERFLY_DATAFLOW.vhd
	109	Z29 F../LPP_BUTTERFLY_DATAFLOW.vhd
	110	l0
	111	L29
	112	VI`_;hfaYCNQ1Zkm5<`LHT3
	113	R7
	114	31
	115	R8
	116	R9
	117	!s100 I>e@N:Zca9<ZOHLLWOFMc2
	118	Aar_butterfly_dataflow
	119	R13
	120	R2
	121	R3
	122	DEx4 work 18 butterfly_dataflow 0 22 I`_;hfaYCNQ1Zkm5<`LHT3
	123	l69
	124	L58
	125	V9jb[@[oeF?z?6BZP=Db;:2
	126	R7
	127	31
	128	R16
	129	R17
	130	R18
	131	R8
	132	R9
	133	!s100 ]RTo^ViMemeIA;L0:4EiO2
	134	Ebutterfly_top
	135	Z30 w1387454433
	136	R20
	137	R13
	138	R2
	139	R3
	140	R4
	141	Z31 8../BUTTERFLY_TOP.vhd
	142	Z32 F../BUTTERFLY_TOP.vhd
	143	l0
	144	L31
	145	Vk:EL]Kgc6lPW6FVMb6M=c1
	146	R7
	147	31
	148	R8
	149	R9
	150	!s100 zDSRB=<7mP`35NFaM3k;d2
	151	Aar_butterfly_top
	152	R20
	153	R13
	154	R2
	155	R3
	156	DEx4 work 13 butterfly_top 0 22 k:EL]Kgc6lPW6FVMb6M=c1
	157	l67
	158	L59
	159	VJQVgjbV4Dbd?2l5^]><VR2
	160	!s100 1WiJUEMk^A1MjhRPz66P_1
	161	R7
	162	31
	163	R23
	164	R24
	165	R25
	166	R26
	167	R8
	168	R9
	169	Emac
	170	Z33 w1387453300
	171	R13
	172	R2
	173	R3
	174	R4
	175	Z34 8../../../general_purpose/MAC.vhd
	176	Z35 F../../../general_purpose/MAC.vhd
	177	l0
	178	L32
	179	Vz:J>WlmWN@nE@`EDad]Cf2
	180	R7
	181	31
	182	R8
	183	R9
	184	!s100 22G:]MmP6`P]S5a<^zaIG3
	185	Aar_mac
	186	R13
	187	R2
	188	R3
	189	DEx4 work 3 mac 0 22 z:J>WlmWN@nE@`EDad]Cf2
	190	l86
	191	L54
	192	V3nAA^GI7Ym8m@PF<9[<a_0
	193	R7
	194	31
	195	R16
	196	R17
	197	R18
	198	R8
	199	R9
	200	!s100 [;@eekK>0=cIVS2X`8MPG0
	201	Emac_controler
	202	R1
	203	R2
	204	R3
	205	R4
	206	Z36 8../../../general_purpose/MAC_CONTROLER.vhd
	207	Z37 F../../../general_purpose/MAC_CONTROLER.vhd
	208	l0
	209	L29
	210	V3F`]dJZY][ZC4@mMDbUjF1
	211	R7
	212	31
	213	R8
	214	R9
	215	!s100 AEHI=CKBB^Y`BRI6Wkb653
	216	Aar_mac_controler
	217	R2
	218	R3
	219	DEx4 work 13 mac_controler 0 22 3F`]dJZY][ZC4@mMDbUjF1
	220	l47
	221	L45
	222	VYKjYF<4O[WUG`U:VRF4<F1
	223	R7
	224	31
	225	R10
	226	R11
	227	R8
	228	R9
	229	!s100 1L?0[RS=fbiUd8o?JRAiJ0
	230	Emac_mux
	231	R1
	232	R2
	233	R3
	234	R4
	235	Z38 8../../../general_purpose/MAC_MUX.vhd
	236	Z39 F../../../general_purpose/MAC_MUX.vhd
	237	l0
	238	L26
	239	V=[k`JBkCz>0=MgDKG1ihL1
	240	R7
	241	31
	242	R8
	243	R9
	244	!s100 VY:^W494N<Y1A=ES9nhFi3
	245	Aar_mac_mux
	246	R2
	247	R3
	248	DEx4 work 7 mac_mux 0 22 =[k`JBkCz>0=MgDKG1ihL1
	249	l48
	250	L46
	251	VY>F?32o4EN<;M8QdcmA>e3
	252	R7
	253	31
	254	R10
	255	R11
	256	R8
	257	R9
	258	!s100 <4^2O;J:P]mD1VL;cC1fD0
	259	Emac_mux2
	260	R1
	261	R2
	262	R3
	263	R4
	264	Z40 8../../../general_purpose/MAC_MUX2.vhd
	265	Z41 F../../../general_purpose/MAC_MUX2.vhd
	266	l0
	267	L27
	268	V^N``KIm1zV?_lMP8EliHk2
	269	R7
	270	31
	271	R8
	272	R9
	273	!s100 TE[`n?T8Qd3^G^XaQFk5m1
	274	Aar_mac_mux2
	275	R2
	276	R3
	277	DEx4 work 8 mac_mux2 0 22 ^N``KIm1zV?_lMP8EliHk2
	278	l42
	279	L40
	280	VhnJjfYH]b0mK:U5e86_Y93
	281	R7
	282	31
	283	R10
	284	R11
	285	R8
	286	R9
	287	!s100 k<jPd;^:@^bWDF>W7HO<H2
	288	Emac_reg
	289	R1
	290	R2
	291	R3
	292	R4
	293	Z42 8../../../general_purpose/MAC_REG.vhd
	294	Z43 F../../../general_purpose/MAC_REG.vhd
	295	l0
	296	L26
	297	V2ciJdFnYB6EEZEC2GLc_z1
	298	R7
	299	31
	300	R8
	301	R9
	302	!s100 kXk_2M@5koRY^4=;=B5n<2
	303	Aar_mac_reg
	304	R2
	305	R3
	306	DEx4 work 7 mac_reg 0 22 2ciJdFnYB6EEZEC2GLc_z1
	307	l39
	308	L38
	309	VB[9zMRU>Q26jFZ8lM42Fj3
	310	R7
	311	31
	312	R10
	313	R11
	314	R8
	315	R9
	316	!s100 7LMbI<5IG<5UVHOI:=m>Y2
	317	Emultiplier
	318	R1
	319	R2
	320	R3
	321	R4
	322	Z44 8../../../general_purpose/Multiplier.vhd
	323	Z45 F../../../general_purpose/Multiplier.vhd
	324	l0
	325	L26
	326	VGSdU:4<=H75L72@<e3jZY0
	327	R7
	328	31
	329	R8
	330	R9
	331	!s100 5OhAd4m5P@V?>b^FY2MR80
	332	Aar_multiplier
	333	R2
	334	R3
	335	DEx4 work 10 multiplier 0 22 GSdU:4<=H75L72@<e3jZY0
	336	l52
	337	L46
	338	Vj]Tio_1A9KeM65>kBeBz42
	339	R7
	340	31
	341	R10
	342	R11
	343	R8
	344	R9
	345	!s100 1GiXjgO@4a3lmRe?YB9lz2
	346	Pple_general_purpose
	347	R2
	348	w1387453210
	349	R4
	350	8../../../general_purpose/general_purpose.vhd
	351	F../../../general_purpose/general_purpose.vhd
	352	l0
	353	L31
	354	VGgYZoG1iL[;Q6W7i9@@LK1
	355	R7
	356	31
	357	R11
	358	R8
	359	R9
	360	!s100 bfW]gJ3gFYVT@iCLKo6Xm2
	361	Pple_lpp_fft
	362	R2
	363	w1387452424
	364	R4
	365	8../lpp_fft.vhd
	366	F../lpp_fft.vhd
	367	l0
	368	L27
	369	Vf<h7ZP]5PX4>R89[BSncW2
	370	R7
	371	31
	372	R11
	373	R8
	374	R9
	375	!s100 5V=4M]3TdF65AgWJYe3e23
	376	Etestbench_butterfly_top
	377	Z46 w1387454494
	378	R20
	379	R2
	380	R3
	381	R4
	382	Z47 8testBench_BUTTERFLY_TOP.vhd
	383	Z48 FtestBench_BUTTERFLY_TOP.vhd
	384	l0
	385	L29
	386	V1NXi==_N]Mcd]D[Rf<oil3
	387	!s100 QZ0NIM1RVC:<gjZijToNY0
	388	R7
	389	31
	390	R8
	391	R9
	392	Atestbench_butterfly_top
	393	R20
	394	R2
	395	R3
	396	Z49 DEx4 work 23 testbench_butterfly_top 0 22 1NXi==_N]Mcd]D[Rf<oil3
	397	l60
	398	L33
	399	Z50 V6F:S5YodREYU8j7idB;CN2
	400	Z51 !s100 f@<W8j;z2U<TEMAm>:5?k2
	401	R7
	402	31
	403	R16
	404	R17
	405	R26
	406	R8
	407	R9
	408	Etwocomplementer
	409	Z52 w1366617970
	410	R2
	411	R3
	412	R4
	413	Z53 8../../../general_purpose/TwoComplementer.vhd
	414	Z54 F../../../general_purpose/TwoComplementer.vhd
	415	l0
	416	L28
	417	V`TEQ4_Q_P_Y7Z7dOQO66=2
	418	R7
	419	31
	420	R8
	421	R9
	422	!s100 1O<5a9=J>TiS<hJJ6?m5e2
	423	Aar_twocomplementer
	424	R2
	425	R3
	426	DEx4 work 15 twocomplementer 0 22 `TEQ4_Q_P_Y7Z7dOQO66=2
	427	l48
	428	L42
	429	VK6c;jL`g2cP38WSQDF7SE1
	430	R7
	431	31
	432	R10
	433	R11
	434	R8
	435	R9
	436	!s100 R>0SnLVVTWS?2cafMo=@W0

lib/staging/LPP/PLE/dsp/lpp_fft/test/staging_lpp/_vmake created 644 +3 0

@@ -0,0 +1,3
	1	m255
	2	K3
	3	cModel Technology

lib/staging/LPP/PLE/dsp/lpp_fft/test/staging_lpp/adder/_primary.dat created 644 binary 0 0