# HG changeset patch # User paul # Date 2013-12-19 12:06:51 # Node ID 74232a5eafa5a328e0a74676b38f54b3cbfe0a47 # Parent fc03c123dc361639108ea75be0ffa80266569ae4 first commit in branch "next" diff --git a/lib/staging/LPP/PLE/dsp/lpp_fft/BUTTERFLY_CTRL.vhd b/lib/staging/LPP/PLE/dsp/lpp_fft/BUTTERFLY_CTRL.vhd new file mode 100644 --- /dev/null +++ b/lib/staging/LPP/PLE/dsp/lpp_fft/BUTTERFLY_CTRL.vhd @@ -0,0 +1,209 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more Cdetails. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Paul LEROY +-- Mail : paul.leroy@lpp.polytechnique.fr +------------------------------------------------------------------------------- + +LIBRARY IEEE; +USE IEEE.numeric_std.ALL; +USE IEEE.std_logic_1164.ALL; + +LIBRARY staging_lpp; +--USE lpp.general_purpose.ALL; +use staging_lpp.PLE_general_purpose.all; +use staging_lpp.PLE_lpp_fft.all; + +ENTITY BUTTERFLY_CTRL IS + PORT ( + rstn : IN STD_LOGIC; + clk : IN STD_LOGIC; + + sample_in_val : IN STD_LOGIC; + sample_out_val : OUT STD_LOGIC; + + sel_op1 : OUT STD_LOGIC_VECTOR( 4 DOWNTO 0 ); -- Are Aim X Y Z + sel_op2 : OUT STD_LOGIC_VECTOR( 4 DOWNTO 0 ); -- Bre Bim C_in cps_in cms_in + sel_xyz : OUT STD_LOGIC_VECTOR( 2 DOWNTO 0 ); -- X Y Z + sel_out : OUT STD_LOGIC_VECTOR( 4 DOWNTO 0 ); + alu_ctrl : OUT STD_LOGIC_VECTOR( 2 DOWNTO 0 ); + alu_comp : OUT STD_LOGIC_VECTOR( 1 DOWNTO 0 ) + ); +END BUTTERFLY_CTRL; + +ARCHITECTURE ar_BUTTERFLY_CTRL OF BUTTERFLY_CTRL IS + + TYPE fsm_BUTTERFLY_CTRL_T IS ( clearMAC, + waiting, + add1, + add2, + add3, + add4, + mult5, + mac6, + mac7, + mult8, + mac9, + last10, + last11); + SIGNAL BUTTERFLY_CTRL_STATE : fsm_BUTTERFLY_CTRL_T; + +BEGIN + +PROCESS (clk, rstn) + + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + --REG ------------------------------------------------------------------- + sel_xyz <= (OTHERS => '0'); + sel_out <= (OTHERS => '0'); + --ALU ------------------------------------------------------------------- + sel_op1 <= (OTHERS => '0'); + sel_op2 <= (OTHERS => '0'); + alu_ctrl <= ctrl_IDLE; + alu_comp <= (OTHERS => '0'); + --OUT + sample_out_val <= '0'; + + BUTTERFLY_CTRL_STATE <= clearMAC; + + ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge + + CASE BUTTERFLY_CTRL_STATE IS + + WHEN clearMAC => + IF sample_in_val = '1' THEN + alu_ctrl <= ctrl_CLRMAC; + BUTTERFLY_CTRL_STATE <= waiting; + END IF; + + WHEN waiting => + sel_op1 <= "10000"; -- Are + sel_op2 <= "10000"; -- Bre + alu_comp <= "10"; + BUTTERFLY_CTRL_STATE <= add1; + + WHEN add1 => + sample_out_val <= '0'; + sel_op1 <= "01000"; -- Aim + sel_op2 <= "01000"; -- Bim + alu_comp <= "10"; + alu_ctrl <= ctrl_ADD; + sel_out <= "10000"; + BUTTERFLY_CTRL_STATE <= add2; + + WHEN add2 => + sample_out_val <= '0'; + sel_op1 <= "10000"; -- Are + sel_op2 <= "10000"; -- Bre + alu_comp <= "00"; + alu_ctrl <= ctrl_ADD; + sel_out <= "10000"; + BUTTERFLY_CTRL_STATE <= add3; + + WHEN add3 => + sample_out_val <= '0'; + sel_op1 <= "01000"; -- Aim + sel_op2 <= "01000"; -- Bim + alu_comp <= "00"; + alu_ctrl <= ctrl_ADD; + sel_out <= "10000"; + sel_xyz <= "100"; -- X + BUTTERFLY_CTRL_STATE <= add4; + + WHEN add4 => + sample_out_val <= '0'; + sel_op1 <= "00100"; -- X + sel_op2 <= "00100"; -- c + alu_comp <= "00"; + alu_ctrl <= ctrl_ADD; + sel_out <= "00000"; + sel_xyz <= "010"; + BUTTERFLY_CTRL_STATE <= mult5; + + WHEN mult5 => + sample_out_val <= '0'; + alu_ctrl <= ctrl_MULT; + sel_op1 <= "00010"; -- Y + sel_op2 <= "00100"; -- c + alu_comp <= "10"; + sel_out <= "00100"; + BUTTERFLY_CTRL_STATE <= mac6; + + WHEN mac6 => + sample_out_val <= '0'; + sel_op1 <= "00010"; -- Y + sel_op2 <= "00001"; -- cms + alu_comp <= "00"; + alu_ctrl <= ctrl_MAC; + sel_out <= "10000"; + BUTTERFLY_CTRL_STATE <= mac7; + + WHEN mac7 => + sample_out_val <= '0'; + sel_op1 <= "00100"; -- X + sel_op2 <= "00010"; -- cps + alu_ctrl <= ctrl_MAC; + alu_comp <= "00"; + sel_out <= "10000"; + BUTTERFLY_CTRL_STATE <= mult8; + + WHEN mult8 => + sample_out_val <= '0'; + alu_ctrl <= ctrl_MULT; + sel_op1 <= "00000"; -- Z is taken directly from the output of the ALU + sel_op2 <= "00000"; -- 1 + alu_comp <= "00"; + sel_out <= "10000"; + BUTTERFLY_CTRL_STATE <= mac9; + + WHEN mac9 => + sample_out_val <= '0'; + sel_op1 <= "10000"; + sel_op2 <= "10000"; + alu_ctrl <= ctrl_MAC; + alu_comp <= "10"; + sel_out <= "10000"; + BUTTERFLY_CTRL_STATE <= last10; + + WHEN last10 => + sample_out_val <= '0'; + sel_op1 <= "10000"; + sel_op2 <= "10000"; + alu_ctrl <= ctrl_IDLE; + alu_comp <= "10"; + sel_out <= "10000"; + BUTTERFLY_CTRL_STATE <= last11; + + WHEN last11 => + sample_out_val <= '0'; + alu_ctrl <= ctrl_IDLE; + alu_comp <= "10"; + sel_out <= "10000"; + BUTTERFLY_CTRL_STATE <= waiting; + + WHEN OTHERS => + NULL; + + END CASE; + + END IF; + + END PROCESS; + +END ar_BUTTERFLY_CTRL; \ No newline at end of file diff --git a/lib/staging/LPP/PLE/dsp/lpp_fft/BUTTERFLY_TOP.vhd b/lib/staging/LPP/PLE/dsp/lpp_fft/BUTTERFLY_TOP.vhd new file mode 100644 --- /dev/null +++ b/lib/staging/LPP/PLE/dsp/lpp_fft/BUTTERFLY_TOP.vhd @@ -0,0 +1,115 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more Cdetails. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Paul LEROY +-- Mail : paul.leroy@lpp.polytechnique.fr +------------------------------------------------------------------------------- + +LIBRARY IEEE; +USE IEEE.numeric_std.ALL; +USE IEEE.std_logic_1164.ALL; + +LIBRARY staging_lpp; +USE staging_lpp.PLE_general_purpose.ALL; +use staging_lpp.PLE_lpp_fft.all; + +ENTITY BUTTERFLY_TOP IS + GENERIC ( + Sample_SZ : INTEGER := 16); + PORT ( + rstn : IN STD_LOGIC; + clk : IN STD_LOGIC; + + sample_in_val : IN STD_LOGIC; + sample_out_val : OUT STD_LOGIC; + + Are : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0); + Aim : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0); + Bre : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0); + Bim : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0); + c_in : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0); + cps_in : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0); + cms_in : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0); + + op1 : OUT STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0); + op2 : OUT STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0); + alu_ctrl : OUT STD_LOGIC_VECTOR( 2 DOWNTO 0 ); + alu_comp : OUT STD_LOGIC_VECTOR( 1 DOWNTO 0 ); + + butterfly_out : OUT STD_LOGIC_VECTOR ( 2*Sample_SZ-1 DOWNTO 0); + sel_out : OUT STD_LOGIC_VECTOR ( 4 DOWNTO 0) + ); +END BUTTERFLY_TOP; + +ARCHITECTURE ar_BUTTERFLY_TOP OF BUTTERFLY_TOP IS + +SIGNAL sel_op1 : STD_LOGIC_VECTOR( 4 DOWNTO 0 ); -- Are Aim X Y Z +SIGNAL sel_op2 : STD_LOGIC_VECTOR( 4 DOWNTO 0 ); -- Bre Bim C_in cps_in cms_in +SIGNAL sel_xyz : STD_LOGIC_VECTOR( 2 DOWNTO 0 ); -- X Y Z +SIGNAL alu_ctrl_sig : STD_LOGIC_VECTOR( 2 DOWNTO 0 ); +SIGNAL alu_comp_sig : STD_LOGIC_VECTOR( 1 DOWNTO 0 ); + +BEGIN + + alu_ctrl <= alu_ctrl_sig; + alu_comp <= alu_comp_sig; + + BUTTERFLY_DATAFLOW_1 : BUTTERFLY_DATAFLOW + GENERIC MAP ( + Sample_SZ => 16) + PORT MAP ( + rstn => rstn, + clk => clk, + + Are => Are, + Aim => Aim, + Bre => Bre, + Bim => Bim, + c_in => c_in, + cps_in => cps_in, + cms_in => cms_in, + + op1 => op1, + op2 => op2, + + out_alu => butterfly_out, + + sel_op1 => sel_op1, + sel_op2 => sel_op2, + sel_xyz => sel_xyz, + alu_ctrl => alu_ctrl_sig, + alu_comp => alu_comp_sig + ); + + BUTTERFLY_CTRL_1 : BUTTERFLY_CTRL + PORT MAP( + rstn => rstn, + clk => clk, + + sample_in_val => sample_in_val, + sample_out_val => sample_out_val, + + sel_op1 => sel_op1, + sel_op2 => sel_op2, + sel_xyz => sel_xyz, + sel_out => sel_out, + alu_ctrl => alu_ctrl_sig, + alu_comp => alu_comp_sig + ); + +END ar_BUTTERFLY_TOP; \ No newline at end of file diff --git a/lib/staging/LPP/PLE/dsp/lpp_fft/LPP_BUTTERFLY_DATAFLOW.vhd b/lib/staging/LPP/PLE/dsp/lpp_fft/LPP_BUTTERFLY_DATAFLOW.vhd new file mode 100644 --- /dev/null +++ b/lib/staging/LPP/PLE/dsp/lpp_fft/LPP_BUTTERFLY_DATAFLOW.vhd @@ -0,0 +1,129 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more Cdetails. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Paul LEROY +-- Mail : paul.leroy@lpp.polytechnique.fr +------------------------------------------------------------------------------- + +LIBRARY IEEE; +USE IEEE.numeric_std.ALL; +USE IEEE.std_logic_1164.ALL; +LIBRARY staging_lpp; +USE staging_lpp.PLE_general_purpose.ALL; + +ENTITY BUTTERFLY_DATAFLOW IS + GENERIC ( + Sample_SZ : INTEGER := 16 + ); + PORT ( + rstn : IN STD_LOGIC; + clk : IN STD_LOGIC; + + Are : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0); + Aim : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0); + Bre : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0); + Bim : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0); + c_in : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0); + cps_in : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0); + cms_in : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0); + + op1 : OUT STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0); + op2 : OUT STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0); + + out_alu : OUT STD_LOGIC_VECTOR ( 2*Sample_SZ-1 DOWNTO 0); + + sel_op1 : IN STD_LOGIC_VECTOR( 4 DOWNTO 0 ); -- Are Aim X Y Z + sel_op2 : IN STD_LOGIC_VECTOR( 4 DOWNTO 0 ); -- Bre Bim C_in cps_in cms_in + sel_xyz : IN STD_LOGIC_VECTOR( 2 DOWNTO 0 ); -- X Y Z + alu_ctrl : IN STD_LOGIC_VECTOR( 2 DOWNTO 0 ); + alu_comp : IN STD_LOGIC_VECTOR( 1 DOWNTO 0 ) + ); +END BUTTERFLY_DATAFLOW; + +ARCHITECTURE ar_BUTTERFLY_DATAFLOW OF BUTTERFLY_DATAFLOW IS + + SIGNAL X : STD_LOGIC_VECTOR( Sample_SZ-1 DOWNTO 0 ); + SIGNAL Y : STD_LOGIC_VECTOR( Sample_SZ-1 DOWNTO 0 ); + SIGNAL Z : STD_LOGIC_VECTOR( Sample_SZ-1 DOWNTO 0 ); + + SIGNAL ALU_OP1 : STD_LOGIC_VECTOR( Sample_SZ-1 DOWNTO 0 ); + SIGNAL ALU_OP2 : STD_LOGIC_VECTOR( Sample_SZ-1 DOWNTO 0 ); + + SIGNAL OUT_ALU_SIG : STD_LOGIC_VECTOR ( 2*Sample_SZ-1 DOWNTO 0); + +BEGIN + +out_alu <= OUT_ALU_SIG; + +PROCESS (clk, rstn) + + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + X <= (OTHERS => '0'); + Y <= (OTHERS => '0'); + Z <= (OTHERS => '0'); + + ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge + + if sel_xyz = "100" THEN + X <= STD_LOGIC_VECTOR(resize(SIGNED(OUT_ALU_SIG), Sample_SZ)); + elsif sel_xyz = "010" THEN + Y <= STD_LOGIC_VECTOR(resize(SIGNED(OUT_ALU_SIG), Sample_SZ)); + elsif sel_xyz = "001" THEN + Z <= STD_LOGIC_VECTOR(resize(SIGNED(OUT_ALU_SIG), Sample_SZ)); + end if; + + END IF; + + END PROCESS; + + op1 <= ALU_OP1; + op2 <= ALU_OP2; + +ALU_OP1 <= Are WHEN sel_op1 = "10000" ELSE + Aim WHEN sel_op1 = "01000" ELSE + X WHEN sel_op1 = "00100" ELSE + Y WHEN sel_op1 = "00010" ELSE + Z WHEN sel_op1 = "00001" ELSE + STD_LOGIC_VECTOR(resize(SIGNED(OUT_ALU_SIG), Sample_SZ)) WHEN sel_op1 = "00000" ELSE + (OTHERS => '0'); + +ALU_OP2 <= Bre WHEN sel_op2 = "10000" ELSE + Bim WHEN sel_op2 = "01000" ELSE + c_in WHEN sel_op2 = "00100" ELSE + cps_in WHEN sel_op2 = "00010" ELSE + cms_in WHEN sel_op2 = "00001" ELSE + std_logic_vector(TO_SIGNED(1,Sample_SZ)) WHEN sel_op2 = "00000" ELSE + (OTHERS => '0'); + +ALU_1: ALU + GENERIC MAP ( + Arith_en => 1, + Input_SZ_1 => Sample_SZ, + Input_SZ_2 => Sample_SZ, + COMP_EN => 0) -- comp is enable when COMP_EN is 0 + PORT MAP ( + clk => clk, + reset => rstn, + ctrl => alu_ctrl, + comp => alu_comp, + OP1 => ALU_OP1, + OP2 => ALU_OP2, + RES => OUT_ALU_SIG); + +END ar_BUTTERFLY_DATAFLOW; \ No newline at end of file diff --git a/lib/staging/LPP/PLE/dsp/lpp_fft/lpp_fft.vhd b/lib/staging/LPP/PLE/dsp/lpp_fft/lpp_fft.vhd new file mode 100644 --- /dev/null +++ b/lib/staging/LPP/PLE/dsp/lpp_fft/lpp_fft.vhd @@ -0,0 +1,102 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Paul Leroy +-- Mail : paul.leroy@lpp.polytechnique.fr +---------------------------------------------------------------------------- + + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; + +PACKAGE PLE_lpp_fft IS + +COMPONENT BUTTERFLY_DATAFLOW + GENERIC ( + Sample_SZ : INTEGER := 16); + PORT ( + rstn : IN STD_LOGIC; + clk : IN STD_LOGIC; + + Are : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0); + Aim : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0); + Bre : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0); + Bim : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0); + c_in : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0); + cps_in : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0); + cms_in : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0); + + op1 : OUT STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0); + op2 : OUT STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0); + + out_alu : OUT STD_LOGIC_VECTOR ( 2*Sample_SZ-1 DOWNTO 0); + + sel_op1 : IN STD_LOGIC_VECTOR( 4 DOWNTO 0 ); -- Are Aim X Y Z + sel_op2 : IN STD_LOGIC_VECTOR( 4 DOWNTO 0 ); -- Bre Bim C_in cps_in cms_in + sel_xyz : IN STD_LOGIC_VECTOR( 2 DOWNTO 0 ); -- X Y Z + alu_ctrl : IN STD_LOGIC_VECTOR( 2 DOWNTO 0 ); + alu_comp : IN STD_LOGIC_VECTOR( 1 DOWNTO 0 ) + ); +END COMPONENT; + +COMPONENT BUTTERFLY_CTRL + PORT ( + rstn : IN STD_LOGIC; + clk : IN STD_LOGIC; + + sample_in_val : IN STD_LOGIC; + sample_out_val : OUT STD_LOGIC; + + sel_op1 : OUT STD_LOGIC_VECTOR( 4 DOWNTO 0 ); -- Are Aim X Y Z + sel_op2 : OUT STD_LOGIC_VECTOR( 4 DOWNTO 0 ); -- Bre Bim C_in cps_in cms_in + sel_xyz : OUT STD_LOGIC_VECTOR( 2 DOWNTO 0 ); -- X Y Z + sel_out : OUT STD_LOGIC_VECTOR( 4 DOWNTO 0 ); + alu_ctrl : OUT STD_LOGIC_VECTOR( 2 DOWNTO 0 ); + alu_comp : OUT STD_LOGIC_VECTOR( 1 DOWNTO 0 ) + ); +END COMPONENT; + +COMPONENT BUTTERFLY_TOP + GENERIC ( + Sample_SZ : INTEGER := 16); + PORT ( + rstn : IN STD_LOGIC; + clk : IN STD_LOGIC; + + sample_in_val : IN STD_LOGIC; + sample_out_val : OUT STD_LOGIC; + + Are : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0); + Aim : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0); + Bre : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0); + Bim : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0); + c_in : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0); + cps_in : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0); + cms_in : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0); + + op1 : OUT STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0); + op2 : OUT STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0); + alu_ctrl : OUT STD_LOGIC_VECTOR( 2 DOWNTO 0 ); + alu_comp : OUT STD_LOGIC_VECTOR( 1 DOWNTO 0 ); + + butterfly_out : OUT STD_LOGIC_VECTOR ( 2*Sample_SZ-1 DOWNTO 0); + sel_out : OUT STD_LOGIC_VECTOR ( 4 DOWNTO 0) + ); +END COMPONENT; + +END; \ No newline at end of file diff --git a/lib/staging/LPP/PLE/dsp/lpp_fft/test/modelsim.ini b/lib/staging/LPP/PLE/dsp/lpp_fft/test/modelsim.ini new file mode 100644 --- /dev/null +++ b/lib/staging/LPP/PLE/dsp/lpp_fft/test/modelsim.ini @@ -0,0 +1,337 @@ +; Copyright 1991-2010 Mentor Graphics Corporation +; +; All Rights Reserved. +; +; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF +; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS. +; + +[Library] +others = $MODEL_TECH/../modelsim.ini + +; Actel Primitive Libraries +; +; VHDL Section +; +;aact1 = $MODEL_TECH/../actel/vhdl/aact1 +;aact2 = $MODEL_TECH/../actel/vhdl/aact2 +;aact3 = $MODEL_TECH/../actel/vhdl/aact3 +;a3200dx = $MODEL_TECH/../actel/vhdl/a3200dx +;a40mx = $MODEL_TECH/../actel/vhdl/a40mx +;a42mx = $MODEL_TECH/../actel/vhdl/a42mx +;a54sxa = $MODEL_TECH/../actel/vhdl/a54sxa +; +; Verilog Section +; +;act1 = $MODEL_TECH/../actel/verilog/act1 +;act2 = $MODEL_TECH/../actel/verilog/act2 +;act3 = $MODEL_TECH/../actel/verilog/act3 +;3200dx = $MODEL_TECH/../actel/verilog/3200dx +;40mx = $MODEL_TECH/../actel/verilog/40mx +;42mx = $MODEL_TECH/../actel/verilog/42mx +;54sxa = $MODEL_TECH/../actel/verilog/54sxa + +staging_lpp = staging_lpp +[vcom] +; VHDL93 variable selects language version as the default. +; Default is VHDL-2002. +; Value of 0 or 1987 for VHDL-1987. +; Value of 1 or 1993 for VHDL-1993. +; Default or value of 2 or 2002 for VHDL-2002. +VHDL93 = 2002 + +; Show source line containing error. Default is off. +; Show_source = 1 + +; Turn off unbound-component warnings. Default is on. +; Show_Warning1 = 0 + +; Turn off process-without-a-wait-statement warnings. Default is on. +; Show_Warning2 = 0 + +; Turn off null-range warnings. Default is on. +; Show_Warning3 = 0 + +; Turn off no-space-in-time-literal warnings. Default is on. +; Show_Warning4 = 0 + +; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on. +; Show_Warning5 = 0 + +; Turn off optimization for IEEE std_logic_1164 package. Default is on. +; Optimize_1164 = 0 + +; Turn on resolving of ambiguous function overloading in favor of the +; "explicit" function declaration (not the one automatically created by +; the compiler for each type declaration). Default is off. +; The .ini file has Explicit enabled so that std_logic_signed/unsigned +; will match the behavior of synthesis tools. +Explicit = 1 + +; Turn off acceleration of the VITAL packages. Default is to accelerate. +; NoVital = 1 + +; Turn off VITAL compliance checking. Default is checking on. +; NoVitalCheck = 1 + +; Ignore VITAL compliance checking errors. Default is to not ignore. +; IgnoreVitalErrors = 1 + +; Turn off VITAL compliance checking warnings. Default is to show warnings. +; Show_VitalChecksWarnings = 0 + +; Keep silent about case statement static warnings. +; Default is to give a warning. +; NoCaseStaticError = 1 + +; Keep silent about warnings caused by aggregates that are not locally static. +; Default is to give a warning. +; NoOthersStaticError = 1 + +; Turn off inclusion of debugging info within design units. +; Default is to include debugging info. +; NoDebug = 1 + +; Turn off "Loading..." messages. Default is messages on. +; Quiet = 1 + +; Turn on some limited synthesis rule compliance checking. Checks only: +; -- signals used (read) by a process must be in the sensitivity list +; CheckSynthesis = 1 + +; Activate optimizations on expressions that do not involve signals, +; waits, or function/procedure/task invocations. Default is off. +; ScalarOpts = 1 + +; Require the user to specify a configuration for all bindings, +; and do not generate a compile time default binding for the +; component. This will result in an elaboration error of +; 'component not bound' if the user fails to do so. Avoids the rare +; issue of a false dependency upon the unused default binding. +; RequireConfigForAllDefaultBinding = 1 + +; Inhibit range checking on subscripts of arrays. Range checking on +; scalars defined with subtypes is inhibited by default. +; NoIndexCheck = 1 + +; Inhibit range checks on all (implicit and explicit) assignments to +; scalar objects defined with subtypes. +; NoRangeCheck = 1 + +[vlog] + +; Turn off inclusion of debugging info within design units. +; Default is to include debugging info. +; NoDebug = 1 + +; Turn off "loading..." messages. Default is messages on. +; Quiet = 1 + +; Turn on Verilog hazard checking (order-dependent accessing of global vars). +; Default is off. +; Hazard = 1 + +; Turn on converting regular Verilog identifiers to uppercase. Allows case +; insensitivity for module names. Default is no conversion. +; UpCase = 1 + +; Turn on incremental compilation of modules. Default is off. +; Incremental = 1 + +; Turns on lint-style checking. +; Show_Lint = 1 + +[vsim] +; Simulator resolution +; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100. +Resolution = ps + +; User time unit for run commands +; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the +; unit specified for Resolution. For example, if Resolution is 100ps, +; then UserTimeUnit defaults to ps. +; Should generally be set to default. +UserTimeUnit = default + +; Default run length +RunLength = 100 + +; Maximum iterations that can be run without advancing simulation time +IterationLimit = 5000 + +; Directive to license manager: +; vhdl Immediately reserve a VHDL license +; vlog Immediately reserve a Verilog license +; plus Immediately reserve a VHDL and Verilog license +; nomgc Do not look for Mentor Graphics Licenses +; nomti Do not look for Model Technology Licenses +; noqueue Do not wait in the license queue when a license isn't available +; viewsim Try for viewer license but accept simulator license(s) instead +; of queuing for viewer license +; License = plus + +; Stop the simulator after a VHDL/Verilog assertion message +; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal +BreakOnAssertion = 3 + +; Assertion Message Format +; %S - Severity Level +; %R - Report Message +; %T - Time of assertion +; %D - Delta +; %I - Instance or Region pathname (if available) +; %% - print '%' character +; AssertionFormat = "** %S: %R\n Time: %T Iteration: %D%I\n" + +; Assertion File - alternate file for storing VHDL/Verilog assertion messages +; AssertFile = assert.log + +; Default radix for all windows and commands... +; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned +DefaultRadix = symbolic + +; VSIM Startup command +; Startup = do startup.do + +; File for saving command transcript +TranscriptFile = transcript + +; File for saving command history +; CommandHistory = cmdhist.log + +; Specify whether paths in simulator commands should be described +; in VHDL or Verilog format. +; For VHDL, PathSeparator = / +; For Verilog, PathSeparator = . +; Must not be the same character as DatasetSeparator. +PathSeparator = / + +; Specify the dataset separator for fully rooted contexts. +; The default is ':'. For example, sim:/top +; Must not be the same character as PathSeparator. +DatasetSeparator = : + +; Disable VHDL assertion messages +; IgnoreNote = 1 +; IgnoreWarning = 1 +; IgnoreError = 1 +; IgnoreFailure = 1 + +; Default force kind. May be freeze, drive, deposit, or default +; or in other terms, fixed, wired, or charged. +; A value of "default" will use the signal kind to determine the +; force kind, drive for resolved signals, freeze for unresolved signals +; DefaultForceKind = freeze + +; If zero, open files when elaborated; otherwise, open files on +; first read or write. Default is 0. +; DelayFileOpen = 1 + +; Control VHDL files opened for write. +; 0 = Buffered, 1 = Unbuffered +UnbufferedOutput = 0 + +; Control the number of VHDL files open concurrently. +; This number should always be less than the current ulimit +; setting for max file descriptors. +; 0 = unlimited +ConcurrentFileLimit = 40 + +; Control the number of hierarchical regions displayed as +; part of a signal name shown in the Wave window. +; A value of zero tells VSIM to display the full name. +; The default is 0. +; WaveSignalNameWidth = 0 + +; Turn off warnings from the std_logic_arith, std_logic_unsigned +; and std_logic_signed packages. +; StdArithNoWarnings = 1 + +; Turn off warnings from the IEEE numeric_std and numeric_bit packages. +; NumericStdNoWarnings = 1 + +; Control the format of the (VHDL) FOR generate statement label +; for each iteration. Do not quote it. +; The format string here must contain the conversion codes %s and %d, +; in that order, and no other conversion codes. The %s represents +; the generate_label; the %d represents the generate parameter value +; at a particular generate iteration (this is the position number if +; the generate parameter is of an enumeration type). Embedded whitespace +; is allowed (but discouraged); leading and trailing whitespace is ignored. +; Application of the format must result in a unique scope name over all +; such names in the design so that name lookup can function properly. +; GenerateFormat = %s__%d + +; Specify whether checkpoint files should be compressed. +; The default is 1 (compressed). +; CheckpointCompressMode = 0 + +; List of dynamically loaded objects for Verilog PLI applications +; Veriuser = veriuser.sl + +; Specify default options for the restart command. Options can be one +; or more of: -force -nobreakpoint -nolist -nolog -nowave +; DefaultRestartOptions = -force + +; HP-UX 10.20 ONLY - Enable memory locking to speed up large designs +; (> 500 megabyte memory footprint). Default is disabled. +; Specify number of megabytes to lock. +; LockedMemory = 1000 + +; Turn on (1) or off (0) WLF file compression. +; The default is 1 (compress WLF file). +; WLFCompress = 0 + +; Specify whether to save all design hierarchy (1) in the WLF file +; or only regions containing logged signals (0). +; The default is 0 (save only regions with logged signals). +; WLFSaveAllRegions = 1 + +; WLF file time limit. Limit WLF file by time, as closely as possible, +; to the specified amount of simulation time. When the limit is exceeded +; the earliest times get truncated from the file. +; If both time and size limits are specified the most restrictive is used. +; UserTimeUnits are used if time units are not specified. +; The default is 0 (no limit). Example: WLFTimeLimit = {100 ms} +; WLFTimeLimit = 0 + +; WLF file size limit. Limit WLF file size, as closely as possible, +; to the specified number of megabytes. If both time and size limits +; are specified then the most restrictive is used. +; The default is 0 (no limit). +; WLFSizeLimit = 1000 + +; Specify whether or not a WLF file should be deleted when the +; simulation ends. A value of 1 will cause the WLF file to be deleted. +; The default is 0 (do not delete WLF file when simulation ends). +; WLFDeleteOnQuit = 1 + +; Automatic SDF compilation +; Disables automatic compilation of SDF files in flows that support it. +; Default is on, uncomment to turn off. +; NoAutoSDFCompile = 1 + +[lmc] + +[msg_system] +; Change a message severity or suppress a message. +; The format is: = [,...] +; Examples: +; note = 3009 +; warning = 3033 +; error = 3010,3016 +; fatal = 3016,3033 +; suppress = 3009,3016,3043 +; The command verror can be used to get the complete +; description of a message. + +; Control transcripting of elaboration/runtime messages. +; The default is to have messages appear in the transcript and +; recorded in the wlf file (messages that are recorded in the +; wlf file can be viewed in the MsgViewer). The other settings +; are to send messages only to the transcript or only to the +; wlf file. The valid values are +; both {default} +; tran {transcript only} +; wlf {wlf file only} +; msgmode = both diff --git a/lib/staging/LPP/PLE/dsp/lpp_fft/test/run.do b/lib/staging/LPP/PLE/dsp/lpp_fft/test/run.do new file mode 100644 --- /dev/null +++ b/lib/staging/LPP/PLE/dsp/lpp_fft/test/run.do @@ -0,0 +1,30 @@ +vlib staging_lpp +vmap staging_lpp "staging_lpp" + +vcom -93 -explicit -work staging_lpp "../../../general_purpose/general_purpose.vhd" +vcom -93 -explicit -work staging_lpp "../../../general_purpose/MAC_CONTROLER.vhd" +vcom -93 -explicit -work staging_lpp "../../../general_purpose/Multiplier.vhd" +vcom -93 -explicit -work staging_lpp "../../../general_purpose/Adder.vhd" +vcom -93 -explicit -work staging_lpp "../../../general_purpose/TwoComplementer.vhd" +vcom -93 -explicit -work staging_lpp "../../../general_purpose/MAC_REG.vhd" +vcom -93 -explicit -work staging_lpp "../../../general_purpose/MAC_MUX.vhd" +vcom -93 -explicit -work staging_lpp "../../../general_purpose/MAC_MUX2.vhd" +vcom -93 -explicit -work staging_lpp "../../../general_purpose/MAC.vhd" +vcom -93 -explicit -work staging_lpp "../../../general_purpose/ALU.vhd" + +vcom -93 -explicit -work staging_lpp "../lpp_fft.vhd" +vcom -93 -explicit -work staging_lpp "../LPP_BUTTERFLY_DATAFLOW.vhd" +vcom -93 -explicit -work staging_lpp "../BUTTERFLY_CTRL.vhd" +vcom -93 -explicit -work staging_lpp "../BUTTERFLY_TOP.vhd" +vcom -93 -explicit -work staging_lpp "testBench_BUTTERFLY_TOP.vhd" + +vsim -L staging_lpp -t 1ps staging_lpp.TestBench_BUTTERFLY_TOP + +do wave.do + +log -R * + +run 1 us +# The following lines are commented because no testbench is associated with the project +# add wave /testbench/* +# run 1000ns diff --git a/lib/staging/LPP/PLE/dsp/lpp_fft/test/staging_lpp/_info b/lib/staging/LPP/PLE/dsp/lpp_fft/test/staging_lpp/_info new file mode 100644 --- /dev/null +++ b/lib/staging/LPP/PLE/dsp/lpp_fft/test/staging_lpp/_info @@ -0,0 +1,436 @@ +m255 +K3 +13 +cModel Technology +Z0 dC:\VHDL\VHD_Lib-next\lib\staging\LPP\PLE\dsp\lpp_fft\test +Eadder +Z1 w1367492167 +Z2 DPx4 ieee 14 std_logic_1164 0 22 GH1=`jDDBJ=`LM;:Ak`kf2 +Z3 DPx4 ieee 11 numeric_std 0 22 =NSdli^?T5OD8;4Fa4c6R:;@zlk5miIO2 +Ebutterfly_ctrl +Z19 w1387452436 +Z20 DPx11 staging_lpp 11 ple_lpp_fft 0 22 fR89[BSncW2 +R13 +R2 +R3 +R4 +Z21 8../BUTTERFLY_CTRL.vhd +Z22 F../BUTTERFLY_CTRL.vhd +l0 +L32 +VkQ?Y4JTf@DHzClk;BN8m?2 +R7 +31 +R8 +R9 +!s100 OFBC17;8gEg8J^PPd26]^0 +Aar_butterfly_ctrl +R20 +R13 +R2 +R3 +DEx4 work 14 butterfly_ctrl 0 22 kQ?Y4JTf@DHzClk;BN8m?2 +l66 +L49 +VUOBVXO?RLc>P4cLYnIOJK3 +R7 +31 +Z23 Mx4 4 ieee 11 numeric_std +Z24 Mx3 4 ieee 14 std_logic_1164 +Z25 Mx2 11 staging_lpp 19 ple_general_purpose +Z26 Mx1 11 staging_lpp 11 ple_lpp_fft +R8 +R9 +!s100 6jJJ^<^7KVK9YiOCAmAfk1 +Ebutterfly_dataflow +Z27 w1387454361 +R13 +R2 +R3 +R4 +Z28 8../LPP_BUTTERFLY_DATAFLOW.vhd +Z29 F../LPP_BUTTERFLY_DATAFLOW.vhd +l0 +L29 +VI`_;hfaYCNQ1Zkm5<`LHT3 +R7 +31 +R8 +R9 +!s100 I>e@N:Zca9WlmWN@nE@`EDad]Cf2 +R7 +31 +R8 +R9 +!s100 22G:]MmP6`P]S5a<^zaIG3 +Aar_mac +R13 +R2 +R3 +DEx4 work 3 mac 0 22 z:J>WlmWN@nE@`EDad]Cf2 +l86 +L54 +V3nAA^GI7Ym8m@PF<9[0=cIVS2X`8MPG0 +Emac_controler +R1 +R2 +R3 +R4 +Z36 8../../../general_purpose/MAC_CONTROLER.vhd +Z37 F../../../general_purpose/MAC_CONTROLER.vhd +l0 +L29 +V3F`]dJZY][ZC4@mMDbUjF1 +R7 +31 +R8 +R9 +!s100 AEHI=CKBB^Y`BRI6Wkb653 +Aar_mac_controler +R2 +R3 +DEx4 work 13 mac_controler 0 22 3F`]dJZY][ZC4@mMDbUjF1 +l47 +L45 +VYKjYF<4O[WUG`U:VRF40=MgDKG1ihL1 +R7 +31 +R8 +R9 +!s100 VY:^W494N0=MgDKG1ihL1 +l48 +L46 +VY>F?32o4EN<;M8QdcmA>e3 +R7 +31 +R10 +R11 +R8 +R9 +!s100 <4^2O;J:P]mD1VL;cC1fD0 +Emac_mux2 +R1 +R2 +R3 +R4 +Z40 8../../../general_purpose/MAC_MUX2.vhd +Z41 F../../../general_purpose/MAC_MUX2.vhd +l0 +L27 +V^N``KIm1zV?_lMP8EliHk2 +R7 +31 +R8 +R9 +!s100 TE[`n?T8Qd3^G^XaQFk5m1 +Aar_mac_mux2 +R2 +R3 +DEx4 work 8 mac_mux2 0 22 ^N``KIm1zV?_lMP8EliHk2 +l42 +L40 +VhnJjfYH]b0mK:U5e86_Y93 +R7 +31 +R10 +R11 +R8 +R9 +!s100 kW7HO

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'0'); +signal c : std_logic_vector( Sample_SZ-1 downto 0 ) := ( others => '0'); +signal cps : std_logic_vector( Sample_SZ-1 downto 0 ) := ( others => '0'); +signal cms : std_logic_vector( Sample_SZ-1 downto 0 ) := ( others => '0'); + +signal op1 : STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0); +signal op2 : STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0); +signal alu_ctrl_sig : STD_LOGIC_VECTOR( 2 DOWNTO 0 ); +signal alu_comp_sig : STD_LOGIC_VECTOR( 1 DOWNTO 0 ); + +signal Resultat : std_logic_vector( 2*Sample_SZ-1 downto 0 ); + +signal sel_out : std_logic_vector( 4 downto 0 ); + +signal sample_in_val : std_logic := '0'; +signal sample_out_val : std_logic; + +begin + +BUTTERFLY_TOP1 : BUTTERFLY_TOP +generic map( + Sample_SZ => Sample_SZ +) +port map( + rstn => rstn, + clk => clk, + + sample_in_val => sample_in_val, + sample_out_val => sample_out_val, + + Are => Are, + Aim => Aim, + Bre => Bre, + Bim => Bim, + c_in => c, + cps_in => cps, + cms_in => cms, + + op1 => op1, + op2 => op2, + alu_ctrl => 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Horloge du composant + reset : in std_logic; --! Reset general du composant + ctrl : in std_logic_vector(2 downto 0); --! Permet de s�lectionner la/les op�ration d�sir�e + comp : in std_logic_vector(1 downto 0); --! (set) Permet de compl�menter les op�randes + OP1 : in std_logic_vector(Input_SZ_1-1 downto 0); --! Premier Op�rande + OP2 : in std_logic_vector(Input_SZ_2-1 downto 0); --! Second Op�rande + RES : out std_logic_vector(Input_SZ_1+Input_SZ_2-1 downto 0) --! R�sultat de l'op�ration +); +end ALU; + +--! @details S�lection grace a l'entr�e "ctrl" : +--! Pause : IDLE = 000 +--! Multiplieur/Accumulateur : MAC = 001 +--! Multiplication : MULT = 010 +--! Addition : ADD = 011 +--! Reset du MAC : CLRMAC = 100 +architecture ar_ALU of ALU is + +begin + +arith : if Arith_en = 1 generate +MACinst : MAC +generic map(Input_SZ_1,Input_SZ_2,COMP_EN) +port map(clk,reset,ctrl(2),ctrl(1 downto 0),comp,OP1,OP2,RES); +end generate; + +end architecture; diff --git a/lib/staging/LPP/PLE/general_purpose/Adder.vhd b/lib/staging/LPP/PLE/general_purpose/Adder.vhd new file mode 100644 --- /dev/null +++ b/lib/staging/LPP/PLE/general_purpose/Adder.vhd @@ -0,0 +1,71 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Alexis Jeandet +-- Mail : alexis.jeandet@lpp.polytechnique.fr +---------------------------------------------------------------------------- +LIBRARY IEEE; +USE IEEE.numeric_std.ALL; +USE IEEE.std_logic_1164.ALL; + +ENTITY Adder IS + GENERIC( + Input_SZ_A : INTEGER := 16; + Input_SZ_B : INTEGER := 16 + + ); + PORT( + clk : IN STD_LOGIC; + reset : IN STD_LOGIC; + clr : IN STD_LOGIC; + load : IN STD_LOGIC; + add : IN STD_LOGIC; + OP1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0); + OP2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0); + RES : OUT STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0) + ); +END ENTITY; + + + + +ARCHITECTURE ar_Adder OF Adder IS + + SIGNAL REG : STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0); + SIGNAL RESADD : STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0); + +BEGIN + + RES <= REG; + RESADD <= STD_LOGIC_VECTOR(resize(SIGNED(OP1)+SIGNED(OP2), Input_SZ_A)); + + PROCESS(clk, reset) + BEGIN + IF reset = '0' THEN + REG <= (OTHERS => '0'); + ELSIF clk'EVENT AND clk = '1' then + IF clr = '1' THEN + REG <= (OTHERS => '0'); + ELSIF add = '1' THEN + REG <= RESADD; + ELSIF load = '1' THEN + REG <= OP2; + END IF; + END IF; + END PROCESS; +END ar_Adder; diff --git a/lib/staging/LPP/PLE/general_purpose/MAC.vhd b/lib/staging/LPP/PLE/general_purpose/MAC.vhd new file mode 100644 --- /dev/null +++ b/lib/staging/LPP/PLE/general_purpose/MAC.vhd @@ -0,0 +1,301 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Alexis Jeandet +-- Mail : alexis.jeandet@lpp.polytechnique.fr +---------------------------------------------------------------------------- +LIBRARY IEEE; +USE IEEE.numeric_std.ALL; +USE IEEE.std_logic_1164.ALL; +LIBRARY staging_lpp; +USE staging_lpp.PLE_general_purpose.ALL; +--TODO +--terminer le testbensh puis changer le resize dans les instanciations +--par un resize sur un vecteur en combi + + +ENTITY MAC IS + GENERIC( + Input_SZ_A : INTEGER := 8; + Input_SZ_B : INTEGER := 8; + COMP_EN : INTEGER := 0 -- 1 => No Comp + + ); + PORT( + clk : IN STD_LOGIC; + reset : IN STD_LOGIC; + clr_MAC : IN STD_LOGIC; + MAC_MUL_ADD : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + Comp_2C : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + OP1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0); + OP2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0); + RES : OUT STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0) + ); +END MAC; + + + + +ARCHITECTURE ar_MAC OF MAC IS + + SIGNAL add, mult : STD_LOGIC; + SIGNAL MULTout : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0); + + SIGNAL ADDERinA : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0); + SIGNAL ADDERinB : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0); + SIGNAL ADDERout : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0); + + SIGNAL MACMUXsel : STD_LOGIC; + SIGNAL OP1_2C_D_Resz : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0); + SIGNAL OP2_2C_D_Resz : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0); + + SIGNAL OP1_2C : STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0); + SIGNAL OP2_2C : STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0); + + SIGNAL MACMUX2sel : STD_LOGIC; + + SIGNAL add_D : STD_LOGIC; + SIGNAL OP1_2C_D : STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0); + SIGNAL OP2_2C_D : STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0); + SIGNAL MULTout_D : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0); + SIGNAL MACMUXsel_D : STD_LOGIC; + SIGNAL MACMUX2sel_D : STD_LOGIC; + SIGNAL MACMUX2sel_D_D : STD_LOGIC; + SIGNAL clr_MAC_D : STD_LOGIC; + SIGNAL clr_MAC_D_D : STD_LOGIC; + SIGNAL MAC_MUL_ADD_2C_D : STD_LOGIC_VECTOR(1 DOWNTO 0); + + SIGNAL load_mult_result : STD_LOGIC; + SIGNAL load_mult_result_D : STD_LOGIC; + +BEGIN + + + + +--============================================================== +--=============M A C C O N T R O L E R========================= +--============================================================== + MAC_CONTROLER1 : MAC_CONTROLER + PORT MAP( + ctrl => MAC_MUL_ADD, + MULT => mult, + ADD => add, + LOAD_ADDER => load_mult_result, + MACMUX_sel => MACMUXsel, + MACMUX2_sel => MACMUX2sel + + ); +--============================================================== + + + + +--============================================================== +--=============M U L T I P L I E R============================== +--============================================================== + Multiplieri_nst : Multiplier + GENERIC MAP( + Input_SZ_A => Input_SZ_A, + Input_SZ_B => Input_SZ_B + ) + PORT MAP( + clk => clk, + reset => reset, + mult => mult, + OP1 => OP1_2C, + OP2 => OP2_2C, + RES => MULTout + ); +--============================================================== + + PROCESS (clk, reset) + BEGIN -- PROCESS + IF reset = '0' THEN -- asynchronous reset (active low) + load_mult_result_D <= '0'; + ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge + load_mult_result_D <= load_mult_result; + END IF; + END PROCESS; + +--============================================================== +--======================A D D E R ============================== +--============================================================== + adder_inst : Adder + GENERIC MAP( + Input_SZ_A => Input_SZ_A+Input_SZ_B, + Input_SZ_B => Input_SZ_A+Input_SZ_B + ) + PORT MAP( + clk => clk, + reset => reset, + clr => clr_MAC_D, + load => load_mult_result_D, + add => add_D, + OP1 => ADDERinA, + OP2 => ADDERinB, + RES => ADDERout + ); + +--============================================================== +--===================TWO COMPLEMENTERS========================== +--============================================================== + gen_comp : IF COMP_EN = 0 GENERATE + TWO_COMPLEMENTER1 : TwoComplementer + GENERIC MAP( + Input_SZ => Input_SZ_A + ) + PORT MAP( + clk => clk, + reset => reset, + clr => clr_MAC, + TwoComp => Comp_2C(0), + OP => OP1, + RES => OP1_2C + ); + + TWO_COMPLEMENTER2 : TwoComplementer + GENERIC MAP( + Input_SZ => Input_SZ_B + ) + PORT MAP( + clk => clk, + reset => reset, + clr => clr_MAC, + TwoComp => Comp_2C(1), + OP => OP2, + RES => OP2_2C + ); + END GENERATE gen_comp; + + no_gen_comp : IF COMP_EN = 1 GENERATE + OP2_2C <= OP2; + OP1_2C <= OP1; + END GENERATE no_gen_comp; +--============================================================== + + clr_MACREG1 : MAC_REG + GENERIC MAP(size => 1) + PORT MAP( + reset => reset, + clk => clk, + D(0) => clr_MAC, + Q(0) => clr_MAC_D + ); + + addREG : MAC_REG + GENERIC MAP(size => 1) + PORT MAP( + reset => reset, + clk => clk, + D(0) => add, + Q(0) => add_D + ); + + OP1REG : MAC_REG + GENERIC MAP(size => Input_SZ_A) + PORT MAP( + reset => reset, + clk => clk, + D => OP1_2C, + Q => OP1_2C_D + ); + + + OP2REG : MAC_REG + GENERIC MAP(size => Input_SZ_B) + PORT MAP( + reset => reset, + clk => clk, + D => OP2_2C, + Q => OP2_2C_D + ); + + MULToutREG : MAC_REG + GENERIC MAP(size => Input_SZ_A+Input_SZ_B) + PORT MAP( + reset => reset, + clk => clk, + D => MULTout, + Q => MULTout_D + ); + + MACMUXselREG : MAC_REG + GENERIC MAP(size => 1) + PORT MAP( + reset => reset, + clk => clk, + D(0) => MACMUXsel, + Q(0) => MACMUXsel_D + ); + + MACMUX2selREG : MAC_REG + GENERIC MAP(size => 1) + PORT MAP( + reset => reset, + clk => clk, + D(0) => MACMUX2sel, + Q(0) => MACMUX2sel_D + ); + + MACMUX2selREG2 : MAC_REG + GENERIC MAP(size => 1) + PORT MAP( + reset => reset, + clk => clk, + D(0) => MACMUX2sel_D, + Q(0) => MACMUX2sel_D_D + ); + +--============================================================== +--======================M A C M U X =========================== +--============================================================== + MACMUX_inst : MAC_MUX + GENERIC MAP( + Input_SZ_A => Input_SZ_A+Input_SZ_B, + Input_SZ_B => Input_SZ_A+Input_SZ_B + + ) + PORT MAP( + sel => MACMUXsel_D, + INA1 => ADDERout, + INA2 => OP2_2C_D_Resz, + INB1 => MULTout, + INB2 => OP1_2C_D_Resz, + OUTA => ADDERinA, + OUTB => ADDERinB + ); + OP1_2C_D_Resz <= STD_LOGIC_VECTOR(resize(SIGNED(OP1_2C_D), Input_SZ_A+Input_SZ_B)); + OP2_2C_D_Resz <= STD_LOGIC_VECTOR(resize(SIGNED(OP2_2C_D), Input_SZ_A+Input_SZ_B)); +--============================================================== + + +--============================================================== +--======================M A C M U X2 ========================== +--============================================================== + MAC_MUX2_inst : MAC_MUX2 + GENERIC MAP(Input_SZ => Input_SZ_A+Input_SZ_B) + PORT MAP( + sel => MACMUX2sel_D_D, + RES2 => MULTout_D, + RES1 => ADDERout, + RES => RES + ); +--============================================================== + +END ar_MAC; diff --git a/lib/staging/LPP/PLE/general_purpose/MAC_CONTROLER.vhd b/lib/staging/LPP/PLE/general_purpose/MAC_CONTROLER.vhd new file mode 100644 --- /dev/null +++ b/lib/staging/LPP/PLE/general_purpose/MAC_CONTROLER.vhd @@ -0,0 +1,71 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Alexis Jeandet +-- Mail : alexis.jeandet@lpp.polytechnique.fr +---------------------------------------------------------------------------- +library IEEE; +use IEEE.numeric_std.all; +use IEEE.std_logic_1164.all; + +--IDLE =00 MAC =01 MULT =10 ADD =11 + + +entity MAC_CONTROLER is +port( + ctrl : in std_logic_vector(1 downto 0); + MULT : out std_logic; + ADD : out std_logic; + LOAD_ADDER : out std_logic; + MACMUX_sel : out std_logic; + MACMUX2_sel : out std_logic + +); +end MAC_CONTROLER; + + + + + +architecture ar_MAC_CONTROLER of MAC_CONTROLER is + +begin + + + +MULT <= '0' when (ctrl = "00" or ctrl = "11") else '1'; +ADD <= '0' when (ctrl = "00" or ctrl = "10") else '1'; +LOAD_ADDER <= '1' when (ctrl = "10") else '0'; -- PATCH JC : mem mult result + -- to permit to compute a + -- MULT follow by a MAC +--MACMUX_sel <= '0' when (ctrl = "00" or ctrl = "01") else '1'; +MACMUX_sel <= '0' when (ctrl = "00" or ctrl = "01" OR ctrl = "10") else '1'; +MACMUX2_sel <= '0' when (ctrl = "00" or ctrl = "01" or ctrl = "11") else '1'; + + +end ar_MAC_CONTROLER; + + + + + + + + + + diff --git a/lib/staging/LPP/PLE/general_purpose/MAC_MUX.vhd b/lib/staging/LPP/PLE/general_purpose/MAC_MUX.vhd new file mode 100644 --- /dev/null +++ b/lib/staging/LPP/PLE/general_purpose/MAC_MUX.vhd @@ -0,0 +1,53 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Alexis Jeandet +-- Mail : alexis.jeandet@lpp.polytechnique.fr +---------------------------------------------------------------------------- +library IEEE; +use IEEE.numeric_std.all; +use IEEE.std_logic_1164.all; + +entity MAC_MUX is +generic( + Input_SZ_A : integer := 16; + Input_SZ_B : integer := 16 + +); +port( + sel : in std_logic; + INA1 : in std_logic_vector(Input_SZ_A-1 downto 0); + INA2 : in std_logic_vector(Input_SZ_A-1 downto 0); + INB1 : in std_logic_vector(Input_SZ_B-1 downto 0); + INB2 : in std_logic_vector(Input_SZ_B-1 downto 0); + OUTA : out std_logic_vector(Input_SZ_A-1 downto 0); + OUTB : out std_logic_vector(Input_SZ_B-1 downto 0) +); +end entity; + + + + +architecture ar_MAC_MUX of MAC_MUX is + +begin + +OUTA <= INA1 when sel = '0' else INA2; +OUTB <= INB1 when sel = '0' else INB2; + +end ar_MAC_MUX; diff --git a/lib/staging/LPP/PLE/general_purpose/MAC_MUX2.vhd b/lib/staging/LPP/PLE/general_purpose/MAC_MUX2.vhd new file mode 100644 --- /dev/null +++ b/lib/staging/LPP/PLE/general_purpose/MAC_MUX2.vhd @@ -0,0 +1,46 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Alexis Jeandet +-- Mail : alexis.jeandet@lpp.polytechnique.fr +---------------------------------------------------------------------------- +library IEEE; +use IEEE.numeric_std.all; +use IEEE.std_logic_1164.all; + + +entity MAC_MUX2 is +generic(Input_SZ : integer := 16); +port( + sel : in std_logic; + RES1 : in std_logic_vector(Input_SZ-1 downto 0); + RES2 : in std_logic_vector(Input_SZ-1 downto 0); + RES : out std_logic_vector(Input_SZ-1 downto 0) +); +end entity; + + + + +architecture ar_MAC_MUX2 of MAC_MUX2 is + +begin + +RES <= RES1 when sel = '0' else RES2; + +end ar_MAC_MUX2; diff --git a/lib/staging/LPP/PLE/general_purpose/MAC_REG.vhd b/lib/staging/LPP/PLE/general_purpose/MAC_REG.vhd new file mode 100644 --- /dev/null +++ b/lib/staging/LPP/PLE/general_purpose/MAC_REG.vhd @@ -0,0 +1,58 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Alexis Jeandet +-- Mail : alexis.jeandet@lpp.polytechnique.fr +---------------------------------------------------------------------------- +library IEEE; +use IEEE.numeric_std.all; +use IEEE.std_logic_1164.all; + +entity MAC_REG is +generic(size : integer := 16); +port( + reset : in std_logic; + clk : in std_logic; + D : in std_logic_vector(size-1 downto 0); + Q : out std_logic_vector(size-1 downto 0) +); +end entity; + + + +architecture ar_MAC_REG of MAC_REG is +begin +process(clk,reset) +begin +if reset = '0' then + Q <= (others => '0'); +elsif clk'event and clk ='1' then + Q <= D; +end if; +end process; +end ar_MAC_REG; + + + + + + + + + + diff --git a/lib/staging/LPP/PLE/general_purpose/Multiplier.vhd b/lib/staging/LPP/PLE/general_purpose/Multiplier.vhd new file mode 100644 --- /dev/null +++ b/lib/staging/LPP/PLE/general_purpose/Multiplier.vhd @@ -0,0 +1,75 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Alexis Jeandet +-- Mail : alexis.jeandet@lpp.polytechnique.fr +---------------------------------------------------------------------------- +library IEEE; +use IEEE.numeric_std.all; +use IEEE.std_logic_1164.all; + +entity Multiplier is +generic( + Input_SZ_A : integer := 16; + Input_SZ_B : integer := 16 + +); +port( + clk : in std_logic; + reset : in std_logic; + mult : in std_logic; + OP1 : in std_logic_vector(Input_SZ_A-1 downto 0); + OP2 : in std_logic_vector(Input_SZ_B-1 downto 0); + RES : out std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0) +); +end Multiplier; + + + + + +architecture ar_Multiplier of Multiplier is + +signal REG : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0); +signal RESMULT : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0); + + +begin + +RES <= REG; +RESMULT <= std_logic_vector(signed(OP1)*signed(OP2)); +process(clk,reset) +begin +if reset = '0' then + REG <= (others => '0'); +elsif clk'event and clk ='1' then + if mult = '1' then + REG <= RESMULT; + end if; +end if; +end process; + +end ar_Multiplier; + + + + + + + + diff --git a/lib/staging/LPP/PLE/general_purpose/TwoComplementer.vhd b/lib/staging/LPP/PLE/general_purpose/TwoComplementer.vhd new file mode 100644 --- /dev/null +++ b/lib/staging/LPP/PLE/general_purpose/TwoComplementer.vhd @@ -0,0 +1,72 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Martin Morlot +-- Mail : martin.morlot@lpp.polytechnique.fr +------------------------------------------------------------------------------- +library IEEE; +use IEEE.numeric_std.all; +use IEEE.std_logic_1164.all; + +--! Programme permetant de compl�menter ou non les entr�es de l'ALU, et ainsi de travailler avec des nombres n�gatifs + +entity TwoComplementer is +generic( + Input_SZ : integer := 16); +port( + clk : in std_logic; --! Horloge du composant + reset : in std_logic; --! Reset general du composant + clr : in std_logic; --! Un reset sp�cifique au programme + TwoComp : in std_logic; --! Autorise l'utilisation du compl�ment + OP : in std_logic_vector(Input_SZ-1 downto 0); --! Op�rande d'entr�e + RES : out std_logic_vector(Input_SZ-1 downto 0) --! R�sultat, op�rande compl�ment� ou non +); +end TwoComplementer; + + +architecture ar_TwoComplementer of TwoComplementer is + +signal REG : std_logic_vector(Input_SZ-1 downto 0); +signal OPinteger : integer; +signal RESCOMP : std_logic_vector(Input_SZ-1 downto 0); + +begin + +RES <= REG; +OPinteger <= to_integer(signed(OP)); +RESCOMP <= std_logic_vector(to_signed(-OPinteger,Input_SZ)); + + process(clk,reset) + begin + + if(reset='0')then + REG <= (others => '0'); + elsif(clk'event and clk='1')then + + if(clr='1')then + REG <= (others => '0'); + elsif(TwoComp='1')then + REG <= RESCOMP; + else + REG <= OP; + end if; + + end if; + + end process; +end ar_TwoComplementer; \ No newline at end of file diff --git a/lib/staging/LPP/PLE/general_purpose/general_purpose.vhd b/lib/staging/LPP/PLE/general_purpose/general_purpose.vhd new file mode 100644 --- /dev/null +++ b/lib/staging/LPP/PLE/general_purpose/general_purpose.vhd @@ -0,0 +1,185 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Alexis Jeandet +-- Mail : alexis.jeandet@lpp.polytechnique.fr +---------------------------------------------------------------------------- +--UPDATE +------------------------------------------------------------------------------- +-- 14-03-2013 - Jean-christophe Pellion +-- ADD MUXN (a parametric multiplexor (N stage of MUX2)) +------------------------------------------------------------------------------- + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; + +PACKAGE PLE_general_purpose IS + + COMPONENT Adder IS + GENERIC( + Input_SZ_A : INTEGER := 16; + Input_SZ_B : INTEGER := 16 + + ); + PORT( + clk : IN STD_LOGIC; + reset : IN STD_LOGIC; + clr : IN STD_LOGIC; + load : IN STD_LOGIC; + add : IN STD_LOGIC; + OP1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0); + OP2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0); + RES : OUT STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0) + ); + END COMPONENT; + + COMPONENT ALU IS + GENERIC( + Arith_en : INTEGER := 1; + Logic_en : INTEGER := 1; + Input_SZ_1 : INTEGER := 16; + Input_SZ_2 : INTEGER := 9; + COMP_EN : INTEGER := 0 -- 1 => No Comp + + ); + PORT( + clk : IN STD_LOGIC; + reset : IN STD_LOGIC; + ctrl : IN STD_LOGIC_VECTOR(2 downto 0); + comp : IN STD_LOGIC_VECTOR(1 downto 0); + OP1 : IN STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0); + OP2 : IN STD_LOGIC_VECTOR(Input_SZ_2-1 DOWNTO 0); + RES : OUT STD_LOGIC_VECTOR(Input_SZ_1+Input_SZ_2-1 DOWNTO 0) + ); + END COMPONENT; + +--------------------------------------------------------- +-------- // Sélection grace a l'entrée "ctrl" \\ -------- +--------------------------------------------------------- +Constant ctrl_IDLE : std_logic_vector(2 downto 0) := "000"; +Constant ctrl_MAC : std_logic_vector(2 downto 0) := "001"; +Constant ctrl_MULT : std_logic_vector(2 downto 0) := "010"; +Constant ctrl_ADD : std_logic_vector(2 downto 0) := "011"; +Constant ctrl_CLRMAC : std_logic_vector(2 downto 0) := "100"; + + +Constant IDLE_V0 : std_logic_vector(3 downto 0) := "0000"; +Constant MAC_op_V0 : std_logic_vector(3 downto 0) := "0001"; +Constant MULT_V0 : std_logic_vector(3 downto 0) := "0010"; +Constant ADD_V0 : std_logic_vector(3 downto 0) := "0011"; +Constant CLR_MAC_V0 : std_logic_vector(3 downto 0) := "0100"; +--------------------------------------------------------- + + COMPONENT MAC IS + GENERIC( + Input_SZ_A : INTEGER := 8; + Input_SZ_B : INTEGER := 8; + COMP_EN : INTEGER := 0 -- 1 => No Comp + ); + PORT( + clk : IN STD_LOGIC; + reset : IN STD_LOGIC; + clr_MAC : IN STD_LOGIC; + MAC_MUL_ADD : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + Comp_2C : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + OP1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0); + OP2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0); + RES : OUT STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0) + ); + END COMPONENT; + + COMPONENT TwoComplementer is + generic( + Input_SZ : integer := 16); + port( + clk : in std_logic; --! Horloge du composant + reset : in std_logic; --! Reset general du composant + clr : in std_logic; --! Un reset spécifique au programme + TwoComp : in std_logic; --! Autorise l'utilisation du complément + OP : in std_logic_vector(Input_SZ-1 downto 0); --! Opérande d'entrée + RES : out std_logic_vector(Input_SZ-1 downto 0) --! Résultat, opérande complémenté ou non + ); + end COMPONENT; + + COMPONENT MAC_CONTROLER IS + PORT( + ctrl : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + MULT : OUT STD_LOGIC; + ADD : OUT STD_LOGIC; + LOAD_ADDER : out std_logic; + MACMUX_sel : OUT STD_LOGIC; + MACMUX2_sel : OUT STD_LOGIC + ); + END COMPONENT; + + COMPONENT MAC_MUX IS + GENERIC( + Input_SZ_A : INTEGER := 16; + Input_SZ_B : INTEGER := 16 + + ); + PORT( + sel : IN STD_LOGIC; + INA1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0); + INA2 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0); + INB1 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0); + INB2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0); + OUTA : OUT STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0); + OUTB : OUT STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0) + ); + END COMPONENT; + + + COMPONENT MAC_MUX2 IS + GENERIC(Input_SZ : INTEGER := 16); + PORT( + sel : IN STD_LOGIC; + RES1 : IN STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0); + RES2 : IN STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0); + RES : OUT STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0) + ); + END COMPONENT; + + + COMPONENT MAC_REG IS + GENERIC(size : INTEGER := 16); + PORT( + reset : IN STD_LOGIC; + clk : IN STD_LOGIC; + D : IN STD_LOGIC_VECTOR(size-1 DOWNTO 0); + Q : OUT STD_LOGIC_VECTOR(size-1 DOWNTO 0) + ); + END COMPONENT; + + COMPONENT Multiplier IS + GENERIC( + Input_SZ_A : INTEGER := 16; + Input_SZ_B : INTEGER := 16 + + ); + PORT( + clk : IN STD_LOGIC; + reset : IN STD_LOGIC; + mult : IN STD_LOGIC; + OP1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0); + OP2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0); + RES : OUT STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0) + ); + END COMPONENT; + +END;