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1 ----------------------------------------------------------------------------------
1 ----------------------------------------------------------------------------------
2 -- Company:
2 -- Company:
3 -- Engineer:
3 -- Engineer:
4 --
4 --
5 -- Create Date: 11:17:05 07/02/2012
5 -- Create Date: 11:17:05 07/02/2012
6 -- Design Name:
6 -- Design Name:
7 -- Module Name: apb_lfr_time_management - Behavioral
7 -- Module Name: apb_lfr_time_management - Behavioral
8 -- Project Name:
8 -- Project Name:
9 -- Target Devices:
9 -- Target Devices:
10 -- Tool versions:
10 -- Tool versions:
11 -- Description:
11 -- Description:
12 --
12 --
13 -- Dependencies:
13 -- Dependencies:
14 --
14 --
15 -- Revision:
15 -- Revision:
16 -- Revision 0.01 - File Created
16 -- Revision 0.01 - File Created
17 -- Additional Comments:
17 -- Additional Comments:
18 --
18 --
19 ----------------------------------------------------------------------------------
19 ----------------------------------------------------------------------------------
20 LIBRARY IEEE;
20 LIBRARY IEEE;
21 USE IEEE.STD_LOGIC_1164.ALL;
21 USE IEEE.STD_LOGIC_1164.ALL;
22 USE IEEE.NUMERIC_STD.ALL;
22 USE IEEE.NUMERIC_STD.ALL;
23 LIBRARY grlib;
23 LIBRARY grlib;
24 USE grlib.amba.ALL;
24 USE grlib.amba.ALL;
25 USE grlib.stdlib.ALL;
25 USE grlib.stdlib.ALL;
26 USE grlib.devices.ALL;
26 USE grlib.devices.ALL;
27 LIBRARY lpp;
27 LIBRARY lpp;
28 USE lpp.apb_devices_list.ALL;
28 USE lpp.apb_devices_list.ALL;
29 USE lpp.lpp_lfr_time_management.ALL;
29 USE lpp.lpp_lfr_time_management.ALL;
30
30
@@ -62,7 +62,7 ARCHITECTURE Behavioral OF apb_lfr_time_
62 --! type apb_config_type is array (0 to NAPBCFG-1) of amba_config_word;
62 --! type apb_config_type is array (0 to NAPBCFG-1) of amba_config_word;
63 CONSTANT pconfig : apb_config_type := (
63 CONSTANT pconfig : apb_config_type := (
64 --! 0 => ahb_device_reg (VENDOR_LPP, LPP_ROTARY, 0, REVISION, 0),
64 --! 0 => ahb_device_reg (VENDOR_LPP, LPP_ROTARY, 0, REVISION, 0),
65 0 => ahb_device_reg (VENDOR_LPP, 0, 0, REVISION, pirq),
65 0 => ahb_device_reg (VENDOR_LPP, 14, 0, REVISION, pirq),
66 1 => apb_iobar(paddr, pmask));
66 1 => apb_iobar(paddr, pmask));
67
67
68 TYPE apb_lfr_time_management_Reg IS RECORD
68 TYPE apb_lfr_time_management_Reg IS RECORD
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@@ -17,224 +17,250
17 -- Additional Comments:
17 -- Additional Comments:
18 --
18 --
19 ----------------------------------------------------------------------------------
19 ----------------------------------------------------------------------------------
20 library IEEE;
20 LIBRARY IEEE;
21 use IEEE.STD_LOGIC_1164.ALL;
21 USE IEEE.STD_LOGIC_1164.ALL;
22 use IEEE.NUMERIC_STD.ALL;
22 USE IEEE.NUMERIC_STD.ALL;
23 library lpp;
23 LIBRARY lpp;
24 use lpp.general_purpose.Clk_divider;
24 USE lpp.general_purpose.Clk_divider;
25
25
26 entity lfr_time_management is
26 ENTITY lfr_time_management IS
27 generic (
27 GENERIC (
28 masterclk : integer := 25000000; -- master clock in Hz
28 masterclk : INTEGER := 25000000; -- master clock in Hz
29 timeclk : integer := 49152000; -- 2nd clock in Hz
29 timeclk : INTEGER := 49152000; -- 2nd clock in Hz
30 finetimeclk : integer := 65536; -- divided clock used for the fine time counter
30 finetimeclk : INTEGER := 65536; -- divided clock used for the fine time counter
31 nb_clk_div_ticks : integer := 1 -- nb ticks before commutation to AUTO state
31 nb_clk_div_ticks : INTEGER := 1 -- nb ticks before commutation to AUTO state
32 );
32 );
33 Port (
33 PORT (
34 master_clock : in std_logic; --! Clock
34 master_clock : IN STD_LOGIC; --! Clock
35 time_clock : in std_logic; --! 2nd Clock
35 time_clock : IN STD_LOGIC; --! 2nd Clock
36 resetn : in std_logic; --! Reset
36 resetn : IN STD_LOGIC; --! Reset
37 grspw_tick : in std_logic;
37 grspw_tick : IN STD_LOGIC;
38 soft_tick : in std_logic; --! soft tick, load the coarse_time value
38 soft_tick : IN STD_LOGIC; --! soft tick, load the coarse_time value
39 coarse_time_load : in std_logic_vector(31 downto 0);
39 coarse_time_load : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
40 coarse_time : out std_logic_vector(31 downto 0);
40 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
41 fine_time : out std_logic_vector(31 downto 0);
41 fine_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
42 next_commutation : in std_logic_vector(31 downto 0);
42 next_commutation : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
43 reset_next_commutation: out std_logic;
43 reset_next_commutation : OUT STD_LOGIC;
44 irq1 : out std_logic;
44 irq1 : OUT STD_LOGIC;
45 irq2 : out std_logic
45 irq2 : OUT STD_LOGIC
46 );
46 );
47 end lfr_time_management;
47 END lfr_time_management;
48
48
49 architecture Behavioral of lfr_time_management is
49 ARCHITECTURE Behavioral OF lfr_time_management IS
50
50
51 signal resetn_clk_div : std_logic;
51 SIGNAL resetn_clk_div : STD_LOGIC;
52 signal clk_div : std_logic;
52 SIGNAL clk_div : STD_LOGIC;
53 --
53 --
54 signal flag : std_logic;
54 SIGNAL flag : STD_LOGIC;
55 signal s_coarse_time : std_logic_vector(31 downto 0);
55 SIGNAL s_coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
56 signal previous_coarse_time_load : std_logic_vector(31 downto 0);
56 SIGNAL previous_coarse_time_load : STD_LOGIC_VECTOR(31 DOWNTO 0);
57 signal cpt : integer range 0 to 100000;
57 SIGNAL cpt : INTEGER RANGE 0 TO 100000;
58 signal secondary_cpt : integer range 0 to 72000;
58 SIGNAL secondary_cpt : INTEGER RANGE 0 TO 72000;
59 --
59 --
60 signal sirq1 : std_logic;
60 SIGNAL sirq1 : STD_LOGIC;
61 signal sirq2 : std_logic;
61 SIGNAL sirq2 : STD_LOGIC;
62 signal cpt_next_commutation : integer range 0 to 100000;
62 SIGNAL cpt_next_commutation : INTEGER RANGE 0 TO 100000;
63 signal p_next_commutation : std_logic_vector(31 downto 0);
63 SIGNAL p_next_commutation : STD_LOGIC_VECTOR(31 DOWNTO 0);
64 signal latched_next_commutation : std_logic_vector(31 downto 0);
64 SIGNAL latched_next_commutation : STD_LOGIC_VECTOR(31 DOWNTO 0);
65 signal p_clk_div : std_logic;
65 SIGNAL p_clk_div : STD_LOGIC;
66 --
66 --
67 type state_type is (auto, slave);
67 TYPE state_type IS (auto, slave);
68 signal state : state_type;
68 SIGNAL state : state_type;
69 type timer_type is (idle, engaged);
69 TYPE timer_type IS (idle, engaged);
70 signal commutation_timer : timer_type;
70 SIGNAL commutation_timer : timer_type;
71
71
72 begin
72 BEGIN
73
73
74 --*******************************************
74 --*******************************************
75 -- COMMUTATION TIMER AND INTERRUPT GENERATION
75 -- COMMUTATION TIMER AND INTERRUPT GENERATION
76 process(master_clock, resetn)
76 PROCESS(master_clock, resetn)
77 begin
77 BEGIN
78
78
79 if resetn = '0' then
79 IF resetn = '0' THEN
80 commutation_timer <= idle;
80 commutation_timer <= idle;
81 cpt_next_commutation <= 0;
81 cpt_next_commutation <= 0;
82 sirq1 <= '0';
82 sirq1 <= '0';
83 sirq2 <= '0';
83 sirq2 <= '0';
84 latched_next_commutation <= x"ffffffff";
84 latched_next_commutation <= x"ffffffff";
85
85
86 elsif master_clock'event and master_clock = '1' then
86 ELSIF master_clock'EVENT AND master_clock = '1' THEN
87
87
88 case commutation_timer is
88 CASE commutation_timer IS
89
89
90 when idle =>
90 WHEN idle =>
91 sirq1 <= '0';
91 sirq1 <= '0';
92 sirq2 <= '0';
92 sirq2 <= '0';
93 if s_coarse_time = latched_next_commutation then
93 IF s_coarse_time = latched_next_commutation THEN
94 commutation_timer <= engaged; -- transition to state "engaged"
94 commutation_timer <= engaged; -- transition to state "engaged"
95 sirq1 <= '1'; -- start the pulse on sirq1
95 sirq1 <= '1'; -- start the pulse on sirq1
96 latched_next_commutation <= x"ffffffff";
96 latched_next_commutation <= x"ffffffff";
97 elsif not(p_next_commutation = next_commutation) then -- next_commutation has changed
97 ELSIF NOT(p_next_commutation = next_commutation) THEN -- next_commutation has changed
98 latched_next_commutation <= next_commutation; -- latch the value
98 latched_next_commutation <= next_commutation; -- latch the value
99 else
99 ELSE
100 commutation_timer <= idle;
100 commutation_timer <= idle;
101 end if;
101 END IF;
102
102
103 when engaged =>
103 WHEN engaged =>
104 sirq1 <= '0'; -- stop the pulse on sirq1
104 sirq1 <= '0'; -- stop the pulse on sirq1
105 if not(p_clk_div = clk_div) and clk_div = '1' then -- detect a clk_div raising edge
105 IF NOT(p_clk_div = clk_div) AND clk_div = '1' THEN -- detect a clk_div raising edge
106 if cpt_next_commutation = 65536 then
106 IF cpt_next_commutation = 65536 THEN
107 cpt_next_commutation <= 0;
107 cpt_next_commutation <= 0;
108 commutation_timer <= idle;
108 commutation_timer <= idle;
109 sirq2 <= '1'; -- start the pulse on sirq2
109 sirq2 <= '1'; -- start the pulse on sirq2
110 else
110 ELSE
111 cpt_next_commutation <= cpt_next_commutation + 1;
111 cpt_next_commutation <= cpt_next_commutation + 1;
112 end if;
112 END IF;
113 end if;
113 END IF;
114
114
115 when others =>
115 WHEN OTHERS =>
116 commutation_timer <= idle;
116 commutation_timer <= idle;
117
117
118 end case;
118 END CASE;
119
120 p_next_commutation <= next_commutation;
121 p_clk_div <= clk_div;
122
123 end if;
124
119
125 end process;
120 p_next_commutation <= next_commutation;
121 p_clk_div <= clk_div;
122
123 END IF;
126
124
127 irq1 <= sirq1;
125 END PROCESS;
128 irq2 <= sirq2;
126
129 reset_next_commutation <= '0';
127 irq1 <= sirq1;
128 irq2 <= sirq2;
129 reset_next_commutation <= '0';
130
130
131 --
131 --
132 --*******************************************
132 --*******************************************
133
133
134 --**********************
134 --**********************
135 -- synchronization stage
135 -- synchronization stage
136 process(master_clock, resetn) -- resynchronisation with clk
136 PROCESS(master_clock, resetn) -- resynchronisation with clk
137 begin
137 BEGIN
138
138
139 if resetn = '0' then
139 IF resetn = '0' THEN
140 coarse_time(31 downto 0) <= x"80000000"; -- set the most significant bit of the coarse time to 1 on reset
140 coarse_time(31 DOWNTO 0) <= x"80000000"; -- set the most significant bit of the coarse time to 1 on reset
141
141
142 elsif master_clock'event and master_clock = '1' then
142 ELSIF master_clock'EVENT AND master_clock = '1' THEN
143 coarse_time(31 downto 0) <= s_coarse_time(31 downto 0); -- coarse_time is changed synchronously with clk
143 coarse_time(31 DOWNTO 0) <= s_coarse_time(31 DOWNTO 0); -- coarse_time is changed synchronously with clk
144 end if;
144 END IF;
145
145
146 end process;
146 END PROCESS;
147 --
147 --
148 --**********************
148 --**********************
149
149
150
150
151 process(clk_div, resetn, grspw_tick, soft_tick, flag, coarse_time_load) --
151 -- PROCESS(clk_div, resetn, grspw_tick, soft_tick, flag, coarse_time_load) -- JC
152 begin
152 PROCESS(clk_div, resetn) -- JC
153 BEGIN
154
155 IF resetn = '0' THEN
156 flag <= '0';
157 cpt <= 0;
158 secondary_cpt <= 0;
159 s_coarse_time <= x"80000000"; -- set the most significant bit of the coarse time to 1 on reset
160 previous_coarse_time_load <= x"80000000";
161 state <= auto;
162
163 --ELSIF grspw_tick = '1' OR soft_tick = '1' THEN
164 -- --IF flag = '1' THEN -- coarse_time_load shall change at least 1/65536 s before the timecode
165 -- -- s_coarse_time <= coarse_time_load;
166 -- -- flag <= '0';
167 -- --ELSE -- if coarse_time_load has not changed, increment the value autonomously
168 -- -- s_coarse_time <= STD_LOGIC_VECTOR(UNSIGNED(s_coarse_time) + 1);
169 -- --END IF;
153
170
154 if resetn = '0' then
171 -- cpt <= 0;
155 flag <= '0';
172 -- secondary_cpt <= 0;
156 cpt <= 0;
173 -- state <= slave;
157 secondary_cpt <= 0;
174
158 s_coarse_time <= x"80000000"; -- set the most significant bit of the coarse time to 1 on reset
175 ELSIF clk_div'EVENT AND clk_div = '1' THEN
159 previous_coarse_time_load <= x"80000000";
176
160 state <= auto;
177 CASE state IS
161
178
162 elsif grspw_tick = '1' or soft_tick = '1' then
179 WHEN auto =>
163 if flag = '1' then -- coarse_time_load shall change at least 1/65536 s before the timecode
180 IF grspw_tick = '1' OR soft_tick = '1' THEN
164 s_coarse_time <= coarse_time_load;
181 IF flag = '1' THEN -- coarse_time_load shall change at least 1/65536 s before the timecode
165 flag <= '0';
182 s_coarse_time <= coarse_time_load;
166 else -- if coarse_time_load has not changed, increment the value autonomously
183 ELSE -- if coarse_time_load has not changed, increment the value autonomously
167 s_coarse_time <= std_logic_vector(unsigned(s_coarse_time) + 1);
184 s_coarse_time <= STD_LOGIC_VECTOR(UNSIGNED(s_coarse_time) + 1);
168 end if;
185 END IF;
169 cpt <= 0;
186 flag <= '0';
170 secondary_cpt <= 0;
187 cpt <= 0;
171 state <= slave;
188 secondary_cpt <= 0;
172
189 state <= slave;
173 elsif clk_div'event and clk_div = '1' then
190 ELSE
174
191 IF cpt = 65535 THEN
175 case state is
192 IF flag = '1' THEN
176
193 s_coarse_time <= coarse_time_load;
177 when auto =>
194 flag <= '0';
178 if cpt = 65535 then
195 ELSE
179 if flag = '1' then
196 s_coarse_time <= STD_LOGIC_VECTOR(UNSIGNED(s_coarse_time) + 1);
180 s_coarse_time <= coarse_time_load;
197 END IF;
181 flag <= '0';
198 cpt <= 0;
182 else
199 secondary_cpt <= secondary_cpt + 1;
183 s_coarse_time <= std_logic_vector(unsigned(s_coarse_time) + 1);
200 ELSE
184 end if;
201 cpt <= cpt + 1;
185 cpt <= 0;
202 END IF;
186 secondary_cpt <= secondary_cpt + 1;
203 END IF;
187 else
204
188 cpt <= cpt + 1 ;
205 WHEN slave =>
189 end if;
206 IF grspw_tick = '1' OR soft_tick = '1' THEN
190
207 IF flag = '1' THEN -- coarse_time_load shall change at least 1/65536 s before the timecode
191 when slave =>
208 s_coarse_time <= coarse_time_load;
192 if cpt = 65536 + nb_clk_div_ticks then -- 1 / 65536 = 15.259 us
209 ELSE -- if coarse_time_load has not changed, increment the value autonomously
193 state <= auto; -- commutation to AUTO state
210 s_coarse_time <= STD_LOGIC_VECTOR(UNSIGNED(s_coarse_time) + 1);
194 if flag = '1' then
211 END IF;
195 s_coarse_time <= coarse_time_load;
212 flag <= '0';
196 flag <= '0';
213 cpt <= 0;
197 else
214 secondary_cpt <= 0;
198 s_coarse_time <= std_logic_vector(unsigned(s_coarse_time) + 1);
215 state <= slave;
199 end if;
216 ELSE
200 cpt <= nb_clk_div_ticks; -- reset cpt at nb_clk_div_ticks
217 IF cpt = 65536 + nb_clk_div_ticks THEN -- 1 / 65536 = 15.259 us
201 secondary_cpt <= secondary_cpt + 1;
218 state <= auto; -- commutation to AUTO state
202 else
219 IF flag = '1' THEN
203 cpt <= cpt + 1;
220 s_coarse_time <= coarse_time_load;
204 end if;
221 flag <= '0';
205
222 ELSE
206 when others =>
223 s_coarse_time <= STD_LOGIC_VECTOR(UNSIGNED(s_coarse_time) + 1);
207 state <= auto;
224 END IF;
225 cpt <= nb_clk_div_ticks; -- reset cpt at nb_clk_div_ticks
226 secondary_cpt <= secondary_cpt + 1;
227 ELSE
228 cpt <= cpt + 1;
229 END IF;
230 END IF;
231
232 WHEN OTHERS =>
233 state <= auto;
208
234
209 end case;
235 END CASE;
210
236
211 if secondary_cpt > 60 then
237 IF secondary_cpt > 60 THEN
212 s_coarse_time(31) <= '1';
238 s_coarse_time(31) <= '1';
213 end if;
239 END IF;
214
240
215 if not(previous_coarse_time_load = coarse_time_load) then
241 IF NOT(previous_coarse_time_load = coarse_time_load) THEN
216 flag <= '1';
242 flag <= '1';
217 end if;
243 END IF;
218
244
219 previous_coarse_time_load <= coarse_time_load;
245 previous_coarse_time_load <= coarse_time_load;
220
246
221 end if;
247 END IF;
222
248
223 end process;
249 END PROCESS;
224
250
225 fine_time <= std_logic_vector(to_unsigned(cpt, 32));
251 fine_time <= STD_LOGIC_VECTOR(to_unsigned(cpt, 32));
226
252
227 -- resetn grspw_tick soft_tick resetn_clk_div
253 -- resetn grspw_tick soft_tick resetn_clk_div
228 -- 0 0 0 0
254 -- 0 0 0 0
229 -- 0 0 1 0
255 -- 0 0 1 0
230 -- 0 1 0 0
256 -- 0 1 0 0
231 -- 0 1 1 0
257 -- 0 1 1 0
232 -- 1 0 0 1
258 -- 1 0 0 1
233 -- 1 0 1 0
259 -- 1 0 1 0
234 -- 1 1 0 0
260 -- 1 1 0 0
235 -- 1 1 1 0
261 -- 1 1 1 0
236 resetn_clk_div <= '1' when ( (resetn='1') and (grspw_tick='0') and (soft_tick='0') ) else '0';
262 resetn_clk_div <= '1' WHEN ((resetn = '1') AND (grspw_tick = '0') AND (soft_tick = '0')) ELSE '0';
237 Clk_divider0 : Clk_divider -- the target frequency is 65536 Hz
263 Clk_divider0 : Clk_divider -- the target frequency is 65536 Hz
238 generic map (timeclk,finetimeclk) port map ( time_clock, resetn_clk_div, clk_div);
264 GENERIC MAP (timeclk, finetimeclk) PORT MAP (time_clock, resetn_clk_div, clk_div);
239
265
240 end Behavioral; No newline at end of file
266 END Behavioral;
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@@ -80,7 +80,7 signal nCE3int : std_logic:='1';
80 Type stateT is (idle,st1,st2,st3,st4);
80 Type stateT is (idle,st1,st2,st3,st4);
81 signal state : stateT;
81 signal state : stateT;
82
82
83 SIGNAL nclk : STD_LOGIC;
83 --SIGNAL nclk : STD_LOGIC;
84
84
85 begin
85 begin
86
86
@@ -104,9 +104,9 begin
104 end if;
104 end if;
105 end process;
105 end process;
106
106
107 nclk <= NOT clk;
107 --nclk <= NOT clk;
108 ssram_clk_pad : outpad generic map (tech => tech)
108 ssram_clk_pad : outpad generic map (tech => tech)
109 port map (SSRAM_CLK,nclk);
109 port map (SSRAM_CLK,NOT clk);
110
110
111
111
112 nBWaint <= mem_ctrlr_o.WRN(3)or mem_ctrlr_o.ramsn(0);
112 nBWaint <= mem_ctrlr_o.WRN(3)or mem_ctrlr_o.ramsn(0);
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@@ -125,7 +125,7 ARCHITECTURE beh OF lpp_top_apbreg IS
125 CONSTANT REVISION : INTEGER := 1;
125 CONSTANT REVISION : INTEGER := 1;
126
126
127 CONSTANT pconfig : apb_config_type := (
127 CONSTANT pconfig : apb_config_type := (
128 0 => ahb_device_reg (VENDOR_LPP, LPP_DMA_TYPE, 0, REVISION, pirq),
128 0 => ahb_device_reg (VENDOR_LPP, LPP_DMA_TYPE, 10, REVISION, pirq),
129 1 => apb_iobar(paddr, pmask));
129 1 => apb_iobar(paddr, pmask));
130
130
131 TYPE lpp_SpectralMatrix_regs IS RECORD
131 TYPE lpp_SpectralMatrix_regs IS RECORD
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This diff has been collapsed as it changes many lines, (768 lines changed) Show them Hide them
@@ -1,384 +1,384
1
1
2 ------------------------------------------------------------------------------
2 ------------------------------------------------------------------------------
3 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- This file is a part of the LPP VHDL IP LIBRARY
4 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
5 --
5 --
6 -- This program is free software; you can redistribute it and/or modify
6 -- This program is free software; you can redistribute it and/or modify
7 -- it under the terms of the GNU General Public License as published by
7 -- it under the terms of the GNU General Public License as published by
8 -- the Free Software Foundation; either version 3 of the License, or
8 -- the Free Software Foundation; either version 3 of the License, or
9 -- (at your option) any later version.
9 -- (at your option) any later version.
10 --
10 --
11 -- This program is distributed in the hope that it will be useful,
11 -- This program is distributed in the hope that it will be useful,
12 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
13 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 -- GNU General Public License for more details.
14 -- GNU General Public License for more details.
15 --
15 --
16 -- You should have received a copy of the GNU General Public License
16 -- You should have received a copy of the GNU General Public License
17 -- along with this program; if not, write to the Free Software
17 -- along with this program; if not, write to the Free Software
18 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 -------------------------------------------------------------------------------
19 -------------------------------------------------------------------------------
20 -- Author : Jean-christophe Pellion
20 -- Author : Jean-christophe Pellion
21 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
22 -- jean-christophe.pellion@easii-ic.com
22 -- jean-christophe.pellion@easii-ic.com
23 -------------------------------------------------------------------------------
23 -------------------------------------------------------------------------------
24 -- 1.0 - initial version
24 -- 1.0 - initial version
25 -- 1.1 - (01/11/2013) FIX boundary error (1kB address should not be crossed by BURSTS)
25 -- 1.1 - (01/11/2013) FIX boundary error (1kB address should not be crossed by BURSTS)
26 -------------------------------------------------------------------------------
26 -------------------------------------------------------------------------------
27 LIBRARY ieee;
27 LIBRARY ieee;
28 USE ieee.std_logic_1164.ALL;
28 USE ieee.std_logic_1164.ALL;
29 USE ieee.numeric_std.ALL;
29 USE ieee.numeric_std.ALL;
30 LIBRARY grlib;
30 LIBRARY grlib;
31 USE grlib.amba.ALL;
31 USE grlib.amba.ALL;
32 USE grlib.stdlib.ALL;
32 USE grlib.stdlib.ALL;
33 USE grlib.devices.ALL;
33 USE grlib.devices.ALL;
34 USE GRLIB.DMA2AHB_Package.ALL;
34 USE GRLIB.DMA2AHB_Package.ALL;
35 LIBRARY lpp;
35 LIBRARY lpp;
36 USE lpp.lpp_amba.ALL;
36 USE lpp.lpp_amba.ALL;
37 USE lpp.apb_devices_list.ALL;
37 USE lpp.apb_devices_list.ALL;
38 USE lpp.lpp_memory.ALL;
38 USE lpp.lpp_memory.ALL;
39 USE lpp.lpp_dma_pkg.ALL;
39 USE lpp.lpp_dma_pkg.ALL;
40 USE lpp.lpp_waveform_pkg.ALL;
40 USE lpp.lpp_waveform_pkg.ALL;
41 LIBRARY techmap;
41 LIBRARY techmap;
42 USE techmap.gencomp.ALL;
42 USE techmap.gencomp.ALL;
43
43
44
44
45 ENTITY lpp_waveform_dma IS
45 ENTITY lpp_waveform_dma IS
46 GENERIC (
46 GENERIC (
47 data_size : INTEGER := 160;
47 data_size : INTEGER := 160;
48 tech : INTEGER := inferred;
48 tech : INTEGER := inferred;
49 hindex : INTEGER := 2;
49 hindex : INTEGER := 2;
50 nb_burst_available_size : INTEGER := 11
50 nb_burst_available_size : INTEGER := 11
51 );
51 );
52 PORT (
52 PORT (
53 -- AMBA AHB system signals
53 -- AMBA AHB system signals
54 HCLK : IN STD_ULOGIC;
54 HCLK : IN STD_ULOGIC;
55 HRESETn : IN STD_ULOGIC;
55 HRESETn : IN STD_ULOGIC;
56 -- AMBA AHB Master Interface
56 -- AMBA AHB Master Interface
57 AHB_Master_In : IN AHB_Mst_In_Type;
57 AHB_Master_In : IN AHB_Mst_In_Type;
58 AHB_Master_Out : OUT AHB_Mst_Out_Type;
58 AHB_Master_Out : OUT AHB_Mst_Out_Type;
59 --
59 --
60 data_ready : IN STD_LOGIC_VECTOR(3 DOWNTO 0); -- todo
60 data_ready : IN STD_LOGIC_VECTOR(3 DOWNTO 0); -- todo
61 data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
61 data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
62 data_data_ren : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- todo
62 data_data_ren : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- todo
63 data_time_ren : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- todo
63 data_time_ren : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- todo
64 -- Reg
64 -- Reg
65 nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
65 nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
66 status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
66 status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
67 status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
67 status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
68 status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
68 status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
69 -- status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- New data f(i) before the current data is write by dma
69 -- status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- New data f(i) before the current data is write by dma
70 addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
70 addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
71 addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
71 addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
72 addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
72 addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
73 addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
73 addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
74 );
74 );
75 END;
75 END;
76
76
77 ARCHITECTURE Behavioral OF lpp_waveform_dma IS
77 ARCHITECTURE Behavioral OF lpp_waveform_dma IS
78 -----------------------------------------------------------------------------
78 -----------------------------------------------------------------------------
79 SIGNAL DMAIn : DMA_In_Type;
79 SIGNAL DMAIn : DMA_In_Type;
80 SIGNAL DMAOut : DMA_OUt_Type;
80 SIGNAL DMAOut : DMA_OUt_Type;
81 -----------------------------------------------------------------------------
81 -----------------------------------------------------------------------------
82 TYPE state_DMAWriteBurst IS (IDLE,
82 TYPE state_DMAWriteBurst IS (IDLE,
83 SEND_TIME_0, WAIT_TIME_0,
83 SEND_TIME_0, WAIT_TIME_0,
84 SEND_TIME_1, WAIT_TIME_1,
84 SEND_TIME_1, WAIT_TIME_1,
85 SEND_5_TIME,
85 SEND_5_TIME,
86 SEND_DATA, WAIT_DATA);
86 SEND_DATA, WAIT_DATA);
87 SIGNAL state : state_DMAWriteBurst := IDLE;
87 SIGNAL state : state_DMAWriteBurst ;
88 -----------------------------------------------------------------------------
88 -----------------------------------------------------------------------------
89 -- CONTROL
89 -- CONTROL
90 SIGNAL sel_data_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
90 SIGNAL sel_data_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
91 SIGNAL sel_data : STD_LOGIC_VECTOR(1 DOWNTO 0);
91 SIGNAL sel_data : STD_LOGIC_VECTOR(1 DOWNTO 0);
92 SIGNAL update : STD_LOGIC_VECTOR(1 DOWNTO 0);
92 SIGNAL update : STD_LOGIC_VECTOR(1 DOWNTO 0);
93 SIGNAL time_select : STD_LOGIC;
93 SIGNAL time_select : STD_LOGIC;
94 SIGNAL time_write : STD_LOGIC;
94 SIGNAL time_write : STD_LOGIC;
95 SIGNAL time_already_send : STD_LOGIC_VECTOR(3 DOWNTO 0);
95 SIGNAL time_already_send : STD_LOGIC_VECTOR(3 DOWNTO 0);
96 SIGNAL time_already_send_s : STD_LOGIC;
96 SIGNAL time_already_send_s : STD_LOGIC;
97 -----------------------------------------------------------------------------
97 -----------------------------------------------------------------------------
98 -- SEND TIME MODULE
98 -- SEND TIME MODULE
99 SIGNAL time_dmai : DMA_In_Type;
99 SIGNAL time_dmai : DMA_In_Type;
100 SIGNAL time_send : STD_LOGIC;
100 SIGNAL time_send : STD_LOGIC;
101 SIGNAL time_send_ok : STD_LOGIC;
101 SIGNAL time_send_ok : STD_LOGIC;
102 SIGNAL time_send_ko : STD_LOGIC;
102 SIGNAL time_send_ko : STD_LOGIC;
103 SIGNAL time_fifo_ren : STD_LOGIC;
103 SIGNAL time_fifo_ren : STD_LOGIC;
104 SIGNAL time_ren : STD_LOGIC;
104 SIGNAL time_ren : STD_LOGIC;
105 -----------------------------------------------------------------------------
105 -----------------------------------------------------------------------------
106 -- SEND DATA MODULE
106 -- SEND DATA MODULE
107 SIGNAL data_dmai : DMA_In_Type;
107 SIGNAL data_dmai : DMA_In_Type;
108 SIGNAL data_send : STD_LOGIC;
108 SIGNAL data_send : STD_LOGIC;
109 SIGNAL data_send_ok : STD_LOGIC;
109 SIGNAL data_send_ok : STD_LOGIC;
110 SIGNAL data_send_ko : STD_LOGIC;
110 SIGNAL data_send_ko : STD_LOGIC;
111 SIGNAL data_fifo_ren : STD_LOGIC;
111 SIGNAL data_fifo_ren : STD_LOGIC;
112 SIGNAL data_ren : STD_LOGIC;
112 SIGNAL data_ren : STD_LOGIC;
113 -----------------------------------------------------------------------------
113 -----------------------------------------------------------------------------
114 -- SELECT ADDRESS
114 -- SELECT ADDRESS
115 SIGNAL data_address : STD_LOGIC_VECTOR(31 DOWNTO 0);
115 SIGNAL data_address : STD_LOGIC_VECTOR(31 DOWNTO 0);
116 SIGNAL update_and_sel : STD_LOGIC_VECTOR(7 DOWNTO 0);
116 SIGNAL update_and_sel : STD_LOGIC_VECTOR(7 DOWNTO 0);
117 SIGNAL addr_data_reg_vector : STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
117 SIGNAL addr_data_reg_vector : STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
118 SIGNAL addr_data_vector : STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
118 SIGNAL addr_data_vector : STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
119 -----------------------------------------------------------------------------
119 -----------------------------------------------------------------------------
120 SIGNAL send_16_3_time_reg : STD_LOGIC_VECTOR(3*4-1 DOWNTO 0);
120 SIGNAL send_16_3_time_reg : STD_LOGIC_VECTOR(3*4-1 DOWNTO 0);
121 SIGNAL send_16_3_time_reg_s : STD_LOGIC_VECTOR(3*4-1 DOWNTO 0);
121 SIGNAL send_16_3_time_reg_s : STD_LOGIC_VECTOR(3*4-1 DOWNTO 0);
122 -----------------------------------------------------------------------------
122 -----------------------------------------------------------------------------
123 SIGNAL send_16_3_time : STD_LOGIC;
123 SIGNAL send_16_3_time : STD_LOGIC;
124 SIGNAL count_send_time : INTEGER;
124 SIGNAL count_send_time : INTEGER;
125 BEGIN
125 BEGIN
126
126
127 -----------------------------------------------------------------------------
127 -----------------------------------------------------------------------------
128 -- DMA to AHB interface
128 -- DMA to AHB interface
129 DMA2AHB_1 : DMA2AHB
129 DMA2AHB_1 : DMA2AHB
130 GENERIC MAP (
130 GENERIC MAP (
131 hindex => hindex,
131 hindex => hindex,
132 vendorid => VENDOR_LPP,
132 vendorid => VENDOR_LPP,
133 deviceid => 0,
133 deviceid => 0,
134 version => 0,
134 version => 0,
135 syncrst => 1,
135 syncrst => 1,
136 boundary => 1) -- FIX 11/01/2013
136 boundary => 1) -- FIX 11/01/2013
137 PORT MAP (
137 PORT MAP (
138 HCLK => HCLK,
138 HCLK => HCLK,
139 HRESETn => HRESETn,
139 HRESETn => HRESETn,
140 DMAIn => DMAIn,
140 DMAIn => DMAIn,
141 DMAOut => DMAOut,
141 DMAOut => DMAOut,
142 AHBIn => AHB_Master_In,
142 AHBIn => AHB_Master_In,
143 AHBOut => AHB_Master_Out);
143 AHBOut => AHB_Master_Out);
144 -----------------------------------------------------------------------------
144 -----------------------------------------------------------------------------
145
145
146 -----------------------------------------------------------------------------
146 -----------------------------------------------------------------------------
147 -- This module memorises when the Times info are write. When FSM send
147 -- This module memorises when the Times info are write. When FSM send
148 -- the Times info, the "reg" is set and when a full_ack is received the "reg" is reset.
148 -- the Times info, the "reg" is set and when a full_ack is received the "reg" is reset.
149 all_time_write : FOR I IN 3 DOWNTO 0 GENERATE
149 all_time_write : FOR I IN 3 DOWNTO 0 GENERATE
150 PROCESS (HCLK, HRESETn)
150 PROCESS (HCLK, HRESETn)
151 BEGIN -- PROCESS
151 BEGIN -- PROCESS
152 IF HRESETn = '0' THEN -- asynchronous reset (active low)
152 IF HRESETn = '0' THEN -- asynchronous reset (active low)
153 time_already_send(I) <= '0';
153 time_already_send(I) <= '0';
154 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
154 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
155 IF time_write = '1' AND UNSIGNED(sel_data) = I THEN
155 IF time_write = '1' AND UNSIGNED(sel_data) = I THEN
156 time_already_send(I) <= '1';
156 time_already_send(I) <= '1';
157 ELSIF status_full_ack(I) = '1' THEN
157 ELSIF status_full_ack(I) = '1' THEN
158 time_already_send(I) <= '0';
158 time_already_send(I) <= '0';
159 END IF;
159 END IF;
160 END IF;
160 END IF;
161 END PROCESS;
161 END PROCESS;
162 END GENERATE all_time_write;
162 END GENERATE all_time_write;
163
163
164
164
165
165
166 -----------------------------------------------------------------------------
166 -----------------------------------------------------------------------------
167 sel_data_s <= "00" WHEN data_ready(0) = '1' ELSE
167 sel_data_s <= "00" WHEN data_ready(0) = '1' ELSE
168 "01" WHEN data_ready(1) = '1' ELSE
168 "01" WHEN data_ready(1) = '1' ELSE
169 "10" WHEN data_ready(2) = '1' ELSE
169 "10" WHEN data_ready(2) = '1' ELSE
170 "11";
170 "11";
171
171
172 time_already_send_s <= time_already_send(0) WHEN data_ready(0) = '1' ELSE
172 time_already_send_s <= time_already_send(0) WHEN data_ready(0) = '1' ELSE
173 time_already_send(1) WHEN data_ready(1) = '1' ELSE
173 time_already_send(1) WHEN data_ready(1) = '1' ELSE
174 time_already_send(2) WHEN data_ready(2) = '1' ELSE
174 time_already_send(2) WHEN data_ready(2) = '1' ELSE
175 time_already_send(3);
175 time_already_send(3);
176
176
177
177
178 send_16_3_time <= send_16_3_time_reg(0) WHEN data_ready(0) = '1' ELSE
178 send_16_3_time <= send_16_3_time_reg(0) WHEN data_ready(0) = '1' ELSE
179 send_16_3_time_reg(3) WHEN data_ready(1) = '1' ELSE
179 send_16_3_time_reg(3) WHEN data_ready(1) = '1' ELSE
180 send_16_3_time_reg(6) WHEN data_ready(2) = '1' ELSE
180 send_16_3_time_reg(6) WHEN data_ready(2) = '1' ELSE
181 send_16_3_time_reg(9) ;
181 send_16_3_time_reg(9) ;
182
182
183 all_send_16_3: FOR I IN 3 DOWNTO 0 GENERATE
183 all_send_16_3: FOR I IN 3 DOWNTO 0 GENERATE
184 send_16_3_time_reg_s(3*(I+1)-1 DOWNTO 3*I) <=
184 send_16_3_time_reg_s(3*(I+1)-1 DOWNTO 3*I) <=
185 send_16_3_time_reg(3*(I+1)-1 DOWNTO 3*I) WHEN data_ready(I) = '0' ELSE
185 send_16_3_time_reg(3*(I+1)-1 DOWNTO 3*I) WHEN data_ready(I) = '0' ELSE
186 send_16_3_time_reg(3*(I+1)-2 DOWNTO 3*I) & send_16_3_time_reg(3*(I+1)-1);
186 send_16_3_time_reg(3*(I+1)-2 DOWNTO 3*I) & send_16_3_time_reg(3*(I+1)-1);
187 END GENERATE all_send_16_3;
187 END GENERATE all_send_16_3;
188
188
189 -- DMA control
189 -- DMA control
190 DMAWriteFSM_p : PROCESS (HCLK, HRESETn)
190 DMAWriteFSM_p : PROCESS (HCLK, HRESETn)
191 BEGIN -- PROCESS DMAWriteBurst_p
191 BEGIN -- PROCESS DMAWriteBurst_p
192 IF HRESETn = '0' THEN
192 IF HRESETn = '0' THEN
193 state <= IDLE;
193 state <= IDLE;
194
194
195 sel_data <= "00";
195 sel_data <= "00";
196 update <= "00";
196 update <= "00";
197 time_select <= '0';
197 time_select <= '0';
198 time_fifo_ren <= '1';
198 time_fifo_ren <= '1';
199 data_send <= '0';
199 data_send <= '0';
200 time_send <= '0';
200 time_send <= '0';
201 time_write <= '0';
201 time_write <= '0';
202 --send_16_3_time <= "001";
202 --send_16_3_time <= "001";
203 send_16_3_time_reg(3*1-1 DOWNTO 3*0) <= "001";
203 send_16_3_time_reg(3*1-1 DOWNTO 3*0) <= "001";
204 send_16_3_time_reg(3*2-1 DOWNTO 3*1) <= "001";
204 send_16_3_time_reg(3*2-1 DOWNTO 3*1) <= "001";
205 send_16_3_time_reg(3*3-1 DOWNTO 3*2) <= "001";
205 send_16_3_time_reg(3*3-1 DOWNTO 3*2) <= "001";
206 send_16_3_time_reg(3*4-1 DOWNTO 3*3) <= "001";
206 send_16_3_time_reg(3*4-1 DOWNTO 3*3) <= "001";
207
207
208 ELSIF HCLK'EVENT AND HCLK = '1' THEN
208 ELSIF HCLK'EVENT AND HCLK = '1' THEN
209
209
210 CASE state IS
210 CASE state IS
211 WHEN IDLE =>
211 WHEN IDLE =>
212 count_send_time <= 0;
212 count_send_time <= 0;
213 sel_data <= "00";
213 sel_data <= "00";
214 update <= "00";
214 update <= "00";
215 time_select <= '0';
215 time_select <= '0';
216 time_fifo_ren <= '1';
216 time_fifo_ren <= '1';
217 data_send <= '0';
217 data_send <= '0';
218 time_send <= '0';
218 time_send <= '0';
219 time_write <= '0';
219 time_write <= '0';
220
220
221 IF data_ready = "0000" THEN
221 IF data_ready = "0000" THEN
222 state <= IDLE;
222 state <= IDLE;
223 ELSE
223 ELSE
224 sel_data <= sel_data_s;
224 sel_data <= sel_data_s;
225 send_16_3_time_reg <= send_16_3_time_reg_s;
225 send_16_3_time_reg <= send_16_3_time_reg_s;
226 IF send_16_3_time = '1' THEN
226 IF send_16_3_time = '1' THEN
227 state <= SEND_TIME_0;
227 state <= SEND_TIME_0;
228 ELSE
228 ELSE
229 state <= SEND_5_TIME;
229 state <= SEND_5_TIME;
230 END IF;
230 END IF;
231 END IF;
231 END IF;
232
232
233 WHEN SEND_TIME_0 =>
233 WHEN SEND_TIME_0 =>
234 time_select <= '1';
234 time_select <= '1';
235 IF time_already_send_s = '0' THEN
235 IF time_already_send_s = '0' THEN
236 time_send <= '1';
236 time_send <= '1';
237 state <= WAIT_TIME_0;
237 state <= WAIT_TIME_0;
238 ELSE
238 ELSE
239 time_send <= '0';
239 time_send <= '0';
240 state <= SEND_TIME_1;
240 state <= SEND_TIME_1;
241 END IF;
241 END IF;
242 time_fifo_ren <= '0';
242 time_fifo_ren <= '0';
243
243
244 WHEN WAIT_TIME_0 =>
244 WHEN WAIT_TIME_0 =>
245 time_fifo_ren <= '1';
245 time_fifo_ren <= '1';
246 update <= "00";
246 update <= "00";
247 time_send <= '0';
247 time_send <= '0';
248 IF time_send_ok = '1' OR time_send_ko = '1' THEN
248 IF time_send_ok = '1' OR time_send_ko = '1' THEN
249 update <= "01";
249 update <= "01";
250 state <= SEND_TIME_1;
250 state <= SEND_TIME_1;
251 END IF;
251 END IF;
252
252
253 WHEN SEND_TIME_1 =>
253 WHEN SEND_TIME_1 =>
254 time_select <= '1';
254 time_select <= '1';
255 IF time_already_send_s = '0' THEN
255 IF time_already_send_s = '0' THEN
256 time_send <= '1';
256 time_send <= '1';
257 state <= WAIT_TIME_1;
257 state <= WAIT_TIME_1;
258 ELSE
258 ELSE
259 time_send <= '0';
259 time_send <= '0';
260 state <= SEND_5_TIME;
260 state <= SEND_5_TIME;
261 END IF;
261 END IF;
262 time_fifo_ren <= '0';
262 time_fifo_ren <= '0';
263
263
264 WHEN WAIT_TIME_1 =>
264 WHEN WAIT_TIME_1 =>
265 time_fifo_ren <= '1';
265 time_fifo_ren <= '1';
266 update <= "00";
266 update <= "00";
267 time_send <= '0';
267 time_send <= '0';
268 IF time_send_ok = '1' OR time_send_ko = '1' THEN
268 IF time_send_ok = '1' OR time_send_ko = '1' THEN
269 time_write <= '1';
269 time_write <= '1';
270 update <= "01";
270 update <= "01";
271 state <= SEND_5_TIME;
271 state <= SEND_5_TIME;
272 END IF;
272 END IF;
273
273
274 WHEN SEND_5_TIME =>
274 WHEN SEND_5_TIME =>
275 update <= "00";
275 update <= "00";
276 time_select <= '1';
276 time_select <= '1';
277 time_fifo_ren <= '0';
277 time_fifo_ren <= '0';
278 count_send_time <= count_send_time + 1;
278 count_send_time <= count_send_time + 1;
279 IF count_send_time = 10 THEN
279 IF count_send_time = 10 THEN
280 state <= SEND_DATA;
280 state <= SEND_DATA;
281 END IF;
281 END IF;
282
282
283 WHEN SEND_DATA =>
283 WHEN SEND_DATA =>
284 time_fifo_ren <= '1';
284 time_fifo_ren <= '1';
285 time_write <= '0';
285 time_write <= '0';
286 time_send <= '0';
286 time_send <= '0';
287
287
288 time_select <= '0';
288 time_select <= '0';
289 data_send <= '1';
289 data_send <= '1';
290 update <= "00";
290 update <= "00";
291 state <= WAIT_DATA;
291 state <= WAIT_DATA;
292
292
293 WHEN WAIT_DATA =>
293 WHEN WAIT_DATA =>
294 data_send <= '0';
294 data_send <= '0';
295
295
296 IF data_send_ok = '1' OR data_send_ko = '1' THEN
296 IF data_send_ok = '1' OR data_send_ko = '1' THEN
297 state <= IDLE;
297 state <= IDLE;
298 update <= "10";
298 update <= "10";
299 END IF;
299 END IF;
300
300
301 WHEN OTHERS => NULL;
301 WHEN OTHERS => NULL;
302 END CASE;
302 END CASE;
303
303
304 END IF;
304 END IF;
305 END PROCESS DMAWriteFSM_p;
305 END PROCESS DMAWriteFSM_p;
306 -----------------------------------------------------------------------------
306 -----------------------------------------------------------------------------
307
307
308
308
309
309
310 -----------------------------------------------------------------------------
310 -----------------------------------------------------------------------------
311 -- SEND 1 word by DMA
311 -- SEND 1 word by DMA
312 -----------------------------------------------------------------------------
312 -----------------------------------------------------------------------------
313 lpp_dma_send_1word_1 : lpp_dma_send_1word
313 lpp_dma_send_1word_1 : lpp_dma_send_1word
314 PORT MAP (
314 PORT MAP (
315 HCLK => HCLK,
315 HCLK => HCLK,
316 HRESETn => HRESETn,
316 HRESETn => HRESETn,
317 DMAIn => time_dmai,
317 DMAIn => time_dmai,
318 DMAOut => DMAOut,
318 DMAOut => DMAOut,
319
319
320 send => time_send,
320 send => time_send,
321 address => data_address,
321 address => data_address,
322 data => data,
322 data => data,
323 send_ok => time_send_ok,
323 send_ok => time_send_ok,
324 send_ko => time_send_ko
324 send_ko => time_send_ko
325 );
325 );
326
326
327 -----------------------------------------------------------------------------
327 -----------------------------------------------------------------------------
328 -- SEND 16 word by DMA (in burst mode)
328 -- SEND 16 word by DMA (in burst mode)
329 -----------------------------------------------------------------------------
329 -----------------------------------------------------------------------------
330 lpp_dma_send_16word_1 : lpp_dma_send_16word
330 lpp_dma_send_16word_1 : lpp_dma_send_16word
331 PORT MAP (
331 PORT MAP (
332 HCLK => HCLK,
332 HCLK => HCLK,
333 HRESETn => HRESETn,
333 HRESETn => HRESETn,
334 DMAIn => data_dmai,
334 DMAIn => data_dmai,
335 DMAOut => DMAOut,
335 DMAOut => DMAOut,
336
336
337 send => data_send,
337 send => data_send,
338 address => data_address,
338 address => data_address,
339 data => data,
339 data => data,
340 ren => data_fifo_ren,
340 ren => data_fifo_ren,
341 send_ok => data_send_ok,
341 send_ok => data_send_ok,
342 send_ko => data_send_ko);
342 send_ko => data_send_ko);
343
343
344 DMAIn <= time_dmai WHEN time_select = '1' ELSE data_dmai;
344 DMAIn <= time_dmai WHEN time_select = '1' ELSE data_dmai;
345 data_ren <= '1' WHEN time_select = '1' ELSE data_fifo_ren;
345 data_ren <= '1' WHEN time_select = '1' ELSE data_fifo_ren;
346 time_ren <= time_fifo_ren WHEN time_select = '1' ELSE '1';
346 time_ren <= time_fifo_ren WHEN time_select = '1' ELSE '1';
347
347
348 all_data_ren : FOR I IN 3 DOWNTO 0 GENERATE
348 all_data_ren : FOR I IN 3 DOWNTO 0 GENERATE
349 data_data_ren(I) <= data_ren WHEN UNSIGNED(sel_data) = I ELSE '1';
349 data_data_ren(I) <= data_ren WHEN UNSIGNED(sel_data) = I ELSE '1';
350 data_time_ren(I) <= time_ren WHEN UNSIGNED(sel_data) = I ELSE '1';
350 data_time_ren(I) <= time_ren WHEN UNSIGNED(sel_data) = I ELSE '1';
351 END GENERATE all_data_ren;
351 END GENERATE all_data_ren;
352
352
353 -----------------------------------------------------------------------------
353 -----------------------------------------------------------------------------
354 -- SELECT ADDRESS
354 -- SELECT ADDRESS
355 addr_data_reg_vector <= addr_data_f3 & addr_data_f2 & addr_data_f1 & addr_data_f0;
355 addr_data_reg_vector <= addr_data_f3 & addr_data_f2 & addr_data_f1 & addr_data_f0;
356
356
357 gen_select_address : FOR I IN 3 DOWNTO 0 GENERATE
357 gen_select_address : FOR I IN 3 DOWNTO 0 GENERATE
358
358
359 update_and_sel((2*I)+1 DOWNTO 2*I) <= update WHEN UNSIGNED(sel_data) = I ELSE "00";
359 update_and_sel((2*I)+1 DOWNTO 2*I) <= update WHEN UNSIGNED(sel_data) = I ELSE "00";
360
360
361 lpp_waveform_dma_selectaddress_I : lpp_waveform_dma_selectaddress
361 lpp_waveform_dma_selectaddress_I : lpp_waveform_dma_selectaddress
362 GENERIC MAP (
362 GENERIC MAP (
363 nb_burst_available_size => nb_burst_available_size)
363 nb_burst_available_size => nb_burst_available_size)
364 PORT MAP (
364 PORT MAP (
365 HCLK => HCLK,
365 HCLK => HCLK,
366 HRESETn => HRESETn,
366 HRESETn => HRESETn,
367 update => update_and_sel((2*I)+1 DOWNTO 2*I),
367 update => update_and_sel((2*I)+1 DOWNTO 2*I),
368 nb_burst_available => nb_burst_available,
368 nb_burst_available => nb_burst_available,
369 addr_data_reg => addr_data_reg_vector(32*I+31 DOWNTO 32*I),
369 addr_data_reg => addr_data_reg_vector(32*I+31 DOWNTO 32*I),
370 addr_data => addr_data_vector(32*I+31 DOWNTO 32*I),
370 addr_data => addr_data_vector(32*I+31 DOWNTO 32*I),
371 status_full => status_full(I),
371 status_full => status_full(I),
372 status_full_ack => status_full_ack(I),
372 status_full_ack => status_full_ack(I),
373 status_full_err => status_full_err(I));
373 status_full_err => status_full_err(I));
374
374
375 END GENERATE gen_select_address;
375 END GENERATE gen_select_address;
376
376
377 data_address <= addr_data_vector(31 DOWNTO 0) WHEN UNSIGNED(sel_data) = 0 ELSE
377 data_address <= addr_data_vector(31 DOWNTO 0) WHEN UNSIGNED(sel_data) = 0 ELSE
378 addr_data_vector(32*1+31 DOWNTO 32*1) WHEN UNSIGNED(sel_data) = 1 ELSE
378 addr_data_vector(32*1+31 DOWNTO 32*1) WHEN UNSIGNED(sel_data) = 1 ELSE
379 addr_data_vector(32*2+31 DOWNTO 32*2) WHEN UNSIGNED(sel_data) = 2 ELSE
379 addr_data_vector(32*2+31 DOWNTO 32*2) WHEN UNSIGNED(sel_data) = 2 ELSE
380 addr_data_vector(32*3+31 DOWNTO 32*3);
380 addr_data_vector(32*3+31 DOWNTO 32*3);
381 -----------------------------------------------------------------------------
381 -----------------------------------------------------------------------------
382
382
383
383
384 END Behavioral;
384 END Behavioral; No newline at end of file
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