# HG changeset patch # User pellion # Date 2013-05-27 06:38:16 # Node ID 6bd9124e267bb0c5f14c52072046ccf7961d98e3 # Parent 0a2e89e955b6bb9da26e7e74eeca2cdbd4dd70be temp diff --git a/lib/lpp/lfr_time_management/apb_lfr_time_management.vhd b/lib/lpp/lfr_time_management/apb_lfr_time_management.vhd --- a/lib/lpp/lfr_time_management/apb_lfr_time_management.vhd +++ b/lib/lpp/lfr_time_management/apb_lfr_time_management.vhd @@ -1,30 +1,30 @@ ----------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 11:17:05 07/02/2012 --- Design Name: --- Module Name: apb_lfr_time_management - Behavioral --- Project Name: --- Target Devices: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- ----------------------------------------------------------------------------------- -LIBRARY IEEE; -USE IEEE.STD_LOGIC_1164.ALL; -USE IEEE.NUMERIC_STD.ALL; -LIBRARY grlib; -USE grlib.amba.ALL; -USE grlib.stdlib.ALL; -USE grlib.devices.ALL; -LIBRARY lpp; +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 11:17:05 07/02/2012 +-- Design Name: +-- Module Name: apb_lfr_time_management - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.NUMERIC_STD.ALL; +LIBRARY grlib; +USE grlib.amba.ALL; +USE grlib.stdlib.ALL; +USE grlib.devices.ALL; +LIBRARY lpp; USE lpp.apb_devices_list.ALL; USE lpp.lpp_lfr_time_management.ALL; @@ -62,7 +62,7 @@ ARCHITECTURE Behavioral OF apb_lfr_time_ --! type apb_config_type is array (0 to NAPBCFG-1) of amba_config_word; CONSTANT pconfig : apb_config_type := ( --! 0 => ahb_device_reg (VENDOR_LPP, LPP_ROTARY, 0, REVISION, 0), - 0 => ahb_device_reg (VENDOR_LPP, 0, 0, REVISION, pirq), + 0 => ahb_device_reg (VENDOR_LPP, 14, 0, REVISION, pirq), 1 => apb_iobar(paddr, pmask)); TYPE apb_lfr_time_management_Reg IS RECORD diff --git a/lib/lpp/lfr_time_management/lfr_time_management.vhd b/lib/lpp/lfr_time_management/lfr_time_management.vhd --- a/lib/lpp/lfr_time_management/lfr_time_management.vhd +++ b/lib/lpp/lfr_time_management/lfr_time_management.vhd @@ -17,224 +17,250 @@ -- Additional Comments: -- ---------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.NUMERIC_STD.ALL; -library lpp; -use lpp.general_purpose.Clk_divider; +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.NUMERIC_STD.ALL; +LIBRARY lpp; +USE lpp.general_purpose.Clk_divider; -entity lfr_time_management is - generic ( - masterclk : integer := 25000000; -- master clock in Hz - timeclk : integer := 49152000; -- 2nd clock in Hz - finetimeclk : integer := 65536; -- divided clock used for the fine time counter - nb_clk_div_ticks : integer := 1 -- nb ticks before commutation to AUTO state - ); - Port ( - master_clock : in std_logic; --! Clock - time_clock : in std_logic; --! 2nd Clock - resetn : in std_logic; --! Reset - grspw_tick : in std_logic; - soft_tick : in std_logic; --! soft tick, load the coarse_time value - coarse_time_load : in std_logic_vector(31 downto 0); - coarse_time : out std_logic_vector(31 downto 0); - fine_time : out std_logic_vector(31 downto 0); - next_commutation : in std_logic_vector(31 downto 0); - reset_next_commutation: out std_logic; - irq1 : out std_logic; - irq2 : out std_logic - ); -end lfr_time_management; +ENTITY lfr_time_management IS + GENERIC ( + masterclk : INTEGER := 25000000; -- master clock in Hz + timeclk : INTEGER := 49152000; -- 2nd clock in Hz + finetimeclk : INTEGER := 65536; -- divided clock used for the fine time counter + nb_clk_div_ticks : INTEGER := 1 -- nb ticks before commutation to AUTO state + ); + PORT ( + master_clock : IN STD_LOGIC; --! Clock + time_clock : IN STD_LOGIC; --! 2nd Clock + resetn : IN STD_LOGIC; --! Reset + grspw_tick : IN STD_LOGIC; + soft_tick : IN STD_LOGIC; --! soft tick, load the coarse_time value + coarse_time_load : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + fine_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + next_commutation : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + reset_next_commutation : OUT STD_LOGIC; + irq1 : OUT STD_LOGIC; + irq2 : OUT STD_LOGIC + ); +END lfr_time_management; -architecture Behavioral of lfr_time_management is +ARCHITECTURE Behavioral OF lfr_time_management IS -signal resetn_clk_div : std_logic; -signal clk_div : std_logic; + SIGNAL resetn_clk_div : STD_LOGIC; + SIGNAL clk_div : STD_LOGIC; -- -signal flag : std_logic; -signal s_coarse_time : std_logic_vector(31 downto 0); -signal previous_coarse_time_load : std_logic_vector(31 downto 0); -signal cpt : integer range 0 to 100000; -signal secondary_cpt : integer range 0 to 72000; + SIGNAL flag : STD_LOGIC; + SIGNAL s_coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL previous_coarse_time_load : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL cpt : INTEGER RANGE 0 TO 100000; + SIGNAL secondary_cpt : INTEGER RANGE 0 TO 72000; -- -signal sirq1 : std_logic; -signal sirq2 : std_logic; -signal cpt_next_commutation : integer range 0 to 100000; -signal p_next_commutation : std_logic_vector(31 downto 0); -signal latched_next_commutation : std_logic_vector(31 downto 0); -signal p_clk_div : std_logic; + SIGNAL sirq1 : STD_LOGIC; + SIGNAL sirq2 : STD_LOGIC; + SIGNAL cpt_next_commutation : INTEGER RANGE 0 TO 100000; + SIGNAL p_next_commutation : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL latched_next_commutation : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL p_clk_div : STD_LOGIC; -- -type state_type is (auto, slave); -signal state : state_type; -type timer_type is (idle, engaged); -signal commutation_timer : timer_type; + TYPE state_type IS (auto, slave); + SIGNAL state : state_type; + TYPE timer_type IS (idle, engaged); + SIGNAL commutation_timer : timer_type; -begin +BEGIN --******************************************* -- COMMUTATION TIMER AND INTERRUPT GENERATION -process(master_clock, resetn) -begin + PROCESS(master_clock, resetn) + BEGIN - if resetn = '0' then - commutation_timer <= idle; - cpt_next_commutation <= 0; - sirq1 <= '0'; - sirq2 <= '0'; - latched_next_commutation <= x"ffffffff"; - - elsif master_clock'event and master_clock = '1' then - - case commutation_timer is - - when idle => - sirq1 <= '0'; - sirq2 <= '0'; - if s_coarse_time = latched_next_commutation then - commutation_timer <= engaged; -- transition to state "engaged" - sirq1 <= '1'; -- start the pulse on sirq1 - latched_next_commutation <= x"ffffffff"; - elsif not(p_next_commutation = next_commutation) then -- next_commutation has changed - latched_next_commutation <= next_commutation; -- latch the value - else - commutation_timer <= idle; - end if; - - when engaged => - sirq1 <= '0'; -- stop the pulse on sirq1 - if not(p_clk_div = clk_div) and clk_div = '1' then -- detect a clk_div raising edge - if cpt_next_commutation = 65536 then - cpt_next_commutation <= 0; - commutation_timer <= idle; - sirq2 <= '1'; -- start the pulse on sirq2 - else - cpt_next_commutation <= cpt_next_commutation + 1; - end if; - end if; - - when others => - commutation_timer <= idle; - - end case; - - p_next_commutation <= next_commutation; - p_clk_div <= clk_div; - - end if; + IF resetn = '0' THEN + commutation_timer <= idle; + cpt_next_commutation <= 0; + sirq1 <= '0'; + sirq2 <= '0'; + latched_next_commutation <= x"ffffffff"; + + ELSIF master_clock'EVENT AND master_clock = '1' THEN + + CASE commutation_timer IS + + WHEN idle => + sirq1 <= '0'; + sirq2 <= '0'; + IF s_coarse_time = latched_next_commutation THEN + commutation_timer <= engaged; -- transition to state "engaged" + sirq1 <= '1'; -- start the pulse on sirq1 + latched_next_commutation <= x"ffffffff"; + ELSIF NOT(p_next_commutation = next_commutation) THEN -- next_commutation has changed + latched_next_commutation <= next_commutation; -- latch the value + ELSE + commutation_timer <= idle; + END IF; + + WHEN engaged => + sirq1 <= '0'; -- stop the pulse on sirq1 + IF NOT(p_clk_div = clk_div) AND clk_div = '1' THEN -- detect a clk_div raising edge + IF cpt_next_commutation = 65536 THEN + cpt_next_commutation <= 0; + commutation_timer <= idle; + sirq2 <= '1'; -- start the pulse on sirq2 + ELSE + cpt_next_commutation <= cpt_next_commutation + 1; + END IF; + END IF; + + WHEN OTHERS => + commutation_timer <= idle; + + END CASE; -end process; + p_next_commutation <= next_commutation; + p_clk_div <= clk_div; + + END IF; -irq1 <= sirq1; -irq2 <= sirq2; -reset_next_commutation <= '0'; + END PROCESS; + + irq1 <= sirq1; + irq2 <= sirq2; + reset_next_commutation <= '0'; -- --******************************************* --********************** -- synchronization stage -process(master_clock, resetn) -- resynchronisation with clk -begin + PROCESS(master_clock, resetn) -- resynchronisation with clk + BEGIN - if resetn = '0' then - coarse_time(31 downto 0) <= x"80000000"; -- set the most significant bit of the coarse time to 1 on reset + IF resetn = '0' THEN + coarse_time(31 DOWNTO 0) <= x"80000000"; -- set the most significant bit of the coarse time to 1 on reset - elsif master_clock'event and master_clock = '1' then - coarse_time(31 downto 0) <= s_coarse_time(31 downto 0); -- coarse_time is changed synchronously with clk - end if; + ELSIF master_clock'EVENT AND master_clock = '1' THEN + coarse_time(31 DOWNTO 0) <= s_coarse_time(31 DOWNTO 0); -- coarse_time is changed synchronously with clk + END IF; -end process; + END PROCESS; -- --********************** -process(clk_div, resetn, grspw_tick, soft_tick, flag, coarse_time_load) -- -begin + -- PROCESS(clk_div, resetn, grspw_tick, soft_tick, flag, coarse_time_load) -- JC + PROCESS(clk_div, resetn) -- JC + BEGIN + + IF resetn = '0' THEN + flag <= '0'; + cpt <= 0; + secondary_cpt <= 0; + s_coarse_time <= x"80000000"; -- set the most significant bit of the coarse time to 1 on reset + previous_coarse_time_load <= x"80000000"; + state <= auto; + + --ELSIF grspw_tick = '1' OR soft_tick = '1' THEN + -- --IF flag = '1' THEN -- coarse_time_load shall change at least 1/65536 s before the timecode + -- -- s_coarse_time <= coarse_time_load; + -- -- flag <= '0'; + -- --ELSE -- if coarse_time_load has not changed, increment the value autonomously + -- -- s_coarse_time <= STD_LOGIC_VECTOR(UNSIGNED(s_coarse_time) + 1); + -- --END IF; - if resetn = '0' then - flag <= '0'; - cpt <= 0; - secondary_cpt <= 0; - s_coarse_time <= x"80000000"; -- set the most significant bit of the coarse time to 1 on reset - previous_coarse_time_load <= x"80000000"; - state <= auto; - - elsif grspw_tick = '1' or soft_tick = '1' then - if flag = '1' then -- coarse_time_load shall change at least 1/65536 s before the timecode - s_coarse_time <= coarse_time_load; - flag <= '0'; - else -- if coarse_time_load has not changed, increment the value autonomously - s_coarse_time <= std_logic_vector(unsigned(s_coarse_time) + 1); - end if; - cpt <= 0; - secondary_cpt <= 0; - state <= slave; - - elsif clk_div'event and clk_div = '1' then - - case state is - - when auto => - if cpt = 65535 then - if flag = '1' then - s_coarse_time <= coarse_time_load; - flag <= '0'; - else - s_coarse_time <= std_logic_vector(unsigned(s_coarse_time) + 1); - end if; - cpt <= 0; - secondary_cpt <= secondary_cpt + 1; - else - cpt <= cpt + 1 ; - end if; - - when slave => - if cpt = 65536 + nb_clk_div_ticks then -- 1 / 65536 = 15.259 us - state <= auto; -- commutation to AUTO state - if flag = '1' then - s_coarse_time <= coarse_time_load; - flag <= '0'; - else - s_coarse_time <= std_logic_vector(unsigned(s_coarse_time) + 1); - end if; - cpt <= nb_clk_div_ticks; -- reset cpt at nb_clk_div_ticks - secondary_cpt <= secondary_cpt + 1; - else - cpt <= cpt + 1; - end if; - - when others => - state <= auto; + -- cpt <= 0; + -- secondary_cpt <= 0; + -- state <= slave; + + ELSIF clk_div'EVENT AND clk_div = '1' THEN + + CASE state IS + + WHEN auto => + IF grspw_tick = '1' OR soft_tick = '1' THEN + IF flag = '1' THEN -- coarse_time_load shall change at least 1/65536 s before the timecode + s_coarse_time <= coarse_time_load; + ELSE -- if coarse_time_load has not changed, increment the value autonomously + s_coarse_time <= STD_LOGIC_VECTOR(UNSIGNED(s_coarse_time) + 1); + END IF; + flag <= '0'; + cpt <= 0; + secondary_cpt <= 0; + state <= slave; + ELSE + IF cpt = 65535 THEN + IF flag = '1' THEN + s_coarse_time <= coarse_time_load; + flag <= '0'; + ELSE + s_coarse_time <= STD_LOGIC_VECTOR(UNSIGNED(s_coarse_time) + 1); + END IF; + cpt <= 0; + secondary_cpt <= secondary_cpt + 1; + ELSE + cpt <= cpt + 1; + END IF; + END IF; + + WHEN slave => + IF grspw_tick = '1' OR soft_tick = '1' THEN + IF flag = '1' THEN -- coarse_time_load shall change at least 1/65536 s before the timecode + s_coarse_time <= coarse_time_load; + ELSE -- if coarse_time_load has not changed, increment the value autonomously + s_coarse_time <= STD_LOGIC_VECTOR(UNSIGNED(s_coarse_time) + 1); + END IF; + flag <= '0'; + cpt <= 0; + secondary_cpt <= 0; + state <= slave; + ELSE + IF cpt = 65536 + nb_clk_div_ticks THEN -- 1 / 65536 = 15.259 us + state <= auto; -- commutation to AUTO state + IF flag = '1' THEN + s_coarse_time <= coarse_time_load; + flag <= '0'; + ELSE + s_coarse_time <= STD_LOGIC_VECTOR(UNSIGNED(s_coarse_time) + 1); + END IF; + cpt <= nb_clk_div_ticks; -- reset cpt at nb_clk_div_ticks + secondary_cpt <= secondary_cpt + 1; + ELSE + cpt <= cpt + 1; + END IF; + END IF; + + WHEN OTHERS => + state <= auto; - end case; - - if secondary_cpt > 60 then - s_coarse_time(31) <= '1'; - end if; + END CASE; + + IF secondary_cpt > 60 THEN + s_coarse_time(31) <= '1'; + END IF; - if not(previous_coarse_time_load = coarse_time_load) then - flag <= '1'; - end if; + IF NOT(previous_coarse_time_load = coarse_time_load) THEN + flag <= '1'; + END IF; - previous_coarse_time_load <= coarse_time_load; - - end if; - -end process; + previous_coarse_time_load <= coarse_time_load; + + END IF; + + END PROCESS; -fine_time <= std_logic_vector(to_unsigned(cpt, 32)); + fine_time <= STD_LOGIC_VECTOR(to_unsigned(cpt, 32)); --- resetn grspw_tick soft_tick resetn_clk_div --- 0 0 0 0 --- 0 0 1 0 --- 0 1 0 0 --- 0 1 1 0 --- 1 0 0 1 --- 1 0 1 0 --- 1 1 0 0 --- 1 1 1 0 -resetn_clk_div <= '1' when ( (resetn='1') and (grspw_tick='0') and (soft_tick='0') ) else '0'; -Clk_divider0 : Clk_divider -- the target frequency is 65536 Hz -generic map (timeclk,finetimeclk) port map ( time_clock, resetn_clk_div, clk_div); +-- resetn grspw_tick soft_tick resetn_clk_div +-- 0 0 0 0 +-- 0 0 1 0 +-- 0 1 0 0 +-- 0 1 1 0 +-- 1 0 0 1 +-- 1 0 1 0 +-- 1 1 0 0 +-- 1 1 1 0 + resetn_clk_div <= '1' WHEN ((resetn = '1') AND (grspw_tick = '0') AND (soft_tick = '0')) ELSE '0'; + Clk_divider0 : Clk_divider -- the target frequency is 65536 Hz + GENERIC MAP (timeclk, finetimeclk) PORT MAP (time_clock, resetn_clk_div, clk_div); -end Behavioral; \ No newline at end of file +END Behavioral; diff --git a/lib/lpp/lpp_memory/SSRAM_plugin.vhd b/lib/lpp/lpp_memory/SSRAM_plugin.vhd --- a/lib/lpp/lpp_memory/SSRAM_plugin.vhd +++ b/lib/lpp/lpp_memory/SSRAM_plugin.vhd @@ -80,7 +80,7 @@ signal nCE3int : std_logic:='1'; Type stateT is (idle,st1,st2,st3,st4); signal state : stateT; -SIGNAL nclk : STD_LOGIC; +--SIGNAL nclk : STD_LOGIC; begin @@ -104,9 +104,9 @@ begin end if; end process; -nclk <= NOT clk; +--nclk <= NOT clk; ssram_clk_pad : outpad generic map (tech => tech) - port map (SSRAM_CLK,nclk); + port map (SSRAM_CLK,NOT clk); nBWaint <= mem_ctrlr_o.WRN(3)or mem_ctrlr_o.ramsn(0); diff --git a/lib/lpp/lpp_top_lfr/lpp_top_apbreg.vhd b/lib/lpp/lpp_top_lfr/lpp_top_apbreg.vhd --- a/lib/lpp/lpp_top_lfr/lpp_top_apbreg.vhd +++ b/lib/lpp/lpp_top_lfr/lpp_top_apbreg.vhd @@ -125,7 +125,7 @@ ARCHITECTURE beh OF lpp_top_apbreg IS CONSTANT REVISION : INTEGER := 1; CONSTANT pconfig : apb_config_type := ( - 0 => ahb_device_reg (VENDOR_LPP, LPP_DMA_TYPE, 0, REVISION, pirq), + 0 => ahb_device_reg (VENDOR_LPP, LPP_DMA_TYPE, 10, REVISION, pirq), 1 => apb_iobar(paddr, pmask)); TYPE lpp_SpectralMatrix_regs IS RECORD diff --git a/lib/lpp/lpp_waveform/lpp_waveform_dma.vhd b/lib/lpp/lpp_waveform/lpp_waveform_dma.vhd --- a/lib/lpp/lpp_waveform/lpp_waveform_dma.vhd +++ b/lib/lpp/lpp_waveform/lpp_waveform_dma.vhd @@ -1,384 +1,384 @@ - ------------------------------------------------------------------------------- --- This file is a part of the LPP VHDL IP LIBRARY --- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program; if not, write to the Free Software --- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -------------------------------------------------------------------------------- --- Author : Jean-christophe Pellion --- Mail : jean-christophe.pellion@lpp.polytechnique.fr --- jean-christophe.pellion@easii-ic.com -------------------------------------------------------------------------------- --- 1.0 - initial version --- 1.1 - (01/11/2013) FIX boundary error (1kB address should not be crossed by BURSTS) -------------------------------------------------------------------------------- -LIBRARY ieee; -USE ieee.std_logic_1164.ALL; -USE ieee.numeric_std.ALL; -LIBRARY grlib; -USE grlib.amba.ALL; -USE grlib.stdlib.ALL; -USE grlib.devices.ALL; -USE GRLIB.DMA2AHB_Package.ALL; -LIBRARY lpp; -USE lpp.lpp_amba.ALL; -USE lpp.apb_devices_list.ALL; -USE lpp.lpp_memory.ALL; -USE lpp.lpp_dma_pkg.ALL; -USE lpp.lpp_waveform_pkg.ALL; -LIBRARY techmap; -USE techmap.gencomp.ALL; - - -ENTITY lpp_waveform_dma IS - GENERIC ( - data_size : INTEGER := 160; - tech : INTEGER := inferred; - hindex : INTEGER := 2; - nb_burst_available_size : INTEGER := 11 - ); - PORT ( - -- AMBA AHB system signals - HCLK : IN STD_ULOGIC; - HRESETn : IN STD_ULOGIC; - -- AMBA AHB Master Interface - AHB_Master_In : IN AHB_Mst_In_Type; - AHB_Master_Out : OUT AHB_Mst_Out_Type; - -- - data_ready : IN STD_LOGIC_VECTOR(3 DOWNTO 0); -- todo - data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo - data_data_ren : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- todo - data_time_ren : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- todo - -- Reg - nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0); - status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); - status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0); - status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); --- status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- New data f(i) before the current data is write by dma - addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0) - ); -END; - -ARCHITECTURE Behavioral OF lpp_waveform_dma IS - ----------------------------------------------------------------------------- - SIGNAL DMAIn : DMA_In_Type; - SIGNAL DMAOut : DMA_OUt_Type; - ----------------------------------------------------------------------------- - TYPE state_DMAWriteBurst IS (IDLE, - SEND_TIME_0, WAIT_TIME_0, - SEND_TIME_1, WAIT_TIME_1, - SEND_5_TIME, - SEND_DATA, WAIT_DATA); - SIGNAL state : state_DMAWriteBurst := IDLE; - ----------------------------------------------------------------------------- - -- CONTROL - SIGNAL sel_data_s : STD_LOGIC_VECTOR(1 DOWNTO 0); - SIGNAL sel_data : STD_LOGIC_VECTOR(1 DOWNTO 0); - SIGNAL update : STD_LOGIC_VECTOR(1 DOWNTO 0); - SIGNAL time_select : STD_LOGIC; - SIGNAL time_write : STD_LOGIC; - SIGNAL time_already_send : STD_LOGIC_VECTOR(3 DOWNTO 0); - SIGNAL time_already_send_s : STD_LOGIC; - ----------------------------------------------------------------------------- - -- SEND TIME MODULE - SIGNAL time_dmai : DMA_In_Type; - SIGNAL time_send : STD_LOGIC; - SIGNAL time_send_ok : STD_LOGIC; - SIGNAL time_send_ko : STD_LOGIC; - SIGNAL time_fifo_ren : STD_LOGIC; - SIGNAL time_ren : STD_LOGIC; - ----------------------------------------------------------------------------- - -- SEND DATA MODULE - SIGNAL data_dmai : DMA_In_Type; - SIGNAL data_send : STD_LOGIC; - SIGNAL data_send_ok : STD_LOGIC; - SIGNAL data_send_ko : STD_LOGIC; - SIGNAL data_fifo_ren : STD_LOGIC; - SIGNAL data_ren : STD_LOGIC; - ----------------------------------------------------------------------------- - -- SELECT ADDRESS - SIGNAL data_address : STD_LOGIC_VECTOR(31 DOWNTO 0); - SIGNAL update_and_sel : STD_LOGIC_VECTOR(7 DOWNTO 0); - SIGNAL addr_data_reg_vector : STD_LOGIC_VECTOR(32*4-1 DOWNTO 0); - SIGNAL addr_data_vector : STD_LOGIC_VECTOR(32*4-1 DOWNTO 0); - ----------------------------------------------------------------------------- - SIGNAL send_16_3_time_reg : STD_LOGIC_VECTOR(3*4-1 DOWNTO 0); - SIGNAL send_16_3_time_reg_s : STD_LOGIC_VECTOR(3*4-1 DOWNTO 0); - ----------------------------------------------------------------------------- - SIGNAL send_16_3_time : STD_LOGIC; - SIGNAL count_send_time : INTEGER; -BEGIN - - ----------------------------------------------------------------------------- - -- DMA to AHB interface - DMA2AHB_1 : DMA2AHB - GENERIC MAP ( - hindex => hindex, - vendorid => VENDOR_LPP, - deviceid => 0, - version => 0, - syncrst => 1, - boundary => 1) -- FIX 11/01/2013 - PORT MAP ( - HCLK => HCLK, - HRESETn => HRESETn, - DMAIn => DMAIn, - DMAOut => DMAOut, - AHBIn => AHB_Master_In, - AHBOut => AHB_Master_Out); - ----------------------------------------------------------------------------- - - ----------------------------------------------------------------------------- - -- This module memorises when the Times info are write. When FSM send - -- the Times info, the "reg" is set and when a full_ack is received the "reg" is reset. - all_time_write : FOR I IN 3 DOWNTO 0 GENERATE - PROCESS (HCLK, HRESETn) - BEGIN -- PROCESS - IF HRESETn = '0' THEN -- asynchronous reset (active low) - time_already_send(I) <= '0'; - ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge - IF time_write = '1' AND UNSIGNED(sel_data) = I THEN - time_already_send(I) <= '1'; - ELSIF status_full_ack(I) = '1' THEN - time_already_send(I) <= '0'; - END IF; - END IF; - END PROCESS; - END GENERATE all_time_write; - - - - ----------------------------------------------------------------------------- - sel_data_s <= "00" WHEN data_ready(0) = '1' ELSE - "01" WHEN data_ready(1) = '1' ELSE - "10" WHEN data_ready(2) = '1' ELSE - "11"; - - time_already_send_s <= time_already_send(0) WHEN data_ready(0) = '1' ELSE - time_already_send(1) WHEN data_ready(1) = '1' ELSE - time_already_send(2) WHEN data_ready(2) = '1' ELSE - time_already_send(3); - - - send_16_3_time <= send_16_3_time_reg(0) WHEN data_ready(0) = '1' ELSE - send_16_3_time_reg(3) WHEN data_ready(1) = '1' ELSE - send_16_3_time_reg(6) WHEN data_ready(2) = '1' ELSE - send_16_3_time_reg(9) ; - - all_send_16_3: FOR I IN 3 DOWNTO 0 GENERATE - send_16_3_time_reg_s(3*(I+1)-1 DOWNTO 3*I) <= - send_16_3_time_reg(3*(I+1)-1 DOWNTO 3*I) WHEN data_ready(I) = '0' ELSE - send_16_3_time_reg(3*(I+1)-2 DOWNTO 3*I) & send_16_3_time_reg(3*(I+1)-1); - END GENERATE all_send_16_3; - - -- DMA control - DMAWriteFSM_p : PROCESS (HCLK, HRESETn) - BEGIN -- PROCESS DMAWriteBurst_p - IF HRESETn = '0' THEN - state <= IDLE; - - sel_data <= "00"; - update <= "00"; - time_select <= '0'; - time_fifo_ren <= '1'; - data_send <= '0'; - time_send <= '0'; - time_write <= '0'; - --send_16_3_time <= "001"; - send_16_3_time_reg(3*1-1 DOWNTO 3*0) <= "001"; - send_16_3_time_reg(3*2-1 DOWNTO 3*1) <= "001"; - send_16_3_time_reg(3*3-1 DOWNTO 3*2) <= "001"; - send_16_3_time_reg(3*4-1 DOWNTO 3*3) <= "001"; - - ELSIF HCLK'EVENT AND HCLK = '1' THEN - - CASE state IS - WHEN IDLE => - count_send_time <= 0; - sel_data <= "00"; - update <= "00"; - time_select <= '0'; - time_fifo_ren <= '1'; - data_send <= '0'; - time_send <= '0'; - time_write <= '0'; - - IF data_ready = "0000" THEN - state <= IDLE; - ELSE - sel_data <= sel_data_s; - send_16_3_time_reg <= send_16_3_time_reg_s; - IF send_16_3_time = '1' THEN - state <= SEND_TIME_0; - ELSE - state <= SEND_5_TIME; - END IF; - END IF; - - WHEN SEND_TIME_0 => - time_select <= '1'; - IF time_already_send_s = '0' THEN - time_send <= '1'; - state <= WAIT_TIME_0; - ELSE - time_send <= '0'; - state <= SEND_TIME_1; - END IF; - time_fifo_ren <= '0'; - - WHEN WAIT_TIME_0 => - time_fifo_ren <= '1'; - update <= "00"; - time_send <= '0'; - IF time_send_ok = '1' OR time_send_ko = '1' THEN - update <= "01"; - state <= SEND_TIME_1; - END IF; - - WHEN SEND_TIME_1 => - time_select <= '1'; - IF time_already_send_s = '0' THEN - time_send <= '1'; - state <= WAIT_TIME_1; - ELSE - time_send <= '0'; - state <= SEND_5_TIME; - END IF; - time_fifo_ren <= '0'; - - WHEN WAIT_TIME_1 => - time_fifo_ren <= '1'; - update <= "00"; - time_send <= '0'; - IF time_send_ok = '1' OR time_send_ko = '1' THEN - time_write <= '1'; - update <= "01"; - state <= SEND_5_TIME; - END IF; - - WHEN SEND_5_TIME => - update <= "00"; - time_select <= '1'; - time_fifo_ren <= '0'; - count_send_time <= count_send_time + 1; - IF count_send_time = 10 THEN - state <= SEND_DATA; - END IF; - - WHEN SEND_DATA => - time_fifo_ren <= '1'; - time_write <= '0'; - time_send <= '0'; - - time_select <= '0'; - data_send <= '1'; - update <= "00"; - state <= WAIT_DATA; - - WHEN WAIT_DATA => - data_send <= '0'; - - IF data_send_ok = '1' OR data_send_ko = '1' THEN - state <= IDLE; - update <= "10"; - END IF; - - WHEN OTHERS => NULL; - END CASE; - - END IF; - END PROCESS DMAWriteFSM_p; - ----------------------------------------------------------------------------- - - - - ----------------------------------------------------------------------------- - -- SEND 1 word by DMA - ----------------------------------------------------------------------------- - lpp_dma_send_1word_1 : lpp_dma_send_1word - PORT MAP ( - HCLK => HCLK, - HRESETn => HRESETn, - DMAIn => time_dmai, - DMAOut => DMAOut, - - send => time_send, - address => data_address, - data => data, - send_ok => time_send_ok, - send_ko => time_send_ko - ); - - ----------------------------------------------------------------------------- - -- SEND 16 word by DMA (in burst mode) - ----------------------------------------------------------------------------- - lpp_dma_send_16word_1 : lpp_dma_send_16word - PORT MAP ( - HCLK => HCLK, - HRESETn => HRESETn, - DMAIn => data_dmai, - DMAOut => DMAOut, - - send => data_send, - address => data_address, - data => data, - ren => data_fifo_ren, - send_ok => data_send_ok, - send_ko => data_send_ko); - - DMAIn <= time_dmai WHEN time_select = '1' ELSE data_dmai; - data_ren <= '1' WHEN time_select = '1' ELSE data_fifo_ren; - time_ren <= time_fifo_ren WHEN time_select = '1' ELSE '1'; - - all_data_ren : FOR I IN 3 DOWNTO 0 GENERATE - data_data_ren(I) <= data_ren WHEN UNSIGNED(sel_data) = I ELSE '1'; - data_time_ren(I) <= time_ren WHEN UNSIGNED(sel_data) = I ELSE '1'; - END GENERATE all_data_ren; - - ----------------------------------------------------------------------------- - -- SELECT ADDRESS - addr_data_reg_vector <= addr_data_f3 & addr_data_f2 & addr_data_f1 & addr_data_f0; - - gen_select_address : FOR I IN 3 DOWNTO 0 GENERATE - - update_and_sel((2*I)+1 DOWNTO 2*I) <= update WHEN UNSIGNED(sel_data) = I ELSE "00"; - - lpp_waveform_dma_selectaddress_I : lpp_waveform_dma_selectaddress - GENERIC MAP ( - nb_burst_available_size => nb_burst_available_size) - PORT MAP ( - HCLK => HCLK, - HRESETn => HRESETn, - update => update_and_sel((2*I)+1 DOWNTO 2*I), - nb_burst_available => nb_burst_available, - addr_data_reg => addr_data_reg_vector(32*I+31 DOWNTO 32*I), - addr_data => addr_data_vector(32*I+31 DOWNTO 32*I), - status_full => status_full(I), - status_full_ack => status_full_ack(I), - status_full_err => status_full_err(I)); - - END GENERATE gen_select_address; - - data_address <= addr_data_vector(31 DOWNTO 0) WHEN UNSIGNED(sel_data) = 0 ELSE - addr_data_vector(32*1+31 DOWNTO 32*1) WHEN UNSIGNED(sel_data) = 1 ELSE - addr_data_vector(32*2+31 DOWNTO 32*2) WHEN UNSIGNED(sel_data) = 2 ELSE - addr_data_vector(32*3+31 DOWNTO 32*3); - ----------------------------------------------------------------------------- - - -END Behavioral; + +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Jean-christophe Pellion +-- Mail : jean-christophe.pellion@lpp.polytechnique.fr +-- jean-christophe.pellion@easii-ic.com +------------------------------------------------------------------------------- +-- 1.0 - initial version +-- 1.1 - (01/11/2013) FIX boundary error (1kB address should not be crossed by BURSTS) +------------------------------------------------------------------------------- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; +LIBRARY grlib; +USE grlib.amba.ALL; +USE grlib.stdlib.ALL; +USE grlib.devices.ALL; +USE GRLIB.DMA2AHB_Package.ALL; +LIBRARY lpp; +USE lpp.lpp_amba.ALL; +USE lpp.apb_devices_list.ALL; +USE lpp.lpp_memory.ALL; +USE lpp.lpp_dma_pkg.ALL; +USE lpp.lpp_waveform_pkg.ALL; +LIBRARY techmap; +USE techmap.gencomp.ALL; + + +ENTITY lpp_waveform_dma IS + GENERIC ( + data_size : INTEGER := 160; + tech : INTEGER := inferred; + hindex : INTEGER := 2; + nb_burst_available_size : INTEGER := 11 + ); + PORT ( + -- AMBA AHB system signals + HCLK : IN STD_ULOGIC; + HRESETn : IN STD_ULOGIC; + -- AMBA AHB Master Interface + AHB_Master_In : IN AHB_Mst_In_Type; + AHB_Master_Out : OUT AHB_Mst_Out_Type; + -- + data_ready : IN STD_LOGIC_VECTOR(3 DOWNTO 0); -- todo + data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo + data_data_ren : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- todo + data_time_ren : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- todo + -- Reg + nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0); + status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); +-- status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- New data f(i) before the current data is write by dma + addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0) + ); +END; + +ARCHITECTURE Behavioral OF lpp_waveform_dma IS + ----------------------------------------------------------------------------- + SIGNAL DMAIn : DMA_In_Type; + SIGNAL DMAOut : DMA_OUt_Type; + ----------------------------------------------------------------------------- + TYPE state_DMAWriteBurst IS (IDLE, + SEND_TIME_0, WAIT_TIME_0, + SEND_TIME_1, WAIT_TIME_1, + SEND_5_TIME, + SEND_DATA, WAIT_DATA); + SIGNAL state : state_DMAWriteBurst ; + ----------------------------------------------------------------------------- + -- CONTROL + SIGNAL sel_data_s : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL sel_data : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL update : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL time_select : STD_LOGIC; + SIGNAL time_write : STD_LOGIC; + SIGNAL time_already_send : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL time_already_send_s : STD_LOGIC; + ----------------------------------------------------------------------------- + -- SEND TIME MODULE + SIGNAL time_dmai : DMA_In_Type; + SIGNAL time_send : STD_LOGIC; + SIGNAL time_send_ok : STD_LOGIC; + SIGNAL time_send_ko : STD_LOGIC; + SIGNAL time_fifo_ren : STD_LOGIC; + SIGNAL time_ren : STD_LOGIC; + ----------------------------------------------------------------------------- + -- SEND DATA MODULE + SIGNAL data_dmai : DMA_In_Type; + SIGNAL data_send : STD_LOGIC; + SIGNAL data_send_ok : STD_LOGIC; + SIGNAL data_send_ko : STD_LOGIC; + SIGNAL data_fifo_ren : STD_LOGIC; + SIGNAL data_ren : STD_LOGIC; + ----------------------------------------------------------------------------- + -- SELECT ADDRESS + SIGNAL data_address : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL update_and_sel : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL addr_data_reg_vector : STD_LOGIC_VECTOR(32*4-1 DOWNTO 0); + SIGNAL addr_data_vector : STD_LOGIC_VECTOR(32*4-1 DOWNTO 0); + ----------------------------------------------------------------------------- + SIGNAL send_16_3_time_reg : STD_LOGIC_VECTOR(3*4-1 DOWNTO 0); + SIGNAL send_16_3_time_reg_s : STD_LOGIC_VECTOR(3*4-1 DOWNTO 0); + ----------------------------------------------------------------------------- + SIGNAL send_16_3_time : STD_LOGIC; + SIGNAL count_send_time : INTEGER; +BEGIN + + ----------------------------------------------------------------------------- + -- DMA to AHB interface + DMA2AHB_1 : DMA2AHB + GENERIC MAP ( + hindex => hindex, + vendorid => VENDOR_LPP, + deviceid => 0, + version => 0, + syncrst => 1, + boundary => 1) -- FIX 11/01/2013 + PORT MAP ( + HCLK => HCLK, + HRESETn => HRESETn, + DMAIn => DMAIn, + DMAOut => DMAOut, + AHBIn => AHB_Master_In, + AHBOut => AHB_Master_Out); + ----------------------------------------------------------------------------- + + ----------------------------------------------------------------------------- + -- This module memorises when the Times info are write. When FSM send + -- the Times info, the "reg" is set and when a full_ack is received the "reg" is reset. + all_time_write : FOR I IN 3 DOWNTO 0 GENERATE + PROCESS (HCLK, HRESETn) + BEGIN -- PROCESS + IF HRESETn = '0' THEN -- asynchronous reset (active low) + time_already_send(I) <= '0'; + ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge + IF time_write = '1' AND UNSIGNED(sel_data) = I THEN + time_already_send(I) <= '1'; + ELSIF status_full_ack(I) = '1' THEN + time_already_send(I) <= '0'; + END IF; + END IF; + END PROCESS; + END GENERATE all_time_write; + + + + ----------------------------------------------------------------------------- + sel_data_s <= "00" WHEN data_ready(0) = '1' ELSE + "01" WHEN data_ready(1) = '1' ELSE + "10" WHEN data_ready(2) = '1' ELSE + "11"; + + time_already_send_s <= time_already_send(0) WHEN data_ready(0) = '1' ELSE + time_already_send(1) WHEN data_ready(1) = '1' ELSE + time_already_send(2) WHEN data_ready(2) = '1' ELSE + time_already_send(3); + + + send_16_3_time <= send_16_3_time_reg(0) WHEN data_ready(0) = '1' ELSE + send_16_3_time_reg(3) WHEN data_ready(1) = '1' ELSE + send_16_3_time_reg(6) WHEN data_ready(2) = '1' ELSE + send_16_3_time_reg(9) ; + + all_send_16_3: FOR I IN 3 DOWNTO 0 GENERATE + send_16_3_time_reg_s(3*(I+1)-1 DOWNTO 3*I) <= + send_16_3_time_reg(3*(I+1)-1 DOWNTO 3*I) WHEN data_ready(I) = '0' ELSE + send_16_3_time_reg(3*(I+1)-2 DOWNTO 3*I) & send_16_3_time_reg(3*(I+1)-1); + END GENERATE all_send_16_3; + + -- DMA control + DMAWriteFSM_p : PROCESS (HCLK, HRESETn) + BEGIN -- PROCESS DMAWriteBurst_p + IF HRESETn = '0' THEN + state <= IDLE; + + sel_data <= "00"; + update <= "00"; + time_select <= '0'; + time_fifo_ren <= '1'; + data_send <= '0'; + time_send <= '0'; + time_write <= '0'; + --send_16_3_time <= "001"; + send_16_3_time_reg(3*1-1 DOWNTO 3*0) <= "001"; + send_16_3_time_reg(3*2-1 DOWNTO 3*1) <= "001"; + send_16_3_time_reg(3*3-1 DOWNTO 3*2) <= "001"; + send_16_3_time_reg(3*4-1 DOWNTO 3*3) <= "001"; + + ELSIF HCLK'EVENT AND HCLK = '1' THEN + + CASE state IS + WHEN IDLE => + count_send_time <= 0; + sel_data <= "00"; + update <= "00"; + time_select <= '0'; + time_fifo_ren <= '1'; + data_send <= '0'; + time_send <= '0'; + time_write <= '0'; + + IF data_ready = "0000" THEN + state <= IDLE; + ELSE + sel_data <= sel_data_s; + send_16_3_time_reg <= send_16_3_time_reg_s; + IF send_16_3_time = '1' THEN + state <= SEND_TIME_0; + ELSE + state <= SEND_5_TIME; + END IF; + END IF; + + WHEN SEND_TIME_0 => + time_select <= '1'; + IF time_already_send_s = '0' THEN + time_send <= '1'; + state <= WAIT_TIME_0; + ELSE + time_send <= '0'; + state <= SEND_TIME_1; + END IF; + time_fifo_ren <= '0'; + + WHEN WAIT_TIME_0 => + time_fifo_ren <= '1'; + update <= "00"; + time_send <= '0'; + IF time_send_ok = '1' OR time_send_ko = '1' THEN + update <= "01"; + state <= SEND_TIME_1; + END IF; + + WHEN SEND_TIME_1 => + time_select <= '1'; + IF time_already_send_s = '0' THEN + time_send <= '1'; + state <= WAIT_TIME_1; + ELSE + time_send <= '0'; + state <= SEND_5_TIME; + END IF; + time_fifo_ren <= '0'; + + WHEN WAIT_TIME_1 => + time_fifo_ren <= '1'; + update <= "00"; + time_send <= '0'; + IF time_send_ok = '1' OR time_send_ko = '1' THEN + time_write <= '1'; + update <= "01"; + state <= SEND_5_TIME; + END IF; + + WHEN SEND_5_TIME => + update <= "00"; + time_select <= '1'; + time_fifo_ren <= '0'; + count_send_time <= count_send_time + 1; + IF count_send_time = 10 THEN + state <= SEND_DATA; + END IF; + + WHEN SEND_DATA => + time_fifo_ren <= '1'; + time_write <= '0'; + time_send <= '0'; + + time_select <= '0'; + data_send <= '1'; + update <= "00"; + state <= WAIT_DATA; + + WHEN WAIT_DATA => + data_send <= '0'; + + IF data_send_ok = '1' OR data_send_ko = '1' THEN + state <= IDLE; + update <= "10"; + END IF; + + WHEN OTHERS => NULL; + END CASE; + + END IF; + END PROCESS DMAWriteFSM_p; + ----------------------------------------------------------------------------- + + + + ----------------------------------------------------------------------------- + -- SEND 1 word by DMA + ----------------------------------------------------------------------------- + lpp_dma_send_1word_1 : lpp_dma_send_1word + PORT MAP ( + HCLK => HCLK, + HRESETn => HRESETn, + DMAIn => time_dmai, + DMAOut => DMAOut, + + send => time_send, + address => data_address, + data => data, + send_ok => time_send_ok, + send_ko => time_send_ko + ); + + ----------------------------------------------------------------------------- + -- SEND 16 word by DMA (in burst mode) + ----------------------------------------------------------------------------- + lpp_dma_send_16word_1 : lpp_dma_send_16word + PORT MAP ( + HCLK => HCLK, + HRESETn => HRESETn, + DMAIn => data_dmai, + DMAOut => DMAOut, + + send => data_send, + address => data_address, + data => data, + ren => data_fifo_ren, + send_ok => data_send_ok, + send_ko => data_send_ko); + + DMAIn <= time_dmai WHEN time_select = '1' ELSE data_dmai; + data_ren <= '1' WHEN time_select = '1' ELSE data_fifo_ren; + time_ren <= time_fifo_ren WHEN time_select = '1' ELSE '1'; + + all_data_ren : FOR I IN 3 DOWNTO 0 GENERATE + data_data_ren(I) <= data_ren WHEN UNSIGNED(sel_data) = I ELSE '1'; + data_time_ren(I) <= time_ren WHEN UNSIGNED(sel_data) = I ELSE '1'; + END GENERATE all_data_ren; + + ----------------------------------------------------------------------------- + -- SELECT ADDRESS + addr_data_reg_vector <= addr_data_f3 & addr_data_f2 & addr_data_f1 & addr_data_f0; + + gen_select_address : FOR I IN 3 DOWNTO 0 GENERATE + + update_and_sel((2*I)+1 DOWNTO 2*I) <= update WHEN UNSIGNED(sel_data) = I ELSE "00"; + + lpp_waveform_dma_selectaddress_I : lpp_waveform_dma_selectaddress + GENERIC MAP ( + nb_burst_available_size => nb_burst_available_size) + PORT MAP ( + HCLK => HCLK, + HRESETn => HRESETn, + update => update_and_sel((2*I)+1 DOWNTO 2*I), + nb_burst_available => nb_burst_available, + addr_data_reg => addr_data_reg_vector(32*I+31 DOWNTO 32*I), + addr_data => addr_data_vector(32*I+31 DOWNTO 32*I), + status_full => status_full(I), + status_full_ack => status_full_ack(I), + status_full_err => status_full_err(I)); + + END GENERATE gen_select_address; + + data_address <= addr_data_vector(31 DOWNTO 0) WHEN UNSIGNED(sel_data) = 0 ELSE + addr_data_vector(32*1+31 DOWNTO 32*1) WHEN UNSIGNED(sel_data) = 1 ELSE + addr_data_vector(32*2+31 DOWNTO 32*2) WHEN UNSIGNED(sel_data) = 2 ELSE + addr_data_vector(32*3+31 DOWNTO 32*3); + ----------------------------------------------------------------------------- + + +END Behavioral; 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