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[WFP] Register the DMA "send" signal to permit the start of 2 burst consecutively.
pellion -
r302:6b992ec40bf9 WaveFormPicker-0-0-10 (MINI-LFR) JC
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@@ -1,23 +1,23
1 vcom -quiet -93 -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/lpp_dma_pkg.vhd
1 vcom -quiet -93 -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/lpp_dma_pkg.vhd
2 vcom -quiet -93 -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/fifo_latency_correction.vhd
2 vcom -quiet -93 -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/fifo_latency_correction.vhd
3 vcom -quiet -93 -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/lpp_dma.vhd
3 vcom -quiet -93 -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/lpp_dma.vhd
4 vcom -quiet -93 -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/lpp_dma_ip.vhd
4 vcom -quiet -93 -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/lpp_dma_ip.vhd
5 vcom -quiet -93 -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/lpp_dma_send_16word.vhd
5 vcom -quiet -93 -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/lpp_dma_send_16word.vhd
6 vcom -quiet -93 -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/lpp_dma_send_1word.vhd
6 vcom -quiet -93 -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/lpp_dma_send_1word.vhd
7 vcom -quiet -93 -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/lpp_dma_singleOrBurst.vhd
7 vcom -quiet -93 -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/lpp_dma_singleOrBurst.vhd
8
8
9 vcom -quiet -93 -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_waveform/lpp_waveform_snapshot.vhd
9 vcom -quiet -93 -work lpp ../../../grlib-ft-fpga-grlfpu-spw-1.2.4-b4126/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_waveform/lpp_waveform_snapshot.vhd
10
10
11 vcom -quiet -93 -work lpp ../../lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/iir_filter/RAM_CEL_N.vhd
11 vcom -quiet -93 -work lpp ../../lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/iir_filter/RAM_CEL_N.vhd
12
12
13 vcom -quiet -93 -work lpp testbench_package.vhd
13 vcom -quiet -93 -work lpp testbench_package.vhd
14
14
15 vcom -quiet -93 -work work tb_waveform.vhd
15 vcom -quiet -93 -work work tb_waveform.vhd
16
16
17 vsim work.testbench
17 vsim work.testbench
18
18
19 log -r *
19 log -r *
20
20
21 do wave_waveform_longsim.do
21 do wave_waveform_longsim.do
22
22
23 run 500 ms
23 run 40 ms
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@@ -1,591 +1,616
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- LEON3 Demonstration design test bench
2 -- LEON3 Demonstration design test bench
3 -- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
3 -- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
4 ------------------------------------------------------------------------------
4 ------------------------------------------------------------------------------
5 -- This file is a part of the GRLIB VHDL IP LIBRARY
5 -- This file is a part of the GRLIB VHDL IP LIBRARY
6 -- Copyright (C) 2013, Aeroflex Gaisler AB - all rights reserved.
6 -- Copyright (C) 2013, Aeroflex Gaisler AB - all rights reserved.
7 --
7 --
8 -- ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
8 -- ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
9 -- ACCORDANCE WITH THE GAISLER LICENSE AGREEMENT AND MUST BE APPROVED
9 -- ACCORDANCE WITH THE GAISLER LICENSE AGREEMENT AND MUST BE APPROVED
10 -- IN ADVANCE IN WRITING.
10 -- IN ADVANCE IN WRITING.
11 ------------------------------------------------------------------------------
11 ------------------------------------------------------------------------------
12
12
13 LIBRARY ieee;
13 LIBRARY ieee;
14 USE ieee.std_logic_1164.ALL;
14 USE ieee.std_logic_1164.ALL;
15
15
16 --LIBRARY std;
16 --LIBRARY std;
17 --USE std.textio.ALL;
17 --USE std.textio.ALL;
18
18
19 LIBRARY grlib;
19 LIBRARY grlib;
20 USE grlib.amba.ALL;
20 USE grlib.amba.ALL;
21 USE grlib.stdlib.ALL;
21 USE grlib.stdlib.ALL;
22 USE grlib.AMBA_TestPackage.ALL;
22 LIBRARY gaisler;
23 LIBRARY gaisler;
23 USE gaisler.memctrl.ALL;
24 USE gaisler.memctrl.ALL;
24 USE gaisler.leon3.ALL;
25 USE gaisler.leon3.ALL;
25 USE gaisler.uart.ALL;
26 USE gaisler.uart.ALL;
26 USE gaisler.misc.ALL;
27 USE gaisler.misc.ALL;
27 USE gaisler.libdcom.ALL;
28 USE gaisler.libdcom.ALL;
28 USE gaisler.sim.ALL;
29 USE gaisler.sim.ALL;
29 USE gaisler.jtagtst.ALL;
30 USE gaisler.jtagtst.ALL;
30 USE gaisler.misc.ALL;
31 USE gaisler.misc.ALL;
31 LIBRARY techmap;
32 LIBRARY techmap;
32 USE techmap.gencomp.ALL;
33 USE techmap.gencomp.ALL;
33 LIBRARY esa;
34 LIBRARY esa;
34 USE esa.memoryctrl.ALL;
35 USE esa.memoryctrl.ALL;
35 --LIBRARY micron;
36 --LIBRARY micron;
36 --USE micron.components.ALL;
37 --USE micron.components.ALL;
37 LIBRARY lpp;
38 LIBRARY lpp;
38 USE lpp.lpp_waveform_pkg.ALL;
39 USE lpp.lpp_waveform_pkg.ALL;
39 USE lpp.lpp_memory.ALL;
40 USE lpp.lpp_memory.ALL;
40 USE lpp.lpp_ad_conv.ALL;
41 USE lpp.lpp_ad_conv.ALL;
41 USE lpp.testbench_package.ALL;
42 USE lpp.testbench_package.ALL;
42 USE lpp.lpp_lfr_pkg.ALL;
43 USE lpp.lpp_lfr_pkg.ALL;
43 USE lpp.iir_filter.ALL;
44 USE lpp.iir_filter.ALL;
44 USE lpp.general_purpose.ALL;
45 USE lpp.general_purpose.ALL;
45 USE lpp.CY7C1061DV33_pkg.ALL;
46 USE lpp.CY7C1061DV33_pkg.ALL;
46
47
47 ENTITY testbench IS
48 ENTITY testbench IS
48 END;
49 END;
49
50
50 ARCHITECTURE behav OF testbench IS
51 ARCHITECTURE behav OF testbench IS
51 -- REG ADDRESS
52 -- REG ADDRESS
52 CONSTANT INDEX_WAVEFORM_PICKER : INTEGER := 15;
53 CONSTANT INDEX_WAVEFORM_PICKER : INTEGER := 15;
53 CONSTANT ADDR_WAVEFORM_PICKER : INTEGER := 15;
54 CONSTANT ADDR_WAVEFORM_PICKER : INTEGER := 15;
54 CONSTANT ADDR_WAVEFORM_PICKER_DATASHAPING : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F20";
55 CONSTANT ADDR_WAVEFORM_PICKER_DATASHAPING : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F20";
55 CONSTANT ADDR_WAVEFORM_PICKER_CONTROL : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F24";
56 CONSTANT ADDR_WAVEFORM_PICKER_CONTROL : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F24";
56 CONSTANT ADDR_WAVEFORM_PICKER_ADDRESS_F0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F28";
57 CONSTANT ADDR_WAVEFORM_PICKER_ADDRESS_F0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F28";
57 CONSTANT ADDR_WAVEFORM_PICKER_ADDRESS_F1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F2C";
58 CONSTANT ADDR_WAVEFORM_PICKER_ADDRESS_F1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F2C";
58 CONSTANT ADDR_WAVEFORM_PICKER_ADDRESS_F2 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F30";
59 CONSTANT ADDR_WAVEFORM_PICKER_ADDRESS_F2 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F30";
59 CONSTANT ADDR_WAVEFORM_PICKER_ADDRESS_F3 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F34";
60 CONSTANT ADDR_WAVEFORM_PICKER_ADDRESS_F3 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F34";
60 CONSTANT ADDR_WAVEFORM_PICKER_STATUS : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F38";
61 CONSTANT ADDR_WAVEFORM_PICKER_STATUS : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F38";
61 CONSTANT ADDR_WAVEFORM_PICKER_DELTASNAPSHOT : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F3C";
62 CONSTANT ADDR_WAVEFORM_PICKER_DELTASNAPSHOT : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F3C";
62 CONSTANT ADDR_WAVEFORM_PICKER_DELTA_F0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F40";
63 CONSTANT ADDR_WAVEFORM_PICKER_DELTA_F0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F40";
63 CONSTANT ADDR_WAVEFORM_PICKER_DELTA_F0_2 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F44";
64 CONSTANT ADDR_WAVEFORM_PICKER_DELTA_F0_2 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F44";
64 CONSTANT ADDR_WAVEFORM_PICKER_DELTA_F1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F48";
65 CONSTANT ADDR_WAVEFORM_PICKER_DELTA_F1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F48";
65 CONSTANT ADDR_WAVEFORM_PICKER_DELTA_F2 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F4C";
66 CONSTANT ADDR_WAVEFORM_PICKER_DELTA_F2 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F4C";
66 CONSTANT ADDR_WAVEFORM_PICKER_NB_DATA_IN_BUFFER : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F50";
67 CONSTANT ADDR_WAVEFORM_PICKER_NB_DATA_IN_BUFFER : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F50";
67 CONSTANT ADDR_WAVEFORM_PICKER_NBSNAPSHOT : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F54";
68 CONSTANT ADDR_WAVEFORM_PICKER_NBSNAPSHOT : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F54";
68 CONSTANT ADDR_WAVEFORM_PICKER_START_DATE : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F58";
69 CONSTANT ADDR_WAVEFORM_PICKER_START_DATE : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F58";
69 CONSTANT ADDR_WAVEFORM_PICKER_NB_WORD_IN_BUFFER : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F5C";
70 CONSTANT ADDR_WAVEFORM_PICKER_NB_WORD_IN_BUFFER : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F5C";
70 -- RAM ADDRESS
71 -- RAM ADDRESS
71 CONSTANT AHB_RAM_ADDR_0 : INTEGER := 16#100#;
72 CONSTANT AHB_RAM_ADDR_0 : INTEGER := 16#100#;
72 CONSTANT AHB_RAM_ADDR_1 : INTEGER := 16#200#;
73 CONSTANT AHB_RAM_ADDR_1 : INTEGER := 16#200#;
73 CONSTANT AHB_RAM_ADDR_2 : INTEGER := 16#300#;
74 CONSTANT AHB_RAM_ADDR_2 : INTEGER := 16#300#;
74 CONSTANT AHB_RAM_ADDR_3 : INTEGER := 16#400#;
75 CONSTANT AHB_RAM_ADDR_3 : INTEGER := 16#400#;
75
76
76
77
77 -- Common signal
78 -- Common signal
78 SIGNAL clk49_152MHz : STD_LOGIC := '0';
79 SIGNAL clk49_152MHz : STD_LOGIC := '0';
79 SIGNAL clk25MHz : STD_LOGIC := '0';
80 SIGNAL clk25MHz : STD_LOGIC := '0';
80 SIGNAL rstn : STD_LOGIC := '0';
81 SIGNAL rstn : STD_LOGIC := '0';
81
82
82 -- ADC interface
83 -- ADC interface
83 SIGNAL ADC_OEB_bar_CH : STD_LOGIC_VECTOR(7 DOWNTO 0); -- OUT
84 SIGNAL ADC_OEB_bar_CH : STD_LOGIC_VECTOR(7 DOWNTO 0); -- OUT
84 SIGNAL ADC_smpclk : STD_LOGIC; -- OUT
85 SIGNAL ADC_smpclk : STD_LOGIC; -- OUT
85 SIGNAL ADC_data : STD_LOGIC_VECTOR(13 DOWNTO 0); -- IN
86 SIGNAL ADC_data : STD_LOGIC_VECTOR(13 DOWNTO 0); -- IN
86
87
87 -- AD Converter RHF1401
88 -- AD Converter RHF1401
88 SIGNAL sample : Samples14v(7 DOWNTO 0);
89 SIGNAL sample : Samples14v(7 DOWNTO 0);
89 SIGNAL sample_val : STD_LOGIC;
90 SIGNAL sample_val : STD_LOGIC;
90
91
91 -- AHB/APB SIGNAL
92 -- AHB/APB SIGNAL
92 SIGNAL apbi : apb_slv_in_type;
93 SIGNAL apbi : apb_slv_in_type;
93 SIGNAL apbo : apb_slv_out_vector := (OTHERS => apb_none);
94 SIGNAL apbo : apb_slv_out_vector := (OTHERS => apb_none);
94 SIGNAL ahbsi : ahb_slv_in_type;
95 SIGNAL ahbsi : ahb_slv_in_type;
95 SIGNAL ahbso : ahb_slv_out_vector := (OTHERS => ahbs_none);
96 SIGNAL ahbso : ahb_slv_out_vector := (OTHERS => ahbs_none);
96 SIGNAL ahbmi : ahb_mst_in_type;
97 SIGNAL ahbmi : ahb_mst_in_type;
97 SIGNAL ahbmo : ahb_mst_out_vector := (OTHERS => ahbm_none);
98 SIGNAL ahbmo : ahb_mst_out_vector := (OTHERS => ahbm_none);
98
99
99 SIGNAL bias_fail_bw : STD_LOGIC;
100 SIGNAL bias_fail_bw : STD_LOGIC;
100
101
101 -----------------------------------------------------------------------------
102 -----------------------------------------------------------------------------
102 -- LPP_WAVEFORM
103 -- LPP_WAVEFORM
103 -----------------------------------------------------------------------------
104 -----------------------------------------------------------------------------
104 CONSTANT data_size : INTEGER := 96;
105 CONSTANT data_size : INTEGER := 96;
105 CONSTANT nb_burst_available_size : INTEGER := 50;
106 CONSTANT nb_burst_available_size : INTEGER := 50;
106 CONSTANT nb_snapshot_param_size : INTEGER := 2;
107 CONSTANT nb_snapshot_param_size : INTEGER := 2;
107 CONSTANT delta_vector_size : INTEGER := 2;
108 CONSTANT delta_vector_size : INTEGER := 2;
108 CONSTANT delta_vector_size_f0_2 : INTEGER := 2;
109 CONSTANT delta_vector_size_f0_2 : INTEGER := 2;
109
110
110 SIGNAL reg_run : STD_LOGIC;
111 SIGNAL reg_run : STD_LOGIC;
111 SIGNAL reg_start_date : STD_LOGIC_VECTOR(30 DOWNTO 0);
112 SIGNAL reg_start_date : STD_LOGIC_VECTOR(30 DOWNTO 0);
112 SIGNAL reg_delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
113 SIGNAL reg_delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
113 SIGNAL reg_delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
114 SIGNAL reg_delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
114 SIGNAL reg_delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
115 SIGNAL reg_delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
115 SIGNAL reg_delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
116 SIGNAL reg_delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
116 SIGNAL reg_delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
117 SIGNAL reg_delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
117 SIGNAL enable_f0 : STD_LOGIC;
118 SIGNAL enable_f0 : STD_LOGIC;
118 SIGNAL enable_f1 : STD_LOGIC;
119 SIGNAL enable_f1 : STD_LOGIC;
119 SIGNAL enable_f2 : STD_LOGIC;
120 SIGNAL enable_f2 : STD_LOGIC;
120 SIGNAL enable_f3 : STD_LOGIC;
121 SIGNAL enable_f3 : STD_LOGIC;
121 SIGNAL burst_f0 : STD_LOGIC;
122 SIGNAL burst_f0 : STD_LOGIC;
122 SIGNAL burst_f1 : STD_LOGIC;
123 SIGNAL burst_f1 : STD_LOGIC;
123 SIGNAL burst_f2 : STD_LOGIC;
124 SIGNAL burst_f2 : STD_LOGIC;
124 SIGNAL nb_data_by_buffer : STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
125 SIGNAL nb_data_by_buffer : STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
125 SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
126 SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
126 SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
127 SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
127 SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0);
128 SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0);
128 SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
129 SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
129 SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
130 SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
130 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
131 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
131 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
132 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
132 SIGNAL addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
133 SIGNAL addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
133 SIGNAL data_f0_in_valid : STD_LOGIC;
134 SIGNAL data_f0_in_valid : STD_LOGIC;
134 SIGNAL data_f0_in : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
135 SIGNAL data_f0_in : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
135 SIGNAL addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
136 SIGNAL addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
136 SIGNAL data_f1_in_valid : STD_LOGIC;
137 SIGNAL data_f1_in_valid : STD_LOGIC;
137 SIGNAL data_f1_in : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
138 SIGNAL data_f1_in : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
138 SIGNAL addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
139 SIGNAL addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
139 SIGNAL data_f2_in_valid : STD_LOGIC;
140 SIGNAL data_f2_in_valid : STD_LOGIC;
140 SIGNAL data_f2_in : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
141 SIGNAL data_f2_in : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
141 SIGNAL addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
142 SIGNAL addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
142 SIGNAL data_f3_in_valid : STD_LOGIC;
143 SIGNAL data_f3_in_valid : STD_LOGIC;
143 SIGNAL data_f3_in : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
144 SIGNAL data_f3_in : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
144 SIGNAL data_f0_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
145 SIGNAL data_f0_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
145 SIGNAL data_f0_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
146 SIGNAL data_f0_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
146 SIGNAL data_f0_data_out_valid : STD_LOGIC;
147 SIGNAL data_f0_data_out_valid : STD_LOGIC;
147 SIGNAL data_f0_data_out_valid_burst : STD_LOGIC;
148 SIGNAL data_f0_data_out_valid_burst : STD_LOGIC;
148 SIGNAL data_f0_data_out_ack : STD_LOGIC;
149 SIGNAL data_f0_data_out_ack : STD_LOGIC;
149 SIGNAL data_f1_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
150 SIGNAL data_f1_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
150 SIGNAL data_f1_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
151 SIGNAL data_f1_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
151 SIGNAL data_f1_data_out_valid : STD_LOGIC;
152 SIGNAL data_f1_data_out_valid : STD_LOGIC;
152 SIGNAL data_f1_data_out_valid_burst : STD_LOGIC;
153 SIGNAL data_f1_data_out_valid_burst : STD_LOGIC;
153 SIGNAL data_f1_data_out_ack : STD_LOGIC;
154 SIGNAL data_f1_data_out_ack : STD_LOGIC;
154 SIGNAL data_f2_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
155 SIGNAL data_f2_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
155 SIGNAL data_f2_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
156 SIGNAL data_f2_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
156 SIGNAL data_f2_data_out_valid : STD_LOGIC;
157 SIGNAL data_f2_data_out_valid : STD_LOGIC;
157 SIGNAL data_f2_data_out_valid_burst : STD_LOGIC;
158 SIGNAL data_f2_data_out_valid_burst : STD_LOGIC;
158 SIGNAL data_f2_data_out_ack : STD_LOGIC;
159 SIGNAL data_f2_data_out_ack : STD_LOGIC;
159 SIGNAL data_f3_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
160 SIGNAL data_f3_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
160 SIGNAL data_f3_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
161 SIGNAL data_f3_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
161 SIGNAL data_f3_data_out_valid : STD_LOGIC;
162 SIGNAL data_f3_data_out_valid : STD_LOGIC;
162 SIGNAL data_f3_data_out_valid_burst : STD_LOGIC;
163 SIGNAL data_f3_data_out_valid_burst : STD_LOGIC;
163 SIGNAL data_f3_data_out_ack : STD_LOGIC;
164 SIGNAL data_f3_data_out_ack : STD_LOGIC;
164
165
165 --MEM CTRLR
166 --MEM CTRLR
166 SIGNAL memi : memory_in_type;
167 SIGNAL memi : memory_in_type;
167 SIGNAL memo : memory_out_type;
168 SIGNAL memo : memory_out_type;
168 SIGNAL wpo : wprot_out_type;
169 SIGNAL wpo : wprot_out_type;
169 SIGNAL sdo : sdram_out_type;
170 SIGNAL sdo : sdram_out_type;
170
171
171 SIGNAL address : STD_LOGIC_VECTOR(19 DOWNTO 0);
172 SIGNAL address : STD_LOGIC_VECTOR(19 DOWNTO 0);
172 SIGNAL data : STD_LOGIC_VECTOR(31 DOWNTO 0);
173 SIGNAL data : STD_LOGIC_VECTOR(31 DOWNTO 0);
173 SIGNAL nSRAM_BE0 : STD_LOGIC;
174 SIGNAL nSRAM_BE0 : STD_LOGIC;
174 SIGNAL nSRAM_BE1 : STD_LOGIC;
175 SIGNAL nSRAM_BE1 : STD_LOGIC;
175 SIGNAL nSRAM_BE2 : STD_LOGIC;
176 SIGNAL nSRAM_BE2 : STD_LOGIC;
176 SIGNAL nSRAM_BE3 : STD_LOGIC;
177 SIGNAL nSRAM_BE3 : STD_LOGIC;
177 SIGNAL nSRAM_WE : STD_LOGIC;
178 SIGNAL nSRAM_WE : STD_LOGIC;
178 SIGNAL nSRAM_CE : STD_LOGIC;
179 SIGNAL nSRAM_CE : STD_LOGIC;
179 SIGNAL nSRAM_OE : STD_LOGIC;
180 SIGNAL nSRAM_OE : STD_LOGIC;
180
181
181 CONSTANT padtech : INTEGER := inferred;
182 CONSTANT padtech : INTEGER := inferred;
182 SIGNAL not_ramsn_0 : STD_LOGIC;
183 SIGNAL not_ramsn_0 : STD_LOGIC;
183
184
184 -----------------------------------------------------------------------------
185 -----------------------------------------------------------------------------
185 SIGNAL status : STD_LOGIC_VECTOR(31 DOWNTO 0);
186 SIGNAL status : STD_LOGIC_VECTOR(31 DOWNTO 0);
186 SIGNAL read_buffer : STD_LOGIC;
187 SIGNAL read_buffer : STD_LOGIC;
187 -----------------------------------------------------------------------------
188 -----------------------------------------------------------------------------
188 SIGNAL run_test_waveform_picker : STD_LOGIC := '1';
189 SIGNAL run_test_waveform_picker : STD_LOGIC := '1';
189 SIGNAL state_read_buffer_on_going : STD_LOGIC;
190 SIGNAL state_read_buffer_on_going : STD_LOGIC;
190 CONSTANT hindex : INTEGER := 1;
191 CONSTANT hindex : INTEGER := 1;
191 SIGNAL time_mem_f0 : STD_LOGIC_VECTOR(63 DOWNTO 0);
192 SIGNAL time_mem_f0 : STD_LOGIC_VECTOR(63 DOWNTO 0);
192 SIGNAL time_mem_f1 : STD_LOGIC_VECTOR(63 DOWNTO 0);
193 SIGNAL time_mem_f1 : STD_LOGIC_VECTOR(63 DOWNTO 0);
193 SIGNAL time_mem_f2 : STD_LOGIC_VECTOR(63 DOWNTO 0);
194 SIGNAL time_mem_f2 : STD_LOGIC_VECTOR(63 DOWNTO 0);
194 SIGNAL time_mem_f3 : STD_LOGIC_VECTOR(63 DOWNTO 0);
195 SIGNAL time_mem_f3 : STD_LOGIC_VECTOR(63 DOWNTO 0);
195
196
196 SIGNAL data_mem_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
197 SIGNAL data_mem_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
197 SIGNAL data_mem_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
198 SIGNAL data_mem_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
198 SIGNAL data_mem_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
199 SIGNAL data_mem_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
199 SIGNAL data_mem_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
200 SIGNAL data_mem_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
200
201
201 SIGNAL data_0_f1 : STD_LOGIC_VECTOR(15 DOWNTO 0);
202 SIGNAL data_0_f1 : STD_LOGIC_VECTOR(15 DOWNTO 0);
202 SIGNAL data_0_f2 : STD_LOGIC_VECTOR(15 DOWNTO 0);
203 SIGNAL data_0_f2 : STD_LOGIC_VECTOR(15 DOWNTO 0);
203 SIGNAL data_0_f0 : STD_LOGIC_VECTOR(15 DOWNTO 0);
204 SIGNAL data_0_f0 : STD_LOGIC_VECTOR(15 DOWNTO 0);
204
205
205 SIGNAL data_1_f1 : STD_LOGIC_VECTOR(15 DOWNTO 0);
206 SIGNAL data_1_f1 : STD_LOGIC_VECTOR(15 DOWNTO 0);
206 SIGNAL data_1_f2 : STD_LOGIC_VECTOR(15 DOWNTO 0);
207 SIGNAL data_1_f2 : STD_LOGIC_VECTOR(15 DOWNTO 0);
207 SIGNAL data_1_f0 : STD_LOGIC_VECTOR(15 DOWNTO 0);
208 SIGNAL data_1_f0 : STD_LOGIC_VECTOR(15 DOWNTO 0);
208
209
209 SIGNAL data_2_f1 : STD_LOGIC_VECTOR(15 DOWNTO 0);
210 SIGNAL data_2_f1 : STD_LOGIC_VECTOR(15 DOWNTO 0);
210 SIGNAL data_2_f2 : STD_LOGIC_VECTOR(15 DOWNTO 0);
211 SIGNAL data_2_f2 : STD_LOGIC_VECTOR(15 DOWNTO 0);
211 SIGNAL data_2_f0 : STD_LOGIC_VECTOR(15 DOWNTO 0);
212 SIGNAL data_2_f0 : STD_LOGIC_VECTOR(15 DOWNTO 0);
212
213
213 SIGNAL data_3_f1 : STD_LOGIC_VECTOR(15 DOWNTO 0);
214 SIGNAL data_3_f1 : STD_LOGIC_VECTOR(15 DOWNTO 0);
214 SIGNAL data_3_f2 : STD_LOGIC_VECTOR(15 DOWNTO 0);
215 SIGNAL data_3_f2 : STD_LOGIC_VECTOR(15 DOWNTO 0);
215 SIGNAL data_3_f0 : STD_LOGIC_VECTOR(15 DOWNTO 0);
216 SIGNAL data_3_f0 : STD_LOGIC_VECTOR(15 DOWNTO 0);
216
217
217 SIGNAL data_4_f1 : STD_LOGIC_VECTOR(15 DOWNTO 0);
218 SIGNAL data_4_f1 : STD_LOGIC_VECTOR(15 DOWNTO 0);
218 SIGNAL data_4_f2 : STD_LOGIC_VECTOR(15 DOWNTO 0);
219 SIGNAL data_4_f2 : STD_LOGIC_VECTOR(15 DOWNTO 0);
219 SIGNAL data_4_f0 : STD_LOGIC_VECTOR(15 DOWNTO 0);
220 SIGNAL data_4_f0 : STD_LOGIC_VECTOR(15 DOWNTO 0);
220
221
221 SIGNAL data_5_f1 : STD_LOGIC_VECTOR(15 DOWNTO 0);
222 SIGNAL data_5_f1 : STD_LOGIC_VECTOR(15 DOWNTO 0);
222 SIGNAL data_5_f2 : STD_LOGIC_VECTOR(15 DOWNTO 0);
223 SIGNAL data_5_f2 : STD_LOGIC_VECTOR(15 DOWNTO 0);
223 SIGNAL data_5_f0 : STD_LOGIC_VECTOR(15 DOWNTO 0);
224 SIGNAL data_5_f0 : STD_LOGIC_VECTOR(15 DOWNTO 0);
224 -----------------------------------------------------------------------------
225 -----------------------------------------------------------------------------
225
226
226 SIGNAL current_data : INTEGER;
227 SIGNAL current_data : INTEGER;
227 SIGNAL LIMIT_DATA : INTEGER := 194;
228 SIGNAL LIMIT_DATA : INTEGER := 64;
228
229
229 SIGNAL read_buffer_temp : STD_LOGIC;
230 SIGNAL read_buffer_temp : STD_LOGIC;
230 SIGNAL read_buffer_temp_2 : STD_LOGIC;
231 SIGNAL read_buffer_temp_2 : STD_LOGIC;
231
232
232
233
233 BEGIN
234 BEGIN
234
235
235 -----------------------------------------------------------------------------
236 -----------------------------------------------------------------------------
236
237
237 clk49_152MHz <= NOT clk49_152MHz AFTER 10173 ps; -- 49.152/2 MHz
238 clk49_152MHz <= NOT clk49_152MHz AFTER 10173 ps; -- 49.152/2 MHz
238 clk25MHz <= NOT clk25MHz AFTER 5 ns; -- 100 MHz
239 clk25MHz <= NOT clk25MHz AFTER 5 ns; -- 100 MHz
239
240
240 -----------------------------------------------------------------------------
241 -----------------------------------------------------------------------------
241
242
242 MODULE_RHF1401 : FOR I IN 0 TO 7 GENERATE
243 MODULE_RHF1401 : FOR I IN 0 TO 7 GENERATE
243 TestModule_RHF1401_1 : TestModule_RHF1401
244 TestModule_RHF1401_1 : TestModule_RHF1401
244 GENERIC MAP (
245 GENERIC MAP (
245 freq => 24*(I+1),
246 freq => 24*(I+1),
246 amplitude => 8000/(I+1),
247 amplitude => 8000/(I+1),
247 impulsion => 0)
248 impulsion => 0)
248 PORT MAP (
249 PORT MAP (
249 ADC_smpclk => ADC_smpclk,
250 ADC_smpclk => ADC_smpclk,
250 ADC_OEB_bar => ADC_OEB_bar_CH(I),
251 ADC_OEB_bar => ADC_OEB_bar_CH(I),
251 ADC_data => ADC_data);
252 ADC_data => ADC_data);
252 END GENERATE MODULE_RHF1401;
253 END GENERATE MODULE_RHF1401;
253
254
254 -----------------------------------------------------------------------------
255 -----------------------------------------------------------------------------
255
256
256 top_ad_conv_RHF1401_1 : top_ad_conv_RHF1401
257 top_ad_conv_RHF1401_1 : top_ad_conv_RHF1401
257 GENERIC MAP (
258 GENERIC MAP (
258 ChanelCount => 8,
259 ChanelCount => 8,
259 ncycle_cnv_high => 79,
260 ncycle_cnv_high => 79,
260 ncycle_cnv => 500)
261 ncycle_cnv => 500)
261 PORT MAP (
262 PORT MAP (
262 cnv_clk => clk49_152MHz,
263 cnv_clk => clk49_152MHz,
263 cnv_rstn => rstn,
264 cnv_rstn => rstn,
264 cnv => ADC_smpclk,
265 cnv => ADC_smpclk,
265 clk => clk25MHz,
266 clk => clk25MHz,
266 rstn => rstn,
267 rstn => rstn,
267 ADC_data => ADC_data,
268 ADC_data => ADC_data,
268 ADC_nOE => ADC_OEB_bar_CH,
269 ADC_nOE => ADC_OEB_bar_CH,
269 sample => sample,
270 sample => sample,
270 sample_val => sample_val);
271 sample_val => sample_val);
271
272
272 -----------------------------------------------------------------------------
273 -----------------------------------------------------------------------------
273
274
274 lpp_lfr_1 : lpp_lfr
275 lpp_lfr_1 : lpp_lfr
275 GENERIC MAP (
276 GENERIC MAP (
276 Mem_use => use_CEL, -- use_RAM
277 Mem_use => use_CEL, -- use_RAM
277 nb_data_by_buffer_size => 32,
278 nb_data_by_buffer_size => 32,
278 nb_word_by_buffer_size => 30,
279 nb_word_by_buffer_size => 30,
279 nb_snapshot_param_size => 32,
280 nb_snapshot_param_size => 32,
280 delta_vector_size => 32,
281 delta_vector_size => 32,
281 delta_vector_size_f0_2 => 32,
282 delta_vector_size_f0_2 => 32,
282 pindex => INDEX_WAVEFORM_PICKER,
283 pindex => INDEX_WAVEFORM_PICKER,
283 paddr => ADDR_WAVEFORM_PICKER,
284 paddr => ADDR_WAVEFORM_PICKER,
284 pmask => 16#fff#,
285 pmask => 16#fff#,
285 pirq_ms => 6,
286 pirq_ms => 6,
286 pirq_wfp => 14,
287 pirq_wfp => 14,
287 hindex => 0,
288 hindex => 0,
288 top_lfr_version => X"000001")
289 top_lfr_version => X"000001")
289 PORT MAP (
290 PORT MAP (
290 clk => clk25MHz,
291 clk => clk25MHz,
291 rstn => rstn,
292 rstn => rstn,
292 sample_B => sample(2 DOWNTO 0),
293 sample_B => sample(2 DOWNTO 0),
293 sample_E => sample(7 DOWNTO 3),
294 sample_E => sample(7 DOWNTO 3),
294 sample_val => sample_val,
295 sample_val => sample_val,
295 apbi => apbi,
296 apbi => apbi,
296 apbo => apbo(15),
297 apbo => apbo(15),
297 ahbi => ahbmi,
298 ahbi => ahbmi,
298 ahbo => ahbmo(0),
299 ahbo => ahbmo(0),
299 coarse_time => coarse_time,
300 coarse_time => coarse_time,
300 fine_time => fine_time,
301 fine_time => fine_time,
301 data_shaping_BW => bias_fail_bw);
302 data_shaping_BW => bias_fail_bw);
302
303
303 -----------------------------------------------------------------------------
304 -----------------------------------------------------------------------------
304 --- AHB CONTROLLER -------------------------------------------------
305 --- AHB CONTROLLER -------------------------------------------------
305 ahb0 : ahbctrl -- AHB arbiter/multiplexer
306 ahb0 : ahbctrl -- AHB arbiter/multiplexer
306 GENERIC MAP (defmast => 0, split => 0,
307 GENERIC MAP (defmast => 0, split => 0,
307 rrobin => 1, ioaddr => 16#FFF#,
308 rrobin => 1, ioaddr => 16#FFF#,
308 ioen => 0, nahbm => 2, nahbs => 1)
309 ioen => 0, nahbm => 2, nahbs => 1)
309 PORT MAP (rstn, clk25MHz, ahbmi, ahbmo, ahbsi, ahbso);
310 PORT MAP (rstn, clk25MHz, ahbmi, ahbmo, ahbsi, ahbso);
310
311
311 --- AHB RAM ----------------------------------------------------------
312 --- AHB RAM ----------------------------------------------------------
312 --ahbram0 : ahbram
313 --ahbram0 : ahbram
313 -- GENERIC MAP (hindex => 0, haddr => AHB_RAM_ADDR_0, tech => inferred, kbytes => 1, pipe => 0)
314 -- GENERIC MAP (hindex => 0, haddr => AHB_RAM_ADDR_0, tech => inferred, kbytes => 1, pipe => 0)
314 -- PORT MAP (rstn, clk25MHz, ahbsi, ahbso(0));
315 -- PORT MAP (rstn, clk25MHz, ahbsi, ahbso(0));
315 --ahbram1 : ahbram
316 --ahbram1 : ahbram
316 -- GENERIC MAP (hindex => 1, haddr => AHB_RAM_ADDR_1, tech => inferred, kbytes => 1, pipe => 0)
317 -- GENERIC MAP (hindex => 1, haddr => AHB_RAM_ADDR_1, tech => inferred, kbytes => 1, pipe => 0)
317 -- PORT MAP (rstn, clk25MHz, ahbsi, ahbso(1));
318 -- PORT MAP (rstn, clk25MHz, ahbsi, ahbso(1));
318 --ahbram2 : ahbram
319 --ahbram2 : ahbram
319 -- GENERIC MAP (hindex => 2, haddr => AHB_RAM_ADDR_2, tech => inferred, kbytes => 1, pipe => 0)
320 -- GENERIC MAP (hindex => 2, haddr => AHB_RAM_ADDR_2, tech => inferred, kbytes => 1, pipe => 0)
320 -- PORT MAP (rstn, clk25MHz, ahbsi, ahbso(2));
321 -- PORT MAP (rstn, clk25MHz, ahbsi, ahbso(2));
321 --ahbram3 : ahbram
322 --ahbram3 : ahbram
322 -- GENERIC MAP (hindex => 3, haddr => AHB_RAM_ADDR_3, tech => inferred, kbytes => 1, pipe => 0)
323 -- GENERIC MAP (hindex => 3, haddr => AHB_RAM_ADDR_3, tech => inferred, kbytes => 1, pipe => 0)
323 -- PORT MAP (rstn, clk25MHz, ahbsi, ahbso(3));
324 -- PORT MAP (rstn, clk25MHz, ahbsi, ahbso(3));
324
325
325 -----------------------------------------------------------------------------
326 -----------------------------------------------------------------------------
326 ----------------------------------------------------------------------
327 ----------------------------------------------------------------------
327 --- Memory controllers ---------------------------------------------
328 --- Memory controllers ---------------------------------------------
328 ----------------------------------------------------------------------
329 ----------------------------------------------------------------------
329 memctrlr : mctrl GENERIC MAP (
330 memctrlr : mctrl GENERIC MAP (
330 hindex => 0,
331 hindex => 0,
331 pindex => 0,
332 pindex => 0,
332 paddr => 0,
333 paddr => 0,
333 srbanks => 1
334 srbanks => 1
334 )
335 )
335 PORT MAP (rstn, clk25MHz, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
336 PORT MAP (rstn, clk25MHz, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
336
337
337 memi.brdyn <= '1';
338 memi.brdyn <= '1';
338 memi.bexcn <= '1';
339 memi.bexcn <= '1';
339 memi.writen <= '1';
340 memi.writen <= '1';
340 memi.wrn <= "1111";
341 memi.wrn <= "1111";
341 memi.bwidth <= "10";
342 memi.bwidth <= "10";
342
343
343 bdr : FOR i IN 0 TO 3 GENERATE
344 bdr : FOR i IN 0 TO 3 GENERATE
344 data_pad : iopadv GENERIC MAP (tech => padtech, width => 8)
345 data_pad : iopadv GENERIC MAP (tech => padtech, width => 8)
345 PORT MAP (
346 PORT MAP (
346 data(31-i*8 DOWNTO 24-i*8),
347 data(31-i*8 DOWNTO 24-i*8),
347 memo.data(31-i*8 DOWNTO 24-i*8),
348 memo.data(31-i*8 DOWNTO 24-i*8),
348 memo.bdrive(i),
349 memo.bdrive(i),
349 memi.data(31-i*8 DOWNTO 24-i*8));
350 memi.data(31-i*8 DOWNTO 24-i*8));
350 END GENERATE;
351 END GENERATE;
351
352
352 addr_pad : outpadv GENERIC MAP (width => 20, tech => padtech)
353 addr_pad : outpadv GENERIC MAP (width => 20, tech => padtech)
353 PORT MAP (address, memo.address(21 DOWNTO 2));
354 PORT MAP (address, memo.address(21 DOWNTO 2));
354
355
355 not_ramsn_0 <= NOT(memo.ramsn(0));
356 not_ramsn_0 <= NOT(memo.ramsn(0));
356
357
357 rams_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_CE, not_ramsn_0);
358 rams_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_CE, not_ramsn_0);
358 oen_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_OE, memo.ramoen(0));
359 oen_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_OE, memo.ramoen(0));
359 nBWE_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_WE, memo.writen);
360 nBWE_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_WE, memo.writen);
360 nBWa_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE0, memo.mben(3));
361 nBWa_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE0, memo.mben(3));
361 nBWb_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE1, memo.mben(2));
362 nBWb_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE1, memo.mben(2));
362 nBWc_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE2, memo.mben(1));
363 nBWc_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE2, memo.mben(1));
363 nBWd_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE3, memo.mben(0));
364 nBWd_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE3, memo.mben(0));
364
365
365 async_1Mx16_0: CY7C1061DV33
366 async_1Mx16_0: CY7C1061DV33
366 GENERIC MAP (
367 GENERIC MAP (
367 ADDR_BITS => 20,
368 ADDR_BITS => 20,
368 DATA_BITS => 16,
369 DATA_BITS => 16,
369 depth => 1048576,
370 depth => 1048576,
371 MEM_ARRAY_DEBUG => 194,
370 TimingInfo => TRUE,
372 TimingInfo => TRUE,
371 TimingChecks => '1')
373 TimingChecks => '1')
372 PORT MAP (
374 PORT MAP (
373 CE1_b => '0',
375 CE1_b => '0',
374 CE2 => nSRAM_CE,
376 CE2 => nSRAM_CE,
375 WE_b => nSRAM_WE,
377 WE_b => nSRAM_WE,
376 OE_b => nSRAM_OE,
378 OE_b => nSRAM_OE,
377 BHE_b => nSRAM_BE1,
379 BHE_b => nSRAM_BE1,
378 BLE_b => nSRAM_BE0,
380 BLE_b => nSRAM_BE0,
379 A => address,
381 A => address,
380 DQ => data(15 DOWNTO 0));
382 DQ => data(15 DOWNTO 0));
381
383
382 async_1Mx16_1: CY7C1061DV33
384 async_1Mx16_1: CY7C1061DV33
383 GENERIC MAP (
385 GENERIC MAP (
384 ADDR_BITS => 20,
386 ADDR_BITS => 20,
385 DATA_BITS => 16,
387 DATA_BITS => 16,
386 depth => 1048576,
388 depth => 1048576,
389 MEM_ARRAY_DEBUG => 194,
387 TimingInfo => TRUE,
390 TimingInfo => TRUE,
388 TimingChecks => '1')
391 TimingChecks => '1')
389 PORT MAP (
392 PORT MAP (
390 CE1_b => '0',
393 CE1_b => '0',
391 CE2 => nSRAM_CE,
394 CE2 => nSRAM_CE,
392 WE_b => nSRAM_WE,
395 WE_b => nSRAM_WE,
393 OE_b => nSRAM_OE,
396 OE_b => nSRAM_OE,
394 BHE_b => nSRAM_BE3,
397 BHE_b => nSRAM_BE3,
395 BLE_b => nSRAM_BE2,
398 BLE_b => nSRAM_BE2,
396 A => address,
399 A => address,
397 DQ => data(31 DOWNTO 16));
400 DQ => data(31 DOWNTO 16));
398
401
399
402
400
403
401 -----------------------------------------------------------------------------
404 -----------------------------------------------------------------------------
402
405
403 WaveGen_Proc : PROCESS
406 WaveGen_Proc : PROCESS
404 BEGIN
407 BEGIN
405
408
406 -- insert signal assignments here
409 -- insert signal assignments here
407 WAIT UNTIL clk25MHz = '1';
410 WAIT UNTIL clk25MHz = '1';
408 rstn <= '0';
411 rstn <= '0';
409 apbi.psel(15) <= '0';
412 apbi.psel(15) <= '0';
410 apbi.pwrite <= '0';
413 apbi.pwrite <= '0';
411 apbi.penable <= '0';
414 apbi.penable <= '0';
412 apbi.paddr <= (OTHERS => '0');
415 apbi.paddr <= (OTHERS => '0');
413 apbi.pwdata <= (OTHERS => '0');
416 apbi.pwdata <= (OTHERS => '0');
414 fine_time <= (OTHERS => '0');
417 fine_time <= (OTHERS => '0');
415 coarse_time <= (OTHERS => '0');
418 coarse_time <= (OTHERS => '0');
416 WAIT UNTIL clk25MHz = '1';
419 WAIT UNTIL clk25MHz = '1';
417 -- ahbmi.HGRANT(2) <= '1';
420 -- ahbmi.HGRANT(2) <= '1';
418 -- ahbmi.HREADY <= '1';
421 -- ahbmi.HREADY <= '1';
419 -- ahbmi.HRESP <= HRESP_OKAY;
422 -- ahbmi.HRESP <= HRESP_OKAY;
420
423
421 WAIT UNTIL clk25MHz = '1';
424 WAIT UNTIL clk25MHz = '1';
422 WAIT UNTIL clk25MHz = '1';
425 WAIT UNTIL clk25MHz = '1';
423 rstn <= '1';
426 rstn <= '1';
424 WAIT UNTIL clk25MHz = '1';
427 WAIT UNTIL clk25MHz = '1';
425 WAIT UNTIL clk25MHz = '1';
428 WAIT UNTIL clk25MHz = '1';
426 ---------------------------------------------------------------------------
429 ---------------------------------------------------------------------------
427 -- CONFIGURATION STEP
430 -- CONFIGURATION STEP
428 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F0 , X"40000000");
431 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F0 , X"40000000");
429 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F1 , X"40020000");
432 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F1 , X"40020000");
430 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F2 , X"40040000");
433 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F2 , X"40040000");
431 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F3 , X"40060000");
434 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F3 , X"40060000");
432
435
433 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_DELTASNAPSHOT, X"00000080");--"00000020"
436 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_DELTASNAPSHOT , X"00000080");--"00000020"
434 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_DELTA_F0 , X"00000060");--"00000019"
437 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_DELTA_F0 , X"00000060");--"00000019"
435 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_DELTA_F0_2 , X"00000007");--"00000007"
438 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_DELTA_F0_2 , X"00000007");--"00000007"
436 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_DELTA_F1 , X"00000062");--"00000019"
439 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_DELTA_F1 , X"00000062");--"00000019"
437 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_DELTA_F2 , X"00000001");--"00000001"
440 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_DELTA_F2 , X"00000001");--"00000001"
438
439 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_NB_DATA_IN_BUFFER , X"0000003f"); -- X"00000010"
441 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_NB_DATA_IN_BUFFER , X"0000003f"); -- X"00000010"
440 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_NBSNAPSHOT , X"00000040");
442 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_NBSNAPSHOT , X"00000040");
441 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_START_DATE , X"00000001");
443 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_START_DATE , X"00000001");
442 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_NB_WORD_IN_BUFFER , X"000000c2");
444 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_NB_WORD_IN_BUFFER , X"000000C2");-- 0xC2 = 64 * 3 + 2
445
446 --APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_DELTASNAPSHOT , X"00000010");--"00000020"
447 --APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_DELTA_F0 , X"0000000C");--"00000019"
448 --APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_DELTA_F0_2 , X"00000007");--"00000007"
449 --APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_DELTA_F1 , X"0000000C");--"00000019"
450 --APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_DELTA_F2 , X"00000001");--"00000001"
451 --APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_NB_DATA_IN_BUFFER , X"00000007"); -- X"00000010"
452 --APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_NBSNAPSHOT , X"00000008");
453 --APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_START_DATE , X"00000001");
454 --APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_NB_WORD_IN_BUFFER , X"0000001A");-- 0xC2 = 8 * 3 + 2
455
443
456
444
457
445 WAIT UNTIL clk25MHz = '1';
458 WAIT UNTIL clk25MHz = '1';
446 WAIT UNTIL clk25MHz = '1';
459 WAIT UNTIL clk25MHz = '1';
447 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"00000087");
460 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"00000087");
448 WAIT UNTIL clk25MHz = '1';
461 WAIT UNTIL clk25MHz = '1';
449 WAIT UNTIL clk25MHz = '1';
462 WAIT UNTIL clk25MHz = '1';
450 WAIT UNTIL clk25MHz = '1';
463 WAIT UNTIL clk25MHz = '1';
451 WAIT UNTIL clk25MHz = '1';
464 WAIT UNTIL clk25MHz = '1';
452 WAIT UNTIL clk25MHz = '1';
465 WAIT UNTIL clk25MHz = '1';
453 WAIT UNTIL clk25MHz = '1';
466 WAIT UNTIL clk25MHz = '1';
454 WAIT FOR 1 us;
467 WAIT FOR 1 us;
455 coarse_time <= X"00000001";
468 coarse_time <= X"00000001";
456
469
457 WAIT UNTIL clk25MHz = '1';
470 WAIT UNTIL clk25MHz = '1';
458
471
459 while_loop: WHILE run_test_waveform_picker = '1' LOOP
472 while_loop: WHILE run_test_waveform_picker = '1' LOOP
460 WAIT UNTIL apbo(INDEX_WAVEFORM_PICKER).pirq(14) = '1';
473 WAIT UNTIL apbo(INDEX_WAVEFORM_PICKER).pirq(14) = '1';
461 APB_READ(clk25MHz,INDEX_WAVEFORM_PICKER,apbi,apbo(INDEX_WAVEFORM_PICKER),ADDR_WAVEFORM_PICKER_STATUS,status);
474 APB_READ(clk25MHz,INDEX_WAVEFORM_PICKER,apbi,apbo(INDEX_WAVEFORM_PICKER),ADDR_WAVEFORM_PICKER_STATUS,status);
462
475
463 IF status(2 DOWNTO 0) = "111" THEN
476 IF status(2 DOWNTO 0) = "111" THEN
464 APB_WRITE(clk25MHz,INDEX_WAVEFORM_PICKER,apbi,ADDR_WAVEFORM_PICKER_STATUS,X"00000000");
477 APB_WRITE(clk25MHz,INDEX_WAVEFORM_PICKER,apbi,ADDR_WAVEFORM_PICKER_STATUS,X"00000000");
465 END IF;
478 END IF;
466 WAIT UNTIL clk25MHz = '1';
479 WAIT UNTIL clk25MHz = '1';
467 END LOOP while_loop;
480 END LOOP while_loop;
468
481
469
482
470 ---------------------------------------------------------------------------
483 ---------------------------------------------------------------------------
471 -- RUN STEP
484 -- RUN STEP
472 WAIT FOR 20000 ms;
485 WAIT FOR 20000 ms;
473 REPORT "*** END simulation ***" SEVERITY failure;
486 REPORT "*** END simulation ***" SEVERITY failure;
474 --APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"00000000");
487 --APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"00000000");
475 --APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_START_DATE, X"00000010");
488 --APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_START_DATE, X"00000010");
476 --WAIT FOR 10 us;
489 --WAIT FOR 10 us;
477 --WAIT UNTIL clk25MHz = '1';
490 --WAIT UNTIL clk25MHz = '1';
478 --WAIT UNTIL clk25MHz = '1';
491 --WAIT UNTIL clk25MHz = '1';
479 --APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"000000FF");
492 --APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"000000FF");
480 --WAIT UNTIL clk25MHz = '1';
493 --WAIT UNTIL clk25MHz = '1';
481 --coarse_time <= X"00000010";
494 --coarse_time <= X"00000010";
482 --WAIT FOR 100 ms;
495 --WAIT FOR 100 ms;
483 --APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"00000000");
496 --APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"00000000");
484 --WAIT FOR 10 us;
497 --WAIT FOR 10 us;
485 --APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"000000AF");
498 --APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"000000AF");
486 --WAIT FOR 200 ms;
499 --WAIT FOR 200 ms;
487 --REPORT "*** END simulation ***" SEVERITY failure;
500 --REPORT "*** END simulation ***" SEVERITY failure;
488
501
489
502
490
503
491 WAIT;
504 WAIT;
492
505
493 END PROCESS WaveGen_Proc;
506 END PROCESS WaveGen_Proc;
494 -----------------------------------------------------------------------------
507 -----------------------------------------------------------------------------
495
508
496 read_buffer_temp <= '1' WHEN status(2 DOWNTO 0) = "111" ELSE '0';
509 read_buffer_temp <= '1' WHEN status(2 DOWNTO 0) = "111" ELSE '0';
497 PROCESS (clk25MHz, rstn)
510 PROCESS (clk25MHz, rstn)
498 BEGIN -- PROCESS
511 BEGIN -- PROCESS
499 IF rstn = '0' THEN -- asynchronous reset (active low)
512 IF rstn = '0' THEN -- asynchronous reset (active low)
500 read_buffer <= '0';
513 read_buffer <= '0';
501 read_buffer_temp_2 <= '0';
514 read_buffer_temp_2 <= '0';
502 ELSIF clk25MHz'event AND clk25MHz = '1' THEN -- rising clock edge
515 ELSIF clk25MHz'event AND clk25MHz = '1' THEN -- rising clock edge
503 read_buffer_temp_2 <= read_buffer_temp;
516 read_buffer_temp_2 <= read_buffer_temp;
504 read_buffer <= read_buffer_temp AND NOT read_buffer_temp_2;
517 read_buffer <= read_buffer_temp AND NOT read_buffer_temp_2;
505 END IF;
518 END IF;
506 END PROCESS;
519 END PROCESS;
507
520
508 -----------------------------------------------------------------------------
521 -----------------------------------------------------------------------------
509 -- IRQ
522 -- IRQ
510 -----------------------------------------------------------------------------
523 -----------------------------------------------------------------------------
511 PROCESS
524 PROCESS
512 BEGIN -- PROCESS
525 BEGIN -- PROCESS
513 state_read_buffer_on_going <= '0';
526 state_read_buffer_on_going <= '0';
514 current_data <= 0;
527 current_data <= 0;
515 time_mem_f0 <= (OTHERS => '0');
528 time_mem_f0 <= (OTHERS => '0');
516 time_mem_f1 <= (OTHERS => '0');
529 time_mem_f1 <= (OTHERS => '0');
517 time_mem_f2 <= (OTHERS => '0');
530 time_mem_f2 <= (OTHERS => '0');
518 time_mem_f3 <= (OTHERS => '0');
531 time_mem_f3 <= (OTHERS => '0');
519 data_mem_f0 <= (OTHERS => '0');
532 data_mem_f0 <= (OTHERS => '0');
520 data_mem_f1 <= (OTHERS => '0');
533 data_mem_f1 <= (OTHERS => '0');
521 data_mem_f2 <= (OTHERS => '0');
534 data_mem_f2 <= (OTHERS => '0');
522 data_mem_f3 <= (OTHERS => '0');
535 data_mem_f3 <= (OTHERS => '0');
523
536
524 while_loop2: WHILE run_test_waveform_picker = '1' LOOP
537 while_loop2: WHILE run_test_waveform_picker = '1' LOOP
525 WAIT UNTIL clk25MHz = '1';
538 WAIT UNTIL clk25MHz = '1';
526 IF read_buffer = '1' THEN
539 IF read_buffer = '1' THEN
527 state_read_buffer_on_going <= '1';
540 state_read_buffer_on_going <= '1';
541
542 --AHBRead(X"40000000",time_mem_f0(31 DOWNTO 0),clk25MHz,
543 --constant Address: in Std_Logic_Vector(31 downto 0);
544 --variable Data: out Std_Logic_Vector(31 downto 0);
545 --signal HCLK: in Std_ULogic;
546
547 --signal AHBIn: out AHB_Slv_In_Type;
548 --signal AHBOut: in AHB_Slv_Out_Type;
549 --variable TP: inout Boolean;
550 --constant InstancePath: in String := "AHBRead";
551 --constant ScreenOutput: in Boolean := False;
552 --constant cBack2Back: in Boolean := False;
553 --constant HINDEX: in Integer := 0;
554 --constant HMBINDEX: in Integer := 0);
528
555
529 AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40000000", time_mem_f0(31 DOWNTO 0));
556 AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40000000", time_mem_f0(31 DOWNTO 0));
530 AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40020000", time_mem_f1(31 DOWNTO 0));
557 AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40020000", time_mem_f1(31 DOWNTO 0));
531 AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40040000", time_mem_f2(31 DOWNTO 0));
558 AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40040000", time_mem_f2(31 DOWNTO 0));
532
559
533 AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40000004", time_mem_f0(63 DOWNTO 32));
560 AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40000004", time_mem_f0(63 DOWNTO 32));
534 AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40020004", time_mem_f1(63 DOWNTO 32));
561 AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40020004", time_mem_f1(63 DOWNTO 32));
535 AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40040004", time_mem_f2(63 DOWNTO 32));
562 AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40040004", time_mem_f2(63 DOWNTO 32));
536
563
537 current_data <= 8;
564 current_data <= 0;
538 ELSE
565 ELSE
539 IF state_read_buffer_on_going = '1' THEN
566 IF state_read_buffer_on_going = '1' THEN
540 -- READ ALL DATA in memory
567 -- READ ALL DATA in memory
541 AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40000000" + current_data, data_mem_f0);
568 AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40000000" + (current_data * 12) + 8, data_mem_f0);
542 AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40020000" + current_data, data_mem_f1);
569 AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40020000" + (current_data * 12) + 8, data_mem_f1);
543 AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40040000" + current_data, data_mem_f2);
570 AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40040000" + (current_data * 12) + 8, data_mem_f2);
544 data_0_f0 <= data_mem_f0(15 DOWNTO 0);
571 data_0_f0 <= data_mem_f0(15 DOWNTO 0);
545 data_1_f0 <= data_mem_f0(31 DOWNTO 16);
572 data_1_f0 <= data_mem_f0(31 DOWNTO 16);
546 data_0_f1 <= data_mem_f1(15 DOWNTO 0);
573 data_0_f1 <= data_mem_f1(15 DOWNTO 0);
547 data_1_f1 <= data_mem_f1(31 DOWNTO 16);
574 data_1_f1 <= data_mem_f1(31 DOWNTO 16);
548 data_0_f2 <= data_mem_f2(15 DOWNTO 0);
575 data_0_f2 <= data_mem_f2(15 DOWNTO 0);
549 data_1_f2 <= data_mem_f2(31 DOWNTO 16);
576 data_1_f2 <= data_mem_f2(31 DOWNTO 16);
550 current_data <= current_data + 4;
551
577
552 AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40000000" + current_data, data_mem_f0);
578 AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40000000" + (current_data * 12) + 4 + 8, data_mem_f0);
553 AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40020000" + current_data, data_mem_f1);
579 AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40020000" + (current_data * 12) + 4 + 8, data_mem_f1);
554 AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40040000" + current_data, data_mem_f2);
580 AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40040000" + (current_data * 12) + 4 + 8, data_mem_f2);
555 data_2_f0 <= data_mem_f0(15 DOWNTO 0);
581 data_2_f0 <= data_mem_f0(15 DOWNTO 0);
556 data_3_f0 <= data_mem_f0(31 DOWNTO 16);
582 data_3_f0 <= data_mem_f0(31 DOWNTO 16);
557 data_2_f1 <= data_mem_f1(15 DOWNTO 0);
583 data_2_f1 <= data_mem_f1(15 DOWNTO 0);
558 data_3_f1 <= data_mem_f1(31 DOWNTO 16);
584 data_3_f1 <= data_mem_f1(31 DOWNTO 16);
559 data_2_f2 <= data_mem_f2(15 DOWNTO 0);
585 data_2_f2 <= data_mem_f2(15 DOWNTO 0);
560 data_3_f2 <= data_mem_f2(31 DOWNTO 16);
586 data_3_f2 <= data_mem_f2(31 DOWNTO 16);
561 current_data <= current_data + 4;
562
587
563 AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40000000" + current_data, data_mem_f0);
588 AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40000000" + (current_data * 12) + 8 + 8, data_mem_f0);
564 AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40020000" + current_data, data_mem_f1);
589 AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40020000" + (current_data * 12) + 8 + 8, data_mem_f1);
565 AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40040000" + current_data, data_mem_f2);
590 AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40040000" + (current_data * 12) + 8 + 8, data_mem_f2);
566 data_4_f0 <= data_mem_f0(15 DOWNTO 0);
591 data_4_f0 <= data_mem_f0(15 DOWNTO 0);
567 data_5_f0 <= data_mem_f0(31 DOWNTO 16);
592 data_5_f0 <= data_mem_f0(31 DOWNTO 16);
568 data_4_f1 <= data_mem_f1(15 DOWNTO 0);
593 data_4_f1 <= data_mem_f1(15 DOWNTO 0);
569 data_5_f1 <= data_mem_f1(31 DOWNTO 16);
594 data_5_f1 <= data_mem_f1(31 DOWNTO 16);
570 data_4_f2 <= data_mem_f2(15 DOWNTO 0);
595 data_4_f2 <= data_mem_f2(15 DOWNTO 0);
571 data_5_f2 <= data_mem_f2(31 DOWNTO 16);
596 data_5_f2 <= data_mem_f2(31 DOWNTO 16);
572 current_data <= current_data + 4;
597 current_data <= current_data + 1;
573
598
574 IF current_data > LIMIT_DATA THEN
599 IF current_data >= LIMIT_DATA THEN
575 state_read_buffer_on_going <= '0';
600 state_read_buffer_on_going <= '0';
576 time_mem_f0 <= (OTHERS => '0');
601 time_mem_f0 <= (OTHERS => '0');
577 time_mem_f1 <= (OTHERS => '0');
602 time_mem_f1 <= (OTHERS => '0');
578 time_mem_f2 <= (OTHERS => '0');
603 time_mem_f2 <= (OTHERS => '0');
579 time_mem_f3 <= (OTHERS => '0');
604 time_mem_f3 <= (OTHERS => '0');
580 data_mem_f0 <= (OTHERS => '0');
605 data_mem_f0 <= (OTHERS => '0');
581 data_mem_f1 <= (OTHERS => '0');
606 data_mem_f1 <= (OTHERS => '0');
582 data_mem_f2 <= (OTHERS => '0');
607 data_mem_f2 <= (OTHERS => '0');
583 data_mem_f3 <= (OTHERS => '0');
608 data_mem_f3 <= (OTHERS => '0');
584 END IF;
609 END IF;
585 END IF;
610 END IF;
586 END IF;
611 END IF;
587 END LOOP while_loop2;
612 END LOOP while_loop2;
588 END PROCESS;
613 END PROCESS;
589 -----------------------------------------------------------------------------
614 -----------------------------------------------------------------------------
590
615
591 END;
616 END;
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@@ -1,120 +1,136
1
1
2 LIBRARY ieee;
2 LIBRARY ieee;
3 USE ieee.std_logic_1164.ALL;
3 USE ieee.std_logic_1164.ALL;
4 LIBRARY grlib;
4 LIBRARY grlib;
5 USE grlib.amba.ALL;
5 USE grlib.amba.ALL;
6 USE grlib.stdlib.ALL;
6 USE grlib.stdlib.ALL;
7 --LIBRARY gaisler;
7 --LIBRARY gaisler;
8 --USE gaisler.libdcom.ALL;
8 --USE gaisler.libdcom.ALL;
9 --USE gaisler.sim.ALL;
9 --USE gaisler.sim.ALL;
10 --USE gaisler.jtagtst.ALL;
10 --USE gaisler.jtagtst.ALL;
11 --LIBRARY techmap;
11 --LIBRARY techmap;
12 --USE techmap.gencomp.ALL;
12 --USE techmap.gencomp.ALL;
13
13
14
14
15 PACKAGE testbench_package IS
15 PACKAGE testbench_package IS
16
16
17 PROCEDURE APB_WRITE (
17 PROCEDURE APB_WRITE (
18 SIGNAL clk : IN STD_LOGIC;
18 SIGNAL clk : IN STD_LOGIC;
19 CONSTANT pindex : IN INTEGER;
19 CONSTANT pindex : IN INTEGER;
20 SIGNAL apbi : OUT apb_slv_in_type;
20 SIGNAL apbi : OUT apb_slv_in_type;
21 CONSTANT paddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
21 CONSTANT paddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
22 CONSTANT pwdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
22 CONSTANT pwdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
23 );
23 );
24
24
25 PROCEDURE APB_READ (
25 PROCEDURE APB_READ (
26 SIGNAL clk : IN STD_LOGIC;
26 SIGNAL clk : IN STD_LOGIC;
27 CONSTANT pindex : IN INTEGER;
27 CONSTANT pindex : IN INTEGER;
28 SIGNAL apbi : OUT apb_slv_in_type;
28 SIGNAL apbi : OUT apb_slv_in_type;
29 SIGNAL apbo : IN apb_slv_out_type;
29 SIGNAL apbo : IN apb_slv_out_type;
30 CONSTANT paddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
30 CONSTANT paddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
31 SIGNAL prdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
31 SIGNAL prdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
32 );
32 );
33
33
34 PROCEDURE AHB_READ (
34 PROCEDURE AHB_READ (
35 SIGNAL clk : IN STD_LOGIC;
35 SIGNAL clk : IN STD_LOGIC;
36 CONSTANT hindex : IN INTEGER;
36 CONSTANT hindex : IN INTEGER;
37 SIGNAL ahbmi : IN ahb_mst_in_type;
37 SIGNAL ahbmi : IN ahb_mst_in_type;
38 SIGNAL ahbmo : OUT ahb_mst_out_type;
38 SIGNAL ahbmo : OUT ahb_mst_out_type;
39 CONSTANT haddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
39 CONSTANT haddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
40 SIGNAL hrdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
40 SIGNAL hrdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
41 );
41 );
42
42
43 END testbench_package;
43 END testbench_package;
44
44
45 PACKAGE BODY testbench_package IS
45 PACKAGE BODY testbench_package IS
46
46
47 PROCEDURE APB_WRITE (
47 PROCEDURE APB_WRITE (
48 SIGNAL clk : IN STD_LOGIC;
48 SIGNAL clk : IN STD_LOGIC;
49 CONSTANT pindex : IN INTEGER;
49 CONSTANT pindex : IN INTEGER;
50 SIGNAL apbi : OUT apb_slv_in_type;
50 SIGNAL apbi : OUT apb_slv_in_type;
51 CONSTANT paddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
51 CONSTANT paddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
52 CONSTANT pwdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
52 CONSTANT pwdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
53 ) IS
53 ) IS
54 BEGIN
54 BEGIN
55 apbi.psel(pindex) <= '1';
55 apbi.psel(pindex) <= '1';
56 apbi.pwrite <= '1';
56 apbi.pwrite <= '1';
57 apbi.penable <= '1';
57 apbi.penable <= '1';
58 apbi.paddr <= paddr;
58 apbi.paddr <= paddr;
59 apbi.pwdata <= pwdata;
59 apbi.pwdata <= pwdata;
60 WAIT UNTIL clk = '1';
60 WAIT UNTIL clk = '0';
61 apbi.psel(pindex) <= '0';
61 WAIT UNTIL clk = '1';
62 apbi.pwrite <= '0';
62 apbi.psel(pindex) <= '0';
63 apbi.penable <= '0';
63 apbi.pwrite <= '0';
64 apbi.paddr <= (OTHERS => '0');
64 apbi.penable <= '0';
65 apbi.pwdata <= (OTHERS => '0');
65 apbi.paddr <= (OTHERS => '0');
66 WAIT UNTIL clk = '1';
66 apbi.pwdata <= (OTHERS => '0');
67
67 WAIT UNTIL clk = '0';
68 END APB_WRITE;
68 WAIT UNTIL clk = '1';
69
69
70 PROCEDURE APB_READ (
70 END APB_WRITE;
71 SIGNAL clk : IN STD_LOGIC;
71
72 CONSTANT pindex : IN INTEGER;
72 PROCEDURE APB_READ (
73 SIGNAL apbi : OUT apb_slv_in_type;
73 SIGNAL clk : IN STD_LOGIC;
74 SIGNAL apbo : IN apb_slv_out_type;
74 CONSTANT pindex : IN INTEGER;
75 CONSTANT paddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
75 SIGNAL apbi : OUT apb_slv_in_type;
76 SIGNAL prdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
76 SIGNAL apbo : IN apb_slv_out_type;
77 ) IS
77 CONSTANT paddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
78 BEGIN
78 SIGNAL prdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
79 apbi.psel(pindex) <= '1';
79 ) IS
80 apbi.pwrite <= '0';
80 BEGIN
81 apbi.penable <= '1';
81 apbi.psel(pindex) <= '1';
82 apbi.paddr <= paddr;
82 apbi.pwrite <= '0';
83 WAIT UNTIL clk = '1';
83 apbi.penable <= '1';
84 apbi.psel(pindex) <= '0';
84 apbi.paddr <= paddr;
85 apbi.pwrite <= '0';
85 WAIT UNTIL clk = '0';
86 apbi.penable <= '0';
86 WAIT UNTIL clk = '1';
87 apbi.paddr <= (OTHERS => '0');
87 apbi.psel(pindex) <= '0';
88 WAIT UNTIL clk = '1';
88 apbi.pwrite <= '0';
89 prdata <= apbo.prdata;
89 apbi.penable <= '0';
90 END APB_READ;
90 apbi.paddr <= (OTHERS => '0');
91
91 WAIT UNTIL clk = '0';
92 PROCEDURE AHB_READ (
92 WAIT UNTIL clk = '1';
93 SIGNAL clk : IN STD_LOGIC;
93 prdata <= apbo.prdata;
94 CONSTANT hindex : IN INTEGER;
94 END APB_READ;
95 SIGNAL ahbmi : IN ahb_mst_in_type;
95
96 SIGNAL ahbmo : OUT ahb_mst_out_type;
96 PROCEDURE AHB_READ (
97 CONSTANT haddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
97 SIGNAL clk : IN STD_LOGIC;
98 SIGNAL hrdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
98 CONSTANT hindex : IN INTEGER;
99 ) IS
99 SIGNAL ahbmi : IN ahb_mst_in_type;
100 BEGIN
100 SIGNAL ahbmo : OUT ahb_mst_out_type;
101 ahbmo.HADDR <= haddr;
101 CONSTANT haddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
102 ahbmo.HPROT <= "0011";
102 SIGNAL hrdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
103 ahbmo.HIRQ <= (OTHERS => '0');
103 ) IS
104 ahbmo.HCONFIG <= (0 => (OTHERS => '0'), OTHERS => (OTHERS => '0'));
104 BEGIN
105 ahbmo.HINDEX <= hindex;
105 WAIT UNTIL clk = '1';
106 ahbmo.HBUSREQ <= '1';
106 ahbmo.HADDR <= haddr;
107 ahbmo.HLOCK <= '1';
107 ahbmo.HPROT <= "0011";
108 ahbmo.HSIZE <= HSIZE_WORD;
108 ahbmo.HIRQ <= (OTHERS => '0');
109 ahbmo.HBURST <= HBURST_SINGLE;
109 ahbmo.HCONFIG <= (0 => (OTHERS => '0'), OTHERS => (OTHERS => '0'));
110 ahbmo.HTRANS <= HTRANS_NONSEQ;
110 ahbmo.HINDEX <= hindex;
111 ahbmo.HWRITE <= '0';
111 ahbmo.HBUSREQ <= '1';
112 WAIT UNTIL clk = '1' AND ahbmi.HREADY = '1' AND ahbmi.HGRANT(hindex) = '1';
112 ahbmo.HLOCK <= '1';
113 hrdata <= ahbmi.HRDATA;
113 ahbmo.HSIZE <= HSIZE_WORD;
114 WAIT UNTIL clk = '1' AND ahbmi.HREADY = '1' AND ahbmi.HGRANT(hindex) = '1';
114 ahbmo.HBURST <= HBURST_SINGLE;
115 ahbmo.HTRANS <= HTRANS_IDLE;
115 ahbmo.HTRANS <= HTRANS_NONSEQ;
116 ahbmo.HBUSREQ <= '0';
116 ahbmo.HWRITE <= '0';
117 ahbmo.HLOCK <= '0';
117 WHILE ahbmi.HREADY = '0' LOOP
118 END AHB_READ;
118 WAIT UNTIL clk = '1';
119
119 END LOOP;
120 END testbench_package;
120 WAIT UNTIL clk = '1';
121 --WAIT UNTIL clk = '1' AND ahbmi.HREADY = '1' AND ahbmi.HGRANT(hindex) = '1';
122 ahbmo.HBUSREQ <= '0';
123 ahbmo.HLOCK <= '0';
124 ahbmo.HTRANS <= HTRANS_IDLE;
125 WHILE ahbmi.HREADY = '0' LOOP
126 WAIT UNTIL clk = '1';
127 END LOOP;
128 WAIT UNTIL clk = '1';
129 hrdata <= ahbmi.HRDATA;
130 --WAIT UNTIL clk = '1' AND ahbmi.HREADY = '1' AND ahbmi.HGRANT(hindex) = '1';
131 ahbmo.HLOCK <= '0';
132 WAIT UNTIL clk = '1';
133
134 END AHB_READ;
135
136 END testbench_package;
Show file before | Show file after | Hide comments
@@ -1,580 +1,580
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
21 -------------------------------------------------------------------------------
22 LIBRARY IEEE;
22 LIBRARY IEEE;
23 USE IEEE.numeric_std.ALL;
23 USE IEEE.numeric_std.ALL;
24 USE IEEE.std_logic_1164.ALL;
24 USE IEEE.std_logic_1164.ALL;
25 LIBRARY grlib;
25 LIBRARY grlib;
26 USE grlib.amba.ALL;
26 USE grlib.amba.ALL;
27 USE grlib.stdlib.ALL;
27 USE grlib.stdlib.ALL;
28 LIBRARY techmap;
28 LIBRARY techmap;
29 USE techmap.gencomp.ALL;
29 USE techmap.gencomp.ALL;
30 LIBRARY gaisler;
30 LIBRARY gaisler;
31 USE gaisler.memctrl.ALL;
31 USE gaisler.memctrl.ALL;
32 USE gaisler.leon3.ALL;
32 USE gaisler.leon3.ALL;
33 USE gaisler.uart.ALL;
33 USE gaisler.uart.ALL;
34 USE gaisler.misc.ALL;
34 USE gaisler.misc.ALL;
35 USE gaisler.spacewire.ALL;
35 USE gaisler.spacewire.ALL;
36 LIBRARY esa;
36 LIBRARY esa;
37 USE esa.memoryctrl.ALL;
37 USE esa.memoryctrl.ALL;
38 LIBRARY lpp;
38 LIBRARY lpp;
39 USE lpp.lpp_memory.ALL;
39 USE lpp.lpp_memory.ALL;
40 USE lpp.lpp_ad_conv.ALL;
40 USE lpp.lpp_ad_conv.ALL;
41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
43 USE lpp.iir_filter.ALL;
43 USE lpp.iir_filter.ALL;
44 USE lpp.general_purpose.ALL;
44 USE lpp.general_purpose.ALL;
45 USE lpp.lpp_lfr_time_management.ALL;
45 USE lpp.lpp_lfr_time_management.ALL;
46 USE lpp.lpp_leon3_soc_pkg.ALL;
46 USE lpp.lpp_leon3_soc_pkg.ALL;
47
47
48 ENTITY MINI_LFR_top IS
48 ENTITY MINI_LFR_top IS
49
49
50 PORT (
50 PORT (
51 clk_50 : IN STD_LOGIC;
51 clk_50 : IN STD_LOGIC;
52 clk_49 : IN STD_LOGIC;
52 clk_49 : IN STD_LOGIC;
53 reset : IN STD_LOGIC;
53 reset : IN STD_LOGIC;
54 --BPs
54 --BPs
55 BP0 : IN STD_LOGIC;
55 BP0 : IN STD_LOGIC;
56 BP1 : IN STD_LOGIC;
56 BP1 : IN STD_LOGIC;
57 --LEDs
57 --LEDs
58 LED0 : OUT STD_LOGIC;
58 LED0 : OUT STD_LOGIC;
59 LED1 : OUT STD_LOGIC;
59 LED1 : OUT STD_LOGIC;
60 LED2 : OUT STD_LOGIC;
60 LED2 : OUT STD_LOGIC;
61 --UARTs
61 --UARTs
62 TXD1 : IN STD_LOGIC;
62 TXD1 : IN STD_LOGIC;
63 RXD1 : OUT STD_LOGIC;
63 RXD1 : OUT STD_LOGIC;
64 nCTS1 : OUT STD_LOGIC;
64 nCTS1 : OUT STD_LOGIC;
65 nRTS1 : IN STD_LOGIC;
65 nRTS1 : IN STD_LOGIC;
66
66
67 TXD2 : IN STD_LOGIC;
67 TXD2 : IN STD_LOGIC;
68 RXD2 : OUT STD_LOGIC;
68 RXD2 : OUT STD_LOGIC;
69 nCTS2 : OUT STD_LOGIC;
69 nCTS2 : OUT STD_LOGIC;
70 nDTR2 : IN STD_LOGIC;
70 nDTR2 : IN STD_LOGIC;
71 nRTS2 : IN STD_LOGIC;
71 nRTS2 : IN STD_LOGIC;
72 nDCD2 : OUT STD_LOGIC;
72 nDCD2 : OUT STD_LOGIC;
73
73
74 --EXT CONNECTOR
74 --EXT CONNECTOR
75 IO0 : INOUT STD_LOGIC;
75 IO0 : INOUT STD_LOGIC;
76 IO1 : INOUT STD_LOGIC;
76 IO1 : INOUT STD_LOGIC;
77 IO2 : INOUT STD_LOGIC;
77 IO2 : INOUT STD_LOGIC;
78 IO3 : INOUT STD_LOGIC;
78 IO3 : INOUT STD_LOGIC;
79 IO4 : INOUT STD_LOGIC;
79 IO4 : INOUT STD_LOGIC;
80 IO5 : INOUT STD_LOGIC;
80 IO5 : INOUT STD_LOGIC;
81 IO6 : INOUT STD_LOGIC;
81 IO6 : INOUT STD_LOGIC;
82 IO7 : INOUT STD_LOGIC;
82 IO7 : INOUT STD_LOGIC;
83 IO8 : INOUT STD_LOGIC;
83 IO8 : INOUT STD_LOGIC;
84 IO9 : INOUT STD_LOGIC;
84 IO9 : INOUT STD_LOGIC;
85 IO10 : INOUT STD_LOGIC;
85 IO10 : INOUT STD_LOGIC;
86 IO11 : INOUT STD_LOGIC;
86 IO11 : INOUT STD_LOGIC;
87
87
88 --SPACE WIRE
88 --SPACE WIRE
89 SPW_EN : OUT STD_LOGIC; -- 0 => off
89 SPW_EN : OUT STD_LOGIC; -- 0 => off
90 SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK
90 SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK
91 SPW_NOM_SIN : IN STD_LOGIC;
91 SPW_NOM_SIN : IN STD_LOGIC;
92 SPW_NOM_DOUT : OUT STD_LOGIC;
92 SPW_NOM_DOUT : OUT STD_LOGIC;
93 SPW_NOM_SOUT : OUT STD_LOGIC;
93 SPW_NOM_SOUT : OUT STD_LOGIC;
94 SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK
94 SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK
95 SPW_RED_SIN : IN STD_LOGIC;
95 SPW_RED_SIN : IN STD_LOGIC;
96 SPW_RED_DOUT : OUT STD_LOGIC;
96 SPW_RED_DOUT : OUT STD_LOGIC;
97 SPW_RED_SOUT : OUT STD_LOGIC;
97 SPW_RED_SOUT : OUT STD_LOGIC;
98 -- MINI LFR ADC INPUTS
98 -- MINI LFR ADC INPUTS
99 ADC_nCS : OUT STD_LOGIC;
99 ADC_nCS : OUT STD_LOGIC;
100 ADC_CLK : OUT STD_LOGIC;
100 ADC_CLK : OUT STD_LOGIC;
101 ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
101 ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
102
102
103 -- SRAM
103 -- SRAM
104 SRAM_nWE : OUT STD_LOGIC;
104 SRAM_nWE : OUT STD_LOGIC;
105 SRAM_CE : OUT STD_LOGIC;
105 SRAM_CE : OUT STD_LOGIC;
106 SRAM_nOE : OUT STD_LOGIC;
106 SRAM_nOE : OUT STD_LOGIC;
107 SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
107 SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
108 SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
108 SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
109 SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0)
109 SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0)
110 );
110 );
111
111
112 END MINI_LFR_top;
112 END MINI_LFR_top;
113
113
114
114
115 ARCHITECTURE beh OF MINI_LFR_top IS
115 ARCHITECTURE beh OF MINI_LFR_top IS
116 SIGNAL clk_50_s : STD_LOGIC := '0';
116 SIGNAL clk_50_s : STD_LOGIC := '0';
117 SIGNAL clk_25 : STD_LOGIC := '0';
117 SIGNAL clk_25 : STD_LOGIC := '0';
118 SIGNAL clk_24 : STD_LOGIC := '0';
118 SIGNAL clk_24 : STD_LOGIC := '0';
119 -----------------------------------------------------------------------------
119 -----------------------------------------------------------------------------
120 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
120 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
121 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
121 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
122 --
122 --
123 SIGNAL errorn : STD_LOGIC;
123 SIGNAL errorn : STD_LOGIC;
124 -- UART AHB ---------------------------------------------------------------
124 -- UART AHB ---------------------------------------------------------------
125 SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data
125 SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data
126 SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data
126 SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data
127
127
128 -- UART APB ---------------------------------------------------------------
128 -- UART APB ---------------------------------------------------------------
129 SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data
129 SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data
130 SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data
130 SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data
131 --
131 --
132 SIGNAL I00_s : STD_LOGIC;
132 SIGNAL I00_s : STD_LOGIC;
133
133
134 -- CONSTANTS
134 -- CONSTANTS
135 CONSTANT CFG_PADTECH : INTEGER := inferred;
135 CONSTANT CFG_PADTECH : INTEGER := inferred;
136 --
136 --
137 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
137 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
138 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
138 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
139 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
139 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
140
140
141 SIGNAL apbi_ext : apb_slv_in_type;
141 SIGNAL apbi_ext : apb_slv_in_type;
142 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
142 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
143 SIGNAL ahbi_s_ext : ahb_slv_in_type;
143 SIGNAL ahbi_s_ext : ahb_slv_in_type;
144 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none);
144 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none);
145 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
145 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
146 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
146 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
147
147
148 -- Spacewire signals
148 -- Spacewire signals
149 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
149 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
150 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
150 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
151 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
151 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
152 SIGNAL spw_rxtxclk : STD_ULOGIC;
152 SIGNAL spw_rxtxclk : STD_ULOGIC;
153 SIGNAL spw_rxclkn : STD_ULOGIC;
153 SIGNAL spw_rxclkn : STD_ULOGIC;
154 SIGNAL spw_clk : STD_LOGIC;
154 SIGNAL spw_clk : STD_LOGIC;
155 SIGNAL swni : grspw_in_type;
155 SIGNAL swni : grspw_in_type;
156 SIGNAL swno : grspw_out_type;
156 SIGNAL swno : grspw_out_type;
157 -- SIGNAL clkmn : STD_ULOGIC;
157 -- SIGNAL clkmn : STD_ULOGIC;
158 -- SIGNAL txclk : STD_ULOGIC;
158 -- SIGNAL txclk : STD_ULOGIC;
159
159
160 --GPIO
160 --GPIO
161 SIGNAL gpioi : gpio_in_type;
161 SIGNAL gpioi : gpio_in_type;
162 SIGNAL gpioo : gpio_out_type;
162 SIGNAL gpioo : gpio_out_type;
163
163
164 -- AD Converter ADS7886
164 -- AD Converter ADS7886
165 SIGNAL sample : Samples14v(7 DOWNTO 0);
165 SIGNAL sample : Samples14v(7 DOWNTO 0);
166 SIGNAL sample_val : STD_LOGIC;
166 SIGNAL sample_val : STD_LOGIC;
167 SIGNAL ADC_nCS_sig : STD_LOGIC;
167 SIGNAL ADC_nCS_sig : STD_LOGIC;
168 SIGNAL ADC_CLK_sig : STD_LOGIC;
168 SIGNAL ADC_CLK_sig : STD_LOGIC;
169 SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
169 SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
170
170
171 SIGNAL bias_fail_sw_sig : STD_LOGIC;
171 SIGNAL bias_fail_sw_sig : STD_LOGIC;
172
172
173 -----------------------------------------------------------------------------
173 -----------------------------------------------------------------------------
174 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
174 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
175
175
176 BEGIN -- beh
176 BEGIN -- beh
177
177
178 -----------------------------------------------------------------------------
178 -----------------------------------------------------------------------------
179 -- CLK
179 -- CLK
180 -----------------------------------------------------------------------------
180 -----------------------------------------------------------------------------
181
181
182 PROCESS(clk_50)
182 PROCESS(clk_50)
183 BEGIN
183 BEGIN
184 IF clk_50'EVENT AND clk_50 = '1' THEN
184 IF clk_50'EVENT AND clk_50 = '1' THEN
185 clk_50_s <= NOT clk_50_s;
185 clk_50_s <= NOT clk_50_s;
186 END IF;
186 END IF;
187 END PROCESS;
187 END PROCESS;
188
188
189 PROCESS(clk_50_s)
189 PROCESS(clk_50_s)
190 BEGIN
190 BEGIN
191 IF clk_50_s'EVENT AND clk_50_s = '1' THEN
191 IF clk_50_s'EVENT AND clk_50_s = '1' THEN
192 clk_25 <= NOT clk_25;
192 clk_25 <= NOT clk_25;
193 END IF;
193 END IF;
194 END PROCESS;
194 END PROCESS;
195
195
196 PROCESS(clk_49)
196 PROCESS(clk_49)
197 BEGIN
197 BEGIN
198 IF clk_49'EVENT AND clk_49 = '1' THEN
198 IF clk_49'EVENT AND clk_49 = '1' THEN
199 clk_24 <= NOT clk_24;
199 clk_24 <= NOT clk_24;
200 END IF;
200 END IF;
201 END PROCESS;
201 END PROCESS;
202
202
203 -----------------------------------------------------------------------------
203 -----------------------------------------------------------------------------
204
204
205 PROCESS (clk_25, reset)
205 PROCESS (clk_25, reset)
206 BEGIN -- PROCESS
206 BEGIN -- PROCESS
207 IF reset = '0' THEN -- asynchronous reset (active low)
207 IF reset = '0' THEN -- asynchronous reset (active low)
208 LED0 <= '0';
208 LED0 <= '0';
209 LED1 <= '0';
209 LED1 <= '0';
210 LED2 <= '0';
210 LED2 <= '0';
211 --IO1 <= '0';
211 --IO1 <= '0';
212 --IO2 <= '1';
212 --IO2 <= '1';
213 --IO3 <= '0';
213 --IO3 <= '0';
214 --IO4 <= '0';
214 --IO4 <= '0';
215 --IO5 <= '0';
215 --IO5 <= '0';
216 --IO6 <= '0';
216 --IO6 <= '0';
217 --IO7 <= '0';
217 --IO7 <= '0';
218 --IO8 <= '0';
218 --IO8 <= '0';
219 --IO9 <= '0';
219 --IO9 <= '0';
220 --IO10 <= '0';
220 --IO10 <= '0';
221 --IO11 <= '0';
221 --IO11 <= '0';
222 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
222 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
223 LED0 <= '0';
223 LED0 <= '0';
224 LED1 <= '1';
224 LED1 <= '1';
225 LED2 <= BP0 OR BP1 OR nDTR2 OR nRTS2 OR nRTS1;
225 LED2 <= BP0 OR BP1 OR nDTR2 OR nRTS2 OR nRTS1;
226 --IO1 <= '1';
226 --IO1 <= '1';
227 --IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN;
227 --IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN;
228 --IO3 <= ADC_SDO(0);
228 --IO3 <= ADC_SDO(0);
229 --IO4 <= ADC_SDO(1);
229 --IO4 <= ADC_SDO(1);
230 --IO5 <= ADC_SDO(2);
230 --IO5 <= ADC_SDO(2);
231 --IO6 <= ADC_SDO(3);
231 --IO6 <= ADC_SDO(3);
232 --IO7 <= ADC_SDO(4);
232 --IO7 <= ADC_SDO(4);
233 --IO8 <= ADC_SDO(5);
233 --IO8 <= ADC_SDO(5);
234 --IO9 <= ADC_SDO(6);
234 --IO9 <= ADC_SDO(6);
235 --IO10 <= ADC_SDO(7);
235 --IO10 <= ADC_SDO(7);
236 --IO11 <= ;
236 --IO11 <= ;
237 END IF;
237 END IF;
238 END PROCESS;
238 END PROCESS;
239
239
240 PROCESS (clk_24, reset)
240 PROCESS (clk_24, reset)
241 BEGIN -- PROCESS
241 BEGIN -- PROCESS
242 IF reset = '0' THEN -- asynchronous reset (active low)
242 IF reset = '0' THEN -- asynchronous reset (active low)
243 I00_s <= '0';
243 I00_s <= '0';
244 ELSIF clk_24'EVENT AND clk_24 = '1' THEN -- rising clock edge
244 ELSIF clk_24'EVENT AND clk_24 = '1' THEN -- rising clock edge
245 I00_s <= NOT I00_s;
245 I00_s <= NOT I00_s;
246 END IF;
246 END IF;
247 END PROCESS;
247 END PROCESS;
248 -- IO0 <= I00_s;
248 -- IO0 <= I00_s;
249
249
250 --UARTs
250 --UARTs
251 nCTS1 <= '1';
251 nCTS1 <= '1';
252 nCTS2 <= '1';
252 nCTS2 <= '1';
253 nDCD2 <= '1';
253 nDCD2 <= '1';
254
254
255 --EXT CONNECTOR
255 --EXT CONNECTOR
256
256
257 --SPACE WIRE
257 --SPACE WIRE
258
258
259 leon3_soc_1 : leon3_soc
259 leon3_soc_1 : leon3_soc
260 GENERIC MAP (
260 GENERIC MAP (
261 fabtech => apa3e,
261 fabtech => apa3e,
262 memtech => apa3e,
262 memtech => apa3e,
263 padtech => inferred,
263 padtech => inferred,
264 clktech => inferred,
264 clktech => inferred,
265 disas => 0,
265 disas => 0,
266 dbguart => 0,
266 dbguart => 0,
267 pclow => 2,
267 pclow => 2,
268 clk_freq => 25000,
268 clk_freq => 25000,
269 NB_CPU => 1,
269 NB_CPU => 1,
270 ENABLE_FPU => 1,
270 ENABLE_FPU => 1,
271 FPU_NETLIST => 0,
271 FPU_NETLIST => 0,
272 ENABLE_DSU => 1,
272 ENABLE_DSU => 1,
273 ENABLE_AHB_UART => 1,
273 ENABLE_AHB_UART => 1,
274 ENABLE_APB_UART => 1,
274 ENABLE_APB_UART => 1,
275 ENABLE_IRQMP => 1,
275 ENABLE_IRQMP => 1,
276 ENABLE_GPT => 1,
276 ENABLE_GPT => 1,
277 NB_AHB_MASTER => NB_AHB_MASTER,
277 NB_AHB_MASTER => NB_AHB_MASTER,
278 NB_AHB_SLAVE => NB_AHB_SLAVE,
278 NB_AHB_SLAVE => NB_AHB_SLAVE,
279 NB_APB_SLAVE => NB_APB_SLAVE)
279 NB_APB_SLAVE => NB_APB_SLAVE)
280 PORT MAP (
280 PORT MAP (
281 clk => clk_25,
281 clk => clk_25,
282 reset => reset,
282 reset => reset,
283 errorn => errorn,
283 errorn => errorn,
284 ahbrxd => TXD1,
284 ahbrxd => TXD1,
285 ahbtxd => RXD1,
285 ahbtxd => RXD1,
286 urxd1 => TXD2,
286 urxd1 => TXD2,
287 utxd1 => RXD2,
287 utxd1 => RXD2,
288 address => SRAM_A,
288 address => SRAM_A,
289 data => SRAM_DQ,
289 data => SRAM_DQ,
290 nSRAM_BE0 => SRAM_nBE(0),
290 nSRAM_BE0 => SRAM_nBE(0),
291 nSRAM_BE1 => SRAM_nBE(1),
291 nSRAM_BE1 => SRAM_nBE(1),
292 nSRAM_BE2 => SRAM_nBE(2),
292 nSRAM_BE2 => SRAM_nBE(2),
293 nSRAM_BE3 => SRAM_nBE(3),
293 nSRAM_BE3 => SRAM_nBE(3),
294 nSRAM_WE => SRAM_nWE,
294 nSRAM_WE => SRAM_nWE,
295 nSRAM_CE => SRAM_CE,
295 nSRAM_CE => SRAM_CE,
296 nSRAM_OE => SRAM_nOE,
296 nSRAM_OE => SRAM_nOE,
297
297
298 apbi_ext => apbi_ext,
298 apbi_ext => apbi_ext,
299 apbo_ext => apbo_ext,
299 apbo_ext => apbo_ext,
300 ahbi_s_ext => ahbi_s_ext,
300 ahbi_s_ext => ahbi_s_ext,
301 ahbo_s_ext => ahbo_s_ext,
301 ahbo_s_ext => ahbo_s_ext,
302 ahbi_m_ext => ahbi_m_ext,
302 ahbi_m_ext => ahbi_m_ext,
303 ahbo_m_ext => ahbo_m_ext);
303 ahbo_m_ext => ahbo_m_ext);
304
304
305 -------------------------------------------------------------------------------
305 -------------------------------------------------------------------------------
306 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
306 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
307 -------------------------------------------------------------------------------
307 -------------------------------------------------------------------------------
308 apb_lfr_time_management_1 : apb_lfr_time_management
308 apb_lfr_time_management_1 : apb_lfr_time_management
309 GENERIC MAP (
309 GENERIC MAP (
310 pindex => 6,
310 pindex => 6,
311 paddr => 6,
311 paddr => 6,
312 pmask => 16#fff#,
312 pmask => 16#fff#,
313 pirq => 12,
313 pirq => 12,
314 nb_wait_pediod => 375) -- (49.152/2) /2^16 = 375
314 nb_wait_pediod => 375) -- (49.152/2) /2^16 = 375
315 PORT MAP (
315 PORT MAP (
316 clk25MHz => clk_25,
316 clk25MHz => clk_25,
317 clk49_152MHz => clk_24, -- 49.152MHz/2
317 clk49_152MHz => clk_24, -- 49.152MHz/2
318 resetn => reset,
318 resetn => reset,
319 grspw_tick => swno.tickout,
319 grspw_tick => swno.tickout,
320 apbi => apbi_ext,
320 apbi => apbi_ext,
321 apbo => apbo_ext(6),
321 apbo => apbo_ext(6),
322 coarse_time => coarse_time,
322 coarse_time => coarse_time,
323 fine_time => fine_time);
323 fine_time => fine_time);
324
324
325 -----------------------------------------------------------------------
325 -----------------------------------------------------------------------
326 --- SpaceWire --------------------------------------------------------
326 --- SpaceWire --------------------------------------------------------
327 -----------------------------------------------------------------------
327 -----------------------------------------------------------------------
328
328
329 SPW_EN <= '1';
329 SPW_EN <= '1';
330
330
331 spw_clk <= clk_50_s;
331 spw_clk <= clk_50_s;
332 spw_rxtxclk <= spw_clk;
332 spw_rxtxclk <= spw_clk;
333 spw_rxclkn <= NOT spw_rxtxclk;
333 spw_rxclkn <= NOT spw_rxtxclk;
334
334
335 -- PADS for SPW1
335 -- PADS for SPW1
336 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
336 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
337 PORT MAP (SPW_NOM_DIN, dtmp(0));
337 PORT MAP (SPW_NOM_DIN, dtmp(0));
338 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
338 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
339 PORT MAP (SPW_NOM_SIN, stmp(0));
339 PORT MAP (SPW_NOM_SIN, stmp(0));
340 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
340 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
341 PORT MAP (SPW_NOM_DOUT, swno.d(0));
341 PORT MAP (SPW_NOM_DOUT, swno.d(0));
342 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
342 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
343 PORT MAP (SPW_NOM_SOUT, swno.s(0));
343 PORT MAP (SPW_NOM_SOUT, swno.s(0));
344 -- PADS FOR SPW2
344 -- PADS FOR SPW2
345 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
345 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
346 PORT MAP (SPW_RED_SIN, dtmp(1));
346 PORT MAP (SPW_RED_SIN, dtmp(1));
347 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
347 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
348 PORT MAP (SPW_RED_DIN, stmp(1));
348 PORT MAP (SPW_RED_DIN, stmp(1));
349 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
349 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
350 PORT MAP (SPW_RED_DOUT, swno.d(1));
350 PORT MAP (SPW_RED_DOUT, swno.d(1));
351 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
351 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
352 PORT MAP (SPW_RED_SOUT, swno.s(1));
352 PORT MAP (SPW_RED_SOUT, swno.s(1));
353
353
354 -- GRSPW PHY
354 -- GRSPW PHY
355 --spw1_input: if CFG_SPW_GRSPW = 1 generate
355 --spw1_input: if CFG_SPW_GRSPW = 1 generate
356 spw_inputloop : FOR j IN 0 TO 1 GENERATE
356 spw_inputloop : FOR j IN 0 TO 1 GENERATE
357 spw_phy0 : grspw_phy
357 spw_phy0 : grspw_phy
358 GENERIC MAP(
358 GENERIC MAP(
359 tech => apa3e,
359 tech => apa3e,
360 rxclkbuftype => 1,
360 rxclkbuftype => 1,
361 scantest => 0)
361 scantest => 0)
362 PORT MAP(
362 PORT MAP(
363 rxrst => swno.rxrst,
363 rxrst => swno.rxrst,
364 di => dtmp(j),
364 di => dtmp(j),
365 si => stmp(j),
365 si => stmp(j),
366 rxclko => spw_rxclk(j),
366 rxclko => spw_rxclk(j),
367 do => swni.d(j),
367 do => swni.d(j),
368 ndo => swni.nd(j*5+4 DOWNTO j*5),
368 ndo => swni.nd(j*5+4 DOWNTO j*5),
369 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
369 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
370 END GENERATE spw_inputloop;
370 END GENERATE spw_inputloop;
371
371
372 -- SPW core
372 -- SPW core
373 sw0 : grspwm GENERIC MAP(
373 sw0 : grspwm GENERIC MAP(
374 tech => apa3e,
374 tech => apa3e,
375 hindex => 1,
375 hindex => 1,
376 pindex => 5,
376 pindex => 5,
377 paddr => 5,
377 paddr => 5,
378 pirq => 11,
378 pirq => 11,
379 sysfreq => 25000, -- CPU_FREQ
379 sysfreq => 25000, -- CPU_FREQ
380 rmap => 1,
380 rmap => 1,
381 rmapcrc => 1,
381 rmapcrc => 1,
382 fifosize1 => 16,
382 fifosize1 => 16,
383 fifosize2 => 16,
383 fifosize2 => 16,
384 rxclkbuftype => 1,
384 rxclkbuftype => 1,
385 rxunaligned => 0,
385 rxunaligned => 0,
386 rmapbufs => 4,
386 rmapbufs => 4,
387 ft => 0,
387 ft => 0,
388 netlist => 0,
388 netlist => 0,
389 ports => 2,
389 ports => 2,
390 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
390 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
391 memtech => apa3e,
391 memtech => apa3e,
392 destkey => 2,
392 destkey => 2,
393 spwcore => 1
393 spwcore => 1
394 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
394 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
395 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
395 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
396 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
396 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
397 )
397 )
398 PORT MAP(reset, clk_25, spw_rxclk(0),
398 PORT MAP(reset, clk_25, spw_rxclk(0),
399 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
399 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
400 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
400 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
401 swni, swno);
401 swni, swno);
402
402
403 swni.tickin <= '0';
403 swni.tickin <= '0';
404 swni.rmapen <= '1';
404 swni.rmapen <= '1';
405 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
405 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
406 swni.tickinraw <= '0';
406 swni.tickinraw <= '0';
407 swni.timein <= (OTHERS => '0');
407 swni.timein <= (OTHERS => '0');
408 swni.dcrstval <= (OTHERS => '0');
408 swni.dcrstval <= (OTHERS => '0');
409 swni.timerrstval <= (OTHERS => '0');
409 swni.timerrstval <= (OTHERS => '0');
410
410
411 -------------------------------------------------------------------------------
411 -------------------------------------------------------------------------------
412 -- LFR ------------------------------------------------------------------------
412 -- LFR ------------------------------------------------------------------------
413 -------------------------------------------------------------------------------
413 -------------------------------------------------------------------------------
414 lpp_lfr_1 : lpp_lfr
414 lpp_lfr_1 : lpp_lfr
415 GENERIC MAP (
415 GENERIC MAP (
416 Mem_use => use_RAM,
416 Mem_use => use_RAM,
417 nb_data_by_buffer_size => 32,
417 nb_data_by_buffer_size => 32,
418 nb_word_by_buffer_size => 30,
418 nb_word_by_buffer_size => 30,
419 nb_snapshot_param_size => 32,
419 nb_snapshot_param_size => 32,
420 delta_vector_size => 32,
420 delta_vector_size => 32,
421 delta_vector_size_f0_2 => 7, -- log2(96)
421 delta_vector_size_f0_2 => 7, -- log2(96)
422 pindex => 15,
422 pindex => 15,
423 paddr => 15,
423 paddr => 15,
424 pmask => 16#fff#,
424 pmask => 16#fff#,
425 pirq_ms => 6,
425 pirq_ms => 6,
426 pirq_wfp => 14,
426 pirq_wfp => 14,
427 hindex => 2,
427 hindex => 2,
428 top_lfr_version => X"00000F") -- aa.bb.cc version
428 top_lfr_version => X"000010") -- aa.bb.cc version
429 PORT MAP (
429 PORT MAP (
430 clk => clk_25,
430 clk => clk_25,
431 rstn => reset,
431 rstn => reset,
432 sample_B => sample(2 DOWNTO 0),
432 sample_B => sample(2 DOWNTO 0),
433 sample_E => sample(7 DOWNTO 3),
433 sample_E => sample(7 DOWNTO 3),
434 sample_val => sample_val,
434 sample_val => sample_val,
435 apbi => apbi_ext,
435 apbi => apbi_ext,
436 apbo => apbo_ext(15),
436 apbo => apbo_ext(15),
437 ahbi => ahbi_m_ext,
437 ahbi => ahbi_m_ext,
438 ahbo => ahbo_m_ext(2),
438 ahbo => ahbo_m_ext(2),
439 coarse_time => coarse_time,
439 coarse_time => coarse_time,
440 fine_time => fine_time,
440 fine_time => fine_time,
441 data_shaping_BW => bias_fail_sw_sig,
441 data_shaping_BW => bias_fail_sw_sig,
442 observation_reg => observation_reg);
442 observation_reg => observation_reg);
443
443
444 top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2
444 top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2
445 GENERIC MAP(
445 GENERIC MAP(
446 ChannelCount => 8,
446 ChannelCount => 8,
447 SampleNbBits => 14,
447 SampleNbBits => 14,
448 ncycle_cnv_high => 40, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 /2 = 31.5
448 ncycle_cnv_high => 40, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 /2 = 31.5
449 ncycle_cnv => 249) -- 49 152 000 / 98304 /2
449 ncycle_cnv => 249) -- 49 152 000 / 98304 /2
450 PORT MAP (
450 PORT MAP (
451 -- CONV
451 -- CONV
452 cnv_clk => clk_24,
452 cnv_clk => clk_24,
453 cnv_rstn => reset,
453 cnv_rstn => reset,
454 cnv => ADC_nCS_sig,
454 cnv => ADC_nCS_sig,
455 -- DATA
455 -- DATA
456 clk => clk_25,
456 clk => clk_25,
457 rstn => reset,
457 rstn => reset,
458 sck => ADC_CLK_sig,
458 sck => ADC_CLK_sig,
459 sdo => ADC_SDO_sig,
459 sdo => ADC_SDO_sig,
460 -- SAMPLE
460 -- SAMPLE
461 sample => sample,
461 sample => sample,
462 sample_val => sample_val);
462 sample_val => sample_val);
463
463
464 --IO10 <= ADC_SDO_sig(5);
464 --IO10 <= ADC_SDO_sig(5);
465 --IO9 <= ADC_SDO_sig(4);
465 --IO9 <= ADC_SDO_sig(4);
466 --IO8 <= ADC_SDO_sig(3);
466 --IO8 <= ADC_SDO_sig(3);
467
467
468 ADC_nCS <= ADC_nCS_sig;
468 ADC_nCS <= ADC_nCS_sig;
469 ADC_CLK <= ADC_CLK_sig;
469 ADC_CLK <= ADC_CLK_sig;
470 ADC_SDO_sig <= ADC_SDO;
470 ADC_SDO_sig <= ADC_SDO;
471
471
472 ----------------------------------------------------------------------
472 ----------------------------------------------------------------------
473 --- GPIO -----------------------------------------------------------
473 --- GPIO -----------------------------------------------------------
474 ----------------------------------------------------------------------
474 ----------------------------------------------------------------------
475
475
476 grgpio0 : grgpio
476 grgpio0 : grgpio
477 GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8)
477 GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8)
478 PORT MAP(reset, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo);
478 PORT MAP(reset, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo);
479
479
480 --pio_pad_0 : iopad
480 --pio_pad_0 : iopad
481 -- GENERIC MAP (tech => CFG_PADTECH)
481 -- GENERIC MAP (tech => CFG_PADTECH)
482 -- PORT MAP (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0));
482 -- PORT MAP (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0));
483 --pio_pad_1 : iopad
483 --pio_pad_1 : iopad
484 -- GENERIC MAP (tech => CFG_PADTECH)
484 -- GENERIC MAP (tech => CFG_PADTECH)
485 -- PORT MAP (IO1, gpioo.dout(1), gpioo.oen(1), gpioi.din(1));
485 -- PORT MAP (IO1, gpioo.dout(1), gpioo.oen(1), gpioi.din(1));
486 --pio_pad_2 : iopad
486 --pio_pad_2 : iopad
487 -- GENERIC MAP (tech => CFG_PADTECH)
487 -- GENERIC MAP (tech => CFG_PADTECH)
488 -- PORT MAP (IO2, gpioo.dout(2), gpioo.oen(2), gpioi.din(2));
488 -- PORT MAP (IO2, gpioo.dout(2), gpioo.oen(2), gpioi.din(2));
489 --pio_pad_3 : iopad
489 --pio_pad_3 : iopad
490 -- GENERIC MAP (tech => CFG_PADTECH)
490 -- GENERIC MAP (tech => CFG_PADTECH)
491 -- PORT MAP (IO3, gpioo.dout(3), gpioo.oen(3), gpioi.din(3));
491 -- PORT MAP (IO3, gpioo.dout(3), gpioo.oen(3), gpioi.din(3));
492 --pio_pad_4 : iopad
492 --pio_pad_4 : iopad
493 -- GENERIC MAP (tech => CFG_PADTECH)
493 -- GENERIC MAP (tech => CFG_PADTECH)
494 -- PORT MAP (IO4, gpioo.dout(4), gpioo.oen(4), gpioi.din(4));
494 -- PORT MAP (IO4, gpioo.dout(4), gpioo.oen(4), gpioi.din(4));
495 --pio_pad_5 : iopad
495 --pio_pad_5 : iopad
496 -- GENERIC MAP (tech => CFG_PADTECH)
496 -- GENERIC MAP (tech => CFG_PADTECH)
497 -- PORT MAP (IO5, gpioo.dout(5), gpioo.oen(5), gpioi.din(5));
497 -- PORT MAP (IO5, gpioo.dout(5), gpioo.oen(5), gpioi.din(5));
498 --pio_pad_6 : iopad
498 --pio_pad_6 : iopad
499 -- GENERIC MAP (tech => CFG_PADTECH)
499 -- GENERIC MAP (tech => CFG_PADTECH)
500 -- PORT MAP (IO6, gpioo.dout(6), gpioo.oen(6), gpioi.din(6));
500 -- PORT MAP (IO6, gpioo.dout(6), gpioo.oen(6), gpioi.din(6));
501 --pio_pad_7 : iopad
501 --pio_pad_7 : iopad
502 -- GENERIC MAP (tech => CFG_PADTECH)
502 -- GENERIC MAP (tech => CFG_PADTECH)
503 -- PORT MAP (IO7, gpioo.dout(7), gpioo.oen(7), gpioi.din(7));
503 -- PORT MAP (IO7, gpioo.dout(7), gpioo.oen(7), gpioi.din(7));
504
504
505 PROCESS (clk_25, reset)
505 PROCESS (clk_25, reset)
506 BEGIN -- PROCESS
506 BEGIN -- PROCESS
507 IF reset = '0' THEN -- asynchronous reset (active low)
507 IF reset = '0' THEN -- asynchronous reset (active low)
508 IO0 <= '0';
508 IO0 <= '0';
509 IO1 <= '0';
509 IO1 <= '0';
510 IO2 <= '0';
510 IO2 <= '0';
511 IO3 <= '0';
511 IO3 <= '0';
512 IO4 <= '0';
512 IO4 <= '0';
513 IO5 <= '0';
513 IO5 <= '0';
514 IO6 <= '0';
514 IO6 <= '0';
515 IO7 <= '0';
515 IO7 <= '0';
516 IO8 <= '0';
516 IO8 <= '0';
517 IO9 <= '0';
517 IO9 <= '0';
518 IO10 <= '0';
518 IO10 <= '0';
519 IO11 <= '0';
519 IO11 <= '0';
520 ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge
520 ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge
521 CASE gpioo.dout(1 DOWNTO 0) IS
521 CASE gpioo.dout(1 DOWNTO 0) IS
522 WHEN "00" =>
522 WHEN "00" =>
523 IO0 <= observation_reg(0 );
523 IO0 <= observation_reg(0 );
524 IO1 <= observation_reg(1 );
524 IO1 <= observation_reg(1 );
525 IO2 <= observation_reg(2 );
525 IO2 <= observation_reg(2 );
526 IO3 <= observation_reg(3 );
526 IO3 <= observation_reg(3 );
527 IO4 <= observation_reg(4 );
527 IO4 <= observation_reg(4 );
528 IO5 <= observation_reg(5 );
528 IO5 <= observation_reg(5 );
529 IO6 <= observation_reg(6 );
529 IO6 <= observation_reg(6 );
530 IO7 <= observation_reg(7 );
530 IO7 <= observation_reg(7 );
531 IO8 <= observation_reg(8 );
531 IO8 <= observation_reg(8 );
532 IO9 <= observation_reg(9 );
532 IO9 <= observation_reg(9 );
533 IO10 <= observation_reg(10);
533 IO10 <= observation_reg(10);
534 IO11 <= observation_reg(11);
534 IO11 <= observation_reg(11);
535 WHEN "01" =>
535 WHEN "01" =>
536 IO0 <= observation_reg(0 + 12);
536 IO0 <= observation_reg(0 + 12);
537 IO1 <= observation_reg(1 + 12);
537 IO1 <= observation_reg(1 + 12);
538 IO2 <= observation_reg(2 + 12);
538 IO2 <= observation_reg(2 + 12);
539 IO3 <= observation_reg(3 + 12);
539 IO3 <= observation_reg(3 + 12);
540 IO4 <= observation_reg(4 + 12);
540 IO4 <= observation_reg(4 + 12);
541 IO5 <= observation_reg(5 + 12);
541 IO5 <= observation_reg(5 + 12);
542 IO6 <= observation_reg(6 + 12);
542 IO6 <= observation_reg(6 + 12);
543 IO7 <= observation_reg(7 + 12);
543 IO7 <= observation_reg(7 + 12);
544 IO8 <= observation_reg(8 + 12);
544 IO8 <= observation_reg(8 + 12);
545 IO9 <= observation_reg(9 + 12);
545 IO9 <= observation_reg(9 + 12);
546 IO10 <= observation_reg(10 + 12);
546 IO10 <= observation_reg(10 + 12);
547 IO11 <= observation_reg(11 + 12);
547 IO11 <= observation_reg(11 + 12);
548 WHEN "10" =>
548 WHEN "10" =>
549 IO0 <= observation_reg(0 + 12 + 12);
549 IO0 <= observation_reg(0 + 12 + 12);
550 IO1 <= observation_reg(1 + 12 + 12);
550 IO1 <= observation_reg(1 + 12 + 12);
551 IO2 <= observation_reg(2 + 12 + 12);
551 IO2 <= observation_reg(2 + 12 + 12);
552 IO3 <= observation_reg(3 + 12 + 12);
552 IO3 <= observation_reg(3 + 12 + 12);
553 IO4 <= observation_reg(4 + 12 + 12);
553 IO4 <= observation_reg(4 + 12 + 12);
554 IO5 <= observation_reg(5 + 12 + 12);
554 IO5 <= observation_reg(5 + 12 + 12);
555 IO6 <= observation_reg(6 + 12 + 12);
555 IO6 <= observation_reg(6 + 12 + 12);
556 IO7 <= observation_reg(7 + 12 + 12);
556 IO7 <= observation_reg(7 + 12 + 12);
557 IO8 <= '0';
557 IO8 <= '0';
558 IO9 <= '0';
558 IO9 <= '0';
559 IO10 <= '0';
559 IO10 <= '0';
560 IO11 <= '0';
560 IO11 <= '0';
561 WHEN "11" =>
561 WHEN "11" =>
562 IO0 <= '0';
562 IO0 <= '0';
563 IO1 <= '0';
563 IO1 <= '0';
564 IO2 <= '0';
564 IO2 <= '0';
565 IO3 <= '0';
565 IO3 <= '0';
566 IO4 <= '0';
566 IO4 <= '0';
567 IO5 <= '0';
567 IO5 <= '0';
568 IO6 <= '0';
568 IO6 <= '0';
569 IO7 <= '0';
569 IO7 <= '0';
570 IO8 <= '0';
570 IO8 <= '0';
571 IO9 <= '0';
571 IO9 <= '0';
572 IO10 <= '0';
572 IO10 <= '0';
573 IO11 <= '0';
573 IO11 <= '0';
574 WHEN OTHERS => NULL;
574 WHEN OTHERS => NULL;
575 END CASE;
575 END CASE;
576
576
577 END IF;
577 END IF;
578 END PROCESS;
578 END PROCESS;
579
579
580 END beh; No newline at end of file
580 END beh;
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@@ -1,191 +1,205
1
1
2 ------------------------------------------------------------------------------
2 ------------------------------------------------------------------------------
3 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- This file is a part of the LPP VHDL IP LIBRARY
4 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
5 --
5 --
6 -- This program is free software; you can redistribute it and/or modify
6 -- This program is free software; you can redistribute it and/or modify
7 -- it under the terms of the GNU General Public License as published by
7 -- it under the terms of the GNU General Public License as published by
8 -- the Free Software Foundation; either version 3 of the License, or
8 -- the Free Software Foundation; either version 3 of the License, or
9 -- (at your option) any later version.
9 -- (at your option) any later version.
10 --
10 --
11 -- This program is distributed in the hope that it will be useful,
11 -- This program is distributed in the hope that it will be useful,
12 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
13 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 -- GNU General Public License for more details.
14 -- GNU General Public License for more details.
15 --
15 --
16 -- You should have received a copy of the GNU General Public License
16 -- You should have received a copy of the GNU General Public License
17 -- along with this program; if not, write to the Free Software
17 -- along with this program; if not, write to the Free Software
18 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 -------------------------------------------------------------------------------
19 -------------------------------------------------------------------------------
20 -- Author : Jean-christophe Pellion
20 -- Author : Jean-christophe Pellion
21 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
22 -- jean-christophe.pellion@easii-ic.com
22 -- jean-christophe.pellion@easii-ic.com
23 -------------------------------------------------------------------------------
23 -------------------------------------------------------------------------------
24 -- 1.0 - initial version
24 -- 1.0 - initial version
25 -- 1.1 - (01/11/2013) FIX boundary error (1kB address should not be crossed by BURSTS)
25 -- 1.1 - (01/11/2013) FIX boundary error (1kB address should not be crossed by BURSTS)
26 -------------------------------------------------------------------------------
26 -------------------------------------------------------------------------------
27 LIBRARY ieee;
27 LIBRARY ieee;
28 USE ieee.std_logic_1164.ALL;
28 USE ieee.std_logic_1164.ALL;
29 USE ieee.numeric_std.ALL;
29 USE ieee.numeric_std.ALL;
30 LIBRARY grlib;
30 LIBRARY grlib;
31 USE grlib.amba.ALL;
31 USE grlib.amba.ALL;
32 USE grlib.stdlib.ALL;
32 USE grlib.stdlib.ALL;
33 USE grlib.devices.ALL;
33 USE grlib.devices.ALL;
34 USE GRLIB.DMA2AHB_Package.ALL;
34 USE GRLIB.DMA2AHB_Package.ALL;
35 LIBRARY lpp;
35 LIBRARY lpp;
36 USE lpp.lpp_amba.ALL;
36 USE lpp.lpp_amba.ALL;
37 USE lpp.apb_devices_list.ALL;
37 USE lpp.apb_devices_list.ALL;
38 USE lpp.lpp_memory.ALL;
38 USE lpp.lpp_memory.ALL;
39 USE lpp.lpp_dma_pkg.ALL;
39 USE lpp.lpp_dma_pkg.ALL;
40 USE lpp.lpp_waveform_pkg.ALL;
40 USE lpp.lpp_waveform_pkg.ALL;
41 LIBRARY techmap;
41 LIBRARY techmap;
42 USE techmap.gencomp.ALL;
42 USE techmap.gencomp.ALL;
43
43
44
44
45 ENTITY lpp_dma_singleOrBurst IS
45 ENTITY lpp_dma_singleOrBurst IS
46 GENERIC (
46 GENERIC (
47 tech : INTEGER := inferred;
47 tech : INTEGER := inferred;
48 hindex : INTEGER := 2
48 hindex : INTEGER := 2
49 );
49 );
50 PORT (
50 PORT (
51 -- AMBA AHB system signals
51 -- AMBA AHB system signals
52 HCLK : IN STD_ULOGIC;
52 HCLK : IN STD_ULOGIC;
53 HRESETn : IN STD_ULOGIC;
53 HRESETn : IN STD_ULOGIC;
54 --
54 --
55 run : IN STD_LOGIC;
55 run : IN STD_LOGIC;
56 -- AMBA AHB Master Interface
56 -- AMBA AHB Master Interface
57 AHB_Master_In : IN AHB_Mst_In_Type;
57 AHB_Master_In : IN AHB_Mst_In_Type;
58 AHB_Master_Out : OUT AHB_Mst_Out_Type;
58 AHB_Master_Out : OUT AHB_Mst_Out_Type;
59 --
59 --
60 send : IN STD_LOGIC;
60 send : IN STD_LOGIC;
61 valid_burst : IN STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
61 valid_burst : IN STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
62 done : OUT STD_LOGIC;
62 done : OUT STD_LOGIC;
63 ren : OUT STD_LOGIC;
63 ren : OUT STD_LOGIC;
64 address : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
64 address : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
65 data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
65 data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
66 --
66 --
67 debug_dmaout_okay : OUT STD_LOGIC
67 debug_dmaout_okay : OUT STD_LOGIC
68
68
69 );
69 );
70 END;
70 END;
71
71
72 ARCHITECTURE Behavioral OF lpp_dma_singleOrBurst IS
72 ARCHITECTURE Behavioral OF lpp_dma_singleOrBurst IS
73 -----------------------------------------------------------------------------
73 -----------------------------------------------------------------------------
74 SIGNAL DMAIn : DMA_In_Type;
74 SIGNAL DMAIn : DMA_In_Type;
75 SIGNAL DMAOut : DMA_OUt_Type;
75 SIGNAL DMAOut : DMA_OUt_Type;
76 -----------------------------------------------------------------------------
76 -----------------------------------------------------------------------------
77 -----------------------------------------------------------------------------
77 -----------------------------------------------------------------------------
78 -- CONTROL
78 -- CONTROL
79 SIGNAL single_send : STD_LOGIC;
79 SIGNAL single_send : STD_LOGIC;
80 SIGNAL burst_send : STD_LOGIC;
80 SIGNAL burst_send : STD_LOGIC;
81
81
82 -----------------------------------------------------------------------------
82 -----------------------------------------------------------------------------
83 -- SEND SINGLE MODULE
83 -- SEND SINGLE MODULE
84 SIGNAL single_dmai : DMA_In_Type;
84 SIGNAL single_dmai : DMA_In_Type;
85
85
86 SIGNAL single_send_ok : STD_LOGIC;
86 SIGNAL single_send_ok : STD_LOGIC;
87 SIGNAL single_send_ko : STD_LOGIC;
87 SIGNAL single_send_ko : STD_LOGIC;
88 SIGNAL single_ren : STD_LOGIC;
88 SIGNAL single_ren : STD_LOGIC;
89 -----------------------------------------------------------------------------
89 -----------------------------------------------------------------------------
90 -- SEND SINGLE MODULE
90 -- SEND SINGLE MODULE
91 SIGNAL burst_dmai : DMA_In_Type;
91 SIGNAL burst_dmai : DMA_In_Type;
92
92
93 SIGNAL burst_send_ok : STD_LOGIC;
93 SIGNAL burst_send_ok : STD_LOGIC;
94 SIGNAL burst_send_ko : STD_LOGIC;
94 SIGNAL burst_send_ko : STD_LOGIC;
95 SIGNAL burst_ren : STD_LOGIC;
95 SIGNAL burst_ren : STD_LOGIC;
96 -----------------------------------------------------------------------------
96 -----------------------------------------------------------------------------
97 SIGNAL data_2_halfword : STD_LOGIC_VECTOR(31 DOWNTO 0);
97 SIGNAL data_2_halfword : STD_LOGIC_VECTOR(31 DOWNTO 0);
98 -----------------------------------------------------------------------------
99 -- \/ -- 20/02/2014 -- JC Pellion
100 SIGNAL send_reg : STD_LOGIC;
101 SIGNAL send_s : STD_LOGIC;
102 -- /\ --
103
104
98 BEGIN
105 BEGIN
99
106
100 debug_dmaout_okay <= DMAOut.OKAY;
107 debug_dmaout_okay <= DMAOut.OKAY;
101
108
102
109
103 -----------------------------------------------------------------------------
110 -----------------------------------------------------------------------------
104 -- DMA to AHB interface
111 -- DMA to AHB interface
105 DMA2AHB_1 : DMA2AHB
112 DMA2AHB_1 : DMA2AHB
106 GENERIC MAP (
113 GENERIC MAP (
107 hindex => hindex,
114 hindex => hindex,
108 vendorid => VENDOR_LPP,
115 vendorid => VENDOR_LPP,
109 deviceid => 10,
116 deviceid => 10,
110 version => 0,
117 version => 0,
111 syncrst => 1,
118 syncrst => 1,
112 boundary => 1) -- FIX 11/01/2013
119 boundary => 1) -- FIX 11/01/2013
113 PORT MAP (
120 PORT MAP (
114 HCLK => HCLK,
121 HCLK => HCLK,
115 HRESETn => HRESETn,
122 HRESETn => HRESETn,
116 DMAIn => DMAIn,
123 DMAIn => DMAIn,
117 DMAOut => DMAOut,
124 DMAOut => DMAOut,
118
125
119 AHBIn => AHB_Master_In,
126 AHBIn => AHB_Master_In,
120 AHBOut => AHB_Master_Out);
127 AHBOut => AHB_Master_Out);
121 -----------------------------------------------------------------------------
128 -----------------------------------------------------------------------------
122
129
123 -----------------------------------------------------------------------------
130 -----------------------------------------------------------------------------
124 -----------------------------------------------------------------------------
131 -- \/ -- 20/02/2014 -- JC Pellion
125 -- LE PROBLEME EST LA !!!!!
132 PROCESS (HCLK, HRESETn)
126 -----------------------------------------------------------------------------
133 BEGIN
127 -----------------------------------------------------------------------------
134 IF HRESETn = '0' THEN
128 -- C'est le signal valid_burst qui n'est pas assez long.
135 send_reg <= '0';
129 -----------------------------------------------------------------------------
136 ELSIF HCLK'event AND HCLK = '1' THEN
130 single_send <= send WHEN valid_burst = '0' ELSE '0';
137 send_reg <= send;
131 burst_send <= send WHEN valid_burst = '1' ELSE '0';
138 END IF;
139 END PROCESS;
140 send_s <= send_reg;
141
142 single_send <= send_s WHEN valid_burst = '0' ELSE '0';
143 burst_send <= send_s WHEN valid_burst = '1' ELSE '0';
144 -- /\ --
145
132 DMAIn <= single_dmai WHEN valid_burst = '0' ELSE burst_dmai;
146 DMAIn <= single_dmai WHEN valid_burst = '0' ELSE burst_dmai;
133
147
134 -- TODO : verifier
148 -- TODO : verifier
135 done <= single_send_ok OR single_send_ko OR burst_send_ok OR burst_send_ko;
149 done <= single_send_ok OR single_send_ko OR burst_send_ok OR burst_send_ko;
136 --done <= single_send_ok OR single_send_ko WHEN valid_burst = '0' ELSE
150 --done <= single_send_ok OR single_send_ko WHEN valid_burst = '0' ELSE
137 -- burst_send_ok OR burst_send_ko;
151 -- burst_send_ok OR burst_send_ko;
138
152
139 --ren <= burst_ren WHEN valid_burst = '1' ELSE
153 --ren <= burst_ren WHEN valid_burst = '1' ELSE
140 -- NOT single_send_ok;
154 -- NOT single_send_ok;
141 --ren <= burst_ren AND single_ren;
155 --ren <= burst_ren AND single_ren;
142
156
143 -- \/ JC - 20/01/2014 \/
157 -- \/ JC - 20/01/2014 \/
144 ren <= burst_ren WHEN valid_burst = '1' ELSE
158 ren <= burst_ren WHEN valid_burst = '1' ELSE
145 single_ren;
159 single_ren;
146
160
147
161
148 --ren <= '0' WHEN DMAOut.OKAY = '1' ELSE
162 --ren <= '0' WHEN DMAOut.OKAY = '1' ELSE
149 -- '1';
163 -- '1';
150 -- /\ JC - 20/01/2014 /\
164 -- /\ JC - 20/01/2014 /\
151
165
152 -----------------------------------------------------------------------------
166 -----------------------------------------------------------------------------
153 -- SEND 1 word by DMA
167 -- SEND 1 word by DMA
154 -----------------------------------------------------------------------------
168 -----------------------------------------------------------------------------
155 lpp_dma_send_1word_1 : lpp_dma_send_1word
169 lpp_dma_send_1word_1 : lpp_dma_send_1word
156 PORT MAP (
170 PORT MAP (
157 HCLK => HCLK,
171 HCLK => HCLK,
158 HRESETn => HRESETn,
172 HRESETn => HRESETn,
159 DMAIn => single_dmai,
173 DMAIn => single_dmai,
160 DMAOut => DMAOut,
174 DMAOut => DMAOut,
161
175
162 send => single_send,
176 send => single_send,
163 address => address,
177 address => address,
164 data => data_2_halfword,
178 data => data_2_halfword,
165 ren => single_ren,
179 ren => single_ren,
166
180
167 send_ok => single_send_ok, -- TODO
181 send_ok => single_send_ok, -- TODO
168 send_ko => single_send_ko -- TODO
182 send_ko => single_send_ko -- TODO
169 );
183 );
170
184
171 -----------------------------------------------------------------------------
185 -----------------------------------------------------------------------------
172 -- SEND 16 word by DMA (in burst mode)
186 -- SEND 16 word by DMA (in burst mode)
173 -----------------------------------------------------------------------------
187 -----------------------------------------------------------------------------
174 data_2_halfword(31 DOWNTO 0) <= data(15 DOWNTO 0) & data (31 DOWNTO 16);
188 data_2_halfword(31 DOWNTO 0) <= data(15 DOWNTO 0) & data (31 DOWNTO 16);
175
189
176 lpp_dma_send_16word_1 : lpp_dma_send_16word
190 lpp_dma_send_16word_1 : lpp_dma_send_16word
177 PORT MAP (
191 PORT MAP (
178 HCLK => HCLK,
192 HCLK => HCLK,
179 HRESETn => HRESETn,
193 HRESETn => HRESETn,
180 DMAIn => burst_dmai,
194 DMAIn => burst_dmai,
181 DMAOut => DMAOut,
195 DMAOut => DMAOut,
182
196
183 send => burst_send,
197 send => burst_send,
184 address => address,
198 address => address,
185 data => data_2_halfword,
199 data => data_2_halfword,
186 ren => burst_ren,
200 ren => burst_ren,
187
201
188 send_ok => burst_send_ok,
202 send_ok => burst_send_ok,
189 send_ko => burst_send_ko);
203 send_ko => burst_send_ko);
190
204
191 END Behavioral;
205 END Behavioral;
Show file before | Show file after | Hide comments
@@ -1,662 +1,664
1 --************************************************************************
1 --************************************************************************
2 --** MODEL : async_1Mx16.vhd **
2 --** MODEL : async_1Mx16.vhd **
3 --** COMPANY : Cypress Semiconductor **
3 --** COMPANY : Cypress Semiconductor **
4 --** REVISION: 1.0 Created new base model **
4 --** REVISION: 1.0 Created new base model **
5 --************************************************************************
5 --************************************************************************
6
6
7 -------------------------------------------------------------------------------JC\/
7 -------------------------------------------------------------------------------JC\/
8 --Library ieee,work;
8 --Library ieee,work;
9 LIBRARY ieee;
9 LIBRARY ieee;
10 -------------------------------------------------------------------------------JC/\
10 -------------------------------------------------------------------------------JC/\
11 USE IEEE.Std_Logic_1164.ALL;
11 USE IEEE.Std_Logic_1164.ALL;
12 USE IEEE.Std_Logic_unsigned.ALL;
12 USE IEEE.Std_Logic_unsigned.ALL;
13
13
14 -------------------------------------------------------------------------------JC\/
14 -------------------------------------------------------------------------------JC\/
15 --use work.package_timing.all;
15 --use work.package_timing.all;
16 --use work.package_utility.all;
16 --use work.package_utility.all;
17 LIBRARY lpp;
17 LIBRARY lpp;
18 USE lpp.package_timing.ALL;
18 USE lpp.package_timing.ALL;
19 USE lpp.package_utility.ALL;
19 USE lpp.package_utility.ALL;
20 -------------------------------------------------------------------------------JC/\
20 -------------------------------------------------------------------------------JC/\
21
21
22 ------------------------
22 ------------------------
23 -- Entity Description
23 -- Entity Description
24 ------------------------
24 ------------------------
25
25
26 ENTITY CY7C1061DV33 IS
26 ENTITY CY7C1061DV33 IS
27 GENERIC
27 GENERIC
28 (ADDR_BITS : INTEGER := 20;
28 (ADDR_BITS : INTEGER := 20;
29 DATA_BITS : INTEGER := 16;
29 DATA_BITS : INTEGER := 16;
30 depth : INTEGER := 1048576;
30 depth : INTEGER := 1048576;
31
31
32 MEM_ARRAY_DEBUG : INTEGER := 32;
33
32 TimingInfo : BOOLEAN := true;
34 TimingInfo : BOOLEAN := true;
33 TimingChecks : STD_LOGIC := '1'
35 TimingChecks : STD_LOGIC := '1'
34 );
36 );
35 PORT (
37 PORT (
36 CE1_b : IN STD_LOGIC; -- Chip Enable CE1#
38 CE1_b : IN STD_LOGIC; -- Chip Enable CE1#
37 CE2 : IN STD_LOGIC; -- Chip Enable CE2
39 CE2 : IN STD_LOGIC; -- Chip Enable CE2
38 WE_b : IN STD_LOGIC; -- Write Enable WE#
40 WE_b : IN STD_LOGIC; -- Write Enable WE#
39 OE_b : IN STD_LOGIC; -- Output Enable OE#
41 OE_b : IN STD_LOGIC; -- Output Enable OE#
40 BHE_b : IN STD_LOGIC; -- Byte Enable High BHE#
42 BHE_b : IN STD_LOGIC; -- Byte Enable High BHE#
41 BLE_b : IN STD_LOGIC; -- Byte Enable Low BLE#
43 BLE_b : IN STD_LOGIC; -- Byte Enable Low BLE#
42 A : IN STD_LOGIC_VECTOR(addr_bits-1 DOWNTO 0); -- Address Inputs A
44 A : IN STD_LOGIC_VECTOR(addr_bits-1 DOWNTO 0); -- Address Inputs A
43 DQ : INOUT STD_LOGIC_VECTOR(DATA_BITS-1 DOWNTO 0) := (OTHERS => 'Z')-- Read/Write Data IO;
45 DQ : INOUT STD_LOGIC_VECTOR(DATA_BITS-1 DOWNTO 0) := (OTHERS => 'Z')-- Read/Write Data IO;
44 );
46 );
45 END CY7C1061DV33;
47 END CY7C1061DV33;
46
48
47 -----------------------------
49 -----------------------------
48 -- End Entity Description
50 -- End Entity Description
49 -----------------------------
51 -----------------------------
50 -----------------------------
52 -----------------------------
51 -- Architecture Description
53 -- Architecture Description
52 -----------------------------
54 -----------------------------
53
55
54 ARCHITECTURE behave_arch OF CY7C1061DV33 IS
56 ARCHITECTURE behave_arch OF CY7C1061DV33 IS
55
57
56 TYPE mem_array_type IS ARRAY (depth-1 DOWNTO 0) OF STD_LOGIC_VECTOR(DATA_BITS-1 DOWNTO 0);
58 TYPE mem_array_type IS ARRAY (depth-1 DOWNTO 0) OF STD_LOGIC_VECTOR(DATA_BITS-1 DOWNTO 0);
57
59
58 SIGNAL write_enable : STD_LOGIC;
60 SIGNAL write_enable : STD_LOGIC;
59 SIGNAL read_enable : STD_LOGIC;
61 SIGNAL read_enable : STD_LOGIC;
60 SIGNAL byte_enable : STD_LOGIC;
62 SIGNAL byte_enable : STD_LOGIC;
61 SIGNAL CE_b : STD_LOGIC;
63 SIGNAL CE_b : STD_LOGIC;
62
64
63 SIGNAL data_skew : STD_LOGIC_VECTOR(DATA_BITS-1 DOWNTO 0);
65 SIGNAL data_skew : STD_LOGIC_VECTOR(DATA_BITS-1 DOWNTO 0);
64
66
65 SIGNAL address_internal, address_skew : STD_LOGIC_VECTOR(addr_bits-1 DOWNTO 0);
67 SIGNAL address_internal, address_skew : STD_LOGIC_VECTOR(addr_bits-1 DOWNTO 0);
66
68
67 CONSTANT tSD_dataskew : TIME := tSD - 1 ns;
69 CONSTANT tSD_dataskew : TIME := tSD - 1 ns;
68 CONSTANT tskew : TIME := 1 ns;
70 CONSTANT tskew : TIME := 1 ns;
69
71
70 -------------------------------------------------------------------------------JC\/
72 -------------------------------------------------------------------------------JC\/
71 TYPE mem_array_type_t IS ARRAY (31 DOWNTO 0) OF STD_LOGIC_VECTOR(DATA_BITS-1 DOWNTO 0);
73 TYPE mem_array_type_t IS ARRAY (MEM_ARRAY_DEBUG-1 DOWNTO 0) OF STD_LOGIC_VECTOR(DATA_BITS-1 DOWNTO 0);
72 SIGNAL mem_array_0 : mem_array_type_t;
74 SIGNAL mem_array_0 : mem_array_type_t;
73 SIGNAL mem_array_1 : mem_array_type_t;
75 SIGNAL mem_array_1 : mem_array_type_t;
74 SIGNAL mem_array_2 : mem_array_type_t;
76 SIGNAL mem_array_2 : mem_array_type_t;
75 SIGNAL mem_array_3 : mem_array_type_t;
77 SIGNAL mem_array_3 : mem_array_type_t;
76 -------------------------------------------------------------------------------JC/\
78 -------------------------------------------------------------------------------JC/\
77
79
78
80
79
81
80 BEGIN
82 BEGIN
81 CE_b <= CE1_b OR NOT(CE2);
83 CE_b <= CE1_b OR NOT(CE2);
82 byte_enable <= NOT(BHE_b AND BLE_b);
84 byte_enable <= NOT(BHE_b AND BLE_b);
83 write_enable <= NOT(CE1_b) AND CE2 AND NOT(WE_b) AND NOT(BHE_b AND BLE_b);
85 write_enable <= NOT(CE1_b) AND CE2 AND NOT(WE_b) AND NOT(BHE_b AND BLE_b);
84 read_enable <= NOT(CE1_b) AND CE2 AND (WE_b) AND NOT(OE_b) AND NOT(BHE_b AND BLE_b);
86 read_enable <= NOT(CE1_b) AND CE2 AND (WE_b) AND NOT(OE_b) AND NOT(BHE_b AND BLE_b);
85
87
86 data_skew <= DQ AFTER 1 ns; -- changed on feb 15
88 data_skew <= DQ AFTER 1 ns; -- changed on feb 15
87 address_skew <= A AFTER 1 ns;
89 address_skew <= A AFTER 1 ns;
88
90
89 PROCESS (OE_b)
91 PROCESS (OE_b)
90 BEGIN
92 BEGIN
91 IF (OE_b'EVENT AND OE_b = '1' AND write_enable /= '1') THEN
93 IF (OE_b'EVENT AND OE_b = '1' AND write_enable /= '1') THEN
92 DQ <= (OTHERS => 'Z') after tHZOE;
94 DQ <= (OTHERS => 'Z') after tHZOE;
93 END IF;
95 END IF;
94 END PROCESS;
96 END PROCESS;
95
97
96 PROCESS (CE_b)
98 PROCESS (CE_b)
97 BEGIN
99 BEGIN
98 IF (CE_b'EVENT AND CE_b = '1') THEN
100 IF (CE_b'EVENT AND CE_b = '1') THEN
99 DQ <= (OTHERS => 'Z') after tHZCE;
101 DQ <= (OTHERS => 'Z') after tHZCE;
100 END IF;
102 END IF;
101 END PROCESS;
103 END PROCESS;
102
104
103 PROCESS (write_enable'DELAYED(tHA))
105 PROCESS (write_enable'DELAYED(tHA))
104 BEGIN
106 BEGIN
105 IF (write_enable'DELAYED(tHA) = '0' AND TimingInfo) THEN
107 IF (write_enable'DELAYED(tHA) = '0' AND TimingInfo) THEN
106 ASSERT (A'LAST_EVENT = 0 ns) OR (A'LAST_EVENT > tHA)
108 ASSERT (A'LAST_EVENT = 0 ns) OR (A'LAST_EVENT > tHA)
107 REPORT "Address hold time tHA violated";
109 REPORT "Address hold time tHA violated";
108 END IF;
110 END IF;
109 END PROCESS;
111 END PROCESS;
110
112
111 PROCESS (write_enable'DELAYED(tHD))
113 PROCESS (write_enable'DELAYED(tHD))
112 BEGIN
114 BEGIN
113 IF (write_enable'DELAYED(tHD) = '0' AND TimingInfo) THEN
115 IF (write_enable'DELAYED(tHD) = '0' AND TimingInfo) THEN
114 ASSERT (DQ'LAST_EVENT > tHD) OR (DQ'LAST_EVENT = 0 ns)
116 ASSERT (DQ'LAST_EVENT > tHD) OR (DQ'LAST_EVENT = 0 ns)
115 REPORT "Data hold time tHD violated";
117 REPORT "Data hold time tHD violated";
116 END IF;
118 END IF;
117 END PROCESS;
119 END PROCESS;
118
120
119 -- main process
121 -- main process
120 PROCESS
122 PROCESS
121
123
122 VARIABLE mem_array : mem_array_type;
124 VARIABLE mem_array : mem_array_type;
123
125
124 --- Variables for timing checks
126 --- Variables for timing checks
125 VARIABLE tPWE_chk : TIME := -10 ns;
127 VARIABLE tPWE_chk : TIME := -10 ns;
126 VARIABLE tAW_chk : TIME := -10 ns;
128 VARIABLE tAW_chk : TIME := -10 ns;
127 VARIABLE tSD_chk : TIME := -10 ns;
129 VARIABLE tSD_chk : TIME := -10 ns;
128 VARIABLE tRC_chk : TIME := 0 ns;
130 VARIABLE tRC_chk : TIME := 0 ns;
129 VARIABLE tBAW_chk : TIME := 0 ns;
131 VARIABLE tBAW_chk : TIME := 0 ns;
130 VARIABLE tBBW_chk : TIME := 0 ns;
132 VARIABLE tBBW_chk : TIME := 0 ns;
131 VARIABLE tBCW_chk : TIME := 0 ns;
133 VARIABLE tBCW_chk : TIME := 0 ns;
132 VARIABLE tBDW_chk : TIME := 0 ns;
134 VARIABLE tBDW_chk : TIME := 0 ns;
133 VARIABLE tSA_chk : TIME := 0 ns;
135 VARIABLE tSA_chk : TIME := 0 ns;
134 VARIABLE tSA_skew : TIME := 0 ns;
136 VARIABLE tSA_skew : TIME := 0 ns;
135 VARIABLE tAint_chk : TIME := -10 ns;
137 VARIABLE tAint_chk : TIME := -10 ns;
136
138
137 VARIABLE write_flag : BOOLEAN := true;
139 VARIABLE write_flag : BOOLEAN := true;
138
140
139 VARIABLE accesstime : TIME := 0 ns;
141 VARIABLE accesstime : TIME := 0 ns;
140
142
141 BEGIN
143 BEGIN
142 IF (address_skew'EVENT) THEN
144 IF (address_skew'EVENT) THEN
143 tSA_skew := NOW;
145 tSA_skew := NOW;
144 END IF;
146 END IF;
145
147
146 -- start of write
148 -- start of write
147 IF (write_enable = '1' AND write_enable'EVENT) THEN
149 IF (write_enable = '1' AND write_enable'EVENT) THEN
148
150
149 DQ(DATA_BITS-1 DOWNTO 0) <= (OTHERS => 'Z') after tHZWE;
151 DQ(DATA_BITS-1 DOWNTO 0) <= (OTHERS => 'Z') after tHZWE;
150
152
151 IF (A'LAST_EVENT >= tSA) THEN
153 IF (A'LAST_EVENT >= tSA) THEN
152 address_internal <= A;
154 address_internal <= A;
153 tPWE_chk := NOW;
155 tPWE_chk := NOW;
154 tAW_chk := A'LAST_EVENT;
156 tAW_chk := A'LAST_EVENT;
155 tAint_chk := NOW;
157 tAint_chk := NOW;
156 write_flag := true;
158 write_flag := true;
157
159
158 ELSE
160 ELSE
159 IF (TimingInfo) THEN
161 IF (TimingInfo) THEN
160 ASSERT false
162 ASSERT false
161 REPORT "Address setup violated";
163 REPORT "Address setup violated";
162 END IF;
164 END IF;
163 write_flag := false;
165 write_flag := false;
164
166
165 END IF;
167 END IF;
166
168
167 -- end of write (with CE high or WE high)
169 -- end of write (with CE high or WE high)
168 ELSIF (write_enable = '0' AND write_enable'EVENT) THEN
170 ELSIF (write_enable = '0' AND write_enable'EVENT) THEN
169
171
170 --- check for pulse width
172 --- check for pulse width
171 IF (NOW - tPWE_chk >= tPWE OR NOW - tPWE_chk <= 0.1 ns OR NOW = 0 ns) THEN
173 IF (NOW - tPWE_chk >= tPWE OR NOW - tPWE_chk <= 0.1 ns OR NOW = 0 ns) THEN
172 --- pulse width OK, do nothing
174 --- pulse width OK, do nothing
173 ELSE
175 ELSE
174 IF (TimingInfo) THEN
176 IF (TimingInfo) THEN
175 ASSERT false
177 ASSERT false
176 REPORT "Pulse Width violation";
178 REPORT "Pulse Width violation";
177 END IF;
179 END IF;
178
180
179 write_flag := false;
181 write_flag := false;
180 END IF;
182 END IF;
181
183
182
184
183 IF (NOW > 0 ns) THEN
185 IF (NOW > 0 ns) THEN
184 IF (tSA_skew - tAint_chk > tskew) THEN
186 IF (tSA_skew - tAint_chk > tskew) THEN
185 ASSERT false
187 ASSERT false
186 REPORT "Negative address setup";
188 REPORT "Negative address setup";
187 write_flag := false;
189 write_flag := false;
188 END IF;
190 END IF;
189 END IF;
191 END IF;
190
192
191 --- check for address setup with write end, i.e., tAW
193 --- check for address setup with write end, i.e., tAW
192 IF (NOW - tAW_chk >= tAW OR NOW = 0 ns) THEN
194 IF (NOW - tAW_chk >= tAW OR NOW = 0 ns) THEN
193 --- tAW OK, do nothing
195 --- tAW OK, do nothing
194 ELSE
196 ELSE
195 IF (TimingInfo) THEN
197 IF (TimingInfo) THEN
196 ASSERT false
198 ASSERT false
197 REPORT "Address setup tAW violation";
199 REPORT "Address setup tAW violation";
198 END IF;
200 END IF;
199
201
200 write_flag := false;
202 write_flag := false;
201 END IF;
203 END IF;
202
204
203 --- check for data setup with write end, i.e., tSD
205 --- check for data setup with write end, i.e., tSD
204 IF (NOW - tSD_chk >= tSD_dataskew OR NOW - tSD_chk <= 0.1 ns OR NOW = 0 ns) THEN
206 IF (NOW - tSD_chk >= tSD_dataskew OR NOW - tSD_chk <= 0.1 ns OR NOW = 0 ns) THEN
205 --- tSD OK, do nothing
207 --- tSD OK, do nothing
206 ELSE
208 ELSE
207 IF (TimingInfo) THEN
209 IF (TimingInfo) THEN
208 ASSERT false
210 ASSERT false
209 REPORT "Data setup tSD violation";
211 REPORT "Data setup tSD violation";
210 END IF;
212 END IF;
211 write_flag := false;
213 write_flag := false;
212 END IF;
214 END IF;
213
215
214 -- perform write operation if no violations
216 -- perform write operation if no violations
215 IF (write_flag = true) THEN
217 IF (write_flag = true) THEN
216
218
217 IF (BLE_b = '1' AND BLE_b'LAST_EVENT = write_enable'LAST_EVENT AND NOW /= 0 ns) THEN
219 IF (BLE_b = '1' AND BLE_b'LAST_EVENT = write_enable'LAST_EVENT AND NOW /= 0 ns) THEN
218 mem_array(conv_integer1(address_internal))(7 DOWNTO 0) := data_skew(7 DOWNTO 0);
220 mem_array(conv_integer1(address_internal))(7 DOWNTO 0) := data_skew(7 DOWNTO 0);
219 END IF;
221 END IF;
220
222
221 IF (BHE_b = '1' AND BHE_b'LAST_EVENT = write_enable'LAST_EVENT AND NOW /= 0 ns) THEN
223 IF (BHE_b = '1' AND BHE_b'LAST_EVENT = write_enable'LAST_EVENT AND NOW /= 0 ns) THEN
222 mem_array(conv_integer1(address_internal))(15 DOWNTO 8) := data_skew(15 DOWNTO 8);
224 mem_array(conv_integer1(address_internal))(15 DOWNTO 8) := data_skew(15 DOWNTO 8);
223 END IF;
225 END IF;
224
226
225 IF (BLE_b = '0' AND NOW - tBAW_chk >= tBW) THEN
227 IF (BLE_b = '0' AND NOW - tBAW_chk >= tBW) THEN
226 mem_array(conv_integer1(address_internal))(7 DOWNTO 0) := data_skew(7 DOWNTO 0);
228 mem_array(conv_integer1(address_internal))(7 DOWNTO 0) := data_skew(7 DOWNTO 0);
227 ELSIF (NOW - tBAW_chk < tBW AND NOW - tBAW_chk > 0.1 ns AND NOW > 0 ns) THEN
229 ELSIF (NOW - tBAW_chk < tBW AND NOW - tBAW_chk > 0.1 ns AND NOW > 0 ns) THEN
228 ASSERT false REPORT "Insufficient pulse width for lower byte to be written";
230 ASSERT false REPORT "Insufficient pulse width for lower byte to be written";
229 END IF;
231 END IF;
230
232
231 IF (BHE_b = '0' AND NOW - tBBW_chk >= tBW) THEN
233 IF (BHE_b = '0' AND NOW - tBBW_chk >= tBW) THEN
232 mem_array(conv_integer1(address_internal))(15 DOWNTO 8) := data_skew(15 DOWNTO 8);
234 mem_array(conv_integer1(address_internal))(15 DOWNTO 8) := data_skew(15 DOWNTO 8);
233 ELSIF (NOW - tBBW_chk < tBW AND NOW - tBBW_chk > 0.1 ns AND NOW > 0 ns) THEN
235 ELSIF (NOW - tBBW_chk < tBW AND NOW - tBBW_chk > 0.1 ns AND NOW > 0 ns) THEN
234 ASSERT false REPORT "Insufficient pulse width for higher byte to be written";
236 ASSERT false REPORT "Insufficient pulse width for higher byte to be written";
235 END IF;
237 END IF;
236
238
237
239
238 -------------------------------------------------------------------------------JC\/
240 -------------------------------------------------------------------------------JC\/
239 all_mem_array_obs: FOR I IN 0 TO 31 LOOP
241 all_mem_array_obs: FOR I IN 0 TO MEM_ARRAY_DEBUG-1 LOOP
240 IF I + ((2**15) *0) < depth THEN mem_array_0(I) <= mem_array(I+((2**15) *0)); END IF;
242 IF I + ((2**15) *0) < depth THEN mem_array_0(I) <= mem_array(I+((2**15) *0)); END IF;
241 IF I + ((2**15) *1) < depth THEN mem_array_1(I) <= mem_array(I+((2**15) *1)); END IF;
243 IF I + ((2**15) *1) < depth THEN mem_array_1(I) <= mem_array(I+((2**15) *1)); END IF;
242 IF I + ((2**15) *2) < depth THEN mem_array_2(I) <= mem_array(I+((2**15) *2)); END IF;
244 IF I + ((2**15) *2) < depth THEN mem_array_2(I) <= mem_array(I+((2**15) *2)); END IF;
243 IF I + ((2**15) *3) < depth THEN mem_array_3(I) <= mem_array(I+((2**15) *3)); END IF;
245 IF I + ((2**15) *3) < depth THEN mem_array_3(I) <= mem_array(I+((2**15) *3)); END IF;
244 END LOOP all_mem_array_obs;
246 END LOOP all_mem_array_obs;
245 -------------------------------------------------------------------------------JC/\
247 -------------------------------------------------------------------------------JC/\
246
248
247 END IF;
249 END IF;
248
250
249 -- end of write (with BLE high)
251 -- end of write (with BLE high)
250 ELSIF (BLE_b'EVENT AND NOT(BHE_b'EVENT) AND write_enable = '1') THEN
252 ELSIF (BLE_b'EVENT AND NOT(BHE_b'EVENT) AND write_enable = '1') THEN
251
253
252 IF (BLE_b = '0') THEN
254 IF (BLE_b = '0') THEN
253
255
254 --- Reset timing variables
256 --- Reset timing variables
255 tAW_chk := A'LAST_EVENT;
257 tAW_chk := A'LAST_EVENT;
256 tBAW_chk := NOW;
258 tBAW_chk := NOW;
257 write_flag := true;
259 write_flag := true;
258
260
259 ELSIF (BLE_b = '1') THEN
261 ELSIF (BLE_b = '1') THEN
260
262
261 --- check for pulse width
263 --- check for pulse width
262 IF (NOW - tPWE_chk >= tPWE) THEN
264 IF (NOW - tPWE_chk >= tPWE) THEN
263 --- tPWE OK, do nothing
265 --- tPWE OK, do nothing
264 ELSE
266 ELSE
265 IF (TimingInfo) THEN
267 IF (TimingInfo) THEN
266 ASSERT false
268 ASSERT false
267 REPORT "Pulse Width violation";
269 REPORT "Pulse Width violation";
268 END IF;
270 END IF;
269
271
270 write_flag := false;
272 write_flag := false;
271 END IF;
273 END IF;
272
274
273 --- check for address setup with write end, i.e., tAW
275 --- check for address setup with write end, i.e., tAW
274 IF (NOW - tAW_chk >= tAW) THEN
276 IF (NOW - tAW_chk >= tAW) THEN
275 --- tAW OK, do nothing
277 --- tAW OK, do nothing
276 ELSE
278 ELSE
277 IF (TimingInfo) THEN
279 IF (TimingInfo) THEN
278 ASSERT false
280 ASSERT false
279 REPORT "Address setup tAW violation for Lower Byte Write";
281 REPORT "Address setup tAW violation for Lower Byte Write";
280 END IF;
282 END IF;
281
283
282 write_flag := false;
284 write_flag := false;
283 END IF;
285 END IF;
284
286
285 --- check for byte write setup with write end, i.e., tBW
287 --- check for byte write setup with write end, i.e., tBW
286 IF (NOW - tBAW_chk >= tBW) THEN
288 IF (NOW - tBAW_chk >= tBW) THEN
287 --- tBW OK, do nothing
289 --- tBW OK, do nothing
288 ELSE
290 ELSE
289 IF (TimingInfo) THEN
291 IF (TimingInfo) THEN
290 ASSERT false
292 ASSERT false
291 REPORT "Lower Byte setup tBW violation";
293 REPORT "Lower Byte setup tBW violation";
292 END IF;
294 END IF;
293
295
294 write_flag := false;
296 write_flag := false;
295 END IF;
297 END IF;
296
298
297 --- check for data setup with write end, i.e., tSD
299 --- check for data setup with write end, i.e., tSD
298 IF (NOW - tSD_chk >= tSD_dataskew OR NOW - tSD_chk <= 0.1 ns OR NOW = 0 ns) THEN
300 IF (NOW - tSD_chk >= tSD_dataskew OR NOW - tSD_chk <= 0.1 ns OR NOW = 0 ns) THEN
299 --- tSD OK, do nothing
301 --- tSD OK, do nothing
300 ELSE
302 ELSE
301 IF (TimingInfo) THEN
303 IF (TimingInfo) THEN
302 ASSERT false
304 ASSERT false
303 REPORT "Data setup tSD violation for Lower Byte Write";
305 REPORT "Data setup tSD violation for Lower Byte Write";
304 END IF;
306 END IF;
305
307
306 write_flag := false;
308 write_flag := false;
307 END IF;
309 END IF;
308
310
309 --- perform WRITE operation if no violations
311 --- perform WRITE operation if no violations
310 IF (write_flag = true) THEN
312 IF (write_flag = true) THEN
311 mem_array(conv_integer1(address_internal))(7 DOWNTO 0) := data_skew(7 DOWNTO 0);
313 mem_array(conv_integer1(address_internal))(7 DOWNTO 0) := data_skew(7 DOWNTO 0);
312 IF (BHE_b = '0') THEN
314 IF (BHE_b = '0') THEN
313 mem_array(conv_integer1(address_internal))(15 DOWNTO 8) := data_skew(15 DOWNTO 8);
315 mem_array(conv_integer1(address_internal))(15 DOWNTO 8) := data_skew(15 DOWNTO 8);
314 END IF;
316 END IF;
315 END IF;
317 END IF;
316
318
317 --- Reset timing variables
319 --- Reset timing variables
318 tAW_chk := A'LAST_EVENT;
320 tAW_chk := A'LAST_EVENT;
319 tBAW_chk := NOW;
321 tBAW_chk := NOW;
320 write_flag := true;
322 write_flag := true;
321
323
322 END IF;
324 END IF;
323
325
324 -- end of write (with BHE high)
326 -- end of write (with BHE high)
325 ELSIF (BHE_b'EVENT AND NOT(BLE_b'EVENT) AND write_enable = '1') THEN
327 ELSIF (BHE_b'EVENT AND NOT(BLE_b'EVENT) AND write_enable = '1') THEN
326
328
327 IF (BHE_b = '0') THEN
329 IF (BHE_b = '0') THEN
328
330
329 --- Reset timing variables
331 --- Reset timing variables
330 tAW_chk := A'LAST_EVENT;
332 tAW_chk := A'LAST_EVENT;
331 tBBW_chk := NOW;
333 tBBW_chk := NOW;
332 write_flag := true;
334 write_flag := true;
333
335
334 ELSIF (BHE_b = '1') THEN
336 ELSIF (BHE_b = '1') THEN
335
337
336 --- check for pulse width
338 --- check for pulse width
337 IF (NOW - tPWE_chk >= tPWE) THEN
339 IF (NOW - tPWE_chk >= tPWE) THEN
338 --- tPWE OK, do nothing
340 --- tPWE OK, do nothing
339 ELSE
341 ELSE
340 IF (TimingInfo) THEN
342 IF (TimingInfo) THEN
341 ASSERT false
343 ASSERT false
342 REPORT "Pulse Width violation";
344 REPORT "Pulse Width violation";
343 END IF;
345 END IF;
344
346
345 write_flag := false;
347 write_flag := false;
346 END IF;
348 END IF;
347
349
348 --- check for address setup with write end, i.e., tAW
350 --- check for address setup with write end, i.e., tAW
349 IF (NOW - tAW_chk >= tAW) THEN
351 IF (NOW - tAW_chk >= tAW) THEN
350 --- tAW OK, do nothing
352 --- tAW OK, do nothing
351 ELSE
353 ELSE
352 IF (TimingInfo) THEN
354 IF (TimingInfo) THEN
353 ASSERT false
355 ASSERT false
354 REPORT "Address setup tAW violation for Upper Byte Write";
356 REPORT "Address setup tAW violation for Upper Byte Write";
355 END IF;
357 END IF;
356 write_flag := false;
358 write_flag := false;
357 END IF;
359 END IF;
358
360
359 --- check for byte setup with write end, i.e., tBW
361 --- check for byte setup with write end, i.e., tBW
360 IF (NOW - tBBW_chk >= tBW) THEN
362 IF (NOW - tBBW_chk >= tBW) THEN
361 --- tBW OK, do nothing
363 --- tBW OK, do nothing
362 ELSE
364 ELSE
363 IF (TimingInfo) THEN
365 IF (TimingInfo) THEN
364 ASSERT false
366 ASSERT false
365 REPORT "Upper Byte setup tBW violation";
367 REPORT "Upper Byte setup tBW violation";
366 END IF;
368 END IF;
367
369
368 write_flag := false;
370 write_flag := false;
369 END IF;
371 END IF;
370
372
371 --- check for data setup with write end, i.e., tSD
373 --- check for data setup with write end, i.e., tSD
372 IF (NOW - tSD_chk >= tSD_dataskew OR NOW - tSD_chk <= 0.1 ns OR NOW = 0 ns) THEN
374 IF (NOW - tSD_chk >= tSD_dataskew OR NOW - tSD_chk <= 0.1 ns OR NOW = 0 ns) THEN
373 --- tSD OK, do nothing
375 --- tSD OK, do nothing
374 ELSE
376 ELSE
375 IF (TimingInfo) THEN
377 IF (TimingInfo) THEN
376 ASSERT false
378 ASSERT false
377 REPORT "Data setup tSD violation for Upper Byte Write";
379 REPORT "Data setup tSD violation for Upper Byte Write";
378 END IF;
380 END IF;
379
381
380 write_flag := false;
382 write_flag := false;
381 END IF;
383 END IF;
382
384
383 --- perform WRITE operation if no violations
385 --- perform WRITE operation if no violations
384
386
385 IF (write_flag = true) THEN
387 IF (write_flag = true) THEN
386 mem_array(conv_integer1(address_internal))(15 DOWNTO 8) := data_skew(15 DOWNTO 8);
388 mem_array(conv_integer1(address_internal))(15 DOWNTO 8) := data_skew(15 DOWNTO 8);
387 IF (BLE_b = '0') THEN
389 IF (BLE_b = '0') THEN
388 mem_array(conv_integer1(address_internal))(7 DOWNTO 0) := data_skew(7 DOWNTO 0);
390 mem_array(conv_integer1(address_internal))(7 DOWNTO 0) := data_skew(7 DOWNTO 0);
389 END IF;
391 END IF;
390
392
391 END IF;
393 END IF;
392
394
393 --- Reset timing variables
395 --- Reset timing variables
394 tAW_chk := A'LAST_EVENT;
396 tAW_chk := A'LAST_EVENT;
395 tBBW_chk := NOW;
397 tBBW_chk := NOW;
396 write_flag := true;
398 write_flag := true;
397
399
398 END IF;
400 END IF;
399
401
400 END IF;
402 END IF;
401 --- END OF WRITE
403 --- END OF WRITE
402
404
403 IF (data_skew'EVENT AND read_enable /= '1') THEN
405 IF (data_skew'EVENT AND read_enable /= '1') THEN
404 tSD_chk := NOW;
406 tSD_chk := NOW;
405 END IF;
407 END IF;
406
408
407 --- START of READ
409 --- START of READ
408
410
409 --- Tri-state the data bus if CE or OE disabled
411 --- Tri-state the data bus if CE or OE disabled
410 IF (read_enable = '0' AND read_enable'EVENT) THEN
412 IF (read_enable = '0' AND read_enable'EVENT) THEN
411 IF (OE_b'LAST_EVENT >= CE_b'LAST_EVENT) THEN
413 IF (OE_b'LAST_EVENT >= CE_b'LAST_EVENT) THEN
412 DQ <= (OTHERS => 'Z') after tHZCE;
414 DQ <= (OTHERS => 'Z') after tHZCE;
413 ELSIF (CE_b'LAST_EVENT > OE_b'LAST_EVENT) THEN
415 ELSIF (CE_b'LAST_EVENT > OE_b'LAST_EVENT) THEN
414 DQ <= (OTHERS => 'Z') after tHZOE;
416 DQ <= (OTHERS => 'Z') after tHZOE;
415 END IF;
417 END IF;
416 END IF;
418 END IF;
417
419
418 --- Address-controlled READ operation
420 --- Address-controlled READ operation
419 IF (A'EVENT) THEN
421 IF (A'EVENT) THEN
420 IF (A'LAST_EVENT = CE_b'LAST_EVENT AND CE_b = '1') THEN
422 IF (A'LAST_EVENT = CE_b'LAST_EVENT AND CE_b = '1') THEN
421 DQ <= (OTHERS => 'Z') after tHZCE;
423 DQ <= (OTHERS => 'Z') after tHZCE;
422 END IF;
424 END IF;
423
425
424 IF (NOW - tRC_chk >= tRC OR NOW - tRC_chk <= 0.1 ns OR tRC_chk = 0 ns) THEN
426 IF (NOW - tRC_chk >= tRC OR NOW - tRC_chk <= 0.1 ns OR tRC_chk = 0 ns) THEN
425 --- tRC OK, do nothing
427 --- tRC OK, do nothing
426 ELSE
428 ELSE
427
429
428 IF (TimingInfo) THEN
430 IF (TimingInfo) THEN
429 ASSERT false
431 ASSERT false
430 REPORT "Read Cycle time tRC violation";
432 REPORT "Read Cycle time tRC violation";
431 END IF;
433 END IF;
432
434
433 END IF;
435 END IF;
434
436
435 IF (read_enable = '1') THEN
437 IF (read_enable = '1') THEN
436
438
437 IF (BLE_b = '0') THEN
439 IF (BLE_b = '0') THEN
438 DQ (7 DOWNTO 0) <= mem_array (conv_integer1(A))(7 DOWNTO 0) AFTER tAA;
440 DQ (7 DOWNTO 0) <= mem_array (conv_integer1(A))(7 DOWNTO 0) AFTER tAA;
439 END IF;
441 END IF;
440
442
441 IF (BHE_b = '0') THEN
443 IF (BHE_b = '0') THEN
442 DQ (15 DOWNTO 8) <= mem_array (conv_integer1(A))(15 DOWNTO 8) AFTER tAA;
444 DQ (15 DOWNTO 8) <= mem_array (conv_integer1(A))(15 DOWNTO 8) AFTER tAA;
443 END IF;
445 END IF;
444
446
445 tRC_chk := NOW;
447 tRC_chk := NOW;
446
448
447 END IF;
449 END IF;
448
450
449 IF (write_enable = '1') THEN
451 IF (write_enable = '1') THEN
450 --- do nothing
452 --- do nothing
451 END IF;
453 END IF;
452
454
453 END IF;
455 END IF;
454
456
455 IF (read_enable = '0' AND read_enable'EVENT) THEN
457 IF (read_enable = '0' AND read_enable'EVENT) THEN
456 DQ <= (OTHERS => 'Z') after tHZCE;
458 DQ <= (OTHERS => 'Z') after tHZCE;
457 IF (NOW - tRC_chk >= tRC OR tRC_chk = 0 ns OR A'LAST_EVENT = read_enable'LAST_EVENT) THEN
459 IF (NOW - tRC_chk >= tRC OR tRC_chk = 0 ns OR A'LAST_EVENT = read_enable'LAST_EVENT) THEN
458 --- tRC_chk needs to be reset when read ends
460 --- tRC_chk needs to be reset when read ends
459 tRC_CHK := 0 ns;
461 tRC_CHK := 0 ns;
460 ELSE
462 ELSE
461 IF (TimingInfo) THEN
463 IF (TimingInfo) THEN
462 ASSERT false
464 ASSERT false
463 REPORT "Read Cycle time tRC violation";
465 REPORT "Read Cycle time tRC violation";
464 END IF;
466 END IF;
465 tRC_CHK := 0 ns;
467 tRC_CHK := 0 ns;
466 END IF;
468 END IF;
467
469
468 END IF;
470 END IF;
469
471
470 --- READ operation triggered by CE/OE/BHE/BLE
472 --- READ operation triggered by CE/OE/BHE/BLE
471 IF (read_enable = '1' AND read_enable'EVENT) THEN
473 IF (read_enable = '1' AND read_enable'EVENT) THEN
472
474
473 tRC_chk := NOW;
475 tRC_chk := NOW;
474
476
475 --- CE triggered READ
477 --- CE triggered READ
476 IF (CE_b'LAST_EVENT = read_enable'LAST_EVENT) THEN -- changed rev2
478 IF (CE_b'LAST_EVENT = read_enable'LAST_EVENT) THEN -- changed rev2
477
479
478 IF (BLE_b = '0') THEN
480 IF (BLE_b = '0') THEN
479 DQ (7 DOWNTO 0) <= mem_array (conv_integer1(A)) (7 DOWNTO 0) AFTER tACE;
481 DQ (7 DOWNTO 0) <= mem_array (conv_integer1(A)) (7 DOWNTO 0) AFTER tACE;
480 END IF;
482 END IF;
481
483
482 IF (BHE_b = '0') THEN
484 IF (BHE_b = '0') THEN
483 DQ (15 DOWNTO 8) <= mem_array (conv_integer1(A)) (15 DOWNTO 8) AFTER tACE;
485 DQ (15 DOWNTO 8) <= mem_array (conv_integer1(A)) (15 DOWNTO 8) AFTER tACE;
484 END IF;
486 END IF;
485
487
486 END IF;
488 END IF;
487
489
488
490
489 --- OE triggered READ
491 --- OE triggered READ
490 IF (OE_b'LAST_EVENT = read_enable'LAST_EVENT) THEN
492 IF (OE_b'LAST_EVENT = read_enable'LAST_EVENT) THEN
491
493
492 -- if address or CE changes before OE such that tAA/tACE > tDOE
494 -- if address or CE changes before OE such that tAA/tACE > tDOE
493 IF (CE_b'LAST_EVENT < tACE - tDOE AND A'LAST_EVENT < tAA - tDOE) THEN
495 IF (CE_b'LAST_EVENT < tACE - tDOE AND A'LAST_EVENT < tAA - tDOE) THEN
494
496
495 IF (A'LAST_EVENT < CE_b'LAST_EVENT) THEN
497 IF (A'LAST_EVENT < CE_b'LAST_EVENT) THEN
496
498
497 accesstime := tAA-A'LAST_EVENT;
499 accesstime := tAA-A'LAST_EVENT;
498 IF (BLE_b = '0') THEN
500 IF (BLE_b = '0') THEN
499 DQ (7 DOWNTO 0) <= mem_array (conv_integer1(A)) (7 DOWNTO 0) AFTER accesstime;
501 DQ (7 DOWNTO 0) <= mem_array (conv_integer1(A)) (7 DOWNTO 0) AFTER accesstime;
500 END IF;
502 END IF;
501
503
502 IF (BHE_b = '0') THEN
504 IF (BHE_b = '0') THEN
503 DQ (15 DOWNTO 8) <= mem_array (conv_integer1(A)) (15 DOWNTO 8) AFTER accesstime;
505 DQ (15 DOWNTO 8) <= mem_array (conv_integer1(A)) (15 DOWNTO 8) AFTER accesstime;
504 END IF;
506 END IF;
505
507
506 ELSE
508 ELSE
507 accesstime := tACE-CE_b'LAST_EVENT;
509 accesstime := tACE-CE_b'LAST_EVENT;
508 IF (BLE_b = '0') THEN
510 IF (BLE_b = '0') THEN
509 DQ (7 DOWNTO 0) <= mem_array (conv_integer1(A)) (7 DOWNTO 0) AFTER accesstime;
511 DQ (7 DOWNTO 0) <= mem_array (conv_integer1(A)) (7 DOWNTO 0) AFTER accesstime;
510 END IF;
512 END IF;
511
513
512 IF (BHE_b = '0') THEN
514 IF (BHE_b = '0') THEN
513 DQ (15 DOWNTO 8) <= mem_array (conv_integer1(A)) (15 DOWNTO 8) AFTER accesstime;
515 DQ (15 DOWNTO 8) <= mem_array (conv_integer1(A)) (15 DOWNTO 8) AFTER accesstime;
514 END IF;
516 END IF;
515 END IF;
517 END IF;
516
518
517 -- if address changes before OE such that tAA > tDOE
519 -- if address changes before OE such that tAA > tDOE
518 ELSIF (A'LAST_EVENT < tAA - tDOE) THEN
520 ELSIF (A'LAST_EVENT < tAA - tDOE) THEN
519
521
520 accesstime := tAA-A'LAST_EVENT;
522 accesstime := tAA-A'LAST_EVENT;
521 IF (BLE_b = '0') THEN
523 IF (BLE_b = '0') THEN
522 DQ (7 DOWNTO 0) <= mem_array (conv_integer1(A)) (7 DOWNTO 0) AFTER accesstime;
524 DQ (7 DOWNTO 0) <= mem_array (conv_integer1(A)) (7 DOWNTO 0) AFTER accesstime;
523 END IF;
525 END IF;
524
526
525 IF (BHE_b = '0') THEN
527 IF (BHE_b = '0') THEN
526 DQ (15 DOWNTO 8) <= mem_array (conv_integer1(A)) (15 DOWNTO 8) AFTER accesstime;
528 DQ (15 DOWNTO 8) <= mem_array (conv_integer1(A)) (15 DOWNTO 8) AFTER accesstime;
527 END IF;
529 END IF;
528
530
529 -- if CE changes before OE such that tACE > tDOE
531 -- if CE changes before OE such that tACE > tDOE
530 ELSIF (CE_b'LAST_EVENT < tACE - tDOE) THEN
532 ELSIF (CE_b'LAST_EVENT < tACE - tDOE) THEN
531
533
532 accesstime := tACE-CE_b'LAST_EVENT;
534 accesstime := tACE-CE_b'LAST_EVENT;
533 IF (BLE_b = '0') THEN
535 IF (BLE_b = '0') THEN
534 DQ (7 DOWNTO 0) <= mem_array (conv_integer1(A)) (7 DOWNTO 0) AFTER accesstime;
536 DQ (7 DOWNTO 0) <= mem_array (conv_integer1(A)) (7 DOWNTO 0) AFTER accesstime;
535 END IF;
537 END IF;
536
538
537 IF (BHE_b = '0') THEN
539 IF (BHE_b = '0') THEN
538 DQ (15 DOWNTO 8) <= mem_array (conv_integer1(A)) (15 DOWNTO 8) AFTER accesstime;
540 DQ (15 DOWNTO 8) <= mem_array (conv_integer1(A)) (15 DOWNTO 8) AFTER accesstime;
539 END IF;
541 END IF;
540
542
541 -- if OE changes such that tDOE > tAA/tACE
543 -- if OE changes such that tDOE > tAA/tACE
542 ELSE
544 ELSE
543 IF (BLE_b = '0') THEN
545 IF (BLE_b = '0') THEN
544 DQ (7 DOWNTO 0) <= mem_array (conv_integer1(A)) (7 DOWNTO 0) AFTER tDOE;
546 DQ (7 DOWNTO 0) <= mem_array (conv_integer1(A)) (7 DOWNTO 0) AFTER tDOE;
545 END IF;
547 END IF;
546
548
547 IF (BHE_b = '0') THEN
549 IF (BHE_b = '0') THEN
548 DQ (15 DOWNTO 8) <= mem_array (conv_integer1(A)) (15 DOWNTO 8) AFTER tDOE;
550 DQ (15 DOWNTO 8) <= mem_array (conv_integer1(A)) (15 DOWNTO 8) AFTER tDOE;
549 END IF;
551 END IF;
550
552
551 END IF;
553 END IF;
552
554
553 END IF;
555 END IF;
554 --- END of OE triggered READ
556 --- END of OE triggered READ
555
557
556 --- BLE/BHE triggered READ
558 --- BLE/BHE triggered READ
557 IF (BLE_b'LAST_EVENT = read_enable'LAST_EVENT OR BHE_b'LAST_EVENT = read_enable'LAST_EVENT) THEN
559 IF (BLE_b'LAST_EVENT = read_enable'LAST_EVENT OR BHE_b'LAST_EVENT = read_enable'LAST_EVENT) THEN
558
560
559 -- if address or CE changes before BHE/BLE such that tAA/tACE > tDBE
561 -- if address or CE changes before BHE/BLE such that tAA/tACE > tDBE
560 IF (CE_b'LAST_EVENT < tACE - tDBE AND A'LAST_EVENT < tAA - tDBE) THEN
562 IF (CE_b'LAST_EVENT < tACE - tDBE AND A'LAST_EVENT < tAA - tDBE) THEN
561
563
562 IF (A'LAST_EVENT < BLE_b'LAST_EVENT) THEN
564 IF (A'LAST_EVENT < BLE_b'LAST_EVENT) THEN
563 accesstime := tAA-A'LAST_EVENT;
565 accesstime := tAA-A'LAST_EVENT;
564
566
565 IF (BLE_b = '0') THEN
567 IF (BLE_b = '0') THEN
566 DQ (7 DOWNTO 0) <= mem_array (conv_integer1(A)) (7 DOWNTO 0) AFTER accesstime;
568 DQ (7 DOWNTO 0) <= mem_array (conv_integer1(A)) (7 DOWNTO 0) AFTER accesstime;
567 END IF;
569 END IF;
568
570
569 IF (BHE_b = '0') THEN
571 IF (BHE_b = '0') THEN
570 DQ (15 DOWNTO 8) <= mem_array (conv_integer1(A)) (15 DOWNTO 8) AFTER accesstime;
572 DQ (15 DOWNTO 8) <= mem_array (conv_integer1(A)) (15 DOWNTO 8) AFTER accesstime;
571 END IF;
573 END IF;
572
574
573 ELSE
575 ELSE
574 accesstime := tACE-CE_b'LAST_EVENT;
576 accesstime := tACE-CE_b'LAST_EVENT;
575
577
576 IF (BLE_b = '0') THEN
578 IF (BLE_b = '0') THEN
577 DQ (7 DOWNTO 0) <= mem_array (conv_integer1(A)) (7 DOWNTO 0) AFTER accesstime;
579 DQ (7 DOWNTO 0) <= mem_array (conv_integer1(A)) (7 DOWNTO 0) AFTER accesstime;
578 END IF;
580 END IF;
579
581
580 IF (BHE_b = '0') THEN
582 IF (BHE_b = '0') THEN
581 DQ (15 DOWNTO 8) <= mem_array (conv_integer1(A)) (15 DOWNTO 8) AFTER accesstime;
583 DQ (15 DOWNTO 8) <= mem_array (conv_integer1(A)) (15 DOWNTO 8) AFTER accesstime;
582 END IF;
584 END IF;
583 END IF;
585 END IF;
584
586
585 -- if address changes before BHE/BLE such that tAA > tDBE
587 -- if address changes before BHE/BLE such that tAA > tDBE
586 ELSIF (A'LAST_EVENT < tAA - tDBE) THEN
588 ELSIF (A'LAST_EVENT < tAA - tDBE) THEN
587 accesstime := tAA-A'LAST_EVENT;
589 accesstime := tAA-A'LAST_EVENT;
588
590
589 IF (BLE_b = '0') THEN
591 IF (BLE_b = '0') THEN
590 DQ (7 DOWNTO 0) <= mem_array (conv_integer1(A)) (7 DOWNTO 0) AFTER accesstime;
592 DQ (7 DOWNTO 0) <= mem_array (conv_integer1(A)) (7 DOWNTO 0) AFTER accesstime;
591 END IF;
593 END IF;
592
594
593 IF (BHE_b = '0') THEN
595 IF (BHE_b = '0') THEN
594 DQ (15 DOWNTO 8) <= mem_array (conv_integer1(A)) (15 DOWNTO 8) AFTER accesstime;
596 DQ (15 DOWNTO 8) <= mem_array (conv_integer1(A)) (15 DOWNTO 8) AFTER accesstime;
595 END IF;
597 END IF;
596
598
597 -- if CE changes before BHE/BLE such that tACE > tDBE
599 -- if CE changes before BHE/BLE such that tACE > tDBE
598 ELSIF (CE_b'LAST_EVENT < tACE - tDBE) THEN
600 ELSIF (CE_b'LAST_EVENT < tACE - tDBE) THEN
599 accesstime := tACE-CE_b'LAST_EVENT;
601 accesstime := tACE-CE_b'LAST_EVENT;
600
602
601 IF (BLE_b = '0') THEN
603 IF (BLE_b = '0') THEN
602 DQ (7 DOWNTO 0) <= mem_array (conv_integer1(A)) (7 DOWNTO 0) AFTER accesstime;
604 DQ (7 DOWNTO 0) <= mem_array (conv_integer1(A)) (7 DOWNTO 0) AFTER accesstime;
603 END IF;
605 END IF;
604
606
605 IF (BHE_b = '0') THEN
607 IF (BHE_b = '0') THEN
606 DQ (15 DOWNTO 8) <= mem_array (conv_integer1(A)) (15 DOWNTO 8) AFTER accesstime;
608 DQ (15 DOWNTO 8) <= mem_array (conv_integer1(A)) (15 DOWNTO 8) AFTER accesstime;
607 END IF;
609 END IF;
608
610
609 -- if BHE/BLE changes such that tDBE > tAA/tACE
611 -- if BHE/BLE changes such that tDBE > tAA/tACE
610 ELSE
612 ELSE
611 IF (BLE_b = '0') THEN
613 IF (BLE_b = '0') THEN
612 DQ (7 DOWNTO 0) <= mem_array (conv_integer1(A)) (7 DOWNTO 0) AFTER tDBE;
614 DQ (7 DOWNTO 0) <= mem_array (conv_integer1(A)) (7 DOWNTO 0) AFTER tDBE;
613 END IF;
615 END IF;
614
616
615 IF (BHE_b = '0') THEN
617 IF (BHE_b = '0') THEN
616 DQ (15 DOWNTO 8) <= mem_array (conv_integer1(A)) (15 DOWNTO 8) AFTER tDBE;
618 DQ (15 DOWNTO 8) <= mem_array (conv_integer1(A)) (15 DOWNTO 8) AFTER tDBE;
617 END IF;
619 END IF;
618
620
619 END IF;
621 END IF;
620
622
621 END IF;
623 END IF;
622 -- END of BHE/BLE controlled READ
624 -- END of BHE/BLE controlled READ
623
625
624 IF (WE_b'LAST_EVENT = read_enable'LAST_EVENT) THEN
626 IF (WE_b'LAST_EVENT = read_enable'LAST_EVENT) THEN
625
627
626 IF (BLE_b = '0') THEN
628 IF (BLE_b = '0') THEN
627 DQ (7 DOWNTO 0) <= mem_array (conv_integer1(A)) (7 DOWNTO 0) AFTER tACE;
629 DQ (7 DOWNTO 0) <= mem_array (conv_integer1(A)) (7 DOWNTO 0) AFTER tACE;
628 END IF;
630 END IF;
629
631
630 IF (BHE_b = '0') THEN
632 IF (BHE_b = '0') THEN
631 DQ (15 DOWNTO 8) <= mem_array (conv_integer1(A)) (15 DOWNTO 8) AFTER tACE;
633 DQ (15 DOWNTO 8) <= mem_array (conv_integer1(A)) (15 DOWNTO 8) AFTER tACE;
632 END IF;
634 END IF;
633
635
634 END IF;
636 END IF;
635
637
636 END IF;
638 END IF;
637 --- END OF CE/OE/BHE/BLE controlled READ
639 --- END OF CE/OE/BHE/BLE controlled READ
638
640
639 --- If either BHE or BLE toggle during read mode
641 --- If either BHE or BLE toggle during read mode
640 IF (BLE_b'EVENT AND BLE_b = '0' AND read_enable = '1' AND NOT(read_enable'EVENT)) THEN
642 IF (BLE_b'EVENT AND BLE_b = '0' AND read_enable = '1' AND NOT(read_enable'EVENT)) THEN
641 DQ (7 DOWNTO 0) <= mem_array (conv_integer1(A)) (7 DOWNTO 0) AFTER tDBE;
643 DQ (7 DOWNTO 0) <= mem_array (conv_integer1(A)) (7 DOWNTO 0) AFTER tDBE;
642 END IF;
644 END IF;
643
645
644 IF (BHE_b'EVENT AND BHE_b = '0' AND read_enable = '1' AND NOT(read_enable'EVENT)) THEN
646 IF (BHE_b'EVENT AND BHE_b = '0' AND read_enable = '1' AND NOT(read_enable'EVENT)) THEN
645 DQ (15 DOWNTO 8) <= mem_array (conv_integer1(A)) (15 DOWNTO 8) AFTER tDBE;
647 DQ (15 DOWNTO 8) <= mem_array (conv_integer1(A)) (15 DOWNTO 8) AFTER tDBE;
646 END IF;
648 END IF;
647
649
648 --- tri-state bus depending on BHE/BLE
650 --- tri-state bus depending on BHE/BLE
649 IF (BLE_b'EVENT AND BLE_b = '1') THEN
651 IF (BLE_b'EVENT AND BLE_b = '1') THEN
650 DQ (7 DOWNTO 0) <= (OTHERS => 'Z') after tHZBE;
652 DQ (7 DOWNTO 0) <= (OTHERS => 'Z') after tHZBE;
651 END IF;
653 END IF;
652
654
653 IF (BHE_b'EVENT AND BHE_b = '1') THEN
655 IF (BHE_b'EVENT AND BHE_b = '1') THEN
654 DQ (15 DOWNTO 8) <= (OTHERS => 'Z') after tHZBE;
656 DQ (15 DOWNTO 8) <= (OTHERS => 'Z') after tHZBE;
655 END IF;
657 END IF;
656
658
657 WAIT ON write_enable, A, read_enable, DQ, BLE_b, BHE_b, data_skew, address_skew;
659 WAIT ON write_enable, A, read_enable, DQ, BLE_b, BHE_b, data_skew, address_skew;
658
660
659 END PROCESS;
661 END PROCESS;
660
662
661
663
662 END behave_arch;
664 END behave_arch;
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