# HG changeset patch # User pellion # Date 2014-02-20 15:57:20 # Node ID 6b992ec40bf9469247ed098bdd6f86a8a9df5482 # Parent 4ac4e8530e16ade44faea08e38c868b07fd50b6a [WFP] Register the DMA "send" signal to permit the start of 2 burst consecutively. diff --git a/designs/LFR_simu/run_tb_waveform.do b/designs/LFR_simu/run_tb_waveform.do --- a/designs/LFR_simu/run_tb_waveform.do +++ b/designs/LFR_simu/run_tb_waveform.do @@ -20,4 +20,4 @@ log -r * do wave_waveform_longsim.do -run 500 ms +run 40 ms diff --git a/designs/LFR_simu/tb_waveform.vhd b/designs/LFR_simu/tb_waveform.vhd --- a/designs/LFR_simu/tb_waveform.vhd +++ b/designs/LFR_simu/tb_waveform.vhd @@ -19,6 +19,7 @@ USE ieee.std_logic_1164.ALL; LIBRARY grlib; USE grlib.amba.ALL; USE grlib.stdlib.ALL; +USE grlib.AMBA_TestPackage.ALL; LIBRARY gaisler; USE gaisler.memctrl.ALL; USE gaisler.leon3.ALL; @@ -224,7 +225,7 @@ ARCHITECTURE behav OF testbench IS ----------------------------------------------------------------------------- SIGNAL current_data : INTEGER; - SIGNAL LIMIT_DATA : INTEGER := 194; + SIGNAL LIMIT_DATA : INTEGER := 64; SIGNAL read_buffer_temp : STD_LOGIC; SIGNAL read_buffer_temp_2 : STD_LOGIC; @@ -367,6 +368,7 @@ BEGIN ADDR_BITS => 20, DATA_BITS => 16, depth => 1048576, + MEM_ARRAY_DEBUG => 194, TimingInfo => TRUE, TimingChecks => '1') PORT MAP ( @@ -384,6 +386,7 @@ BEGIN ADDR_BITS => 20, DATA_BITS => 16, depth => 1048576, + MEM_ARRAY_DEBUG => 194, TimingInfo => TRUE, TimingChecks => '1') PORT MAP ( @@ -430,16 +433,26 @@ BEGIN APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F2 , X"40040000"); APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F3 , X"40060000"); - APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_DELTASNAPSHOT, X"00000080");--"00000020" - APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_DELTA_F0 , X"00000060");--"00000019" - APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_DELTA_F0_2 , X"00000007");--"00000007" - APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_DELTA_F1 , X"00000062");--"00000019" - APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_DELTA_F2 , X"00000001");--"00000001" - + APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_DELTASNAPSHOT , X"00000080");--"00000020" + APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_DELTA_F0 , X"00000060");--"00000019" + APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_DELTA_F0_2 , X"00000007");--"00000007" + APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_DELTA_F1 , X"00000062");--"00000019" + APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_DELTA_F2 , X"00000001");--"00000001" APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_NB_DATA_IN_BUFFER , X"0000003f"); -- X"00000010" APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_NBSNAPSHOT , X"00000040"); APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_START_DATE , X"00000001"); - APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_NB_WORD_IN_BUFFER , X"000000c2"); + APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_NB_WORD_IN_BUFFER , X"000000C2");-- 0xC2 = 64 * 3 + 2 + + --APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_DELTASNAPSHOT , X"00000010");--"00000020" + --APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_DELTA_F0 , X"0000000C");--"00000019" + --APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_DELTA_F0_2 , X"00000007");--"00000007" + --APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_DELTA_F1 , X"0000000C");--"00000019" + --APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_DELTA_F2 , X"00000001");--"00000001" + --APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_NB_DATA_IN_BUFFER , X"00000007"); -- X"00000010" + --APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_NBSNAPSHOT , X"00000008"); + --APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_START_DATE , X"00000001"); + --APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_NB_WORD_IN_BUFFER , X"0000001A");-- 0xC2 = 8 * 3 + 2 + WAIT UNTIL clk25MHz = '1'; @@ -525,6 +538,20 @@ BEGIN WAIT UNTIL clk25MHz = '1'; IF read_buffer = '1' THEN state_read_buffer_on_going <= '1'; + + --AHBRead(X"40000000",time_mem_f0(31 DOWNTO 0),clk25MHz, + --constant Address: in Std_Logic_Vector(31 downto 0); + --variable Data: out Std_Logic_Vector(31 downto 0); + --signal HCLK: in Std_ULogic; + + --signal AHBIn: out AHB_Slv_In_Type; + --signal AHBOut: in AHB_Slv_Out_Type; + --variable TP: inout Boolean; + --constant InstancePath: in String := "AHBRead"; + --constant ScreenOutput: in Boolean := False; + --constant cBack2Back: in Boolean := False; + --constant HINDEX: in Integer := 0; + --constant HMBINDEX: in Integer := 0); AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40000000", time_mem_f0(31 DOWNTO 0)); AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40020000", time_mem_f1(31 DOWNTO 0)); @@ -534,44 +561,42 @@ BEGIN AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40020004", time_mem_f1(63 DOWNTO 32)); AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40040004", time_mem_f2(63 DOWNTO 32)); - current_data <= 8; + current_data <= 0; ELSE IF state_read_buffer_on_going = '1' THEN -- READ ALL DATA in memory - AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40000000" + current_data, data_mem_f0); - AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40020000" + current_data, data_mem_f1); - AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40040000" + current_data, data_mem_f2); + AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40000000" + (current_data * 12) + 8, data_mem_f0); + AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40020000" + (current_data * 12) + 8, data_mem_f1); + AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40040000" + (current_data * 12) + 8, data_mem_f2); data_0_f0 <= data_mem_f0(15 DOWNTO 0); data_1_f0 <= data_mem_f0(31 DOWNTO 16); data_0_f1 <= data_mem_f1(15 DOWNTO 0); data_1_f1 <= data_mem_f1(31 DOWNTO 16); data_0_f2 <= data_mem_f2(15 DOWNTO 0); data_1_f2 <= data_mem_f2(31 DOWNTO 16); - current_data <= current_data + 4; - AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40000000" + current_data, data_mem_f0); - AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40020000" + current_data, data_mem_f1); - AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40040000" + current_data, data_mem_f2); + AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40000000" + (current_data * 12) + 4 + 8, data_mem_f0); + AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40020000" + (current_data * 12) + 4 + 8, data_mem_f1); + AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40040000" + (current_data * 12) + 4 + 8, data_mem_f2); data_2_f0 <= data_mem_f0(15 DOWNTO 0); data_3_f0 <= data_mem_f0(31 DOWNTO 16); data_2_f1 <= data_mem_f1(15 DOWNTO 0); data_3_f1 <= data_mem_f1(31 DOWNTO 16); data_2_f2 <= data_mem_f2(15 DOWNTO 0); data_3_f2 <= data_mem_f2(31 DOWNTO 16); - current_data <= current_data + 4; - AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40000000" + current_data, data_mem_f0); - AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40020000" + current_data, data_mem_f1); - AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40040000" + current_data, data_mem_f2); + AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40000000" + (current_data * 12) + 8 + 8, data_mem_f0); + AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40020000" + (current_data * 12) + 8 + 8, data_mem_f1); + AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40040000" + (current_data * 12) + 8 + 8, data_mem_f2); data_4_f0 <= data_mem_f0(15 DOWNTO 0); data_5_f0 <= data_mem_f0(31 DOWNTO 16); data_4_f1 <= data_mem_f1(15 DOWNTO 0); data_5_f1 <= data_mem_f1(31 DOWNTO 16); data_4_f2 <= data_mem_f2(15 DOWNTO 0); data_5_f2 <= data_mem_f2(31 DOWNTO 16); - current_data <= current_data + 4; + current_data <= current_data + 1; - IF current_data > LIMIT_DATA THEN + IF current_data >= LIMIT_DATA THEN state_read_buffer_on_going <= '0'; time_mem_f0 <= (OTHERS => '0'); time_mem_f1 <= (OTHERS => '0'); diff --git a/designs/LFR_simu/testbench_package.vhd b/designs/LFR_simu/testbench_package.vhd --- a/designs/LFR_simu/testbench_package.vhd +++ b/designs/LFR_simu/testbench_package.vhd @@ -1,120 +1,136 @@ - -LIBRARY ieee; -USE ieee.std_logic_1164.ALL; -LIBRARY grlib; -USE grlib.amba.ALL; -USE grlib.stdlib.ALL; ---LIBRARY gaisler; ---USE gaisler.libdcom.ALL; ---USE gaisler.sim.ALL; ---USE gaisler.jtagtst.ALL; ---LIBRARY techmap; ---USE techmap.gencomp.ALL; - - -PACKAGE testbench_package IS - - PROCEDURE APB_WRITE ( - SIGNAL clk : IN STD_LOGIC; - CONSTANT pindex : IN INTEGER; - SIGNAL apbi : OUT apb_slv_in_type; - CONSTANT paddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - CONSTANT pwdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0) - ); - - PROCEDURE APB_READ ( - SIGNAL clk : IN STD_LOGIC; - CONSTANT pindex : IN INTEGER; - SIGNAL apbi : OUT apb_slv_in_type; - SIGNAL apbo : IN apb_slv_out_type; - CONSTANT paddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - SIGNAL prdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) - ); - - PROCEDURE AHB_READ ( - SIGNAL clk : IN STD_LOGIC; - CONSTANT hindex : IN INTEGER; - SIGNAL ahbmi : IN ahb_mst_in_type; - SIGNAL ahbmo : OUT ahb_mst_out_type; - CONSTANT haddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - SIGNAL hrdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) - ); - -END testbench_package; - -PACKAGE BODY testbench_package IS - - PROCEDURE APB_WRITE ( - SIGNAL clk : IN STD_LOGIC; - CONSTANT pindex : IN INTEGER; - SIGNAL apbi : OUT apb_slv_in_type; - CONSTANT paddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - CONSTANT pwdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0) - ) IS - BEGIN - apbi.psel(pindex) <= '1'; - apbi.pwrite <= '1'; - apbi.penable <= '1'; - apbi.paddr <= paddr; - apbi.pwdata <= pwdata; - WAIT UNTIL clk = '1'; - apbi.psel(pindex) <= '0'; - apbi.pwrite <= '0'; - apbi.penable <= '0'; - apbi.paddr <= (OTHERS => '0'); - apbi.pwdata <= (OTHERS => '0'); - WAIT UNTIL clk = '1'; - - END APB_WRITE; - - PROCEDURE APB_READ ( - SIGNAL clk : IN STD_LOGIC; - CONSTANT pindex : IN INTEGER; - SIGNAL apbi : OUT apb_slv_in_type; - SIGNAL apbo : IN apb_slv_out_type; - CONSTANT paddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - SIGNAL prdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) - ) IS - BEGIN - apbi.psel(pindex) <= '1'; - apbi.pwrite <= '0'; - apbi.penable <= '1'; - apbi.paddr <= paddr; - WAIT UNTIL clk = '1'; - apbi.psel(pindex) <= '0'; - apbi.pwrite <= '0'; - apbi.penable <= '0'; - apbi.paddr <= (OTHERS => '0'); - WAIT UNTIL clk = '1'; - prdata <= apbo.prdata; - END APB_READ; - - PROCEDURE AHB_READ ( - SIGNAL clk : IN STD_LOGIC; - CONSTANT hindex : IN INTEGER; - SIGNAL ahbmi : IN ahb_mst_in_type; - SIGNAL ahbmo : OUT ahb_mst_out_type; - CONSTANT haddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - SIGNAL hrdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) - ) IS - BEGIN - ahbmo.HADDR <= haddr; - ahbmo.HPROT <= "0011"; - ahbmo.HIRQ <= (OTHERS => '0'); - ahbmo.HCONFIG <= (0 => (OTHERS => '0'), OTHERS => (OTHERS => '0')); - ahbmo.HINDEX <= hindex; - ahbmo.HBUSREQ <= '1'; - ahbmo.HLOCK <= '1'; - ahbmo.HSIZE <= HSIZE_WORD; - ahbmo.HBURST <= HBURST_SINGLE; - ahbmo.HTRANS <= HTRANS_NONSEQ; - ahbmo.HWRITE <= '0'; - WAIT UNTIL clk = '1' AND ahbmi.HREADY = '1' AND ahbmi.HGRANT(hindex) = '1'; - hrdata <= ahbmi.HRDATA; - WAIT UNTIL clk = '1' AND ahbmi.HREADY = '1' AND ahbmi.HGRANT(hindex) = '1'; - ahbmo.HTRANS <= HTRANS_IDLE; - ahbmo.HBUSREQ <= '0'; - ahbmo.HLOCK <= '0'; - END AHB_READ; - -END testbench_package; + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +LIBRARY grlib; +USE grlib.amba.ALL; +USE grlib.stdlib.ALL; +--LIBRARY gaisler; +--USE gaisler.libdcom.ALL; +--USE gaisler.sim.ALL; +--USE gaisler.jtagtst.ALL; +--LIBRARY techmap; +--USE techmap.gencomp.ALL; + + +PACKAGE testbench_package IS + + PROCEDURE APB_WRITE ( + SIGNAL clk : IN STD_LOGIC; + CONSTANT pindex : IN INTEGER; + SIGNAL apbi : OUT apb_slv_in_type; + CONSTANT paddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + CONSTANT pwdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0) + ); + + PROCEDURE APB_READ ( + SIGNAL clk : IN STD_LOGIC; + CONSTANT pindex : IN INTEGER; + SIGNAL apbi : OUT apb_slv_in_type; + SIGNAL apbo : IN apb_slv_out_type; + CONSTANT paddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL prdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) + ); + + PROCEDURE AHB_READ ( + SIGNAL clk : IN STD_LOGIC; + CONSTANT hindex : IN INTEGER; + SIGNAL ahbmi : IN ahb_mst_in_type; + SIGNAL ahbmo : OUT ahb_mst_out_type; + CONSTANT haddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL hrdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) + ); + +END testbench_package; + +PACKAGE BODY testbench_package IS + + PROCEDURE APB_WRITE ( + SIGNAL clk : IN STD_LOGIC; + CONSTANT pindex : IN INTEGER; + SIGNAL apbi : OUT apb_slv_in_type; + CONSTANT paddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + CONSTANT pwdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0) + ) IS + BEGIN + apbi.psel(pindex) <= '1'; + apbi.pwrite <= '1'; + apbi.penable <= '1'; + apbi.paddr <= paddr; + apbi.pwdata <= pwdata; + WAIT UNTIL clk = '0'; + WAIT UNTIL clk = '1'; + apbi.psel(pindex) <= '0'; + apbi.pwrite <= '0'; + apbi.penable <= '0'; + apbi.paddr <= (OTHERS => '0'); + apbi.pwdata <= (OTHERS => '0'); + WAIT UNTIL clk = '0'; + WAIT UNTIL clk = '1'; + + END APB_WRITE; + + PROCEDURE APB_READ ( + SIGNAL clk : IN STD_LOGIC; + CONSTANT pindex : IN INTEGER; + SIGNAL apbi : OUT apb_slv_in_type; + SIGNAL apbo : IN apb_slv_out_type; + CONSTANT paddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL prdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) + ) IS + BEGIN + apbi.psel(pindex) <= '1'; + apbi.pwrite <= '0'; + apbi.penable <= '1'; + apbi.paddr <= paddr; + WAIT UNTIL clk = '0'; + WAIT UNTIL clk = '1'; + apbi.psel(pindex) <= '0'; + apbi.pwrite <= '0'; + apbi.penable <= '0'; + apbi.paddr <= (OTHERS => '0'); + WAIT UNTIL clk = '0'; + WAIT UNTIL clk = '1'; + prdata <= apbo.prdata; + END APB_READ; + + PROCEDURE AHB_READ ( + SIGNAL clk : IN STD_LOGIC; + CONSTANT hindex : IN INTEGER; + SIGNAL ahbmi : IN ahb_mst_in_type; + SIGNAL ahbmo : OUT ahb_mst_out_type; + CONSTANT haddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL hrdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) + ) IS + BEGIN + WAIT UNTIL clk = '1'; + ahbmo.HADDR <= haddr; + ahbmo.HPROT <= "0011"; + ahbmo.HIRQ <= (OTHERS => '0'); + ahbmo.HCONFIG <= (0 => (OTHERS => '0'), OTHERS => (OTHERS => '0')); + ahbmo.HINDEX <= hindex; + ahbmo.HBUSREQ <= '1'; + ahbmo.HLOCK <= '1'; + ahbmo.HSIZE <= HSIZE_WORD; + ahbmo.HBURST <= HBURST_SINGLE; + ahbmo.HTRANS <= HTRANS_NONSEQ; + ahbmo.HWRITE <= '0'; + WHILE ahbmi.HREADY = '0' LOOP + WAIT UNTIL clk = '1'; + END LOOP; + WAIT UNTIL clk = '1'; + --WAIT UNTIL clk = '1' AND ahbmi.HREADY = '1' AND ahbmi.HGRANT(hindex) = '1'; + ahbmo.HBUSREQ <= '0'; + ahbmo.HLOCK <= '0'; + ahbmo.HTRANS <= HTRANS_IDLE; + WHILE ahbmi.HREADY = '0' LOOP + WAIT UNTIL clk = '1'; + END LOOP; + WAIT UNTIL clk = '1'; + hrdata <= ahbmi.HRDATA; + --WAIT UNTIL clk = '1' AND ahbmi.HREADY = '1' AND ahbmi.HGRANT(hindex) = '1'; + ahbmo.HLOCK <= '0'; + WAIT UNTIL clk = '1'; + + END AHB_READ; + +END testbench_package; diff --git a/designs/MINI-LFR_waveformPicker/MINI_LFR_top.vhd b/designs/MINI-LFR_waveformPicker/MINI_LFR_top.vhd --- a/designs/MINI-LFR_waveformPicker/MINI_LFR_top.vhd +++ b/designs/MINI-LFR_waveformPicker/MINI_LFR_top.vhd @@ -425,7 +425,7 @@ BEGIN -- beh pirq_ms => 6, pirq_wfp => 14, hindex => 2, - top_lfr_version => X"00000F") -- aa.bb.cc version + top_lfr_version => X"000010") -- aa.bb.cc version PORT MAP ( clk => clk_25, rstn => reset, diff --git a/lib/lpp/lpp_dma/lpp_dma_singleOrBurst.vhd b/lib/lpp/lpp_dma/lpp_dma_singleOrBurst.vhd --- a/lib/lpp/lpp_dma/lpp_dma_singleOrBurst.vhd +++ b/lib/lpp/lpp_dma/lpp_dma_singleOrBurst.vhd @@ -95,6 +95,13 @@ ARCHITECTURE Behavioral OF lpp_dma_singl SIGNAL burst_ren : STD_LOGIC; ----------------------------------------------------------------------------- SIGNAL data_2_halfword : STD_LOGIC_VECTOR(31 DOWNTO 0); + ----------------------------------------------------------------------------- + -- \/ -- 20/02/2014 -- JC Pellion + SIGNAL send_reg : STD_LOGIC; + SIGNAL send_s : STD_LOGIC; + -- /\ -- + + BEGIN debug_dmaout_okay <= DMAOut.OKAY; @@ -121,14 +128,21 @@ BEGIN ----------------------------------------------------------------------------- ----------------------------------------------------------------------------- - ----------------------------------------------------------------------------- - -- LE PROBLEME EST LA !!!!! - ----------------------------------------------------------------------------- - ----------------------------------------------------------------------------- - -- C'est le signal valid_burst qui n'est pas assez long. - ----------------------------------------------------------------------------- - single_send <= send WHEN valid_burst = '0' ELSE '0'; - burst_send <= send WHEN valid_burst = '1' ELSE '0'; + -- \/ -- 20/02/2014 -- JC Pellion + PROCESS (HCLK, HRESETn) + BEGIN + IF HRESETn = '0' THEN + send_reg <= '0'; + ELSIF HCLK'event AND HCLK = '1' THEN + send_reg <= send; + END IF; + END PROCESS; + send_s <= send_reg; + + single_send <= send_s WHEN valid_burst = '0' ELSE '0'; + burst_send <= send_s WHEN valid_burst = '1' ELSE '0'; + -- /\ -- + DMAIn <= single_dmai WHEN valid_burst = '0' ELSE burst_dmai; -- TODO : verifier diff --git a/lib/lpp/lpp_sim/CY7C1061DV33/CY7C1061DV33.vhd b/lib/lpp/lpp_sim/CY7C1061DV33/CY7C1061DV33.vhd --- a/lib/lpp/lpp_sim/CY7C1061DV33/CY7C1061DV33.vhd +++ b/lib/lpp/lpp_sim/CY7C1061DV33/CY7C1061DV33.vhd @@ -29,6 +29,8 @@ ENTITY CY7C1061DV33 IS DATA_BITS : INTEGER := 16; depth : INTEGER := 1048576; + MEM_ARRAY_DEBUG : INTEGER := 32; + TimingInfo : BOOLEAN := true; TimingChecks : STD_LOGIC := '1' ); @@ -68,7 +70,7 @@ ARCHITECTURE behave_arch OF CY7C1061DV33 CONSTANT tskew : TIME := 1 ns; -------------------------------------------------------------------------------JC\/ - TYPE mem_array_type_t IS ARRAY (31 DOWNTO 0) OF STD_LOGIC_VECTOR(DATA_BITS-1 DOWNTO 0); + TYPE mem_array_type_t IS ARRAY (MEM_ARRAY_DEBUG-1 DOWNTO 0) OF STD_LOGIC_VECTOR(DATA_BITS-1 DOWNTO 0); SIGNAL mem_array_0 : mem_array_type_t; SIGNAL mem_array_1 : mem_array_type_t; SIGNAL mem_array_2 : mem_array_type_t; @@ -236,7 +238,7 @@ BEGIN -------------------------------------------------------------------------------JC\/ - all_mem_array_obs: FOR I IN 0 TO 31 LOOP + all_mem_array_obs: FOR I IN 0 TO MEM_ARRAY_DEBUG-1 LOOP IF I + ((2**15) *0) < depth THEN mem_array_0(I) <= mem_array(I+((2**15) *0)); END IF; IF I + ((2**15) *1) < depth THEN mem_array_1(I) <= mem_array(I+((2**15) *1)); END IF; IF I + ((2**15) *2) < depth THEN mem_array_2(I) <= mem_array(I+((2**15) *2)); END IF;