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EQM debug
pellion -
r569:64f72d322da8 JC
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@@ -3,10 +3,13
3 3 # Clocks
4 4
5 5 create_clock -period 20.000000 -waveform {0.000000 10.000000} clk50MHz
6 create_clock -period 40.000000 -waveform {0.000000 20.000000} clk_25
7
8 #create_generated_clock -name{clk_domain_25} -divide_by 2 -source{clk_25_int:CLK}{clk_25_int:Q}
9
6 10 #create_clock -period 20.344999 -waveform {0.000000 10.172500} clk49_152MHz
7 #create_clock -period 40.000000 -waveform {0.000000 20.000000} clk_25_int:Q
8 11 #create_clock -period 40.690000 -waveform {0.000000 20.345100} clk_24:Q
9 create_clock -name SPW_CLOCK -period 100.000000 -waveform {0.000000 50.000000} {spw1_din spw1_sin spw2_din spw2_sin}
12 #create_clock -name SPW_CLOCK -period 100.000000 -waveform {0.000000 50.000000} {spw1_din spw1_sin spw2_din spw2_sin}
10 13
11 14
12 15 # False Paths Between Clocks
@@ -17,7 +20,6 create_clock -name SPW_CLOCK -period 100
17 20
18 21 # Maximum Delay Constraints
19 22
20
21 23 # Multicycle Constraints
22 24
23 25
@@ -28,3 +30,10 create_clock -name SPW_CLOCK -period 100
28 30 # set_wire_load_mode top
29 31
30 32 # Other Constraints
33
34
35 ## GRSPW constraints
36 create_clock -period 100.00 {spw_inputloop.1.spw_phy0/rxclki_RNO:Y}
37 create_clock -period 100.00 {spw_inputloop.0.spw_phy0/rxclki_RNO:Y}
38 set_max_delay 4.00 -from [all_inputs] -to [get_clocks spw_inputloop.0.spw_phy0/rxclki_RNO:Y]
39 set_max_delay 4.00 -from [all_inputs] -to [get_clocks spw_inputloop.1.spw_phy0/rxclki_RNO:Y]
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@@ -3,10 +3,13
3 3 # Clocks
4 4
5 5 create_clock -period 20.000000 -waveform {0.000000 10.000000} clk50MHz
6 create_clock -period 40.000000 -waveform {0.000000 20.000000} clk_25:Q
7
8 #create_generated_clock -name{clk_domain_25} -divide_by 2 -source{clk_25_int:CLK}{clk_25_int:Q}
9
6 10 create_clock -period 20.344999 -waveform {0.000000 10.172500} clk49_152MHz
7 create_clock -period 40.000000 -waveform {0.000000 20.000000} clk_25:Q
8 11 create_clock -period 40.690000 -waveform {0.000000 20.345100} clk_24:Q
9 create_clock -name SPW_CLOCK -period 100.000000 -waveform {0.000000 50.000000} {spw1_din spw1_sin spw2_din spw2_sin}
12 #create_clock -name SPW_CLOCK -period 100.000000 -waveform {0.000000 50.000000} {spw1_din spw1_sin spw2_din spw2_sin}
10 13
11 14
12 15 # False Paths Between Clocks
@@ -17,7 +20,6 create_clock -name SPW_CLOCK -period 100
17 20
18 21 # Maximum Delay Constraints
19 22
20
21 23 # Multicycle Constraints
22 24
23 25
@@ -28,3 +30,10 create_clock -name SPW_CLOCK -period 100
28 30 # set_wire_load_mode top
29 31
30 32 # Other Constraints
33
34
35 ## GRSPW constraints
36 create_clock -period 100.00 {spw_inputloop.1.spw_phy0/rxclki_RNO:Y}
37 create_clock -period 100.00 {spw_inputloop.0.spw_phy0/rxclki_RNO:Y}
38 set_max_delay 4.00 -from [all_inputs] -to [get_clocks spw_inputloop.0.spw_phy0/rxclki_RNO:Y]
39 set_max_delay 4.00 -from [all_inputs] -to [get_clocks spw_inputloop.1.spw_phy0/rxclki_RNO:Y]
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@@ -2,9 +2,9 PACKAGE=\"\"
2 2 SPEED=Std
3 3 SYNFREQ=50
4 4
5 TECHNOLOGY=ProASIC3E
6 LIBERO_DIE=IT14X14M4
7 PART=A3PE3000
5 TECHNOLOGY=ProASIC3L
6 LIBERO_DIE=A3PE3000L
7 PART=A3PE3000L
8 8
9 9 DESIGNER_VOLTAGE=COM
10 10 DESIGNER_TEMP=COM
@@ -12,8 +12,9 DESIGNER_PACKAGE=FBGA
12 12 DESIGNER_PINS=324
13 13
14 14 MANUFACTURER=Actel
15 MGCTECHNOLOGY=Proasic3
15 MGCTECHNOLOGY=ProASIC3L
16 16 MGCPART=$(PART)
17 17 MGCPACKAGE= {$(DESIGNER_PINS) $(DESIGNER_PACKAGE)}
18 18 LIBERO_PACKAGE=fg$(DESIGNER_PINS)
19 19
20
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@@ -45,8 +45,8 USE lpp.general_purpose.ALL;
45 45 USE lpp.lpp_lfr_management.ALL;
46 46 USE lpp.lpp_leon3_soc_pkg.ALL;
47 47
48 library proasic3e;
49 use proasic3e.clkint;
48 library proasic3l;
49 use proasic3l.all;
50 50
51 51 ENTITY LFR_EQM IS
52 52
@@ -160,6 +160,7 ARCHITECTURE beh OF LFR_EQM IS
160 160 SIGNAL nSRAM_CE : STD_LOGIC_VECTOR(1 DOWNTO 0);
161 161
162 162 SIGNAL clk50MHz_int : STD_LOGIC := '0';
163 SIGNAL clk_25_int : STD_LOGIC := '0';
163 164
164 165 component clkint port(A : in std_ulogic; Y :out std_ulogic); end component;
165 166
@@ -171,14 +172,17 BEGIN -- beh
171 172 rst_domain25 : rstgen PORT MAP (reset, clk_25, '1', rstn_25, OPEN);
172 173 rst_domain24 : rstgen PORT MAP (reset, clk_24, '1', rstn_24, OPEN);
173 174
174 clk_pad : clkint port map (A => clk50MHz, Y => clk50MHz_int );
175 --clk_pad : clkint port map (A => clk50MHz, Y => clk50MHz_int );
176 clk50MHz_int <= clk50MHz;
175 177
176 178 PROCESS(clk50MHz_int)
177 179 BEGIN
178 180 IF clk50MHz_int'EVENT AND clk50MHz_int = '1' THEN
181 --clk_25_int <= NOT clk_25_int;
179 182 clk_25 <= NOT clk_25;
180 183 END IF;
181 184 END PROCESS;
185 --clk_pad_25 : clkint port map (A => clk_25_int, Y => clk_25 );
182 186
183 187 PROCESS(clk49_152MHz)
184 188 BEGIN
@@ -371,7 +375,7 BEGIN -- beh
371 375
372 376 swni.tickin <= '0';
373 377 swni.rmapen <= '1';
374 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
378 swni.clkdiv10 <= "00000100"; -- 50 MHz / (4 + 1) = 10 MHz
375 379 swni.tickinraw <= '0';
376 380 swni.timein <= (OTHERS => '0');
377 381 swni.dcrstval <= (OTHERS => '0');
@@ -451,7 +455,7 BEGIN -- beh
451 455 ADC_smpclk <= ADC_smpclk_s;
452 456 HK_smpclk <= ADC_smpclk_s;
453 457
454 TAG8 <='0';
458 TAG8 <= nSRAM_BUSY;
455 459
456 460 -----------------------------------------------------------------------------
457 461 -- HK
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@@ -416,8 +416,8 BEGIN
416 416 rmw => 1,
417 417 --Aeroflex memory generics:
418 418 mprog => 1, -- program memory by default values after reset
419 mpsrate => 12, -- default scrub rate period
420 mpb2s => 4, -- default busy to scrub delay
419 mpsrate => 15, -- default scrub rate period
420 mpb2s => 14, -- default busy to scrub delay
421 421 mpapb => 1, -- instantiate apb register
422 422 mchipcnt => 2,
423 423 mpenall => 1 -- when 0 program only E1 chip, else program all dies
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