diff --git a/boards/LFR-EQM/LFR_EQM_place_and_route-debug.sdc b/boards/LFR-EQM/LFR_EQM_place_and_route-debug.sdc --- a/boards/LFR-EQM/LFR_EQM_place_and_route-debug.sdc +++ b/boards/LFR-EQM/LFR_EQM_place_and_route-debug.sdc @@ -3,10 +3,13 @@ # Clocks create_clock -period 20.000000 -waveform {0.000000 10.000000} clk50MHz +create_clock -period 40.000000 -waveform {0.000000 20.000000} clk_25 + +#create_generated_clock -name{clk_domain_25} -divide_by 2 -source{clk_25_int:CLK}{clk_25_int:Q} + #create_clock -period 20.344999 -waveform {0.000000 10.172500} clk49_152MHz -#create_clock -period 40.000000 -waveform {0.000000 20.000000} clk_25_int:Q #create_clock -period 40.690000 -waveform {0.000000 20.345100} clk_24:Q -create_clock -name SPW_CLOCK -period 100.000000 -waveform {0.000000 50.000000} {spw1_din spw1_sin spw2_din spw2_sin} +#create_clock -name SPW_CLOCK -period 100.000000 -waveform {0.000000 50.000000} {spw1_din spw1_sin spw2_din spw2_sin} # False Paths Between Clocks @@ -17,7 +20,6 @@ create_clock -name SPW_CLOCK -period 100 # Maximum Delay Constraints - # Multicycle Constraints @@ -28,3 +30,10 @@ create_clock -name SPW_CLOCK -period 100 # set_wire_load_mode top # Other Constraints + + +## GRSPW constraints +create_clock -period 100.00 {spw_inputloop.1.spw_phy0/rxclki_RNO:Y} +create_clock -period 100.00 {spw_inputloop.0.spw_phy0/rxclki_RNO:Y} +set_max_delay 4.00 -from [all_inputs] -to [get_clocks spw_inputloop.0.spw_phy0/rxclki_RNO:Y] +set_max_delay 4.00 -from [all_inputs] -to [get_clocks spw_inputloop.1.spw_phy0/rxclki_RNO:Y] diff --git a/boards/LFR-EQM/LFR_EQM_place_and_route.sdc b/boards/LFR-EQM/LFR_EQM_place_and_route.sdc --- a/boards/LFR-EQM/LFR_EQM_place_and_route.sdc +++ b/boards/LFR-EQM/LFR_EQM_place_and_route.sdc @@ -3,10 +3,13 @@ # Clocks create_clock -period 20.000000 -waveform {0.000000 10.000000} clk50MHz +create_clock -period 40.000000 -waveform {0.000000 20.000000} clk_25:Q + +#create_generated_clock -name{clk_domain_25} -divide_by 2 -source{clk_25_int:CLK}{clk_25_int:Q} + create_clock -period 20.344999 -waveform {0.000000 10.172500} clk49_152MHz -create_clock -period 40.000000 -waveform {0.000000 20.000000} clk_25:Q create_clock -period 40.690000 -waveform {0.000000 20.345100} clk_24:Q -create_clock -name SPW_CLOCK -period 100.000000 -waveform {0.000000 50.000000} {spw1_din spw1_sin spw2_din spw2_sin} +#create_clock -name SPW_CLOCK -period 100.000000 -waveform {0.000000 50.000000} {spw1_din spw1_sin spw2_din spw2_sin} # False Paths Between Clocks @@ -17,7 +20,6 @@ create_clock -name SPW_CLOCK -period 100 # Maximum Delay Constraints - # Multicycle Constraints @@ -28,3 +30,10 @@ create_clock -name SPW_CLOCK -period 100 # set_wire_load_mode top # Other Constraints + + +## GRSPW constraints +create_clock -period 100.00 {spw_inputloop.1.spw_phy0/rxclki_RNO:Y} +create_clock -period 100.00 {spw_inputloop.0.spw_phy0/rxclki_RNO:Y} +set_max_delay 4.00 -from [all_inputs] -to [get_clocks spw_inputloop.0.spw_phy0/rxclki_RNO:Y] +set_max_delay 4.00 -from [all_inputs] -to [get_clocks spw_inputloop.1.spw_phy0/rxclki_RNO:Y] diff --git a/boards/LFR-EQM/Makefile.inc b/boards/LFR-EQM/Makefile.inc --- a/boards/LFR-EQM/Makefile.inc +++ b/boards/LFR-EQM/Makefile.inc @@ -2,9 +2,9 @@ PACKAGE=\"\" SPEED=Std SYNFREQ=50 -TECHNOLOGY=ProASIC3E -LIBERO_DIE=IT14X14M4 -PART=A3PE3000 +TECHNOLOGY=ProASIC3L +LIBERO_DIE=A3PE3000L +PART=A3PE3000L DESIGNER_VOLTAGE=COM DESIGNER_TEMP=COM @@ -12,8 +12,9 @@ DESIGNER_PACKAGE=FBGA DESIGNER_PINS=324 MANUFACTURER=Actel -MGCTECHNOLOGY=Proasic3 +MGCTECHNOLOGY=ProASIC3L MGCPART=$(PART) MGCPACKAGE= {$(DESIGNER_PINS) $(DESIGNER_PACKAGE)} LIBERO_PACKAGE=fg$(DESIGNER_PINS) + diff --git a/designs/LFR-EQM-WFP_MS/LFR-EQM.vhd b/designs/LFR-EQM-WFP_MS/LFR-EQM.vhd --- a/designs/LFR-EQM-WFP_MS/LFR-EQM.vhd +++ b/designs/LFR-EQM-WFP_MS/LFR-EQM.vhd @@ -45,8 +45,8 @@ USE lpp.general_purpose.ALL; USE lpp.lpp_lfr_management.ALL; USE lpp.lpp_leon3_soc_pkg.ALL; -library proasic3e; -use proasic3e.clkint; +library proasic3l; +use proasic3l.all; ENTITY LFR_EQM IS @@ -160,6 +160,7 @@ ARCHITECTURE beh OF LFR_EQM IS SIGNAL nSRAM_CE : STD_LOGIC_VECTOR(1 DOWNTO 0); SIGNAL clk50MHz_int : STD_LOGIC := '0'; + SIGNAL clk_25_int : STD_LOGIC := '0'; component clkint port(A : in std_ulogic; Y :out std_ulogic); end component; @@ -171,14 +172,17 @@ BEGIN -- beh rst_domain25 : rstgen PORT MAP (reset, clk_25, '1', rstn_25, OPEN); rst_domain24 : rstgen PORT MAP (reset, clk_24, '1', rstn_24, OPEN); - clk_pad : clkint port map (A => clk50MHz, Y => clk50MHz_int ); + --clk_pad : clkint port map (A => clk50MHz, Y => clk50MHz_int ); + clk50MHz_int <= clk50MHz; PROCESS(clk50MHz_int) BEGIN IF clk50MHz_int'EVENT AND clk50MHz_int = '1' THEN + --clk_25_int <= NOT clk_25_int; clk_25 <= NOT clk_25; END IF; END PROCESS; + --clk_pad_25 : clkint port map (A => clk_25_int, Y => clk_25 ); PROCESS(clk49_152MHz) BEGIN @@ -371,7 +375,7 @@ BEGIN -- beh swni.tickin <= '0'; swni.rmapen <= '1'; - swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz + swni.clkdiv10 <= "00000100"; -- 50 MHz / (4 + 1) = 10 MHz swni.tickinraw <= '0'; swni.timein <= (OTHERS => '0'); swni.dcrstval <= (OTHERS => '0'); @@ -451,7 +455,7 @@ BEGIN -- beh ADC_smpclk <= ADC_smpclk_s; HK_smpclk <= ADC_smpclk_s; - TAG8 <='0'; + TAG8 <= nSRAM_BUSY; ----------------------------------------------------------------------------- -- HK diff --git a/lib/lpp/lpp_leon3_soc/leon3_soc.vhd b/lib/lpp/lpp_leon3_soc/leon3_soc.vhd --- a/lib/lpp/lpp_leon3_soc/leon3_soc.vhd +++ b/lib/lpp/lpp_leon3_soc/leon3_soc.vhd @@ -416,8 +416,8 @@ BEGIN rmw => 1, --Aeroflex memory generics: mprog => 1, -- program memory by default values after reset - mpsrate => 12, -- default scrub rate period - mpb2s => 4, -- default busy to scrub delay + mpsrate => 15, -- default scrub rate period + mpb2s => 14, -- default busy to scrub delay mpapb => 1, -- instantiate apb register mchipcnt => 2, mpenall => 1 -- when 0 program only E1 chip, else program all dies