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Correction ADS TestModule
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r151:5bc2697e3c21 JC
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1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe PELLION
19 -- Author : Jean-christophe PELLION
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
21 -------------------------------------------------------------------------------
22 LIBRARY IEEE;
22 LIBRARY IEEE;
23 USE IEEE.STD_LOGIC_1164.ALL;
23 USE IEEE.STD_LOGIC_1164.ALL;
24 USE IEEE.std_logic_arith.ALL;
24 USE IEEE.std_logic_arith.ALL;
25 USE IEEE.std_logic_signed.ALL;
25 USE IEEE.std_logic_signed.ALL;
26 USE IEEE.MATH_real.ALL;
26 USE IEEE.MATH_real.ALL;
27
27
28 ENTITY TestModule_ADS7886 IS
28 ENTITY TestModule_ADS7886 IS
29 GENERIC (
29 GENERIC (
30 freq : INTEGER := 24;
30 freq : INTEGER := 24;
31 amplitude : INTEGER := 3000;
31 amplitude : INTEGER := 3000;
32 impulsion : INTEGER := 0 -- 1 => impulsion generation
32 impulsion : INTEGER := 0 -- 1 => impulsion generation
33 );
33 );
34 PORT (
34 PORT (
35 -- CONV --
35 -- CONV --
36 cnv_run : IN STD_LOGIC;
36 cnv_run : IN STD_LOGIC;
37 cnv : IN STD_LOGIC;
37 cnv : IN STD_LOGIC;
38
38
39 -- DATA --
39 -- DATA --
40 sck : IN STD_LOGIC;
40 sck : IN STD_LOGIC;
41 sdo : OUT STD_LOGIC
41 sdo : OUT STD_LOGIC
42 );
42 );
43 END TestModule_ADS7886;
43 END TestModule_ADS7886;
44
44
45 ARCHITECTURE beh OF TestModule_ADS7886 IS
45 ARCHITECTURE beh OF TestModule_ADS7886 IS
46 SIGNAL reg : STD_LOGIC_VECTOR(15 DOWNTO 0);
46 SIGNAL reg : STD_LOGIC_VECTOR(15 DOWNTO 0);
47 SIGNAL n : INTEGER := 0;
47 SIGNAL n : INTEGER := 0;
48 BEGIN -- beh
48 BEGIN -- beh
49
49
50 PROCESS (cnv, sck)
50 PROCESS (cnv, sck)
51 BEGIN -- PROCESS
51 BEGIN -- PROCESS
52 IF cnv = '0' AND cnv'EVENT THEN
52 IF cnv = '0' AND cnv'EVENT THEN
53 n <= n + 1;
53 n <= n + 1;
54 IF impulsion = 1 THEN
54 IF impulsion = 1 THEN
55 IF n = 1 THEN
55 IF n = 1 THEN
56 reg <= conv_std_logic_vector(integer(REAL(amplitude)) , 16);
56 reg <= conv_std_logic_vector(integer(REAL(amplitude)) , 16);
57 ELSE
57 ELSE
58 reg <= conv_std_logic_vector(integer(REAL(0)) , 16);
58 reg <= conv_std_logic_vector(integer(REAL(0)) , 16);
59 END IF;
59 END IF;
60 ELSE
60 ELSE
61 reg <= conv_std_logic_vector(integer(REAL(amplitude) * SIN(MATH_2_PI*REAL(n)/REAL(freq))) , 16);
61 reg <= conv_std_logic_vector(integer(REAL(amplitude) * SIN(MATH_2_PI*REAL(n)/REAL(freq))) , 16);
62 END IF;
62 END IF;
63 ELSIF sck'EVENT AND sck = '0' THEN -- rising clock edge
63 ELSIF sck'EVENT AND sck = '0' THEN -- rising clock edge
64 reg(15) <= 'X';
64 reg(0) <= 'X';
65 reg(14 DOWNTO 0) <= reg(15 DOWNTO 1);
65 reg(15 DOWNTO 1) <= reg(14 DOWNTO 0);
66 END IF;
66 END IF;
67 END PROCESS;
67 END PROCESS;
68 sdo <= reg(0);
68 sdo <= reg(15);
69
69
70 END beh;
70 END beh;
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