HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib Commit - r151:5bc2697e3c21

Correction ADS TestModule

pellion -

r151:5bc2697e3c21 JC

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Context file:

r151:5bc2697e3c21

lib/lpp/lpp_ad_Conv/TestModule_ADS7886.vhd +3 -3

                     reg <= conv_std_logic_vector(integer(REAL(amplitude) * SIN(MATH_2_PI*REAL(n)/REAL(freq))) , 16);
                   END IF;
                 ELSIF sck'EVENT AND sck = '0' THEN  -- rising clock edge
-                  reg(15)          <= 'X';
+                  reg(0)           <= 'X';
-                  reg(14 DOWNTO 0) <= reg(15 DOWNTO 1);
+                  reg(15 DOWNTO 1) <= reg(14 DOWNTO 0);
                 END IF;
               END PROCESS;
-              sdo              <= reg(0);
+              sdo              <= reg(15);
             END beh;

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