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update DMA arbiter
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r374:59891d673686 JC
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1 LIBRARY ieee;
1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
2 USE ieee.std_logic_1164.ALL;
3 USE ieee.numeric_std.ALL;
3 USE ieee.numeric_std.ALL;
4
4
5 LIBRARY lpp;
5 LIBRARY lpp;
6 USE lpp.lpp_ad_conv.ALL;
6 USE lpp.lpp_ad_conv.ALL;
7 USE lpp.iir_filter.ALL;
7 USE lpp.iir_filter.ALL;
8 USE lpp.FILTERcfg.ALL;
8 USE lpp.FILTERcfg.ALL;
9 USE lpp.lpp_memory.ALL;
9 USE lpp.lpp_memory.ALL;
10 USE lpp.lpp_waveform_pkg.ALL;
10 USE lpp.lpp_waveform_pkg.ALL;
11 USE lpp.lpp_dma_pkg.ALL;
11 USE lpp.lpp_dma_pkg.ALL;
12 USE lpp.lpp_top_lfr_pkg.ALL;
12 USE lpp.lpp_top_lfr_pkg.ALL;
13 USE lpp.lpp_lfr_pkg.ALL;
13 USE lpp.lpp_lfr_pkg.ALL;
14 USE lpp.general_purpose.ALL;
14 USE lpp.general_purpose.ALL;
15
15
16 LIBRARY techmap;
16 LIBRARY techmap;
17 USE techmap.gencomp.ALL;
17 USE techmap.gencomp.ALL;
18
18
19 LIBRARY grlib;
19 LIBRARY grlib;
20 USE grlib.amba.ALL;
20 USE grlib.amba.ALL;
21 USE grlib.stdlib.ALL;
21 USE grlib.stdlib.ALL;
22 USE grlib.devices.ALL;
22 USE grlib.devices.ALL;
23 USE GRLIB.DMA2AHB_Package.ALL;
23 USE GRLIB.DMA2AHB_Package.ALL;
24
24
25 ENTITY lpp_lfr IS
25 ENTITY lpp_lfr IS
26 GENERIC (
26 GENERIC (
27 Mem_use : INTEGER := use_RAM;
27 Mem_use : INTEGER := use_RAM;
28 nb_data_by_buffer_size : INTEGER := 11;
28 nb_data_by_buffer_size : INTEGER := 11;
29 nb_word_by_buffer_size : INTEGER := 11;
29 nb_word_by_buffer_size : INTEGER := 11;
30 nb_snapshot_param_size : INTEGER := 11;
30 nb_snapshot_param_size : INTEGER := 11;
31 delta_vector_size : INTEGER := 20;
31 delta_vector_size : INTEGER := 20;
32 delta_vector_size_f0_2 : INTEGER := 7;
32 delta_vector_size_f0_2 : INTEGER := 7;
33
33
34 pindex : INTEGER := 4;
34 pindex : INTEGER := 4;
35 paddr : INTEGER := 4;
35 paddr : INTEGER := 4;
36 pmask : INTEGER := 16#fff#;
36 pmask : INTEGER := 16#fff#;
37 pirq_ms : INTEGER := 0;
37 pirq_ms : INTEGER := 0;
38 pirq_wfp : INTEGER := 1;
38 pirq_wfp : INTEGER := 1;
39
39
40 hindex : INTEGER := 2;
40 hindex : INTEGER := 2;
41
41
42 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) := (OTHERS => '0')
42 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) := (OTHERS => '0')
43
43
44 );
44 );
45 PORT (
45 PORT (
46 clk : IN STD_LOGIC;
46 clk : IN STD_LOGIC;
47 rstn : IN STD_LOGIC;
47 rstn : IN STD_LOGIC;
48 -- SAMPLE
48 -- SAMPLE
49 sample_B : IN Samples(2 DOWNTO 0);
49 sample_B : IN Samples(2 DOWNTO 0);
50 sample_E : IN Samples(4 DOWNTO 0);
50 sample_E : IN Samples(4 DOWNTO 0);
51 sample_val : IN STD_LOGIC;
51 sample_val : IN STD_LOGIC;
52 -- APB
52 -- APB
53 apbi : IN apb_slv_in_type;
53 apbi : IN apb_slv_in_type;
54 apbo : OUT apb_slv_out_type;
54 apbo : OUT apb_slv_out_type;
55 -- AHB
55 -- AHB
56 ahbi : IN AHB_Mst_In_Type;
56 ahbi : IN AHB_Mst_In_Type;
57 ahbo : OUT AHB_Mst_Out_Type;
57 ahbo : OUT AHB_Mst_Out_Type;
58 -- TIME
58 -- TIME
59 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
59 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
60 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
60 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
61 --
61 --
62 data_shaping_BW : OUT STD_LOGIC;
62 data_shaping_BW : OUT STD_LOGIC;
63 --
63 --
64 observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
64 observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
65
65
66 --debug
66 --debug
67 --debug_f0_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
67 --debug_f0_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
68 --debug_f0_data_valid : OUT STD_LOGIC;
68 --debug_f0_data_valid : OUT STD_LOGIC;
69 --debug_f1_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
69 --debug_f1_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
70 --debug_f1_data_valid : OUT STD_LOGIC;
70 --debug_f1_data_valid : OUT STD_LOGIC;
71 --debug_f2_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
71 --debug_f2_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
72 --debug_f2_data_valid : OUT STD_LOGIC;
72 --debug_f2_data_valid : OUT STD_LOGIC;
73 --debug_f3_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
73 --debug_f3_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
74 --debug_f3_data_valid : OUT STD_LOGIC;
74 --debug_f3_data_valid : OUT STD_LOGIC;
75
75
76 ---- debug FIFO_IN
76 ---- debug FIFO_IN
77 --debug_f0_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
77 --debug_f0_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
78 --debug_f0_data_fifo_in_valid : OUT STD_LOGIC;
78 --debug_f0_data_fifo_in_valid : OUT STD_LOGIC;
79 --debug_f1_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
79 --debug_f1_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
80 --debug_f1_data_fifo_in_valid : OUT STD_LOGIC;
80 --debug_f1_data_fifo_in_valid : OUT STD_LOGIC;
81 --debug_f2_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
81 --debug_f2_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
82 --debug_f2_data_fifo_in_valid : OUT STD_LOGIC;
82 --debug_f2_data_fifo_in_valid : OUT STD_LOGIC;
83 --debug_f3_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
83 --debug_f3_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
84 --debug_f3_data_fifo_in_valid : OUT STD_LOGIC;
84 --debug_f3_data_fifo_in_valid : OUT STD_LOGIC;
85
85
86 ----debug FIFO OUT
86 ----debug FIFO OUT
87 --debug_f0_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
87 --debug_f0_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
88 --debug_f0_data_fifo_out_valid : OUT STD_LOGIC;
88 --debug_f0_data_fifo_out_valid : OUT STD_LOGIC;
89 --debug_f1_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
89 --debug_f1_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
90 --debug_f1_data_fifo_out_valid : OUT STD_LOGIC;
90 --debug_f1_data_fifo_out_valid : OUT STD_LOGIC;
91 --debug_f2_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
91 --debug_f2_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
92 --debug_f2_data_fifo_out_valid : OUT STD_LOGIC;
92 --debug_f2_data_fifo_out_valid : OUT STD_LOGIC;
93 --debug_f3_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
93 --debug_f3_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
94 --debug_f3_data_fifo_out_valid : OUT STD_LOGIC;
94 --debug_f3_data_fifo_out_valid : OUT STD_LOGIC;
95
95
96 ----debug DMA IN
96 ----debug DMA IN
97 --debug_f0_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
97 --debug_f0_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
98 --debug_f0_data_dma_in_valid : OUT STD_LOGIC;
98 --debug_f0_data_dma_in_valid : OUT STD_LOGIC;
99 --debug_f1_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
99 --debug_f1_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
100 --debug_f1_data_dma_in_valid : OUT STD_LOGIC;
100 --debug_f1_data_dma_in_valid : OUT STD_LOGIC;
101 --debug_f2_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
101 --debug_f2_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
102 --debug_f2_data_dma_in_valid : OUT STD_LOGIC;
102 --debug_f2_data_dma_in_valid : OUT STD_LOGIC;
103 --debug_f3_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
103 --debug_f3_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
104 --debug_f3_data_dma_in_valid : OUT STD_LOGIC
104 --debug_f3_data_dma_in_valid : OUT STD_LOGIC
105 );
105 );
106 END lpp_lfr;
106 END lpp_lfr;
107
107
108 ARCHITECTURE beh OF lpp_lfr IS
108 ARCHITECTURE beh OF lpp_lfr IS
109 --SIGNAL sample : Samples14v(7 DOWNTO 0);
109 --SIGNAL sample : Samples14v(7 DOWNTO 0);
110 SIGNAL sample_s : Samples(7 DOWNTO 0);
110 SIGNAL sample_s : Samples(7 DOWNTO 0);
111 --
111 --
112 SIGNAL data_shaping_SP0 : STD_LOGIC;
112 SIGNAL data_shaping_SP0 : STD_LOGIC;
113 SIGNAL data_shaping_SP1 : STD_LOGIC;
113 SIGNAL data_shaping_SP1 : STD_LOGIC;
114 SIGNAL data_shaping_R0 : STD_LOGIC;
114 SIGNAL data_shaping_R0 : STD_LOGIC;
115 SIGNAL data_shaping_R1 : STD_LOGIC;
115 SIGNAL data_shaping_R1 : STD_LOGIC;
116 --
116 --
117 SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
117 SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
118 SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
118 SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
119 SIGNAL sample_f3_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
119 SIGNAL sample_f3_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
120 --
120 --
121 SIGNAL sample_f0_val : STD_LOGIC;
121 SIGNAL sample_f0_val : STD_LOGIC;
122 SIGNAL sample_f1_val : STD_LOGIC;
122 SIGNAL sample_f1_val : STD_LOGIC;
123 SIGNAL sample_f2_val : STD_LOGIC;
123 SIGNAL sample_f2_val : STD_LOGIC;
124 SIGNAL sample_f3_val : STD_LOGIC;
124 SIGNAL sample_f3_val : STD_LOGIC;
125 --
125 --
126 SIGNAL sample_f0_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
126 SIGNAL sample_f0_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
127 SIGNAL sample_f1_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
127 SIGNAL sample_f1_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
128 SIGNAL sample_f2_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
128 SIGNAL sample_f2_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
129 SIGNAL sample_f3_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
129 SIGNAL sample_f3_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
130 --
130 --
131 SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
131 SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
132 SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
132 SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
133 SIGNAL sample_f3_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
133 SIGNAL sample_f3_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
134
134
135 -- SM
135 -- SM
136 SIGNAL ready_matrix_f0 : STD_LOGIC;
136 SIGNAL ready_matrix_f0 : STD_LOGIC;
137 SIGNAL ready_matrix_f0_1 : STD_LOGIC;
137 SIGNAL ready_matrix_f0_1 : STD_LOGIC;
138 SIGNAL ready_matrix_f1 : STD_LOGIC;
138 SIGNAL ready_matrix_f1 : STD_LOGIC;
139 SIGNAL ready_matrix_f2 : STD_LOGIC;
139 SIGNAL ready_matrix_f2 : STD_LOGIC;
140 -- SIGNAL error_anticipating_empty_fifo : STD_LOGIC;
140 -- SIGNAL error_anticipating_empty_fifo : STD_LOGIC;
141 SIGNAL error_bad_component_error : STD_LOGIC;
141 SIGNAL error_bad_component_error : STD_LOGIC;
142 -- SIGNAL debug_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
142 -- SIGNAL debug_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
143 SIGNAL status_ready_matrix_f0 : STD_LOGIC;
143 SIGNAL status_ready_matrix_f0 : STD_LOGIC;
144 SIGNAL status_ready_matrix_f0_1 : STD_LOGIC;
144 SIGNAL status_ready_matrix_f0_1 : STD_LOGIC;
145 SIGNAL status_ready_matrix_f1 : STD_LOGIC;
145 SIGNAL status_ready_matrix_f1 : STD_LOGIC;
146 SIGNAL status_ready_matrix_f2 : STD_LOGIC;
146 SIGNAL status_ready_matrix_f2 : STD_LOGIC;
147 -- SIGNAL status_error_anticipating_empty_fifo : STD_LOGIC;
147 -- SIGNAL status_error_anticipating_empty_fifo : STD_LOGIC;
148 -- SIGNAL status_error_bad_component_error : STD_LOGIC;
148 -- SIGNAL status_error_bad_component_error : STD_LOGIC;
149 SIGNAL config_active_interruption_onNewMatrix : STD_LOGIC;
149 SIGNAL config_active_interruption_onNewMatrix : STD_LOGIC;
150 SIGNAL config_active_interruption_onError : STD_LOGIC;
150 SIGNAL config_active_interruption_onError : STD_LOGIC;
151 SIGNAL addr_matrix_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
151 SIGNAL addr_matrix_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
152 -- SIGNAL addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
152 -- SIGNAL addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
153 SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
153 SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
154 SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
154 SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
155
155
156 -- WFP
156 -- WFP
157 SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
157 SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
158 SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0);
158 SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0);
159 SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
159 SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
160 SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
160 SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
161 SIGNAL delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
161 SIGNAL delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
162 SIGNAL delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
162 SIGNAL delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
163 SIGNAL delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
163 SIGNAL delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
164 SIGNAL delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
164 SIGNAL delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
165 SIGNAL delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
165 SIGNAL delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
166
166
167 SIGNAL nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
167 SIGNAL nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
168 SIGNAL nb_word_by_buffer : STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
168 SIGNAL nb_word_by_buffer : STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
169 SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
169 SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
170 SIGNAL enable_f0 : STD_LOGIC;
170 SIGNAL enable_f0 : STD_LOGIC;
171 SIGNAL enable_f1 : STD_LOGIC;
171 SIGNAL enable_f1 : STD_LOGIC;
172 SIGNAL enable_f2 : STD_LOGIC;
172 SIGNAL enable_f2 : STD_LOGIC;
173 SIGNAL enable_f3 : STD_LOGIC;
173 SIGNAL enable_f3 : STD_LOGIC;
174 SIGNAL burst_f0 : STD_LOGIC;
174 SIGNAL burst_f0 : STD_LOGIC;
175 SIGNAL burst_f1 : STD_LOGIC;
175 SIGNAL burst_f1 : STD_LOGIC;
176 SIGNAL burst_f2 : STD_LOGIC;
176 SIGNAL burst_f2 : STD_LOGIC;
177 SIGNAL addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
177 SIGNAL addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
178 SIGNAL addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
178 SIGNAL addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
179 SIGNAL addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
179 SIGNAL addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
180 SIGNAL addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
180 SIGNAL addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
181
181
182 SIGNAL run : STD_LOGIC;
182 SIGNAL run : STD_LOGIC;
183 SIGNAL start_date : STD_LOGIC_VECTOR(30 DOWNTO 0);
183 SIGNAL start_date : STD_LOGIC_VECTOR(30 DOWNTO 0);
184
184
185 SIGNAL data_f0_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
185 SIGNAL data_f0_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
186 SIGNAL data_f0_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
186 SIGNAL data_f0_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
187 SIGNAL data_f0_data_out_valid : STD_LOGIC;
187 SIGNAL data_f0_data_out_valid : STD_LOGIC;
188 SIGNAL data_f0_data_out_valid_burst : STD_LOGIC;
188 SIGNAL data_f0_data_out_valid_burst : STD_LOGIC;
189 SIGNAL data_f0_data_out_ren : STD_LOGIC;
189 SIGNAL data_f0_data_out_ren : STD_LOGIC;
190 --f1
190 --f1
191 SIGNAL data_f1_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
191 SIGNAL data_f1_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
192 SIGNAL data_f1_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
192 SIGNAL data_f1_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
193 SIGNAL data_f1_data_out_valid : STD_LOGIC;
193 SIGNAL data_f1_data_out_valid : STD_LOGIC;
194 SIGNAL data_f1_data_out_valid_burst : STD_LOGIC;
194 SIGNAL data_f1_data_out_valid_burst : STD_LOGIC;
195 SIGNAL data_f1_data_out_ren : STD_LOGIC;
195 SIGNAL data_f1_data_out_ren : STD_LOGIC;
196 --f2
196 --f2
197 SIGNAL data_f2_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
197 SIGNAL data_f2_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
198 SIGNAL data_f2_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
198 SIGNAL data_f2_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
199 SIGNAL data_f2_data_out_valid : STD_LOGIC;
199 SIGNAL data_f2_data_out_valid : STD_LOGIC;
200 SIGNAL data_f2_data_out_valid_burst : STD_LOGIC;
200 SIGNAL data_f2_data_out_valid_burst : STD_LOGIC;
201 SIGNAL data_f2_data_out_ren : STD_LOGIC;
201 SIGNAL data_f2_data_out_ren : STD_LOGIC;
202 --f3
202 --f3
203 SIGNAL data_f3_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
203 SIGNAL data_f3_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
204 SIGNAL data_f3_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
204 SIGNAL data_f3_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
205 SIGNAL data_f3_data_out_valid : STD_LOGIC;
205 SIGNAL data_f3_data_out_valid : STD_LOGIC;
206 SIGNAL data_f3_data_out_valid_burst : STD_LOGIC;
206 SIGNAL data_f3_data_out_valid_burst : STD_LOGIC;
207 SIGNAL data_f3_data_out_ren : STD_LOGIC;
207 SIGNAL data_f3_data_out_ren : STD_LOGIC;
208
208
209 -----------------------------------------------------------------------------
209 -----------------------------------------------------------------------------
210 --
210 --
211 -----------------------------------------------------------------------------
211 -----------------------------------------------------------------------------
212 SIGNAL data_f0_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
212 SIGNAL data_f0_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
213 SIGNAL data_f0_data_out_valid_s : STD_LOGIC;
213 SIGNAL data_f0_data_out_valid_s : STD_LOGIC;
214 SIGNAL data_f0_data_out_valid_burst_s : STD_LOGIC;
214 SIGNAL data_f0_data_out_valid_burst_s : STD_LOGIC;
215 --f1
215 --f1
216 SIGNAL data_f1_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
216 SIGNAL data_f1_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
217 SIGNAL data_f1_data_out_valid_s : STD_LOGIC;
217 SIGNAL data_f1_data_out_valid_s : STD_LOGIC;
218 SIGNAL data_f1_data_out_valid_burst_s : STD_LOGIC;
218 SIGNAL data_f1_data_out_valid_burst_s : STD_LOGIC;
219 --f2
219 --f2
220 SIGNAL data_f2_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
220 SIGNAL data_f2_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
221 SIGNAL data_f2_data_out_valid_s : STD_LOGIC;
221 SIGNAL data_f2_data_out_valid_s : STD_LOGIC;
222 SIGNAL data_f2_data_out_valid_burst_s : STD_LOGIC;
222 SIGNAL data_f2_data_out_valid_burst_s : STD_LOGIC;
223 --f3
223 --f3
224 SIGNAL data_f3_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
224 SIGNAL data_f3_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
225 SIGNAL data_f3_data_out_valid_s : STD_LOGIC;
225 SIGNAL data_f3_data_out_valid_s : STD_LOGIC;
226 SIGNAL data_f3_data_out_valid_burst_s : STD_LOGIC;
226 SIGNAL data_f3_data_out_valid_burst_s : STD_LOGIC;
227
227
228 -----------------------------------------------------------------------------
228 -----------------------------------------------------------------------------
229 -- DMA RR
229 -- DMA RR
230 -----------------------------------------------------------------------------
230 -----------------------------------------------------------------------------
231 SIGNAL dma_sel_valid : STD_LOGIC;
231 SIGNAL dma_sel_valid : STD_LOGIC;
232 SIGNAL dma_rr_valid : STD_LOGIC_VECTOR(3 DOWNTO 0);
232 SIGNAL dma_rr_valid : STD_LOGIC_VECTOR(3 DOWNTO 0);
233 SIGNAL dma_rr_grant_s : STD_LOGIC_VECTOR(3 DOWNTO 0);
233 SIGNAL dma_rr_grant_s : STD_LOGIC_VECTOR(3 DOWNTO 0);
234 SIGNAL dma_rr_grant_ms : STD_LOGIC_VECTOR(3 DOWNTO 0);
234 SIGNAL dma_rr_grant_ms : STD_LOGIC_VECTOR(3 DOWNTO 0);
235 SIGNAL dma_rr_valid_ms : STD_LOGIC_VECTOR(3 DOWNTO 0);
235 SIGNAL dma_rr_valid_ms : STD_LOGIC_VECTOR(3 DOWNTO 0);
236
236
237 SIGNAL dma_rr_grant : STD_LOGIC_VECTOR(4 DOWNTO 0);
237 SIGNAL dma_rr_grant : STD_LOGIC_VECTOR(4 DOWNTO 0);
238 SIGNAL dma_sel : STD_LOGIC_VECTOR(4 DOWNTO 0);
238 SIGNAL dma_sel : STD_LOGIC_VECTOR(4 DOWNTO 0);
239
239
240 -----------------------------------------------------------------------------
240 -----------------------------------------------------------------------------
241 -- DMA_REG
241 -- DMA_REG
242 -----------------------------------------------------------------------------
242 -----------------------------------------------------------------------------
243 SIGNAL ongoing_reg : STD_LOGIC;
243 SIGNAL ongoing_reg : STD_LOGIC;
244 SIGNAL dma_sel_reg : STD_LOGIC_VECTOR(3 DOWNTO 0);
244 SIGNAL dma_sel_reg : STD_LOGIC_VECTOR(3 DOWNTO 0);
245 SIGNAL dma_send_reg : STD_LOGIC;
245 SIGNAL dma_send_reg : STD_LOGIC;
246 SIGNAL dma_valid_burst_reg : STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
246 SIGNAL dma_valid_burst_reg : STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
247 SIGNAL dma_address_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
247 SIGNAL dma_address_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
248 SIGNAL dma_data_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
248 SIGNAL dma_data_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
249
249
250
250
251 -----------------------------------------------------------------------------
251 -----------------------------------------------------------------------------
252 -- DMA
252 -- DMA
253 -----------------------------------------------------------------------------
253 -----------------------------------------------------------------------------
254 SIGNAL dma_send : STD_LOGIC;
254 SIGNAL dma_send : STD_LOGIC;
255 SIGNAL dma_valid_burst : STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
255 SIGNAL dma_valid_burst : STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
256 SIGNAL dma_done : STD_LOGIC;
256 SIGNAL dma_done : STD_LOGIC;
257 SIGNAL dma_ren : STD_LOGIC;
257 SIGNAL dma_ren : STD_LOGIC;
258 SIGNAL dma_address : STD_LOGIC_VECTOR(31 DOWNTO 0);
258 SIGNAL dma_address : STD_LOGIC_VECTOR(31 DOWNTO 0);
259 SIGNAL dma_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
259 SIGNAL dma_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
260 SIGNAL dma_data_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
260 SIGNAL dma_data_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
261
261
262 -----------------------------------------------------------------------------
262 -----------------------------------------------------------------------------
263 -- MS
263 -- MS
264 -----------------------------------------------------------------------------
264 -----------------------------------------------------------------------------
265
265
266 SIGNAL data_ms_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
266 SIGNAL data_ms_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
267 SIGNAL data_ms_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
267 SIGNAL data_ms_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
268 SIGNAL data_ms_valid : STD_LOGIC;
268 SIGNAL data_ms_valid : STD_LOGIC;
269 SIGNAL data_ms_valid_burst : STD_LOGIC;
269 SIGNAL data_ms_valid_burst : STD_LOGIC;
270 SIGNAL data_ms_ren : STD_LOGIC;
270 SIGNAL data_ms_ren : STD_LOGIC;
271 SIGNAL data_ms_done : STD_LOGIC;
271 SIGNAL data_ms_done : STD_LOGIC;
272 SIGNAL dma_ms_ongoing : STD_LOGIC;
272
273
273 SIGNAL run_ms : STD_LOGIC;
274 SIGNAL run_ms : STD_LOGIC;
274 SIGNAL ms_softandhard_rstn : STD_LOGIC;
275 SIGNAL ms_softandhard_rstn : STD_LOGIC;
275
276
276 SIGNAL matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
277 SIGNAL matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
277 -- SIGNAL matrix_time_f0_1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
278 -- SIGNAL matrix_time_f0_1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
278 SIGNAL matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
279 SIGNAL matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
279 SIGNAL matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
280 SIGNAL matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
280
281
281
282
282 SIGNAL error_buffer_full : STD_LOGIC;
283 SIGNAL error_buffer_full : STD_LOGIC;
283 SIGNAL error_input_fifo_write : STD_LOGIC_VECTOR(2 DOWNTO 0);
284 SIGNAL error_input_fifo_write : STD_LOGIC_VECTOR(2 DOWNTO 0);
284
285
285 SIGNAL debug_ms : STD_LOGIC_VECTOR(31 DOWNTO 0);
286 SIGNAL debug_ms : STD_LOGIC_VECTOR(31 DOWNTO 0);
286
287
287 BEGIN
288 BEGIN
288
289
289 sample_s(4 DOWNTO 0) <= sample_E(4 DOWNTO 0);
290 sample_s(4 DOWNTO 0) <= sample_E(4 DOWNTO 0);
290 sample_s(7 DOWNTO 5) <= sample_B(2 DOWNTO 0);
291 sample_s(7 DOWNTO 5) <= sample_B(2 DOWNTO 0);
291
292
292 --all_channel : FOR i IN 7 DOWNTO 0 GENERATE
293 --all_channel : FOR i IN 7 DOWNTO 0 GENERATE
293 -- sample_s(i) <= sample(i)(13) & sample(i)(13) & sample(i);
294 -- sample_s(i) <= sample(i)(13) & sample(i)(13) & sample(i);
294 --END GENERATE all_channel;
295 --END GENERATE all_channel;
295
296
296 -----------------------------------------------------------------------------
297 -----------------------------------------------------------------------------
297 lpp_lfr_filter_1 : lpp_lfr_filter
298 lpp_lfr_filter_1 : lpp_lfr_filter
298 GENERIC MAP (
299 GENERIC MAP (
299 Mem_use => Mem_use)
300 Mem_use => Mem_use)
300 PORT MAP (
301 PORT MAP (
301 sample => sample_s,
302 sample => sample_s,
302 sample_val => sample_val,
303 sample_val => sample_val,
303 clk => clk,
304 clk => clk,
304 rstn => rstn,
305 rstn => rstn,
305 data_shaping_SP0 => data_shaping_SP0,
306 data_shaping_SP0 => data_shaping_SP0,
306 data_shaping_SP1 => data_shaping_SP1,
307 data_shaping_SP1 => data_shaping_SP1,
307 data_shaping_R0 => data_shaping_R0,
308 data_shaping_R0 => data_shaping_R0,
308 data_shaping_R1 => data_shaping_R1,
309 data_shaping_R1 => data_shaping_R1,
309 sample_f0_val => sample_f0_val,
310 sample_f0_val => sample_f0_val,
310 sample_f1_val => sample_f1_val,
311 sample_f1_val => sample_f1_val,
311 sample_f2_val => sample_f2_val,
312 sample_f2_val => sample_f2_val,
312 sample_f3_val => sample_f3_val,
313 sample_f3_val => sample_f3_val,
313 sample_f0_wdata => sample_f0_data,
314 sample_f0_wdata => sample_f0_data,
314 sample_f1_wdata => sample_f1_data,
315 sample_f1_wdata => sample_f1_data,
315 sample_f2_wdata => sample_f2_data,
316 sample_f2_wdata => sample_f2_data,
316 sample_f3_wdata => sample_f3_data);
317 sample_f3_wdata => sample_f3_data);
317
318
318 -----------------------------------------------------------------------------
319 -----------------------------------------------------------------------------
319 lpp_lfr_apbreg_1 : lpp_lfr_apbreg
320 lpp_lfr_apbreg_1 : lpp_lfr_apbreg
320 GENERIC MAP (
321 GENERIC MAP (
321 nb_data_by_buffer_size => nb_data_by_buffer_size,
322 nb_data_by_buffer_size => nb_data_by_buffer_size,
322 nb_word_by_buffer_size => nb_word_by_buffer_size,
323 nb_word_by_buffer_size => nb_word_by_buffer_size,
323 nb_snapshot_param_size => nb_snapshot_param_size,
324 nb_snapshot_param_size => nb_snapshot_param_size,
324 delta_vector_size => delta_vector_size,
325 delta_vector_size => delta_vector_size,
325 delta_vector_size_f0_2 => delta_vector_size_f0_2,
326 delta_vector_size_f0_2 => delta_vector_size_f0_2,
326 pindex => pindex,
327 pindex => pindex,
327 paddr => paddr,
328 paddr => paddr,
328 pmask => pmask,
329 pmask => pmask,
329 pirq_ms => pirq_ms,
330 pirq_ms => pirq_ms,
330 pirq_wfp => pirq_wfp,
331 pirq_wfp => pirq_wfp,
331 top_lfr_version => top_lfr_version)
332 top_lfr_version => top_lfr_version)
332 PORT MAP (
333 PORT MAP (
333 HCLK => clk,
334 HCLK => clk,
334 HRESETn => rstn,
335 HRESETn => rstn,
335 apbi => apbi,
336 apbi => apbi,
336 apbo => apbo,
337 apbo => apbo,
337
338
338 run_ms => run_ms,
339 run_ms => run_ms,
339
340
340 ready_matrix_f0 => ready_matrix_f0,
341 ready_matrix_f0 => ready_matrix_f0,
341 -- ready_matrix_f0_1 => ready_matrix_f0_1,
342 -- ready_matrix_f0_1 => ready_matrix_f0_1,
342 ready_matrix_f1 => ready_matrix_f1,
343 ready_matrix_f1 => ready_matrix_f1,
343 ready_matrix_f2 => ready_matrix_f2,
344 ready_matrix_f2 => ready_matrix_f2,
344 -- error_anticipating_empty_fifo => error_anticipating_empty_fifo,
345 -- error_anticipating_empty_fifo => error_anticipating_empty_fifo,
345 error_bad_component_error => error_bad_component_error,
346 error_bad_component_error => error_bad_component_error,
346 error_buffer_full => error_buffer_full, -- TODO
347 error_buffer_full => error_buffer_full, -- TODO
347 error_input_fifo_write => error_input_fifo_write, -- TODO
348 error_input_fifo_write => error_input_fifo_write, -- TODO
348 -- debug_reg => debug_reg,
349 -- debug_reg => debug_reg,
349 status_ready_matrix_f0 => status_ready_matrix_f0,
350 status_ready_matrix_f0 => status_ready_matrix_f0,
350 -- status_ready_matrix_f0_1 => status_ready_matrix_f0_1,
351 -- status_ready_matrix_f0_1 => status_ready_matrix_f0_1,
351 status_ready_matrix_f1 => status_ready_matrix_f1,
352 status_ready_matrix_f1 => status_ready_matrix_f1,
352 status_ready_matrix_f2 => status_ready_matrix_f2,
353 status_ready_matrix_f2 => status_ready_matrix_f2,
353 -- status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,
354 -- status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,
354 -- status_error_bad_component_error => status_error_bad_component_error,
355 -- status_error_bad_component_error => status_error_bad_component_error,
355 config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
356 config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
356 config_active_interruption_onError => config_active_interruption_onError,
357 config_active_interruption_onError => config_active_interruption_onError,
357
358
358 matrix_time_f0 => matrix_time_f0,
359 matrix_time_f0 => matrix_time_f0,
359 -- matrix_time_f0_1 => matrix_time_f0_1,
360 -- matrix_time_f0_1 => matrix_time_f0_1,
360 matrix_time_f1 => matrix_time_f1,
361 matrix_time_f1 => matrix_time_f1,
361 matrix_time_f2 => matrix_time_f2,
362 matrix_time_f2 => matrix_time_f2,
362
363
363 addr_matrix_f0 => addr_matrix_f0,
364 addr_matrix_f0 => addr_matrix_f0,
364 -- addr_matrix_f0_1 => addr_matrix_f0_1,
365 -- addr_matrix_f0_1 => addr_matrix_f0_1,
365 addr_matrix_f1 => addr_matrix_f1,
366 addr_matrix_f1 => addr_matrix_f1,
366 addr_matrix_f2 => addr_matrix_f2,
367 addr_matrix_f2 => addr_matrix_f2,
367 -------------------------------------------------------------------------
368 -------------------------------------------------------------------------
368 status_full => status_full,
369 status_full => status_full,
369 status_full_ack => status_full_ack,
370 status_full_ack => status_full_ack,
370 status_full_err => status_full_err,
371 status_full_err => status_full_err,
371 status_new_err => status_new_err,
372 status_new_err => status_new_err,
372 data_shaping_BW => data_shaping_BW,
373 data_shaping_BW => data_shaping_BW,
373 data_shaping_SP0 => data_shaping_SP0,
374 data_shaping_SP0 => data_shaping_SP0,
374 data_shaping_SP1 => data_shaping_SP1,
375 data_shaping_SP1 => data_shaping_SP1,
375 data_shaping_R0 => data_shaping_R0,
376 data_shaping_R0 => data_shaping_R0,
376 data_shaping_R1 => data_shaping_R1,
377 data_shaping_R1 => data_shaping_R1,
377 delta_snapshot => delta_snapshot,
378 delta_snapshot => delta_snapshot,
378 delta_f0 => delta_f0,
379 delta_f0 => delta_f0,
379 delta_f0_2 => delta_f0_2,
380 delta_f0_2 => delta_f0_2,
380 delta_f1 => delta_f1,
381 delta_f1 => delta_f1,
381 delta_f2 => delta_f2,
382 delta_f2 => delta_f2,
382 nb_data_by_buffer => nb_data_by_buffer,
383 nb_data_by_buffer => nb_data_by_buffer,
383 nb_word_by_buffer => nb_word_by_buffer,
384 nb_word_by_buffer => nb_word_by_buffer,
384 nb_snapshot_param => nb_snapshot_param,
385 nb_snapshot_param => nb_snapshot_param,
385 enable_f0 => enable_f0,
386 enable_f0 => enable_f0,
386 enable_f1 => enable_f1,
387 enable_f1 => enable_f1,
387 enable_f2 => enable_f2,
388 enable_f2 => enable_f2,
388 enable_f3 => enable_f3,
389 enable_f3 => enable_f3,
389 burst_f0 => burst_f0,
390 burst_f0 => burst_f0,
390 burst_f1 => burst_f1,
391 burst_f1 => burst_f1,
391 burst_f2 => burst_f2,
392 burst_f2 => burst_f2,
392 run => run,
393 run => run,
393 addr_data_f0 => addr_data_f0,
394 addr_data_f0 => addr_data_f0,
394 addr_data_f1 => addr_data_f1,
395 addr_data_f1 => addr_data_f1,
395 addr_data_f2 => addr_data_f2,
396 addr_data_f2 => addr_data_f2,
396 addr_data_f3 => addr_data_f3,
397 addr_data_f3 => addr_data_f3,
397 start_date => start_date);
398 start_date => start_date);
398
399
399 -----------------------------------------------------------------------------
400 -----------------------------------------------------------------------------
400 -----------------------------------------------------------------------------
401 -----------------------------------------------------------------------------
401 lpp_waveform_1 : lpp_waveform
402 lpp_waveform_1 : lpp_waveform
402 GENERIC MAP (
403 GENERIC MAP (
403 tech => inferred,
404 tech => inferred,
404 data_size => 6*16,
405 data_size => 6*16,
405 nb_data_by_buffer_size => nb_data_by_buffer_size,
406 nb_data_by_buffer_size => nb_data_by_buffer_size,
406 nb_word_by_buffer_size => nb_word_by_buffer_size,
407 nb_word_by_buffer_size => nb_word_by_buffer_size,
407 nb_snapshot_param_size => nb_snapshot_param_size,
408 nb_snapshot_param_size => nb_snapshot_param_size,
408 delta_vector_size => delta_vector_size,
409 delta_vector_size => delta_vector_size,
409 delta_vector_size_f0_2 => delta_vector_size_f0_2
410 delta_vector_size_f0_2 => delta_vector_size_f0_2
410 )
411 )
411 PORT MAP (
412 PORT MAP (
412 clk => clk,
413 clk => clk,
413 rstn => rstn,
414 rstn => rstn,
414
415
415 reg_run => run,
416 reg_run => run,
416 reg_start_date => start_date,
417 reg_start_date => start_date,
417 reg_delta_snapshot => delta_snapshot,
418 reg_delta_snapshot => delta_snapshot,
418 reg_delta_f0 => delta_f0,
419 reg_delta_f0 => delta_f0,
419 reg_delta_f0_2 => delta_f0_2,
420 reg_delta_f0_2 => delta_f0_2,
420 reg_delta_f1 => delta_f1,
421 reg_delta_f1 => delta_f1,
421 reg_delta_f2 => delta_f2,
422 reg_delta_f2 => delta_f2,
422
423
423 enable_f0 => enable_f0,
424 enable_f0 => enable_f0,
424 enable_f1 => enable_f1,
425 enable_f1 => enable_f1,
425 enable_f2 => enable_f2,
426 enable_f2 => enable_f2,
426 enable_f3 => enable_f3,
427 enable_f3 => enable_f3,
427 burst_f0 => burst_f0,
428 burst_f0 => burst_f0,
428 burst_f1 => burst_f1,
429 burst_f1 => burst_f1,
429 burst_f2 => burst_f2,
430 burst_f2 => burst_f2,
430
431
431 nb_data_by_buffer => nb_data_by_buffer,
432 nb_data_by_buffer => nb_data_by_buffer,
432 nb_word_by_buffer => nb_word_by_buffer,
433 nb_word_by_buffer => nb_word_by_buffer,
433 nb_snapshot_param => nb_snapshot_param,
434 nb_snapshot_param => nb_snapshot_param,
434 status_full => status_full,
435 status_full => status_full,
435 status_full_ack => status_full_ack,
436 status_full_ack => status_full_ack,
436 status_full_err => status_full_err,
437 status_full_err => status_full_err,
437 status_new_err => status_new_err,
438 status_new_err => status_new_err,
438
439
439 coarse_time => coarse_time,
440 coarse_time => coarse_time,
440 fine_time => fine_time,
441 fine_time => fine_time,
441
442
442 --f0
443 --f0
443 addr_data_f0 => addr_data_f0,
444 addr_data_f0 => addr_data_f0,
444 data_f0_in_valid => sample_f0_val,
445 data_f0_in_valid => sample_f0_val,
445 data_f0_in => sample_f0_data,
446 data_f0_in => sample_f0_data,
446 --f1
447 --f1
447 addr_data_f1 => addr_data_f1,
448 addr_data_f1 => addr_data_f1,
448 data_f1_in_valid => sample_f1_val,
449 data_f1_in_valid => sample_f1_val,
449 data_f1_in => sample_f1_data,
450 data_f1_in => sample_f1_data,
450 --f2
451 --f2
451 addr_data_f2 => addr_data_f2,
452 addr_data_f2 => addr_data_f2,
452 data_f2_in_valid => sample_f2_val,
453 data_f2_in_valid => sample_f2_val,
453 data_f2_in => sample_f2_data,
454 data_f2_in => sample_f2_data,
454 --f3
455 --f3
455 addr_data_f3 => addr_data_f3,
456 addr_data_f3 => addr_data_f3,
456 data_f3_in_valid => sample_f3_val,
457 data_f3_in_valid => sample_f3_val,
457 data_f3_in => sample_f3_data,
458 data_f3_in => sample_f3_data,
458 -- OUTPUT -- DMA interface
459 -- OUTPUT -- DMA interface
459 --f0
460 --f0
460 data_f0_addr_out => data_f0_addr_out_s,
461 data_f0_addr_out => data_f0_addr_out_s,
461 data_f0_data_out => data_f0_data_out,
462 data_f0_data_out => data_f0_data_out,
462 data_f0_data_out_valid => data_f0_data_out_valid_s,
463 data_f0_data_out_valid => data_f0_data_out_valid_s,
463 data_f0_data_out_valid_burst => data_f0_data_out_valid_burst_s,
464 data_f0_data_out_valid_burst => data_f0_data_out_valid_burst_s,
464 data_f0_data_out_ren => data_f0_data_out_ren,
465 data_f0_data_out_ren => data_f0_data_out_ren,
465 --f1
466 --f1
466 data_f1_addr_out => data_f1_addr_out_s,
467 data_f1_addr_out => data_f1_addr_out_s,
467 data_f1_data_out => data_f1_data_out,
468 data_f1_data_out => data_f1_data_out,
468 data_f1_data_out_valid => data_f1_data_out_valid_s,
469 data_f1_data_out_valid => data_f1_data_out_valid_s,
469 data_f1_data_out_valid_burst => data_f1_data_out_valid_burst_s,
470 data_f1_data_out_valid_burst => data_f1_data_out_valid_burst_s,
470 data_f1_data_out_ren => data_f1_data_out_ren,
471 data_f1_data_out_ren => data_f1_data_out_ren,
471 --f2
472 --f2
472 data_f2_addr_out => data_f2_addr_out_s,
473 data_f2_addr_out => data_f2_addr_out_s,
473 data_f2_data_out => data_f2_data_out,
474 data_f2_data_out => data_f2_data_out,
474 data_f2_data_out_valid => data_f2_data_out_valid_s,
475 data_f2_data_out_valid => data_f2_data_out_valid_s,
475 data_f2_data_out_valid_burst => data_f2_data_out_valid_burst_s,
476 data_f2_data_out_valid_burst => data_f2_data_out_valid_burst_s,
476 data_f2_data_out_ren => data_f2_data_out_ren,
477 data_f2_data_out_ren => data_f2_data_out_ren,
477 --f3
478 --f3
478 data_f3_addr_out => data_f3_addr_out_s,
479 data_f3_addr_out => data_f3_addr_out_s,
479 data_f3_data_out => data_f3_data_out,
480 data_f3_data_out => data_f3_data_out,
480 data_f3_data_out_valid => data_f3_data_out_valid_s,
481 data_f3_data_out_valid => data_f3_data_out_valid_s,
481 data_f3_data_out_valid_burst => data_f3_data_out_valid_burst_s,
482 data_f3_data_out_valid_burst => data_f3_data_out_valid_burst_s,
482 data_f3_data_out_ren => data_f3_data_out_ren ,
483 data_f3_data_out_ren => data_f3_data_out_ren ,
483
484
484 -------------------------------------------------------------------------
485 -------------------------------------------------------------------------
485 observation_reg => OPEN
486 observation_reg => OPEN
486
487
487 );
488 );
488
489
489
490
490 -----------------------------------------------------------------------------
491 -----------------------------------------------------------------------------
491 -- TEMP
492 -- TEMP
492 -----------------------------------------------------------------------------
493 -----------------------------------------------------------------------------
493
494
494 PROCESS (clk, rstn)
495 PROCESS (clk, rstn)
495 BEGIN -- PROCESS
496 BEGIN -- PROCESS
496 IF rstn = '0' THEN -- asynchronous reset (active low)
497 IF rstn = '0' THEN -- asynchronous reset (active low)
497 data_f0_data_out_valid <= '0';
498 data_f0_data_out_valid <= '0';
498 data_f0_data_out_valid_burst <= '0';
499 data_f0_data_out_valid_burst <= '0';
499 data_f1_data_out_valid <= '0';
500 data_f1_data_out_valid <= '0';
500 data_f1_data_out_valid_burst <= '0';
501 data_f1_data_out_valid_burst <= '0';
501 data_f2_data_out_valid <= '0';
502 data_f2_data_out_valid <= '0';
502 data_f2_data_out_valid_burst <= '0';
503 data_f2_data_out_valid_burst <= '0';
503 data_f3_data_out_valid <= '0';
504 data_f3_data_out_valid <= '0';
504 data_f3_data_out_valid_burst <= '0';
505 data_f3_data_out_valid_burst <= '0';
505 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
506 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
506 data_f0_data_out_valid <= data_f0_data_out_valid_s;
507 data_f0_data_out_valid <= data_f0_data_out_valid_s;
507 data_f0_data_out_valid_burst <= data_f0_data_out_valid_burst_s;
508 data_f0_data_out_valid_burst <= data_f0_data_out_valid_burst_s;
508 data_f1_data_out_valid <= data_f1_data_out_valid_s;
509 data_f1_data_out_valid <= data_f1_data_out_valid_s;
509 data_f1_data_out_valid_burst <= data_f1_data_out_valid_burst_s;
510 data_f1_data_out_valid_burst <= data_f1_data_out_valid_burst_s;
510 data_f2_data_out_valid <= data_f2_data_out_valid_s;
511 data_f2_data_out_valid <= data_f2_data_out_valid_s;
511 data_f2_data_out_valid_burst <= data_f2_data_out_valid_burst_s;
512 data_f2_data_out_valid_burst <= data_f2_data_out_valid_burst_s;
512 data_f3_data_out_valid <= data_f3_data_out_valid_s;
513 data_f3_data_out_valid <= data_f3_data_out_valid_s;
513 data_f3_data_out_valid_burst <= data_f3_data_out_valid_burst_s;
514 data_f3_data_out_valid_burst <= data_f3_data_out_valid_burst_s;
514 END IF;
515 END IF;
515 END PROCESS;
516 END PROCESS;
516
517
517 data_f0_addr_out <= data_f0_addr_out_s;
518 data_f0_addr_out <= data_f0_addr_out_s;
518 data_f1_addr_out <= data_f1_addr_out_s;
519 data_f1_addr_out <= data_f1_addr_out_s;
519 data_f2_addr_out <= data_f2_addr_out_s;
520 data_f2_addr_out <= data_f2_addr_out_s;
520 data_f3_addr_out <= data_f3_addr_out_s;
521 data_f3_addr_out <= data_f3_addr_out_s;
521
522
522 -----------------------------------------------------------------------------
523 -----------------------------------------------------------------------------
523 -- RoundRobin Selection For DMA
524 -- RoundRobin Selection For DMA
524 -----------------------------------------------------------------------------
525 -----------------------------------------------------------------------------
525
526
526 dma_rr_valid(0) <= data_f0_data_out_valid OR data_f0_data_out_valid_burst;
527 dma_rr_valid(0) <= data_f0_data_out_valid OR data_f0_data_out_valid_burst;
527 dma_rr_valid(1) <= data_f1_data_out_valid OR data_f1_data_out_valid_burst;
528 dma_rr_valid(1) <= data_f1_data_out_valid OR data_f1_data_out_valid_burst;
528 dma_rr_valid(2) <= data_f2_data_out_valid OR data_f2_data_out_valid_burst;
529 dma_rr_valid(2) <= data_f2_data_out_valid OR data_f2_data_out_valid_burst;
529 dma_rr_valid(3) <= data_f3_data_out_valid OR data_f3_data_out_valid_burst;
530 dma_rr_valid(3) <= data_f3_data_out_valid OR data_f3_data_out_valid_burst;
530
531
531 RR_Arbiter_4_1 : RR_Arbiter_4
532 RR_Arbiter_4_1 : RR_Arbiter_4
532 PORT MAP (
533 PORT MAP (
533 clk => clk,
534 clk => clk,
534 rstn => rstn,
535 rstn => rstn,
535 in_valid => dma_rr_valid,
536 in_valid => dma_rr_valid,
536 out_grant => dma_rr_grant_s);
537 out_grant => dma_rr_grant_s);
537
538
538 dma_rr_valid_ms(0) <= data_ms_valid OR data_ms_valid_burst;
539 dma_rr_valid_ms(0) <= data_ms_valid OR data_ms_valid_burst;
539 dma_rr_valid_ms(1) <= '0' WHEN dma_rr_grant_s = "0000" ELSE '1';
540 dma_rr_valid_ms(1) <= '0' WHEN dma_rr_grant_s = "0000" ELSE '1';
540 dma_rr_valid_ms(2) <= '0';
541 dma_rr_valid_ms(2) <= '0';
541 dma_rr_valid_ms(3) <= '0';
542 dma_rr_valid_ms(3) <= '0';
542
543
543 RR_Arbiter_4_2 : RR_Arbiter_4
544 RR_Arbiter_4_2 : RR_Arbiter_4
544 PORT MAP (
545 PORT MAP (
545 clk => clk,
546 clk => clk,
546 rstn => rstn,
547 rstn => rstn,
547 in_valid => dma_rr_valid_ms,
548 in_valid => dma_rr_valid_ms,
548 out_grant => dma_rr_grant_ms);
549 out_grant => dma_rr_grant_ms);
549
550
550 dma_rr_grant <= dma_rr_grant_ms(0) & "0000" WHEN dma_rr_grant_ms(0) = '1' ELSE '0' & dma_rr_grant_s;
551 dma_rr_grant <= dma_rr_grant_ms(0) & "0000" WHEN dma_rr_grant_ms(0) = '1' ELSE '0' & dma_rr_grant_s;
551
552
552
553
553 -----------------------------------------------------------------------------
554 -----------------------------------------------------------------------------
554 -- in : dma_rr_grant
555 -- in : dma_rr_grant
555 -- send
556 -- send
556 -- out : dma_sel
557 -- out : dma_sel
557 -- dma_valid_burst
558 -- dma_valid_burst
558 -- dma_sel_valid
559 -- dma_sel_valid
559 -----------------------------------------------------------------------------
560 -----------------------------------------------------------------------------
560 PROCESS (clk, rstn)
561 PROCESS (clk, rstn)
561 BEGIN -- PROCESS
562 BEGIN -- PROCESS
562 IF rstn = '0' THEN -- asynchronous reset (active low)
563 IF rstn = '0' THEN -- asynchronous reset (active low)
563 dma_sel <= (OTHERS => '0');
564 dma_sel <= (OTHERS => '0');
564 dma_send <= '0';
565 dma_send <= '0';
565 dma_valid_burst <= '0';
566 dma_valid_burst <= '0';
566 data_ms_done <= '0';
567 data_ms_done <= '0';
568 dma_ms_ongoing <= '0';
567 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
569 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
568 IF run = '1' THEN
570 IF run = '1' THEN
569 data_ms_done <= '0';
571 data_ms_done <= '0';
570 IF dma_sel = "00000" OR dma_done = '1' THEN
572 IF dma_sel = "00000" OR dma_done = '1' THEN
571 dma_sel <= dma_rr_grant;
573 dma_sel <= dma_rr_grant;
572 IF dma_rr_grant(0) = '1' THEN
574 IF dma_rr_grant(0) = '1' THEN
575 dma_ms_ongoing <= '0';
573 dma_send <= '1';
576 dma_send <= '1';
574 dma_valid_burst <= data_f0_data_out_valid_burst;
577 dma_valid_burst <= data_f0_data_out_valid_burst;
575 dma_sel_valid <= data_f0_data_out_valid;
578 dma_sel_valid <= data_f0_data_out_valid;
576 ELSIF dma_rr_grant(1) = '1' THEN
579 ELSIF dma_rr_grant(1) = '1' THEN
580 dma_ms_ongoing <= '0';
577 dma_send <= '1';
581 dma_send <= '1';
578 dma_valid_burst <= data_f1_data_out_valid_burst;
582 dma_valid_burst <= data_f1_data_out_valid_burst;
579 dma_sel_valid <= data_f1_data_out_valid;
583 dma_sel_valid <= data_f1_data_out_valid;
580 ELSIF dma_rr_grant(2) = '1' THEN
584 ELSIF dma_rr_grant(2) = '1' THEN
585 dma_ms_ongoing <= '0';
581 dma_send <= '1';
586 dma_send <= '1';
582 dma_valid_burst <= data_f2_data_out_valid_burst;
587 dma_valid_burst <= data_f2_data_out_valid_burst;
583 dma_sel_valid <= data_f2_data_out_valid;
588 dma_sel_valid <= data_f2_data_out_valid;
584 ELSIF dma_rr_grant(3) = '1' THEN
589 ELSIF dma_rr_grant(3) = '1' THEN
590 dma_ms_ongoing <= '0';
585 dma_send <= '1';
591 dma_send <= '1';
586 dma_valid_burst <= data_f3_data_out_valid_burst;
592 dma_valid_burst <= data_f3_data_out_valid_burst;
587 dma_sel_valid <= data_f3_data_out_valid;
593 dma_sel_valid <= data_f3_data_out_valid;
588 ELSIF dma_rr_grant(4) = '1' THEN
594 ELSIF dma_rr_grant(4) = '1' THEN
595 dma_ms_ongoing <= '1';
589 dma_send <= '1';
596 dma_send <= '1';
590 dma_valid_burst <= data_ms_valid_burst;
597 dma_valid_burst <= data_ms_valid_burst;
591 dma_sel_valid <= data_ms_valid;
598 dma_sel_valid <= data_ms_valid;
599 ELSE
600 dma_ms_ongoing <= '0';
592 END IF;
601 END IF;
593
602
594 IF dma_sel(4) = '1' THEN
603 IF dma_ms_ongoing = '1' THEN
595 data_ms_done <= '1';
604 data_ms_done <= '1';
596 END IF;
605 END IF;
597 ELSE
606 ELSE
598 dma_sel <= dma_sel;
607 dma_sel <= dma_sel;
599 dma_send <= '0';
608 dma_send <= '0';
600 END IF;
609 END IF;
601 ELSE
610 ELSE
602 data_ms_done <= '0';
611 data_ms_done <= '0';
603 dma_sel <= (OTHERS => '0');
612 dma_sel <= (OTHERS => '0');
604 dma_send <= '0';
613 dma_send <= '0';
605 dma_valid_burst <= '0';
614 dma_valid_burst <= '0';
606 END IF;
615 END IF;
607 END IF;
616 END IF;
608 END PROCESS;
617 END PROCESS;
609
618
610
619
611 dma_address <= data_f0_addr_out WHEN dma_sel(0) = '1' ELSE
620 dma_address <= data_f0_addr_out WHEN dma_sel(0) = '1' ELSE
612 data_f1_addr_out WHEN dma_sel(1) = '1' ELSE
621 data_f1_addr_out WHEN dma_sel(1) = '1' ELSE
613 data_f2_addr_out WHEN dma_sel(2) = '1' ELSE
622 data_f2_addr_out WHEN dma_sel(2) = '1' ELSE
614 data_f3_addr_out WHEN dma_sel(3) = '1' ELSE
623 data_f3_addr_out WHEN dma_sel(3) = '1' ELSE
615 data_ms_addr;
624 data_ms_addr;
616
625
617 dma_data <= data_f0_data_out WHEN dma_sel(0) = '1' ELSE
626 dma_data <= data_f0_data_out WHEN dma_sel(0) = '1' ELSE
618 data_f1_data_out WHEN dma_sel(1) = '1' ELSE
627 data_f1_data_out WHEN dma_sel(1) = '1' ELSE
619 data_f2_data_out WHEN dma_sel(2) = '1' ELSE
628 data_f2_data_out WHEN dma_sel(2) = '1' ELSE
620 data_f3_data_out WHEN dma_sel(3) = '1' ELSE
629 data_f3_data_out WHEN dma_sel(3) = '1' ELSE
621 data_ms_data;
630 data_ms_data;
622
631
623 data_f0_data_out_ren <= dma_ren WHEN dma_sel(0) = '1' ELSE '1';
632 data_f0_data_out_ren <= dma_ren WHEN dma_sel(0) = '1' ELSE '1';
624 data_f1_data_out_ren <= dma_ren WHEN dma_sel(1) = '1' ELSE '1';
633 data_f1_data_out_ren <= dma_ren WHEN dma_sel(1) = '1' ELSE '1';
625 data_f2_data_out_ren <= dma_ren WHEN dma_sel(2) = '1' ELSE '1';
634 data_f2_data_out_ren <= dma_ren WHEN dma_sel(2) = '1' ELSE '1';
626 data_f3_data_out_ren <= dma_ren WHEN dma_sel(3) = '1' ELSE '1';
635 data_f3_data_out_ren <= dma_ren WHEN dma_sel(3) = '1' ELSE '1';
627 data_ms_ren <= dma_ren WHEN dma_sel(4) = '1' ELSE '1';
636 data_ms_ren <= dma_ren WHEN dma_sel(4) = '1' ELSE '1';
628
637
629 dma_data_2 <= dma_data;
638 dma_data_2 <= dma_data;
630
639
631
640
632 -----------------------------------------------------------------------------
641 -----------------------------------------------------------------------------
633 -- DMA
642 -- DMA
634 -----------------------------------------------------------------------------
643 -----------------------------------------------------------------------------
635 lpp_dma_singleOrBurst_1 : lpp_dma_singleOrBurst
644 lpp_dma_singleOrBurst_1 : lpp_dma_singleOrBurst
636 GENERIC MAP (
645 GENERIC MAP (
637 tech => inferred,
646 tech => inferred,
638 hindex => hindex)
647 hindex => hindex)
639 PORT MAP (
648 PORT MAP (
640 HCLK => clk,
649 HCLK => clk,
641 HRESETn => rstn,
650 HRESETn => rstn,
642 run => run,
651 run => run,
643 AHB_Master_In => ahbi,
652 AHB_Master_In => ahbi,
644 AHB_Master_Out => ahbo,
653 AHB_Master_Out => ahbo,
645
654
646 send => dma_send,
655 send => dma_send,
647 valid_burst => dma_valid_burst,
656 valid_burst => dma_valid_burst,
648 done => dma_done,
657 done => dma_done,
649 ren => dma_ren,
658 ren => dma_ren,
650 address => dma_address,
659 address => dma_address,
651 data => dma_data_2);
660 data => dma_data_2);
652
661
653 -----------------------------------------------------------------------------
662 -----------------------------------------------------------------------------
654 -- Matrix Spectral
663 -- Matrix Spectral
655 -----------------------------------------------------------------------------
664 -----------------------------------------------------------------------------
656 sample_f0_wen <= NOT(sample_f0_val) & NOT(sample_f0_val) & NOT(sample_f0_val) &
665 sample_f0_wen <= NOT(sample_f0_val) & NOT(sample_f0_val) & NOT(sample_f0_val) &
657 NOT(sample_f0_val) & NOT(sample_f0_val);
666 NOT(sample_f0_val) & NOT(sample_f0_val);
658 sample_f1_wen <= NOT(sample_f1_val) & NOT(sample_f1_val) & NOT(sample_f1_val) &
667 sample_f1_wen <= NOT(sample_f1_val) & NOT(sample_f1_val) & NOT(sample_f1_val) &
659 NOT(sample_f1_val) & NOT(sample_f1_val);
668 NOT(sample_f1_val) & NOT(sample_f1_val);
660 sample_f3_wen <= NOT(sample_f3_val) & NOT(sample_f3_val) & NOT(sample_f3_val) &
669 sample_f3_wen <= NOT(sample_f3_val) & NOT(sample_f3_val) & NOT(sample_f3_val) &
661 NOT(sample_f3_val) & NOT(sample_f3_val);
670 NOT(sample_f3_val) & NOT(sample_f3_val);
662
671
663 sample_f0_wdata <= sample_f0_data((3*16)-1 DOWNTO (1*16)) & sample_f0_data((6*16)-1 DOWNTO (3*16)); -- (MSB) E2 E1 B2 B1 B0 (LSB)
672 sample_f0_wdata <= sample_f0_data((3*16)-1 DOWNTO (1*16)) & sample_f0_data((6*16)-1 DOWNTO (3*16)); -- (MSB) E2 E1 B2 B1 B0 (LSB)
664 sample_f1_wdata <= sample_f1_data((3*16)-1 DOWNTO (1*16)) & sample_f1_data((6*16)-1 DOWNTO (3*16));
673 sample_f1_wdata <= sample_f1_data((3*16)-1 DOWNTO (1*16)) & sample_f1_data((6*16)-1 DOWNTO (3*16));
665 sample_f3_wdata <= sample_f3_data((3*16)-1 DOWNTO (1*16)) & sample_f3_data((6*16)-1 DOWNTO (3*16));
674 sample_f3_wdata <= sample_f3_data((3*16)-1 DOWNTO (1*16)) & sample_f3_data((6*16)-1 DOWNTO (3*16));
666
675
667 -------------------------------------------------------------------------------
676 -------------------------------------------------------------------------------
668
677
669 ms_softandhard_rstn <= rstn AND run_ms AND run;
678 ms_softandhard_rstn <= rstn AND run_ms AND run;
670
679
671 -----------------------------------------------------------------------------
680 -----------------------------------------------------------------------------
672 lpp_lfr_ms_1 : lpp_lfr_ms
681 lpp_lfr_ms_1 : lpp_lfr_ms
673 GENERIC MAP (
682 GENERIC MAP (
674 Mem_use => Mem_use)
683 Mem_use => Mem_use)
675 PORT MAP (
684 PORT MAP (
676 clk => clk,
685 clk => clk,
677 rstn => ms_softandhard_rstn, --rstn,
686 rstn => ms_softandhard_rstn, --rstn,
678
687
679 coarse_time => coarse_time,
688 coarse_time => coarse_time,
680 fine_time => fine_time,
689 fine_time => fine_time,
681
690
682 sample_f0_wen => sample_f0_wen,
691 sample_f0_wen => sample_f0_wen,
683 sample_f0_wdata => sample_f0_wdata,
692 sample_f0_wdata => sample_f0_wdata,
684 sample_f1_wen => sample_f1_wen,
693 sample_f1_wen => sample_f1_wen,
685 sample_f1_wdata => sample_f1_wdata,
694 sample_f1_wdata => sample_f1_wdata,
686 sample_f2_wen => sample_f3_wen, -- TODO
695 sample_f2_wen => sample_f3_wen, -- TODO
687 sample_f2_wdata => sample_f3_wdata,-- TODO
696 sample_f2_wdata => sample_f3_wdata,-- TODO
688
697
689 dma_addr => data_ms_addr, --
698 dma_addr => data_ms_addr, --
690 dma_data => data_ms_data, --
699 dma_data => data_ms_data, --
691 dma_valid => data_ms_valid, --
700 dma_valid => data_ms_valid, --
692 dma_valid_burst => data_ms_valid_burst, --
701 dma_valid_burst => data_ms_valid_burst, --
693 dma_ren => data_ms_ren, --
702 dma_ren => data_ms_ren, --
694 dma_done => data_ms_done, --
703 dma_done => data_ms_done, --
695
704
696 ready_matrix_f0 => ready_matrix_f0,
705 ready_matrix_f0 => ready_matrix_f0,
697 ready_matrix_f1 => ready_matrix_f1,
706 ready_matrix_f1 => ready_matrix_f1,
698 ready_matrix_f2 => ready_matrix_f2,
707 ready_matrix_f2 => ready_matrix_f2,
699 error_bad_component_error => error_bad_component_error,
708 error_bad_component_error => error_bad_component_error,
700 error_buffer_full => error_buffer_full,
709 error_buffer_full => error_buffer_full,
701 error_input_fifo_write => error_input_fifo_write,
710 error_input_fifo_write => error_input_fifo_write,
702
711
703 debug_reg => debug_ms,--observation_reg,
712 debug_reg => debug_ms,--observation_reg,
704
713
705 status_ready_matrix_f0 => status_ready_matrix_f0,
714 status_ready_matrix_f0 => status_ready_matrix_f0,
706 status_ready_matrix_f1 => status_ready_matrix_f1,
715 status_ready_matrix_f1 => status_ready_matrix_f1,
707 status_ready_matrix_f2 => status_ready_matrix_f2,
716 status_ready_matrix_f2 => status_ready_matrix_f2,
708 config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
717 config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
709 config_active_interruption_onError => config_active_interruption_onError,
718 config_active_interruption_onError => config_active_interruption_onError,
710 addr_matrix_f0 => addr_matrix_f0,
719 addr_matrix_f0 => addr_matrix_f0,
711 addr_matrix_f1 => addr_matrix_f1,
720 addr_matrix_f1 => addr_matrix_f1,
712 addr_matrix_f2 => addr_matrix_f2,
721 addr_matrix_f2 => addr_matrix_f2,
713
722
714 matrix_time_f0 => matrix_time_f0,
723 matrix_time_f0 => matrix_time_f0,
715 matrix_time_f1 => matrix_time_f1,
724 matrix_time_f1 => matrix_time_f1,
716 matrix_time_f2 => matrix_time_f2);
725 matrix_time_f2 => matrix_time_f2);
717
726
718 -----------------------------------------------------------------------------
727 -----------------------------------------------------------------------------
719 observation_reg(31 DOWNTO 0) <= debug_ms(30 DOWNTO 0) & ms_softandhard_rstn;
728 observation_reg(31 DOWNTO 0) <= debug_ms(30 DOWNTO 0) & ms_softandhard_rstn;
720
729
721
730
722 END beh;
731 END beh;
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