##// END OF EJS Templates
update DMA arbiter
pellion -
r374:59891d673686 JC
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@@ -269,6 +269,7 ARCHITECTURE beh OF lpp_lfr IS
269 SIGNAL data_ms_valid_burst : STD_LOGIC;
269 SIGNAL data_ms_valid_burst : STD_LOGIC;
270 SIGNAL data_ms_ren : STD_LOGIC;
270 SIGNAL data_ms_ren : STD_LOGIC;
271 SIGNAL data_ms_done : STD_LOGIC;
271 SIGNAL data_ms_done : STD_LOGIC;
272 SIGNAL dma_ms_ongoing : STD_LOGIC;
272
273
273 SIGNAL run_ms : STD_LOGIC;
274 SIGNAL run_ms : STD_LOGIC;
274 SIGNAL ms_softandhard_rstn : STD_LOGIC;
275 SIGNAL ms_softandhard_rstn : STD_LOGIC;
@@ -564,34 +565,42 BEGIN
564 dma_send <= '0';
565 dma_send <= '0';
565 dma_valid_burst <= '0';
566 dma_valid_burst <= '0';
566 data_ms_done <= '0';
567 data_ms_done <= '0';
568 dma_ms_ongoing <= '0';
567 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
569 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
568 IF run = '1' THEN
570 IF run = '1' THEN
569 data_ms_done <= '0';
571 data_ms_done <= '0';
570 IF dma_sel = "00000" OR dma_done = '1' THEN
572 IF dma_sel = "00000" OR dma_done = '1' THEN
571 dma_sel <= dma_rr_grant;
573 dma_sel <= dma_rr_grant;
572 IF dma_rr_grant(0) = '1' THEN
574 IF dma_rr_grant(0) = '1' THEN
575 dma_ms_ongoing <= '0';
573 dma_send <= '1';
576 dma_send <= '1';
574 dma_valid_burst <= data_f0_data_out_valid_burst;
577 dma_valid_burst <= data_f0_data_out_valid_burst;
575 dma_sel_valid <= data_f0_data_out_valid;
578 dma_sel_valid <= data_f0_data_out_valid;
576 ELSIF dma_rr_grant(1) = '1' THEN
579 ELSIF dma_rr_grant(1) = '1' THEN
580 dma_ms_ongoing <= '0';
577 dma_send <= '1';
581 dma_send <= '1';
578 dma_valid_burst <= data_f1_data_out_valid_burst;
582 dma_valid_burst <= data_f1_data_out_valid_burst;
579 dma_sel_valid <= data_f1_data_out_valid;
583 dma_sel_valid <= data_f1_data_out_valid;
580 ELSIF dma_rr_grant(2) = '1' THEN
584 ELSIF dma_rr_grant(2) = '1' THEN
585 dma_ms_ongoing <= '0';
581 dma_send <= '1';
586 dma_send <= '1';
582 dma_valid_burst <= data_f2_data_out_valid_burst;
587 dma_valid_burst <= data_f2_data_out_valid_burst;
583 dma_sel_valid <= data_f2_data_out_valid;
588 dma_sel_valid <= data_f2_data_out_valid;
584 ELSIF dma_rr_grant(3) = '1' THEN
589 ELSIF dma_rr_grant(3) = '1' THEN
590 dma_ms_ongoing <= '0';
585 dma_send <= '1';
591 dma_send <= '1';
586 dma_valid_burst <= data_f3_data_out_valid_burst;
592 dma_valid_burst <= data_f3_data_out_valid_burst;
587 dma_sel_valid <= data_f3_data_out_valid;
593 dma_sel_valid <= data_f3_data_out_valid;
588 ELSIF dma_rr_grant(4) = '1' THEN
594 ELSIF dma_rr_grant(4) = '1' THEN
595 dma_ms_ongoing <= '1';
589 dma_send <= '1';
596 dma_send <= '1';
590 dma_valid_burst <= data_ms_valid_burst;
597 dma_valid_burst <= data_ms_valid_burst;
591 dma_sel_valid <= data_ms_valid;
598 dma_sel_valid <= data_ms_valid;
599 ELSE
600 dma_ms_ongoing <= '0';
592 END IF;
601 END IF;
593
602
594 IF dma_sel(4) = '1' THEN
603 IF dma_ms_ongoing = '1' THEN
595 data_ms_done <= '1';
604 data_ms_done <= '1';
596 END IF;
605 END IF;
597 ELSE
606 ELSE
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