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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe PELLION
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
22
23 LIBRARY IEEE;
24 USE IEEE.numeric_std.ALL;
25 USE IEEE.std_logic_1164.ALL;
26
27 LIBRARY techmap;
28 USE techmap.gencomp.ALL;
29
30 LIBRARY lpp;
31 USE lpp.iir_filter.ALL;
32 USE lpp.general_purpose.ALL;
33
34 ENTITY IIR_CEL_CTRLR_v3 IS
35 GENERIC (
36 tech : INTEGER := 0;
37 Mem_use : INTEGER := use_RAM;
38 Sample_SZ : INTEGER := 18;
39 Coef_SZ : INTEGER := 9;
40 Coef_Nb : INTEGER := 25;
41 Coef_sel_SZ : INTEGER := 5;
42 Cels_count : INTEGER := 5;
43 ChanelsCount : INTEGER := 8);
44 PORT (
45 rstn : IN STD_LOGIC;
46 clk : IN STD_LOGIC;
47
48 virg_pos : IN INTEGER;
49 coefs : IN STD_LOGIC_VECTOR((Coef_SZ*Coef_Nb)-1 DOWNTO 0);
50
51 sample_in1_val : IN STD_LOGIC;
52 sample_in1 : IN samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
53 sample_in2_val : IN STD_LOGIC;
54 sample_in2 : IN samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
55
56 sample_out1_val : OUT STD_LOGIC;
57 sample_out1 : OUT samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
58 sample_out2_val : OUT STD_LOGIC;
59 sample_out2 : OUT samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0));
60 END IIR_CEL_CTRLR_v3;
61
62 ARCHITECTURE ar_IIR_CEL_CTRLR_v3 OF IIR_CEL_CTRLR_v3 IS
63
64 COMPONENT RAM_CTRLR_v2
65 GENERIC (
66 tech : INTEGER;
67 Input_SZ_1 : INTEGER;
68 Mem_use : INTEGER);
69 PORT (
70 rstn : IN STD_LOGIC;
71 clk : IN STD_LOGIC;
72 ram_write : IN STD_LOGIC;
73 ram_read : IN STD_LOGIC;
74 raddr_rst : IN STD_LOGIC;
75 raddr_add1 : IN STD_LOGIC;
76 waddr_previous : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
77 sample_in : IN STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0);
78 sample_out : OUT STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0));
79 END COMPONENT;
80
81 COMPONENT IIR_CEL_CTRLR_v3_DATAFLOW
82 GENERIC (
83 Sample_SZ : INTEGER;
84 Coef_SZ : INTEGER;
85 Coef_Nb : INTEGER;
86 Coef_sel_SZ : INTEGER);
87 PORT (
88 rstn : IN STD_LOGIC;
89 clk : IN STD_LOGIC;
90 virg_pos : IN INTEGER;
91 coefs : IN STD_LOGIC_VECTOR((Coef_SZ*Coef_Nb)-1 DOWNTO 0);
92 in_sel_src : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
93 ram_sel_Wdata : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
94 ram_input : OUT STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
95 ram_output : IN STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
96 alu_sel_input : IN STD_LOGIC;
97 alu_sel_coeff : IN STD_LOGIC_VECTOR(Coef_sel_SZ-1 DOWNTO 0);
98 alu_ctrl : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
99 alu_comp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
100 sample_in : IN STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
101 sample_out : OUT STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0));
102 END COMPONENT;
103
104 COMPONENT IIR_CEL_CTRLR_v2_CONTROL
105 GENERIC (
106 Coef_sel_SZ : INTEGER;
107 Cels_count : INTEGER;
108 ChanelsCount : INTEGER);
109 PORT (
110 rstn : IN STD_LOGIC;
111 clk : IN STD_LOGIC;
112 sample_in_val : IN STD_LOGIC;
113 sample_in_rot : OUT STD_LOGIC;
114 sample_out_val : OUT STD_LOGIC;
115 sample_out_rot : OUT STD_LOGIC;
116 in_sel_src : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
117 ram_sel_Wdata : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
118 ram_write : OUT STD_LOGIC;
119 ram_read : OUT STD_LOGIC;
120 raddr_rst : OUT STD_LOGIC;
121 raddr_add1 : OUT STD_LOGIC;
122 waddr_previous : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
123 alu_sel_input : OUT STD_LOGIC;
124 alu_sel_coeff : OUT STD_LOGIC_VECTOR(Coef_sel_SZ-1 DOWNTO 0);
125 alu_ctrl : OUT STD_LOGIC_VECTOR(2 DOWNTO 0));
126 END COMPONENT;
127
128 SIGNAL in_sel_src : STD_LOGIC_VECTOR(1 DOWNTO 0);
129 SIGNAL ram_sel_Wdata : STD_LOGIC_VECTOR(1 DOWNTO 0);
130 SIGNAL ram_write : STD_LOGIC;
131 SIGNAL ram_read : STD_LOGIC;
132 SIGNAL raddr_rst : STD_LOGIC;
133 SIGNAL raddr_add1 : STD_LOGIC;
134 SIGNAL waddr_previous : STD_LOGIC_VECTOR(1 DOWNTO 0);
135 SIGNAL alu_sel_input : STD_LOGIC;
136 SIGNAL alu_sel_coeff : STD_LOGIC_VECTOR(Coef_sel_SZ-1 DOWNTO 0);
137 SIGNAL alu_ctrl : STD_LOGIC_VECTOR(2 DOWNTO 0);
138
139 SIGNAL sample_in_buf : samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
140 SIGNAL sample_in_rotate : STD_LOGIC;
141 SIGNAL sample_in_s : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
142 SIGNAL sample_out_val_s : STD_LOGIC;
143 SIGNAL sample_out_val_s2 : STD_LOGIC;
144 SIGNAL sample_out_rot_s : STD_LOGIC;
145 SIGNAL sample_out_s : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
146
147 SIGNAL sample_out_s2 : samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
148
149 SIGNAL ram_input : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
150 SIGNAL ram_output : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
151 --
152 SIGNAL sample_in_val : STD_LOGIC;
153 SIGNAL sample_in : samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
154 SIGNAL sample_out_val : STD_LOGIC;
155 SIGNAL sample_out : samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
156
157 -----------------------------------------------------------------------------
158 --
159 -----------------------------------------------------------------------------
160 SIGNAL CHANNEL_SEL : STD_LOGIC;
161
162 SIGNAL ram_output_1 : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
163 SIGNAL ram_output_2 : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
164
165 SIGNAL ram_write_1 : STD_LOGIC;
166 SIGNAL ram_read_1 : STD_LOGIC;
167 SIGNAL raddr_rst_1 : STD_LOGIC;
168 SIGNAL raddr_add1_1 : STD_LOGIC;
169 SIGNAL waddr_previous_1 : STD_LOGIC_VECTOR(1 DOWNTO 0);
170
171 SIGNAL ram_write_2 : STD_LOGIC;
172 SIGNAL ram_read_2 : STD_LOGIC;
173 SIGNAL raddr_rst_2 : STD_LOGIC;
174 SIGNAL raddr_add1_2 : STD_LOGIC;
175 SIGNAL waddr_previous_2 : STD_LOGIC_VECTOR(1 DOWNTO 0);
176 -----------------------------------------------------------------------------
177 SIGNAL channel_ready : STD_LOGIC_VECTOR(1 DOWNTO 0);
178 SIGNAL channel_val : STD_LOGIC_VECTOR(1 DOWNTO 0);
179 SIGNAL channel_done : STD_LOGIC_VECTOR(1 DOWNTO 0);
180 -----------------------------------------------------------------------------
181 TYPE FSM_CHANNEL_SELECTION IS (IDLE, ONGOING_1, ONGOING_2, WAIT_STATE);
182 SIGNAL state_channel_selection : FSM_CHANNEL_SELECTION;
183
184 SIGNAL sample_out_zero : samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
185
186 BEGIN
187
188 -----------------------------------------------------------------------------
189 channel_val(0) <= sample_in1_val;
190 channel_val(1) <= sample_in2_val;
191 all_channel_input_valid: FOR I IN 1 DOWNTO 0 GENERATE
192 PROCESS (clk, rstn)
193 BEGIN -- PROCESS
194 IF rstn = '0' THEN -- asynchronous reset (active low)
195 channel_ready(I) <= '0';
196 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
197 IF channel_val(I) = '1' THEN
198 channel_ready(I) <= '1';
199 ELSIF channel_done(I) = '1' THEN
200 channel_ready(I) <= '0';
201 END IF;
202 END IF;
203 END PROCESS;
204 END GENERATE all_channel_input_valid;
205 -----------------------------------------------------------------------------
206 all_channel_sample_out: FOR I IN ChanelsCount-1 DOWNTO 0 GENERATE
207 all_bit: FOR J IN Sample_SZ-1 DOWNTO 0 GENERATE
208 sample_out_zero(I,J) <= '0';
209 END GENERATE all_bit;
210 END GENERATE all_channel_sample_out;
211
212 PROCESS (clk, rstn)
213 BEGIN -- PROCESS
214 IF rstn = '0' THEN -- asynchronous reset (active low)
215 state_channel_selection <= IDLE;
216 CHANNEL_SEL <= '0';
217 sample_in_val <= '0';
218 sample_out1_val <= '0';
219 sample_out2_val <= '0';
220 sample_out1 <= sample_out_zero;
221 sample_out2 <= sample_out_zero;
222 channel_done <= "00";
223
224 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
225 CASE state_channel_selection IS
226 WHEN IDLE =>
227 CHANNEL_SEL <= '0';
228 sample_in_val <= '0';
229 sample_out1_val <= '0';
230 sample_out2_val <= '0';
231 channel_done <= "00";
232 IF channel_ready(0) = '1' THEN
233 state_channel_selection <= ONGOING_1;
234 CHANNEL_SEL <= '0';
235 sample_in_val <= '1';
236 ELSIF channel_ready(1) = '1' THEN
237 state_channel_selection <= ONGOING_2;
238 CHANNEL_SEL <= '1';
239 sample_in_val <= '1';
240 END IF;
241 WHEN ONGOING_1 =>
242 sample_in_val <= '0';
243 IF sample_out_val = '1' THEN
244 state_channel_selection <= WAIT_STATE;
245 sample_out1 <= sample_out;
246 sample_out1_val <= '1';
247 channel_done(0) <= '1';
248 END IF;
249 WHEN ONGOING_2 =>
250 sample_in_val <= '0';
251 IF sample_out_val = '1' THEN
252 state_channel_selection <= WAIT_STATE;
253 sample_out2 <= sample_out;
254 sample_out2_val <= '1';
255 channel_done(1) <= '1';
256 END IF;
257 WHEN WAIT_STATE =>
258 state_channel_selection <= IDLE;
259 CHANNEL_SEL <= '0';
260 sample_in_val <= '0';
261 sample_out1_val <= '0';
262 sample_out2_val <= '0';
263 channel_done <= "00";
264
265 WHEN OTHERS => NULL;
266 END CASE;
267
268 END IF;
269 END PROCESS;
270
271 sample_in <= sample_in1 WHEN CHANNEL_SEL = '0' ELSE sample_in2;
272 -----------------------------------------------------------------------------
273 ram_output <= ram_output_1 WHEN CHANNEL_SEL = '0' ELSE
274 ram_output_2;
275
276 ram_write_1 <= ram_write WHEN CHANNEL_SEL = '0' ELSE '0';
277 ram_read_1 <= ram_read WHEN CHANNEL_SEL = '0' ELSE '0';
278 raddr_rst_1 <= raddr_rst WHEN CHANNEL_SEL = '0' ELSE '1';
279 raddr_add1_1 <= raddr_add1 WHEN CHANNEL_SEL = '0' ELSE '0';
280 waddr_previous_1 <= waddr_previous WHEN CHANNEL_SEL = '0' ELSE "00";
281
282 ram_write_2 <= ram_write WHEN CHANNEL_SEL = '1' ELSE '0';
283 ram_read_2 <= ram_read WHEN CHANNEL_SEL = '1' ELSE '0';
284 raddr_rst_2 <= raddr_rst WHEN CHANNEL_SEL = '1' ELSE '1';
285 raddr_add1_2 <= raddr_add1 WHEN CHANNEL_SEL = '1' ELSE '0';
286 waddr_previous_2 <= waddr_previous WHEN CHANNEL_SEL = '1' ELSE "00";
287
288 RAM_CTRLR_v2_1: RAM_CTRLR_v2
289 GENERIC MAP (
290 tech => tech,
291 Input_SZ_1 => Sample_SZ,
292 Mem_use => Mem_use)
293 PORT MAP (
294 clk => clk,
295 rstn => rstn,
296 ram_write => ram_write_1,
297 ram_read => ram_read_1,
298 raddr_rst => raddr_rst_1,
299 raddr_add1 => raddr_add1_1,
300 waddr_previous => waddr_previous_1,
301 sample_in => ram_input,
302 sample_out => ram_output_1);
303
304 RAM_CTRLR_v2_2: RAM_CTRLR_v2
305 GENERIC MAP (
306 tech => tech,
307 Input_SZ_1 => Sample_SZ,
308 Mem_use => Mem_use)
309 PORT MAP (
310 clk => clk,
311 rstn => rstn,
312 ram_write => ram_write_2,
313 ram_read => ram_read_2,
314 raddr_rst => raddr_rst_2,
315 raddr_add1 => raddr_add1_2,
316 waddr_previous => waddr_previous_2,
317 sample_in => ram_input,
318 sample_out => ram_output_2);
319 -----------------------------------------------------------------------------
320
321 IIR_CEL_CTRLR_v3_DATAFLOW_1 : IIR_CEL_CTRLR_v3_DATAFLOW
322 GENERIC MAP (
323 Sample_SZ => Sample_SZ,
324 Coef_SZ => Coef_SZ,
325 Coef_Nb => Coef_Nb,
326 Coef_sel_SZ => Coef_sel_SZ)
327 PORT MAP (
328 rstn => rstn,
329 clk => clk,
330 virg_pos => virg_pos,
331 coefs => coefs,
332 --CTRL
333 in_sel_src => in_sel_src,
334 ram_sel_Wdata => ram_sel_Wdata,
335 --
336 ram_input => ram_input,
337 ram_output => ram_output,
338 --
339 alu_sel_input => alu_sel_input,
340 alu_sel_coeff => alu_sel_coeff,
341 alu_ctrl => alu_ctrl,
342 alu_comp => "00",
343 --DATA
344 sample_in => sample_in_s,
345 sample_out => sample_out_s);
346 -----------------------------------------------------------------------------
347
348
349 IIR_CEL_CTRLR_v3_CONTROL_1 : IIR_CEL_CTRLR_v2_CONTROL
350 GENERIC MAP (
351 Coef_sel_SZ => Coef_sel_SZ,
352 Cels_count => Cels_count,
353 ChanelsCount => ChanelsCount)
354 PORT MAP (
355 rstn => rstn,
356 clk => clk,
357 sample_in_val => sample_in_val,
358 sample_in_rot => sample_in_rotate,
359 sample_out_val => sample_out_val_s,
360 sample_out_rot => sample_out_rot_s,
361
362 in_sel_src => in_sel_src,
363 ram_sel_Wdata => ram_sel_Wdata,
364 ram_write => ram_write,
365 ram_read => ram_read,
366 raddr_rst => raddr_rst,
367 raddr_add1 => raddr_add1,
368 waddr_previous => waddr_previous,
369 alu_sel_input => alu_sel_input,
370 alu_sel_coeff => alu_sel_coeff,
371 alu_ctrl => alu_ctrl);
372
373 -----------------------------------------------------------------------------
374 -- SAMPLE IN
375 -----------------------------------------------------------------------------
376 loop_all_sample : FOR J IN Sample_SZ-1 DOWNTO 0 GENERATE
377
378 loop_all_chanel : FOR I IN ChanelsCount-1 DOWNTO 0 GENERATE
379 PROCESS (clk, rstn)
380 BEGIN -- PROCESS
381 IF rstn = '0' THEN -- asynchronous reset (active low)
382 sample_in_buf(I, J) <= '0';
383 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
384 IF sample_in_val = '1' THEN
385 sample_in_buf(I, J) <= sample_in(I, J);
386 ELSIF sample_in_rotate = '1' THEN
387 sample_in_buf(I, J) <= sample_in_buf((I+1) MOD ChanelsCount, J);
388 END IF;
389 END IF;
390 END PROCESS;
391 END GENERATE loop_all_chanel;
392
393 sample_in_s(J) <= sample_in(0, J) WHEN sample_in_val = '1' ELSE sample_in_buf(0, J);
394
395 END GENERATE loop_all_sample;
396
397 -----------------------------------------------------------------------------
398 -- SAMPLE OUT
399 -----------------------------------------------------------------------------
400 PROCESS (clk, rstn)
401 BEGIN -- PROCESS
402 IF rstn = '0' THEN -- asynchronous reset (active low)
403 sample_out_val <= '0';
404 sample_out_val_s2 <= '0';
405 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
406 sample_out_val <= sample_out_val_s2;
407 sample_out_val_s2 <= sample_out_val_s;
408 END IF;
409 END PROCESS;
410
411 chanel_HIGH : FOR I IN Sample_SZ-1 DOWNTO 0 GENERATE
412 PROCESS (clk, rstn)
413 BEGIN -- PROCESS
414 IF rstn = '0' THEN -- asynchronous reset (active low)
415 sample_out_s2(ChanelsCount-1, I) <= '0';
416 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
417 IF sample_out_rot_s = '1' THEN
418 sample_out_s2(ChanelsCount-1, I) <= sample_out_s(I);
419 END IF;
420 END IF;
421 END PROCESS;
422 END GENERATE chanel_HIGH;
423
424 chanel_more : IF ChanelsCount > 1 GENERATE
425 all_chanel : FOR J IN ChanelsCount-1 DOWNTO 1 GENERATE
426 all_bit : FOR I IN Sample_SZ-1 DOWNTO 0 GENERATE
427 PROCESS (clk, rstn)
428 BEGIN -- PROCESS
429 IF rstn = '0' THEN -- asynchronous reset (active low)
430 sample_out_s2(J-1, I) <= '0';
431 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
432 IF sample_out_rot_s = '1' THEN
433 sample_out_s2(J-1, I) <= sample_out_s2(J, I);
434 END IF;
435 END IF;
436 END PROCESS;
437 END GENERATE all_bit;
438 END GENERATE all_chanel;
439 END GENERATE chanel_more;
440
441 sample_out <= sample_out_s2;
442 END ar_IIR_CEL_CTRLR_v3;
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@@ -0,0 +1,213
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe PELLION
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
22 LIBRARY IEEE;
23 USE IEEE.numeric_std.ALL;
24 USE IEEE.std_logic_1164.ALL;
25 LIBRARY lpp;
26 USE lpp.iir_filter.ALL;
27 USE lpp.general_purpose.ALL;
28
29
30
31 ENTITY IIR_CEL_CTRLR_v3_DATAFLOW IS
32 GENERIC(
33 Sample_SZ : INTEGER := 16;
34 Coef_SZ : INTEGER := 9;
35 Coef_Nb : INTEGER := 30;
36 Coef_sel_SZ : INTEGER := 5
37 );
38 PORT(
39 rstn : IN STD_LOGIC;
40 clk : IN STD_LOGIC;
41 -- PARAMETER
42 virg_pos : IN INTEGER;
43 coefs : IN STD_LOGIC_VECTOR((Coef_SZ*Coef_Nb)-1 DOWNTO 0);
44 -- CONTROL
45 in_sel_src : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
46 --
47 ram_sel_Wdata : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
48 --
49 ram_input : OUT STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
50 ram_output : IN STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
51
52 --
53 alu_sel_input : IN STD_LOGIC;
54 alu_sel_coeff : IN STD_LOGIC_VECTOR(Coef_sel_SZ-1 DOWNTO 0);
55 alu_ctrl : IN STD_LOGIC_VECTOR(2 DOWNTO 0);--(MAC_op, MULT_with_clear_ADD, IDLE)
56 alu_comp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
57 -- DATA
58 sample_in : IN STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
59 sample_out : OUT STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0)
60 );
61 END IIR_CEL_CTRLR_v3_DATAFLOW;
62
63 ARCHITECTURE ar_IIR_CEL_CTRLR_v3_DATAFLOW OF IIR_CEL_CTRLR_v3_DATAFLOW IS
64
65 SIGNAL reg_sample_in : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
66 SIGNAL alu_output : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
67 SIGNAL alu_sample : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
68 SIGNAL alu_output_s : STD_LOGIC_VECTOR(Sample_SZ+Coef_SZ-1 DOWNTO 0);
69
70 SIGNAL arrayCoeff : MUX_INPUT_TYPE(0 TO (2**Coef_sel_SZ)-1,Coef_SZ-1 DOWNTO 0);
71 SIGNAL alu_coef_s : MUX_OUTPUT_TYPE(Coef_SZ-1 DOWNTO 0);
72
73 SIGNAL alu_coef : STD_LOGIC_VECTOR(Coef_SZ-1 DOWNTO 0);
74
75 BEGIN
76
77 -----------------------------------------------------------------------------
78 -- INPUT
79 -----------------------------------------------------------------------------
80 PROCESS (clk, rstn)
81 BEGIN -- PROCESS
82 IF rstn = '0' THEN -- asynchronous reset (active low)
83 reg_sample_in <= (OTHERS => '0');
84 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
85 CASE in_sel_src IS
86 WHEN "00" => reg_sample_in <= reg_sample_in;
87 WHEN "01" => reg_sample_in <= sample_in;
88 WHEN "10" => reg_sample_in <= ram_output;
89 WHEN "11" => reg_sample_in <= alu_output;
90 WHEN OTHERS => NULL;
91 END CASE;
92 END IF;
93 END PROCESS;
94
95
96 -----------------------------------------------------------------------------
97 -- RAM + CTRL
98 -----------------------------------------------------------------------------
99
100 ram_input <= reg_sample_in WHEN ram_sel_Wdata = "00" ELSE
101 alu_output WHEN ram_sel_Wdata = "01" ELSE
102 ram_output;
103
104 -----------------------------------------------------------------------------
105 -- MAC_ACC
106 -----------------------------------------------------------------------------
107 -- Control : mac_ctrl (MAC_op, MULT_with_clear_ADD, IDLE)
108 -- Data In : mac_sample, mac_coef
109 -- Data Out: mac_output
110
111 alu_sample <= reg_sample_in WHEN alu_sel_input = '0' ELSE ram_output;
112
113 coefftable: FOR I IN 0 TO (2**Coef_sel_SZ)-1 GENERATE
114 coeff_in: IF I < Coef_Nb GENERATE
115 all_bit: FOR J IN Coef_SZ-1 DOWNTO 0 GENERATE
116 arrayCoeff(I,J) <= coefs(Coef_SZ*I+J);
117 END GENERATE all_bit;
118 END GENERATE coeff_in;
119 coeff_null: IF I > (Coef_Nb -1) GENERATE
120 all_bit: FOR J IN Coef_SZ-1 DOWNTO 0 GENERATE
121 arrayCoeff(I,J) <= '0';
122 END GENERATE all_bit;
123 END GENERATE coeff_null;
124 END GENERATE coefftable;
125
126 Coeff_Mux : MUXN
127 GENERIC MAP (
128 Input_SZ => Coef_SZ,
129 NbStage => Coef_sel_SZ)
130 PORT MAP (
131 sel => alu_sel_coeff,
132 INPUT => arrayCoeff,
133 RES => alu_coef_s);
134
135
136 all_bit: FOR J IN Coef_SZ-1 DOWNTO 0 GENERATE
137 alu_coef(J) <= alu_coef_s(J);
138 END GENERATE all_bit;
139
140 -----------------------------------------------------------------------------
141 -- TODO : just for Synthesis test
142
143 --PROCESS (clk, rstn)
144 --BEGIN
145 -- IF rstn = '0' THEN
146 -- alu_coef <= (OTHERS => '0');
147 -- ELSIF clk'event AND clk = '1' THEN
148 -- all_bit: FOR J IN Coef_SZ-1 DOWNTO 0 LOOP
149 -- alu_coef(J) <= alu_coef_s(J);
150 -- END LOOP all_bit;
151 -- END IF;
152 --END PROCESS;
153
154 -----------------------------------------------------------------------------
155
156
157 ALU_1: ALU
158 GENERIC MAP (
159 Arith_en => 1,
160 Input_SZ_1 => Sample_SZ,
161 Input_SZ_2 => Coef_SZ,
162 COMP_EN => 1)
163 PORT MAP (
164 clk => clk,
165 reset => rstn,
166 ctrl => alu_ctrl,
167 comp => alu_comp,
168 OP1 => alu_sample,
169 OP2 => alu_coef,
170 RES => alu_output_s);
171
172 alu_output <= alu_output_s(Sample_SZ+virg_pos-1 DOWNTO virg_pos);
173
174 sample_out <= alu_output;
175
176 END ar_IIR_CEL_CTRLR_v3_DATAFLOW;
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Show file before | Show file after | Hide comments
@@ -1,443 +1,443
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
21 -------------------------------------------------------------------------------
22 LIBRARY IEEE;
22 LIBRARY IEEE;
23 USE IEEE.numeric_std.ALL;
23 USE IEEE.numeric_std.ALL;
24 USE IEEE.std_logic_1164.ALL;
24 USE IEEE.std_logic_1164.ALL;
25 LIBRARY grlib;
25 LIBRARY grlib;
26 USE grlib.amba.ALL;
26 USE grlib.amba.ALL;
27 USE grlib.stdlib.ALL;
27 USE grlib.stdlib.ALL;
28 LIBRARY techmap;
28 LIBRARY techmap;
29 USE techmap.gencomp.ALL;
29 USE techmap.gencomp.ALL;
30 LIBRARY gaisler;
30 LIBRARY gaisler;
31 USE gaisler.memctrl.ALL;
31 USE gaisler.memctrl.ALL;
32 USE gaisler.leon3.ALL;
32 USE gaisler.leon3.ALL;
33 USE gaisler.uart.ALL;
33 USE gaisler.uart.ALL;
34 USE gaisler.misc.ALL;
34 USE gaisler.misc.ALL;
35 USE gaisler.spacewire.ALL;
35 USE gaisler.spacewire.ALL;
36 LIBRARY esa;
36 LIBRARY esa;
37 USE esa.memoryctrl.ALL;
37 USE esa.memoryctrl.ALL;
38 LIBRARY lpp;
38 LIBRARY lpp;
39 USE lpp.lpp_memory.ALL;
39 USE lpp.lpp_memory.ALL;
40 USE lpp.lpp_ad_conv.ALL;
40 USE lpp.lpp_ad_conv.ALL;
41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
43 USE lpp.iir_filter.ALL;
43 USE lpp.iir_filter.ALL;
44 USE lpp.general_purpose.ALL;
44 USE lpp.general_purpose.ALL;
45 USE lpp.lpp_lfr_management.ALL;
45 USE lpp.lpp_lfr_management.ALL;
46 USE lpp.lpp_leon3_soc_pkg.ALL;
46 USE lpp.lpp_leon3_soc_pkg.ALL;
47
47
48 ENTITY LFR_em IS
48 ENTITY LFR_em IS
49
49
50 PORT (
50 PORT (
51 clk100MHz : IN STD_ULOGIC;
51 clk100MHz : IN STD_ULOGIC;
52 clk49_152MHz : IN STD_ULOGIC;
52 clk49_152MHz : IN STD_ULOGIC;
53 reset : IN STD_ULOGIC;
53 reset : IN STD_ULOGIC;
54
54
55 -- TAG --------------------------------------------------------------------
55 -- TAG --------------------------------------------------------------------
56 TAG1 : IN STD_ULOGIC; -- DSU rx data
56 TAG1 : IN STD_ULOGIC; -- DSU rx data
57 TAG3 : OUT STD_ULOGIC; -- DSU tx data
57 TAG3 : OUT STD_ULOGIC; -- DSU tx data
58 -- UART APB ---------------------------------------------------------------
58 -- UART APB ---------------------------------------------------------------
59 TAG2 : IN STD_ULOGIC; -- UART1 rx data
59 TAG2 : IN STD_ULOGIC; -- UART1 rx data
60 TAG4 : OUT STD_ULOGIC; -- UART1 tx data
60 TAG4 : OUT STD_ULOGIC; -- UART1 tx data
61 -- RAM --------------------------------------------------------------------
61 -- RAM --------------------------------------------------------------------
62 address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
62 address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
63 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
63 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
64 nSRAM_BE0 : OUT STD_LOGIC;
64 nSRAM_BE0 : OUT STD_LOGIC;
65 nSRAM_BE1 : OUT STD_LOGIC;
65 nSRAM_BE1 : OUT STD_LOGIC;
66 nSRAM_BE2 : OUT STD_LOGIC;
66 nSRAM_BE2 : OUT STD_LOGIC;
67 nSRAM_BE3 : OUT STD_LOGIC;
67 nSRAM_BE3 : OUT STD_LOGIC;
68 nSRAM_WE : OUT STD_LOGIC;
68 nSRAM_WE : OUT STD_LOGIC;
69 nSRAM_CE : OUT STD_LOGIC;
69 nSRAM_CE : OUT STD_LOGIC;
70 nSRAM_OE : OUT STD_LOGIC;
70 nSRAM_OE : OUT STD_LOGIC;
71 -- SPW --------------------------------------------------------------------
71 -- SPW --------------------------------------------------------------------
72 spw1_din : IN STD_LOGIC;
72 spw1_din : IN STD_LOGIC;
73 spw1_sin : IN STD_LOGIC;
73 spw1_sin : IN STD_LOGIC;
74 spw1_dout : OUT STD_LOGIC;
74 spw1_dout : OUT STD_LOGIC;
75 spw1_sout : OUT STD_LOGIC;
75 spw1_sout : OUT STD_LOGIC;
76 spw2_din : IN STD_LOGIC;
76 spw2_din : IN STD_LOGIC;
77 spw2_sin : IN STD_LOGIC;
77 spw2_sin : IN STD_LOGIC;
78 spw2_dout : OUT STD_LOGIC;
78 spw2_dout : OUT STD_LOGIC;
79 spw2_sout : OUT STD_LOGIC;
79 spw2_sout : OUT STD_LOGIC;
80 -- ADC --------------------------------------------------------------------
80 -- ADC --------------------------------------------------------------------
81 bias_fail_sw : OUT STD_LOGIC;
81 bias_fail_sw : OUT STD_LOGIC;
82 ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
82 ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
83 ADC_smpclk : OUT STD_LOGIC;
83 ADC_smpclk : OUT STD_LOGIC;
84 ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
84 ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
85 -- HK ---------------------------------------------------------------------
85 -- HK ---------------------------------------------------------------------
86 HK_smpclk : OUT STD_LOGIC;
86 HK_smpclk : OUT STD_LOGIC;
87 ADC_OEB_bar_HK : OUT STD_LOGIC;
87 ADC_OEB_bar_HK : OUT STD_LOGIC;
88 HK_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
88 HK_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
89 ---------------------------------------------------------------------------
89 ---------------------------------------------------------------------------
90 TAG8 : OUT STD_LOGIC;
90 TAG8 : OUT STD_LOGIC;
91 led : OUT STD_LOGIC_VECTOR(2 DOWNTO 0)
91 led : OUT STD_LOGIC_VECTOR(2 DOWNTO 0)
92 );
92 );
93
93
94 END LFR_em;
94 END LFR_em;
95
95
96
96
97 ARCHITECTURE beh OF LFR_em IS
97 ARCHITECTURE beh OF LFR_em IS
98 SIGNAL clk_50_s : STD_LOGIC := '0';
98 SIGNAL clk_50_s : STD_LOGIC := '0';
99 SIGNAL clk_25 : STD_LOGIC := '0';
99 SIGNAL clk_25 : STD_LOGIC := '0';
100 SIGNAL clk_24 : STD_LOGIC := '0';
100 SIGNAL clk_24 : STD_LOGIC := '0';
101 -----------------------------------------------------------------------------
101 -----------------------------------------------------------------------------
102 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
102 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
103 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
103 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
104
104
105 -- CONSTANTS
105 -- CONSTANTS
106 CONSTANT CFG_PADTECH : INTEGER := inferred;
106 CONSTANT CFG_PADTECH : INTEGER := inferred;
107 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
107 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
108 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
108 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
109 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
109 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
110
110
111 SIGNAL apbi_ext : apb_slv_in_type;
111 SIGNAL apbi_ext : apb_slv_in_type;
112 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
112 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
113 SIGNAL ahbi_s_ext : ahb_slv_in_type;
113 SIGNAL ahbi_s_ext : ahb_slv_in_type;
114 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none);
114 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none);
115 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
115 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
116 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
116 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
117
117
118 -- Spacewire signals
118 -- Spacewire signals
119 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
119 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
120 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
120 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
121 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
121 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
122 SIGNAL spw_rxtxclk : STD_ULOGIC;
122 SIGNAL spw_rxtxclk : STD_ULOGIC;
123 SIGNAL spw_rxclkn : STD_ULOGIC;
123 SIGNAL spw_rxclkn : STD_ULOGIC;
124 SIGNAL spw_clk : STD_LOGIC;
124 SIGNAL spw_clk : STD_LOGIC;
125 SIGNAL swni : grspw_in_type;
125 SIGNAL swni : grspw_in_type;
126 SIGNAL swno : grspw_out_type;
126 SIGNAL swno : grspw_out_type;
127
127
128 --GPIO
128 --GPIO
129 SIGNAL gpioi : gpio_in_type;
129 SIGNAL gpioi : gpio_in_type;
130 SIGNAL gpioo : gpio_out_type;
130 SIGNAL gpioo : gpio_out_type;
131
131
132 -- AD Converter ADS7886
132 -- AD Converter ADS7886
133 SIGNAL sample : Samples14v(8 DOWNTO 0);
133 SIGNAL sample : Samples14v(8 DOWNTO 0);
134 SIGNAL sample_s : Samples(8 DOWNTO 0);
134 SIGNAL sample_s : Samples(8 DOWNTO 0);
135 SIGNAL sample_val : STD_LOGIC;
135 SIGNAL sample_val : STD_LOGIC;
136 SIGNAL ADC_OEB_bar_CH_s : STD_LOGIC_VECTOR(8 DOWNTO 0);
136 SIGNAL ADC_OEB_bar_CH_s : STD_LOGIC_VECTOR(8 DOWNTO 0);
137
137
138 -----------------------------------------------------------------------------
138 -----------------------------------------------------------------------------
139 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
139 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
140
140
141 -----------------------------------------------------------------------------
141 -----------------------------------------------------------------------------
142 SIGNAL rstn : STD_LOGIC;
142 SIGNAL rstn : STD_LOGIC;
143
143
144 SIGNAL LFR_soft_rstn : STD_LOGIC;
144 SIGNAL LFR_soft_rstn : STD_LOGIC;
145 SIGNAL LFR_rstn : STD_LOGIC;
145 SIGNAL LFR_rstn : STD_LOGIC;
146
146
147 SIGNAL ADC_smpclk_s : STD_LOGIC;
147 SIGNAL ADC_smpclk_s : STD_LOGIC;
148 -----------------------------------------------------------------------------
148 -----------------------------------------------------------------------------
149 SIGNAL nSRAM_CE_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
149 SIGNAL nSRAM_CE_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
150
150
151 BEGIN -- beh
151 BEGIN -- beh
152
152
153 -----------------------------------------------------------------------------
153 -----------------------------------------------------------------------------
154 -- CLK
154 -- CLK
155 -----------------------------------------------------------------------------
155 -----------------------------------------------------------------------------
156 rst0 : rstgen PORT MAP (reset, clk_25, '1', rstn, OPEN);
156 rst0 : rstgen PORT MAP (reset, clk_25, '1', rstn, OPEN);
157
157
158 PROCESS(clk100MHz)
158 PROCESS(clk100MHz)
159 BEGIN
159 BEGIN
160 IF clk100MHz'EVENT AND clk100MHz = '1' THEN
160 IF clk100MHz'EVENT AND clk100MHz = '1' THEN
161 clk_50_s <= NOT clk_50_s;
161 clk_50_s <= NOT clk_50_s;
162 END IF;
162 END IF;
163 END PROCESS;
163 END PROCESS;
164
164
165 PROCESS(clk_50_s)
165 PROCESS(clk_50_s)
166 BEGIN
166 BEGIN
167 IF clk_50_s'EVENT AND clk_50_s = '1' THEN
167 IF clk_50_s'EVENT AND clk_50_s = '1' THEN
168 clk_25 <= NOT clk_25;
168 clk_25 <= NOT clk_25;
169 END IF;
169 END IF;
170 END PROCESS;
170 END PROCESS;
171
171
172 PROCESS(clk49_152MHz)
172 PROCESS(clk49_152MHz)
173 BEGIN
173 BEGIN
174 IF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN
174 IF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN
175 clk_24 <= NOT clk_24;
175 clk_24 <= NOT clk_24;
176 END IF;
176 END IF;
177 END PROCESS;
177 END PROCESS;
178
178
179 -----------------------------------------------------------------------------
179 -----------------------------------------------------------------------------
180
180
181 PROCESS (clk_25, rstn)
181 PROCESS (clk_25, rstn)
182 BEGIN -- PROCESS
182 BEGIN -- PROCESS
183 IF rstn = '0' THEN -- asynchronous reset (active low)
183 IF rstn = '0' THEN -- asynchronous reset (active low)
184 led(0) <= '0';
184 led(0) <= '0';
185 led(1) <= '0';
185 led(1) <= '0';
186 led(2) <= '0';
186 led(2) <= '0';
187 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
187 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
188 led(0) <= '0';
188 led(0) <= '0';
189 led(1) <= '1';
189 led(1) <= '1';
190 led(2) <= '1';
190 led(2) <= '1';
191 END IF;
191 END IF;
192 END PROCESS;
192 END PROCESS;
193
193
194 --
194 --
195 leon3_soc_1 : leon3_soc
195 leon3_soc_1 : leon3_soc
196 GENERIC MAP (
196 GENERIC MAP (
197 fabtech => apa3e,
197 fabtech => apa3e,
198 memtech => apa3e,
198 memtech => apa3e,
199 padtech => inferred,
199 padtech => inferred,
200 clktech => inferred,
200 clktech => inferred,
201 disas => 0,
201 disas => 0,
202 dbguart => 0,
202 dbguart => 0,
203 pclow => 2,
203 pclow => 2,
204 clk_freq => 25000,
204 clk_freq => 25000,
205 NB_CPU => 1,
205 NB_CPU => 1,
206 ENABLE_FPU => 1,
206 ENABLE_FPU => 1,
207 FPU_NETLIST => 0,
207 FPU_NETLIST => 0,
208 ENABLE_DSU => 1,
208 ENABLE_DSU => 1,
209 ENABLE_AHB_UART => 1,
209 ENABLE_AHB_UART => 1,
210 ENABLE_APB_UART => 1,
210 ENABLE_APB_UART => 1,
211 ENABLE_IRQMP => 1,
211 ENABLE_IRQMP => 1,
212 ENABLE_GPT => 1,
212 ENABLE_GPT => 1,
213 NB_AHB_MASTER => NB_AHB_MASTER,
213 NB_AHB_MASTER => NB_AHB_MASTER,
214 NB_AHB_SLAVE => NB_AHB_SLAVE,
214 NB_AHB_SLAVE => NB_AHB_SLAVE,
215 NB_APB_SLAVE => NB_APB_SLAVE,
215 NB_APB_SLAVE => NB_APB_SLAVE,
216 ADDRESS_SIZE => 20,
216 ADDRESS_SIZE => 20,
217 USES_IAP_MEMCTRLR => 0)
217 USES_IAP_MEMCTRLR => 0)
218 PORT MAP (
218 PORT MAP (
219 clk => clk_25,
219 clk => clk_25,
220 reset => rstn,
220 reset => rstn,
221 errorn => OPEN,
221 errorn => OPEN,
222
222
223 ahbrxd => TAG1,
223 ahbrxd => TAG1,
224 ahbtxd => TAG3,
224 ahbtxd => TAG3,
225 urxd1 => TAG2,
225 urxd1 => TAG2,
226 utxd1 => TAG4,
226 utxd1 => TAG4,
227
227
228 address => address,
228 address => address,
229 data => data,
229 data => data,
230 nSRAM_BE0 => nSRAM_BE0,
230 nSRAM_BE0 => nSRAM_BE0,
231 nSRAM_BE1 => nSRAM_BE1,
231 nSRAM_BE1 => nSRAM_BE1,
232 nSRAM_BE2 => nSRAM_BE2,
232 nSRAM_BE2 => nSRAM_BE2,
233 nSRAM_BE3 => nSRAM_BE3,
233 nSRAM_BE3 => nSRAM_BE3,
234 nSRAM_WE => nSRAM_WE,
234 nSRAM_WE => nSRAM_WE,
235 nSRAM_CE => nSRAM_CE_s,
235 nSRAM_CE => nSRAM_CE_s,
236 nSRAM_OE => nSRAM_OE,
236 nSRAM_OE => nSRAM_OE,
237 nSRAM_READY => '0',
237 nSRAM_READY => '0',
238 SRAM_MBE => OPEN,
238 SRAM_MBE => OPEN,
239
239
240 apbi_ext => apbi_ext,
240 apbi_ext => apbi_ext,
241 apbo_ext => apbo_ext,
241 apbo_ext => apbo_ext,
242 ahbi_s_ext => ahbi_s_ext,
242 ahbi_s_ext => ahbi_s_ext,
243 ahbo_s_ext => ahbo_s_ext,
243 ahbo_s_ext => ahbo_s_ext,
244 ahbi_m_ext => ahbi_m_ext,
244 ahbi_m_ext => ahbi_m_ext,
245 ahbo_m_ext => ahbo_m_ext);
245 ahbo_m_ext => ahbo_m_ext);
246
246
247
247
248 nSRAM_CE <= nSRAM_CE_s(0);
248 nSRAM_CE <= nSRAM_CE_s(0);
249
249
250 -------------------------------------------------------------------------------
250 -------------------------------------------------------------------------------
251 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
251 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
252 -------------------------------------------------------------------------------
252 -------------------------------------------------------------------------------
253 apb_lfr_management_1 : apb_lfr_management
253 apb_lfr_management_1 : apb_lfr_management
254 GENERIC MAP (
254 GENERIC MAP (
255 pindex => 6,
255 pindex => 6,
256 paddr => 6,
256 paddr => 6,
257 pmask => 16#fff#,
257 pmask => 16#fff#,
258 FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
258 FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
259 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
259 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
260 PORT MAP (
260 PORT MAP (
261 clk25MHz => clk_25,
261 clk25MHz => clk_25,
262 clk24_576MHz => clk_24, -- 49.152MHz/2
262 clk24_576MHz => clk_24, -- 49.152MHz/2
263 resetn => rstn,
263 resetn => rstn,
264 grspw_tick => swno.tickout,
264 grspw_tick => swno.tickout,
265 apbi => apbi_ext,
265 apbi => apbi_ext,
266 apbo => apbo_ext(6),
266 apbo => apbo_ext(6),
267
267
268 HK_sample => sample_s(8),
268 HK_sample => sample_s(8),
269 HK_val => sample_val,
269 HK_val => sample_val,
270 HK_sel => HK_SEL,
270 HK_sel => HK_SEL,
271
271
272 coarse_time => coarse_time,
272 coarse_time => coarse_time,
273 fine_time => fine_time,
273 fine_time => fine_time,
274 LFR_soft_rstn => LFR_soft_rstn
274 LFR_soft_rstn => LFR_soft_rstn
275 );
275 );
276
276
277 -----------------------------------------------------------------------
277 -----------------------------------------------------------------------
278 --- SpaceWire --------------------------------------------------------
278 --- SpaceWire --------------------------------------------------------
279 -----------------------------------------------------------------------
279 -----------------------------------------------------------------------
280
280
281 -- SPW_EN <= '1';
281 -- SPW_EN <= '1';
282
282
283 spw_clk <= clk_50_s;
283 spw_clk <= clk_50_s;
284 spw_rxtxclk <= spw_clk;
284 spw_rxtxclk <= spw_clk;
285 spw_rxclkn <= NOT spw_rxtxclk;
285 spw_rxclkn <= NOT spw_rxtxclk;
286
286
287 -- PADS for SPW1
287 -- PADS for SPW1
288 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
288 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
289 PORT MAP (spw1_din, dtmp(0));
289 PORT MAP (spw1_din, dtmp(0));
290 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
290 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
291 PORT MAP (spw1_sin, stmp(0));
291 PORT MAP (spw1_sin, stmp(0));
292 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
292 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
293 PORT MAP (spw1_dout, swno.d(0));
293 PORT MAP (spw1_dout, swno.d(0));
294 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
294 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
295 PORT MAP (spw1_sout, swno.s(0));
295 PORT MAP (spw1_sout, swno.s(0));
296 -- PADS FOR SPW2
296 -- PADS FOR SPW2
297 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
297 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
298 PORT MAP (spw2_din, dtmp(1));
298 PORT MAP (spw2_din, dtmp(1));
299 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
299 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
300 PORT MAP (spw2_sin, stmp(1));
300 PORT MAP (spw2_sin, stmp(1));
301 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
301 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
302 PORT MAP (spw2_dout, swno.d(1));
302 PORT MAP (spw2_dout, swno.d(1));
303 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
303 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
304 PORT MAP (spw2_sout, swno.s(1));
304 PORT MAP (spw2_sout, swno.s(1));
305
305
306 -- GRSPW PHY
306 -- GRSPW PHY
307 --spw1_input: if CFG_SPW_GRSPW = 1 generate
307 --spw1_input: if CFG_SPW_GRSPW = 1 generate
308 spw_inputloop : FOR j IN 0 TO 1 GENERATE
308 spw_inputloop : FOR j IN 0 TO 1 GENERATE
309 spw_phy0 : grspw_phy
309 spw_phy0 : grspw_phy
310 GENERIC MAP(
310 GENERIC MAP(
311 tech => apa3e,
311 tech => apa3e,
312 rxclkbuftype => 1,
312 rxclkbuftype => 1,
313 scantest => 0)
313 scantest => 0)
314 PORT MAP(
314 PORT MAP(
315 rxrst => swno.rxrst,
315 rxrst => swno.rxrst,
316 di => dtmp(j),
316 di => dtmp(j),
317 si => stmp(j),
317 si => stmp(j),
318 rxclko => spw_rxclk(j),
318 rxclko => spw_rxclk(j),
319 do => swni.d(j),
319 do => swni.d(j),
320 ndo => swni.nd(j*5+4 DOWNTO j*5),
320 ndo => swni.nd(j*5+4 DOWNTO j*5),
321 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
321 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
322 END GENERATE spw_inputloop;
322 END GENERATE spw_inputloop;
323
323
324 -- SPW core
324 -- SPW core
325 sw0 : grspwm GENERIC MAP(
325 sw0 : grspwm GENERIC MAP(
326 tech => apa3e,
326 tech => apa3e,
327 hindex => 1,
327 hindex => 1,
328 pindex => 5,
328 pindex => 5,
329 paddr => 5,
329 paddr => 5,
330 pirq => 11,
330 pirq => 11,
331 sysfreq => 25000, -- CPU_FREQ
331 sysfreq => 25000, -- CPU_FREQ
332 rmap => 1,
332 rmap => 1,
333 rmapcrc => 1,
333 rmapcrc => 1,
334 fifosize1 => 16,
334 fifosize1 => 16,
335 fifosize2 => 16,
335 fifosize2 => 16,
336 rxclkbuftype => 1,
336 rxclkbuftype => 1,
337 rxunaligned => 0,
337 rxunaligned => 0,
338 rmapbufs => 4,
338 rmapbufs => 4,
339 ft => 0,
339 ft => 0,
340 netlist => 0,
340 netlist => 0,
341 ports => 2,
341 ports => 2,
342 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
342 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
343 memtech => apa3e,
343 memtech => apa3e,
344 destkey => 2,
344 destkey => 2,
345 spwcore => 1
345 spwcore => 1
346 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
346 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
347 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
347 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
348 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
348 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
349 )
349 )
350 PORT MAP(rstn, clk_25, spw_rxclk(0),
350 PORT MAP(rstn, clk_25, spw_rxclk(0),
351 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
351 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
352 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
352 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
353 swni, swno);
353 swni, swno);
354
354
355 swni.tickin <= '0';
355 swni.tickin <= '0';
356 swni.rmapen <= '1';
356 swni.rmapen <= '1';
357 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
357 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
358 swni.tickinraw <= '0';
358 swni.tickinraw <= '0';
359 swni.timein <= (OTHERS => '0');
359 swni.timein <= (OTHERS => '0');
360 swni.dcrstval <= (OTHERS => '0');
360 swni.dcrstval <= (OTHERS => '0');
361 swni.timerrstval <= (OTHERS => '0');
361 swni.timerrstval <= (OTHERS => '0');
362
362
363 -------------------------------------------------------------------------------
363 -------------------------------------------------------------------------------
364 -- LFR ------------------------------------------------------------------------
364 -- LFR ------------------------------------------------------------------------
365 -------------------------------------------------------------------------------
365 -------------------------------------------------------------------------------
366 LFR_rstn <= LFR_soft_rstn AND rstn;
366 LFR_rstn <= LFR_soft_rstn AND rstn;
367
367
368 lpp_lfr_1 : lpp_lfr
368 lpp_lfr_1 : lpp_lfr
369 GENERIC MAP (
369 GENERIC MAP (
370 Mem_use => use_RAM,
370 Mem_use => use_RAM,
371 nb_data_by_buffer_size => 32,
371 nb_data_by_buffer_size => 32,
372 --nb_word_by_buffer_size => 30,
372 --nb_word_by_buffer_size => 30,
373 nb_snapshot_param_size => 32,
373 nb_snapshot_param_size => 32,
374 delta_vector_size => 32,
374 delta_vector_size => 32,
375 delta_vector_size_f0_2 => 7, -- log2(96)
375 delta_vector_size_f0_2 => 7, -- log2(96)
376 pindex => 15,
376 pindex => 15,
377 paddr => 15,
377 paddr => 15,
378 pmask => 16#fff#,
378 pmask => 16#fff#,
379 pirq_ms => 6,
379 pirq_ms => 6,
380 pirq_wfp => 14,
380 pirq_wfp => 14,
381 hindex => 2,
381 hindex => 2,
382 top_lfr_version => X"010131") -- aa.bb.cc version
382 top_lfr_version => X"010135") -- aa.bb.cc version
383 -- AA : BOARD NUMBER
383 -- AA : BOARD NUMBER
384 -- 0 => MINI_LFR
384 -- 0 => MINI_LFR
385 -- 1 => EM
385 -- 1 => EM
386 PORT MAP (
386 PORT MAP (
387 clk => clk_25,
387 clk => clk_25,
388 rstn => LFR_rstn,
388 rstn => LFR_rstn,
389 sample_B => sample_s(2 DOWNTO 0),
389 sample_B => sample_s(2 DOWNTO 0),
390 sample_E => sample_s(7 DOWNTO 3),
390 sample_E => sample_s(7 DOWNTO 3),
391 sample_val => sample_val,
391 sample_val => sample_val,
392 apbi => apbi_ext,
392 apbi => apbi_ext,
393 apbo => apbo_ext(15),
393 apbo => apbo_ext(15),
394 ahbi => ahbi_m_ext,
394 ahbi => ahbi_m_ext,
395 ahbo => ahbo_m_ext(2),
395 ahbo => ahbo_m_ext(2),
396 coarse_time => coarse_time,
396 coarse_time => coarse_time,
397 fine_time => fine_time,
397 fine_time => fine_time,
398 data_shaping_BW => bias_fail_sw,
398 data_shaping_BW => bias_fail_sw,
399 debug_vector => OPEN,
399 debug_vector => OPEN,
400 debug_vector_ms => OPEN); --,
400 debug_vector_ms => OPEN); --,
401 --observation_vector_0 => OPEN,
401 --observation_vector_0 => OPEN,
402 --observation_vector_1 => OPEN,
402 --observation_vector_1 => OPEN,
403 --observation_reg => observation_reg);
403 --observation_reg => observation_reg);
404
404
405
405
406 all_sample : FOR I IN 7 DOWNTO 0 GENERATE
406 all_sample : FOR I IN 7 DOWNTO 0 GENERATE
407 sample_s(I) <= sample(I) & '0' & '0';
407 sample_s(I) <= sample(I) & '0' & '0';
408 END GENERATE all_sample;
408 END GENERATE all_sample;
409 sample_s(8) <= sample(8)(13) & sample(8)(13) & sample(8);
409 sample_s(8) <= sample(8)(13) & sample(8)(13) & sample(8);
410
410
411 -----------------------------------------------------------------------------
411 -----------------------------------------------------------------------------
412 --
412 --
413 -----------------------------------------------------------------------------
413 -----------------------------------------------------------------------------
414 top_ad_conv_RHF1401_withFilter_1 : top_ad_conv_RHF1401_withFilter
414 top_ad_conv_RHF1401_withFilter_1 : top_ad_conv_RHF1401_withFilter
415 GENERIC MAP (
415 GENERIC MAP (
416 ChanelCount => 9,
416 ChanelCount => 9,
417 ncycle_cnv_high => 13,
417 ncycle_cnv_high => 13,
418 ncycle_cnv => 25,
418 ncycle_cnv => 25,
419 FILTER_ENABLED => 16#FF#)
419 FILTER_ENABLED => 16#FF#)
420 PORT MAP (
420 PORT MAP (
421 cnv_clk => clk_24,
421 cnv_clk => clk_24,
422 cnv_rstn => rstn,
422 cnv_rstn => rstn,
423 cnv => ADC_smpclk_s,
423 cnv => ADC_smpclk_s,
424 clk => clk_25,
424 clk => clk_25,
425 rstn => rstn,
425 rstn => rstn,
426 ADC_data => ADC_data,
426 ADC_data => ADC_data,
427 ADC_nOE => ADC_OEB_bar_CH_s,
427 ADC_nOE => ADC_OEB_bar_CH_s,
428 sample => sample,
428 sample => sample,
429 sample_val => sample_val);
429 sample_val => sample_val);
430
430
431 ADC_OEB_bar_CH <= ADC_OEB_bar_CH_s(7 DOWNTO 0);
431 ADC_OEB_bar_CH <= ADC_OEB_bar_CH_s(7 DOWNTO 0);
432
432
433 ADC_smpclk <= ADC_smpclk_s;
433 ADC_smpclk <= ADC_smpclk_s;
434 HK_smpclk <= ADC_smpclk_s;
434 HK_smpclk <= ADC_smpclk_s;
435
435
436 TAG8 <= ADC_smpclk_s;
436 TAG8 <= ADC_smpclk_s;
437
437
438 -----------------------------------------------------------------------------
438 -----------------------------------------------------------------------------
439 -- HK
439 -- HK
440 -----------------------------------------------------------------------------
440 -----------------------------------------------------------------------------
441 ADC_OEB_bar_HK <= ADC_OEB_bar_CH_s(8);
441 ADC_OEB_bar_HK <= ADC_OEB_bar_CH_s(8);
442
442
443 END beh;
443 END beh;
Show file before | Show file after | Hide comments
@@ -1,733 +1,733
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
21 -------------------------------------------------------------------------------
22 LIBRARY IEEE;
22 LIBRARY IEEE;
23 USE IEEE.numeric_std.ALL;
23 USE IEEE.numeric_std.ALL;
24 USE IEEE.std_logic_1164.ALL;
24 USE IEEE.std_logic_1164.ALL;
25 LIBRARY grlib;
25 LIBRARY grlib;
26 USE grlib.amba.ALL;
26 USE grlib.amba.ALL;
27 USE grlib.stdlib.ALL;
27 USE grlib.stdlib.ALL;
28 LIBRARY techmap;
28 LIBRARY techmap;
29 USE techmap.gencomp.ALL;
29 USE techmap.gencomp.ALL;
30 LIBRARY gaisler;
30 LIBRARY gaisler;
31 USE gaisler.memctrl.ALL;
31 USE gaisler.memctrl.ALL;
32 USE gaisler.leon3.ALL;
32 USE gaisler.leon3.ALL;
33 USE gaisler.uart.ALL;
33 USE gaisler.uart.ALL;
34 USE gaisler.misc.ALL;
34 USE gaisler.misc.ALL;
35 USE gaisler.spacewire.ALL;
35 USE gaisler.spacewire.ALL;
36 LIBRARY esa;
36 LIBRARY esa;
37 USE esa.memoryctrl.ALL;
37 USE esa.memoryctrl.ALL;
38 LIBRARY lpp;
38 LIBRARY lpp;
39 USE lpp.lpp_memory.ALL;
39 USE lpp.lpp_memory.ALL;
40 USE lpp.lpp_ad_conv.ALL;
40 USE lpp.lpp_ad_conv.ALL;
41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
43 USE lpp.iir_filter.ALL;
43 USE lpp.iir_filter.ALL;
44 USE lpp.general_purpose.ALL;
44 USE lpp.general_purpose.ALL;
45 USE lpp.lpp_lfr_management.ALL;
45 USE lpp.lpp_lfr_management.ALL;
46 USE lpp.lpp_leon3_soc_pkg.ALL;
46 USE lpp.lpp_leon3_soc_pkg.ALL;
47
47
48 ENTITY MINI_LFR_top IS
48 ENTITY MINI_LFR_top IS
49
49
50 PORT (
50 PORT (
51 clk_50 : IN STD_LOGIC;
51 clk_50 : IN STD_LOGIC;
52 clk_49 : IN STD_LOGIC;
52 clk_49 : IN STD_LOGIC;
53 reset : IN STD_LOGIC;
53 reset : IN STD_LOGIC;
54 --BPs
54 --BPs
55 BP0 : IN STD_LOGIC;
55 BP0 : IN STD_LOGIC;
56 BP1 : IN STD_LOGIC;
56 BP1 : IN STD_LOGIC;
57 --LEDs
57 --LEDs
58 LED0 : OUT STD_LOGIC;
58 LED0 : OUT STD_LOGIC;
59 LED1 : OUT STD_LOGIC;
59 LED1 : OUT STD_LOGIC;
60 LED2 : OUT STD_LOGIC;
60 LED2 : OUT STD_LOGIC;
61 --UARTs
61 --UARTs
62 TXD1 : IN STD_LOGIC;
62 TXD1 : IN STD_LOGIC;
63 RXD1 : OUT STD_LOGIC;
63 RXD1 : OUT STD_LOGIC;
64 nCTS1 : OUT STD_LOGIC;
64 nCTS1 : OUT STD_LOGIC;
65 nRTS1 : IN STD_LOGIC;
65 nRTS1 : IN STD_LOGIC;
66
66
67 TXD2 : IN STD_LOGIC;
67 TXD2 : IN STD_LOGIC;
68 RXD2 : OUT STD_LOGIC;
68 RXD2 : OUT STD_LOGIC;
69 nCTS2 : OUT STD_LOGIC;
69 nCTS2 : OUT STD_LOGIC;
70 nDTR2 : IN STD_LOGIC;
70 nDTR2 : IN STD_LOGIC;
71 nRTS2 : IN STD_LOGIC;
71 nRTS2 : IN STD_LOGIC;
72 nDCD2 : OUT STD_LOGIC;
72 nDCD2 : OUT STD_LOGIC;
73
73
74 --EXT CONNECTOR
74 --EXT CONNECTOR
75 IO0 : INOUT STD_LOGIC;
75 IO0 : INOUT STD_LOGIC;
76 IO1 : INOUT STD_LOGIC;
76 IO1 : INOUT STD_LOGIC;
77 IO2 : INOUT STD_LOGIC;
77 IO2 : INOUT STD_LOGIC;
78 IO3 : INOUT STD_LOGIC;
78 IO3 : INOUT STD_LOGIC;
79 IO4 : INOUT STD_LOGIC;
79 IO4 : INOUT STD_LOGIC;
80 IO5 : INOUT STD_LOGIC;
80 IO5 : INOUT STD_LOGIC;
81 IO6 : INOUT STD_LOGIC;
81 IO6 : INOUT STD_LOGIC;
82 IO7 : INOUT STD_LOGIC;
82 IO7 : INOUT STD_LOGIC;
83 IO8 : INOUT STD_LOGIC;
83 IO8 : INOUT STD_LOGIC;
84 IO9 : INOUT STD_LOGIC;
84 IO9 : INOUT STD_LOGIC;
85 IO10 : INOUT STD_LOGIC;
85 IO10 : INOUT STD_LOGIC;
86 IO11 : INOUT STD_LOGIC;
86 IO11 : INOUT STD_LOGIC;
87
87
88 --SPACE WIRE
88 --SPACE WIRE
89 SPW_EN : OUT STD_LOGIC; -- 0 => off
89 SPW_EN : OUT STD_LOGIC; -- 0 => off
90 SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK
90 SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK
91 SPW_NOM_SIN : IN STD_LOGIC;
91 SPW_NOM_SIN : IN STD_LOGIC;
92 SPW_NOM_DOUT : OUT STD_LOGIC;
92 SPW_NOM_DOUT : OUT STD_LOGIC;
93 SPW_NOM_SOUT : OUT STD_LOGIC;
93 SPW_NOM_SOUT : OUT STD_LOGIC;
94 SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK
94 SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK
95 SPW_RED_SIN : IN STD_LOGIC;
95 SPW_RED_SIN : IN STD_LOGIC;
96 SPW_RED_DOUT : OUT STD_LOGIC;
96 SPW_RED_DOUT : OUT STD_LOGIC;
97 SPW_RED_SOUT : OUT STD_LOGIC;
97 SPW_RED_SOUT : OUT STD_LOGIC;
98 -- MINI LFR ADC INPUTS
98 -- MINI LFR ADC INPUTS
99 ADC_nCS : OUT STD_LOGIC;
99 ADC_nCS : OUT STD_LOGIC;
100 ADC_CLK : OUT STD_LOGIC;
100 ADC_CLK : OUT STD_LOGIC;
101 ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
101 ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
102
102
103 -- SRAM
103 -- SRAM
104 SRAM_nWE : OUT STD_LOGIC;
104 SRAM_nWE : OUT STD_LOGIC;
105 SRAM_CE : OUT STD_LOGIC;
105 SRAM_CE : OUT STD_LOGIC;
106 SRAM_nOE : OUT STD_LOGIC;
106 SRAM_nOE : OUT STD_LOGIC;
107 SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
107 SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
108 SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
108 SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
109 SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0)
109 SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0)
110 );
110 );
111
111
112 END MINI_LFR_top;
112 END MINI_LFR_top;
113
113
114
114
115 ARCHITECTURE beh OF MINI_LFR_top IS
115 ARCHITECTURE beh OF MINI_LFR_top IS
116 SIGNAL clk_50_s : STD_LOGIC := '0';
116 SIGNAL clk_50_s : STD_LOGIC := '0';
117 SIGNAL clk_25 : STD_LOGIC := '0';
117 SIGNAL clk_25 : STD_LOGIC := '0';
118 SIGNAL clk_24 : STD_LOGIC := '0';
118 SIGNAL clk_24 : STD_LOGIC := '0';
119 -----------------------------------------------------------------------------
119 -----------------------------------------------------------------------------
120 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
120 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
121 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
121 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
122 --
122 --
123 SIGNAL errorn : STD_LOGIC;
123 SIGNAL errorn : STD_LOGIC;
124 -- UART AHB ---------------------------------------------------------------
124 -- UART AHB ---------------------------------------------------------------
125 -- SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data
125 -- SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data
126 -- SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data
126 -- SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data
127
127
128 -- UART APB ---------------------------------------------------------------
128 -- UART APB ---------------------------------------------------------------
129 -- SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data
129 -- SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data
130 -- SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data
130 -- SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data
131 --
131 --
132 SIGNAL I00_s : STD_LOGIC;
132 SIGNAL I00_s : STD_LOGIC;
133
133
134 -- CONSTANTS
134 -- CONSTANTS
135 CONSTANT CFG_PADTECH : INTEGER := inferred;
135 CONSTANT CFG_PADTECH : INTEGER := inferred;
136 --
136 --
137 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
137 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
138 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
138 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
139 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
139 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
140
140
141 SIGNAL apbi_ext : apb_slv_in_type;
141 SIGNAL apbi_ext : apb_slv_in_type;
142 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5); -- := (OTHERS => apb_none);
142 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5); -- := (OTHERS => apb_none);
143 SIGNAL ahbi_s_ext : ahb_slv_in_type;
143 SIGNAL ahbi_s_ext : ahb_slv_in_type;
144 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3); -- := (OTHERS => ahbs_none);
144 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3); -- := (OTHERS => ahbs_none);
145 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
145 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
146 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1); -- := (OTHERS => ahbm_none);
146 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1); -- := (OTHERS => ahbm_none);
147
147
148 -- Spacewire signals
148 -- Spacewire signals
149 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
149 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
150 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
150 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
151 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
151 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
152 SIGNAL spw_rxtxclk : STD_ULOGIC;
152 SIGNAL spw_rxtxclk : STD_ULOGIC;
153 SIGNAL spw_rxclkn : STD_ULOGIC;
153 SIGNAL spw_rxclkn : STD_ULOGIC;
154 SIGNAL spw_clk : STD_LOGIC;
154 SIGNAL spw_clk : STD_LOGIC;
155 SIGNAL swni : grspw_in_type;
155 SIGNAL swni : grspw_in_type;
156 SIGNAL swno : grspw_out_type;
156 SIGNAL swno : grspw_out_type;
157 -- SIGNAL clkmn : STD_ULOGIC;
157 -- SIGNAL clkmn : STD_ULOGIC;
158 -- SIGNAL txclk : STD_ULOGIC;
158 -- SIGNAL txclk : STD_ULOGIC;
159
159
160 --GPIO
160 --GPIO
161 SIGNAL gpioi : gpio_in_type;
161 SIGNAL gpioi : gpio_in_type;
162 SIGNAL gpioo : gpio_out_type;
162 SIGNAL gpioo : gpio_out_type;
163
163
164 -- AD Converter ADS7886
164 -- AD Converter ADS7886
165 SIGNAL sample : Samples14v(7 DOWNTO 0);
165 SIGNAL sample : Samples14v(7 DOWNTO 0);
166 SIGNAL sample_s : Samples(7 DOWNTO 0);
166 SIGNAL sample_s : Samples(7 DOWNTO 0);
167 SIGNAL sample_val : STD_LOGIC;
167 SIGNAL sample_val : STD_LOGIC;
168 SIGNAL ADC_nCS_sig : STD_LOGIC;
168 SIGNAL ADC_nCS_sig : STD_LOGIC;
169 SIGNAL ADC_CLK_sig : STD_LOGIC;
169 SIGNAL ADC_CLK_sig : STD_LOGIC;
170 SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
170 SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
171
171
172 SIGNAL bias_fail_sw_sig : STD_LOGIC;
172 SIGNAL bias_fail_sw_sig : STD_LOGIC;
173
173
174 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
174 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
175 SIGNAL observation_vector_0 : STD_LOGIC_VECTOR(11 DOWNTO 0);
175 SIGNAL observation_vector_0 : STD_LOGIC_VECTOR(11 DOWNTO 0);
176 SIGNAL observation_vector_1 : STD_LOGIC_VECTOR(11 DOWNTO 0);
176 SIGNAL observation_vector_1 : STD_LOGIC_VECTOR(11 DOWNTO 0);
177 -----------------------------------------------------------------------------
177 -----------------------------------------------------------------------------
178
178
179 SIGNAL LFR_soft_rstn : STD_LOGIC;
179 SIGNAL LFR_soft_rstn : STD_LOGIC;
180 SIGNAL LFR_rstn : STD_LOGIC;
180 SIGNAL LFR_rstn : STD_LOGIC;
181
181
182
182
183 SIGNAL rstn_25 : STD_LOGIC;
183 SIGNAL rstn_25 : STD_LOGIC;
184 SIGNAL rstn_25_d1 : STD_LOGIC;
184 SIGNAL rstn_25_d1 : STD_LOGIC;
185 SIGNAL rstn_25_d2 : STD_LOGIC;
185 SIGNAL rstn_25_d2 : STD_LOGIC;
186 SIGNAL rstn_25_d3 : STD_LOGIC;
186 SIGNAL rstn_25_d3 : STD_LOGIC;
187
187
188 SIGNAL rstn_50 : STD_LOGIC;
188 SIGNAL rstn_50 : STD_LOGIC;
189 SIGNAL rstn_50_d1 : STD_LOGIC;
189 SIGNAL rstn_50_d1 : STD_LOGIC;
190 SIGNAL rstn_50_d2 : STD_LOGIC;
190 SIGNAL rstn_50_d2 : STD_LOGIC;
191 SIGNAL rstn_50_d3 : STD_LOGIC;
191 SIGNAL rstn_50_d3 : STD_LOGIC;
192
192
193 SIGNAL lfr_debug_vector : STD_LOGIC_VECTOR(11 DOWNTO 0);
193 SIGNAL lfr_debug_vector : STD_LOGIC_VECTOR(11 DOWNTO 0);
194 SIGNAL lfr_debug_vector_ms : STD_LOGIC_VECTOR(11 DOWNTO 0);
194 SIGNAL lfr_debug_vector_ms : STD_LOGIC_VECTOR(11 DOWNTO 0);
195
195
196 --
196 --
197 SIGNAL SRAM_CE_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
197 SIGNAL SRAM_CE_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
198
198
199 --
199 --
200 SIGNAL sample_hk : STD_LOGIC_VECTOR(15 DOWNTO 0);
200 SIGNAL sample_hk : STD_LOGIC_VECTOR(15 DOWNTO 0);
201 SIGNAL HK_SEL : STD_LOGIC_VECTOR( 1 DOWNTO 0);
201 SIGNAL HK_SEL : STD_LOGIC_VECTOR( 1 DOWNTO 0);
202
202
203 BEGIN -- beh
203 BEGIN -- beh
204
204
205 -----------------------------------------------------------------------------
205 -----------------------------------------------------------------------------
206 -- CLK
206 -- CLK
207 -----------------------------------------------------------------------------
207 -----------------------------------------------------------------------------
208
208
209 --PROCESS(clk_50)
209 --PROCESS(clk_50)
210 --BEGIN
210 --BEGIN
211 -- IF clk_50'EVENT AND clk_50 = '1' THEN
211 -- IF clk_50'EVENT AND clk_50 = '1' THEN
212 -- clk_50_s <= NOT clk_50_s;
212 -- clk_50_s <= NOT clk_50_s;
213 -- END IF;
213 -- END IF;
214 --END PROCESS;
214 --END PROCESS;
215
215
216 --PROCESS(clk_50_s)
216 --PROCESS(clk_50_s)
217 --BEGIN
217 --BEGIN
218 -- IF clk_50_s'EVENT AND clk_50_s = '1' THEN
218 -- IF clk_50_s'EVENT AND clk_50_s = '1' THEN
219 -- clk_25 <= NOT clk_25;
219 -- clk_25 <= NOT clk_25;
220 -- END IF;
220 -- END IF;
221 --END PROCESS;
221 --END PROCESS;
222
222
223 --PROCESS(clk_49)
223 --PROCESS(clk_49)
224 --BEGIN
224 --BEGIN
225 -- IF clk_49'EVENT AND clk_49 = '1' THEN
225 -- IF clk_49'EVENT AND clk_49 = '1' THEN
226 -- clk_24 <= NOT clk_24;
226 -- clk_24 <= NOT clk_24;
227 -- END IF;
227 -- END IF;
228 --END PROCESS;
228 --END PROCESS;
229
229
230 --PROCESS(clk_25)
230 --PROCESS(clk_25)
231 --BEGIN
231 --BEGIN
232 -- IF clk_25'EVENT AND clk_25 = '1' THEN
232 -- IF clk_25'EVENT AND clk_25 = '1' THEN
233 -- rstn_25 <= reset;
233 -- rstn_25 <= reset;
234 -- END IF;
234 -- END IF;
235 --END PROCESS;
235 --END PROCESS;
236
236
237 PROCESS (clk_50, reset)
237 PROCESS (clk_50, reset)
238 BEGIN -- PROCESS
238 BEGIN -- PROCESS
239 IF reset = '0' THEN -- asynchronous reset (active low)
239 IF reset = '0' THEN -- asynchronous reset (active low)
240 clk_50_s <= '0';
240 clk_50_s <= '0';
241 rstn_50 <= '0';
241 rstn_50 <= '0';
242 rstn_50_d1 <= '0';
242 rstn_50_d1 <= '0';
243 rstn_50_d2 <= '0';
243 rstn_50_d2 <= '0';
244 rstn_50_d3 <= '0';
244 rstn_50_d3 <= '0';
245
245
246 ELSIF clk_50'EVENT AND clk_50 = '1' THEN -- rising clock edge
246 ELSIF clk_50'EVENT AND clk_50 = '1' THEN -- rising clock edge
247 clk_50_s <= NOT clk_50_s;
247 clk_50_s <= NOT clk_50_s;
248 rstn_50_d1 <= '1';
248 rstn_50_d1 <= '1';
249 rstn_50_d2 <= rstn_50_d1;
249 rstn_50_d2 <= rstn_50_d1;
250 rstn_50_d3 <= rstn_50_d2;
250 rstn_50_d3 <= rstn_50_d2;
251 rstn_50 <= rstn_50_d3;
251 rstn_50 <= rstn_50_d3;
252 END IF;
252 END IF;
253 END PROCESS;
253 END PROCESS;
254
254
255 PROCESS (clk_50_s, rstn_50)
255 PROCESS (clk_50_s, rstn_50)
256 BEGIN -- PROCESS
256 BEGIN -- PROCESS
257 IF rstn_50 = '0' THEN -- asynchronous reset (active low)
257 IF rstn_50 = '0' THEN -- asynchronous reset (active low)
258 clk_25 <= '0';
258 clk_25 <= '0';
259 rstn_25 <= '0';
259 rstn_25 <= '0';
260 rstn_25_d1 <= '0';
260 rstn_25_d1 <= '0';
261 rstn_25_d2 <= '0';
261 rstn_25_d2 <= '0';
262 rstn_25_d3 <= '0';
262 rstn_25_d3 <= '0';
263 ELSIF clk_50_s'EVENT AND clk_50_s = '1' THEN -- rising clock edge
263 ELSIF clk_50_s'EVENT AND clk_50_s = '1' THEN -- rising clock edge
264 clk_25 <= NOT clk_25;
264 clk_25 <= NOT clk_25;
265 rstn_25_d1 <= '1';
265 rstn_25_d1 <= '1';
266 rstn_25_d2 <= rstn_25_d1;
266 rstn_25_d2 <= rstn_25_d1;
267 rstn_25_d3 <= rstn_25_d2;
267 rstn_25_d3 <= rstn_25_d2;
268 rstn_25 <= rstn_25_d3;
268 rstn_25 <= rstn_25_d3;
269 END IF;
269 END IF;
270 END PROCESS;
270 END PROCESS;
271
271
272 PROCESS (clk_49, reset)
272 PROCESS (clk_49, reset)
273 BEGIN -- PROCESS
273 BEGIN -- PROCESS
274 IF reset = '0' THEN -- asynchronous reset (active low)
274 IF reset = '0' THEN -- asynchronous reset (active low)
275 clk_24 <= '0';
275 clk_24 <= '0';
276 ELSIF clk_49'EVENT AND clk_49 = '1' THEN -- rising clock edge
276 ELSIF clk_49'EVENT AND clk_49 = '1' THEN -- rising clock edge
277 clk_24 <= NOT clk_24;
277 clk_24 <= NOT clk_24;
278 END IF;
278 END IF;
279 END PROCESS;
279 END PROCESS;
280
280
281 -----------------------------------------------------------------------------
281 -----------------------------------------------------------------------------
282
282
283 PROCESS (clk_25, rstn_25)
283 PROCESS (clk_25, rstn_25)
284 BEGIN -- PROCESS
284 BEGIN -- PROCESS
285 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
285 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
286 LED0 <= '0';
286 LED0 <= '0';
287 LED1 <= '0';
287 LED1 <= '0';
288 LED2 <= '0';
288 LED2 <= '0';
289 --IO1 <= '0';
289 --IO1 <= '0';
290 --IO2 <= '1';
290 --IO2 <= '1';
291 --IO3 <= '0';
291 --IO3 <= '0';
292 --IO4 <= '0';
292 --IO4 <= '0';
293 --IO5 <= '0';
293 --IO5 <= '0';
294 --IO6 <= '0';
294 --IO6 <= '0';
295 --IO7 <= '0';
295 --IO7 <= '0';
296 --IO8 <= '0';
296 --IO8 <= '0';
297 --IO9 <= '0';
297 --IO9 <= '0';
298 --IO10 <= '0';
298 --IO10 <= '0';
299 --IO11 <= '0';
299 --IO11 <= '0';
300 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
300 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
301 LED0 <= '0';
301 LED0 <= '0';
302 LED1 <= '1';
302 LED1 <= '1';
303 LED2 <= BP0 OR BP1 OR nDTR2 OR nRTS2 OR nRTS1;
303 LED2 <= BP0 OR BP1 OR nDTR2 OR nRTS2 OR nRTS1;
304 --IO1 <= '1';
304 --IO1 <= '1';
305 --IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN;
305 --IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN;
306 --IO3 <= ADC_SDO(0);
306 --IO3 <= ADC_SDO(0);
307 --IO4 <= ADC_SDO(1);
307 --IO4 <= ADC_SDO(1);
308 --IO5 <= ADC_SDO(2);
308 --IO5 <= ADC_SDO(2);
309 --IO6 <= ADC_SDO(3);
309 --IO6 <= ADC_SDO(3);
310 --IO7 <= ADC_SDO(4);
310 --IO7 <= ADC_SDO(4);
311 --IO8 <= ADC_SDO(5);
311 --IO8 <= ADC_SDO(5);
312 --IO9 <= ADC_SDO(6);
312 --IO9 <= ADC_SDO(6);
313 --IO10 <= ADC_SDO(7);
313 --IO10 <= ADC_SDO(7);
314 --IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1;
314 --IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1;
315 END IF;
315 END IF;
316 END PROCESS;
316 END PROCESS;
317
317
318 PROCESS (clk_24, rstn_25)
318 PROCESS (clk_24, rstn_25)
319 BEGIN -- PROCESS
319 BEGIN -- PROCESS
320 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
320 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
321 I00_s <= '0';
321 I00_s <= '0';
322 ELSIF clk_24'EVENT AND clk_24 = '1' THEN -- rising clock edge
322 ELSIF clk_24'EVENT AND clk_24 = '1' THEN -- rising clock edge
323 I00_s <= NOT I00_s;
323 I00_s <= NOT I00_s;
324 END IF;
324 END IF;
325 END PROCESS;
325 END PROCESS;
326 -- IO0 <= I00_s;
326 -- IO0 <= I00_s;
327
327
328 --UARTs
328 --UARTs
329 nCTS1 <= '1';
329 nCTS1 <= '1';
330 nCTS2 <= '1';
330 nCTS2 <= '1';
331 nDCD2 <= '1';
331 nDCD2 <= '1';
332
332
333 --EXT CONNECTOR
333 --EXT CONNECTOR
334
334
335 --SPACE WIRE
335 --SPACE WIRE
336
336
337 leon3_soc_1 : leon3_soc
337 leon3_soc_1 : leon3_soc
338 GENERIC MAP (
338 GENERIC MAP (
339 fabtech => apa3e,
339 fabtech => apa3e,
340 memtech => apa3e,
340 memtech => apa3e,
341 padtech => inferred,
341 padtech => inferred,
342 clktech => inferred,
342 clktech => inferred,
343 disas => 0,
343 disas => 0,
344 dbguart => 0,
344 dbguart => 0,
345 pclow => 2,
345 pclow => 2,
346 clk_freq => 25000,
346 clk_freq => 25000,
347 NB_CPU => 1,
347 NB_CPU => 1,
348 ENABLE_FPU => 1,
348 ENABLE_FPU => 1,
349 FPU_NETLIST => 0,
349 FPU_NETLIST => 0,
350 ENABLE_DSU => 1,
350 ENABLE_DSU => 1,
351 ENABLE_AHB_UART => 1,
351 ENABLE_AHB_UART => 1,
352 ENABLE_APB_UART => 1,
352 ENABLE_APB_UART => 1,
353 ENABLE_IRQMP => 1,
353 ENABLE_IRQMP => 1,
354 ENABLE_GPT => 1,
354 ENABLE_GPT => 1,
355 NB_AHB_MASTER => NB_AHB_MASTER,
355 NB_AHB_MASTER => NB_AHB_MASTER,
356 NB_AHB_SLAVE => NB_AHB_SLAVE,
356 NB_AHB_SLAVE => NB_AHB_SLAVE,
357 NB_APB_SLAVE => NB_APB_SLAVE,
357 NB_APB_SLAVE => NB_APB_SLAVE,
358 ADDRESS_SIZE => 20,
358 ADDRESS_SIZE => 20,
359 USES_IAP_MEMCTRLR => 0)
359 USES_IAP_MEMCTRLR => 0)
360 PORT MAP (
360 PORT MAP (
361 clk => clk_25,
361 clk => clk_25,
362 reset => rstn_25,
362 reset => rstn_25,
363 errorn => errorn,
363 errorn => errorn,
364 ahbrxd => TXD1,
364 ahbrxd => TXD1,
365 ahbtxd => RXD1,
365 ahbtxd => RXD1,
366 urxd1 => TXD2,
366 urxd1 => TXD2,
367 utxd1 => RXD2,
367 utxd1 => RXD2,
368 address => SRAM_A,
368 address => SRAM_A,
369 data => SRAM_DQ,
369 data => SRAM_DQ,
370 nSRAM_BE0 => SRAM_nBE(0),
370 nSRAM_BE0 => SRAM_nBE(0),
371 nSRAM_BE1 => SRAM_nBE(1),
371 nSRAM_BE1 => SRAM_nBE(1),
372 nSRAM_BE2 => SRAM_nBE(2),
372 nSRAM_BE2 => SRAM_nBE(2),
373 nSRAM_BE3 => SRAM_nBE(3),
373 nSRAM_BE3 => SRAM_nBE(3),
374 nSRAM_WE => SRAM_nWE,
374 nSRAM_WE => SRAM_nWE,
375 nSRAM_CE => SRAM_CE_s,
375 nSRAM_CE => SRAM_CE_s,
376 nSRAM_OE => SRAM_nOE,
376 nSRAM_OE => SRAM_nOE,
377 nSRAM_READY => '0',
377 nSRAM_READY => '0',
378 SRAM_MBE => OPEN,
378 SRAM_MBE => OPEN,
379 apbi_ext => apbi_ext,
379 apbi_ext => apbi_ext,
380 apbo_ext => apbo_ext,
380 apbo_ext => apbo_ext,
381 ahbi_s_ext => ahbi_s_ext,
381 ahbi_s_ext => ahbi_s_ext,
382 ahbo_s_ext => ahbo_s_ext,
382 ahbo_s_ext => ahbo_s_ext,
383 ahbi_m_ext => ahbi_m_ext,
383 ahbi_m_ext => ahbi_m_ext,
384 ahbo_m_ext => ahbo_m_ext);
384 ahbo_m_ext => ahbo_m_ext);
385
385
386 SRAM_CE <= SRAM_CE_s(0);
386 SRAM_CE <= SRAM_CE_s(0);
387 -------------------------------------------------------------------------------
387 -------------------------------------------------------------------------------
388 -- APB_LFR_MANAGEMENT ---------------------------------------------------------
388 -- APB_LFR_MANAGEMENT ---------------------------------------------------------
389 -------------------------------------------------------------------------------
389 -------------------------------------------------------------------------------
390 apb_lfr_management_1 : apb_lfr_management
390 apb_lfr_management_1 : apb_lfr_management
391 GENERIC MAP (
391 GENERIC MAP (
392 pindex => 6,
392 pindex => 6,
393 paddr => 6,
393 paddr => 6,
394 pmask => 16#fff#,
394 pmask => 16#fff#,
395 FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
395 FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
396 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
396 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
397 PORT MAP (
397 PORT MAP (
398 clk25MHz => clk_25,
398 clk25MHz => clk_25,
399 clk24_576MHz => clk_24, -- 49.152MHz/2
399 clk24_576MHz => clk_24, -- 49.152MHz/2
400 resetn => rstn_25,
400 resetn => rstn_25,
401 grspw_tick => swno.tickout,
401 grspw_tick => swno.tickout,
402 apbi => apbi_ext,
402 apbi => apbi_ext,
403 apbo => apbo_ext(6),
403 apbo => apbo_ext(6),
404 HK_sample => sample_hk,
404 HK_sample => sample_hk,
405 HK_val => sample_val,
405 HK_val => sample_val,
406 HK_sel => HK_SEL,
406 HK_sel => HK_SEL,
407 coarse_time => coarse_time,
407 coarse_time => coarse_time,
408 fine_time => fine_time,
408 fine_time => fine_time,
409 LFR_soft_rstn => LFR_soft_rstn
409 LFR_soft_rstn => LFR_soft_rstn
410 );
410 );
411
411
412 -----------------------------------------------------------------------
412 -----------------------------------------------------------------------
413 --- SpaceWire --------------------------------------------------------
413 --- SpaceWire --------------------------------------------------------
414 -----------------------------------------------------------------------
414 -----------------------------------------------------------------------
415
415
416 SPW_EN <= '1';
416 SPW_EN <= '1';
417
417
418 spw_clk <= clk_50_s;
418 spw_clk <= clk_50_s;
419 spw_rxtxclk <= spw_clk;
419 spw_rxtxclk <= spw_clk;
420 spw_rxclkn <= NOT spw_rxtxclk;
420 spw_rxclkn <= NOT spw_rxtxclk;
421
421
422 -- PADS for SPW1
422 -- PADS for SPW1
423 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
423 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
424 PORT MAP (SPW_NOM_DIN, dtmp(0));
424 PORT MAP (SPW_NOM_DIN, dtmp(0));
425 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
425 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
426 PORT MAP (SPW_NOM_SIN, stmp(0));
426 PORT MAP (SPW_NOM_SIN, stmp(0));
427 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
427 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
428 PORT MAP (SPW_NOM_DOUT, swno.d(0));
428 PORT MAP (SPW_NOM_DOUT, swno.d(0));
429 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
429 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
430 PORT MAP (SPW_NOM_SOUT, swno.s(0));
430 PORT MAP (SPW_NOM_SOUT, swno.s(0));
431 -- PADS FOR SPW2
431 -- PADS FOR SPW2
432 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
432 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
433 PORT MAP (SPW_RED_SIN, dtmp(1));
433 PORT MAP (SPW_RED_SIN, dtmp(1));
434 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
434 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
435 PORT MAP (SPW_RED_DIN, stmp(1));
435 PORT MAP (SPW_RED_DIN, stmp(1));
436 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
436 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
437 PORT MAP (SPW_RED_DOUT, swno.d(1));
437 PORT MAP (SPW_RED_DOUT, swno.d(1));
438 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
438 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
439 PORT MAP (SPW_RED_SOUT, swno.s(1));
439 PORT MAP (SPW_RED_SOUT, swno.s(1));
440
440
441 -- GRSPW PHY
441 -- GRSPW PHY
442 --spw1_input: if CFG_SPW_GRSPW = 1 generate
442 --spw1_input: if CFG_SPW_GRSPW = 1 generate
443 spw_inputloop : FOR j IN 0 TO 1 GENERATE
443 spw_inputloop : FOR j IN 0 TO 1 GENERATE
444 spw_phy0 : grspw_phy
444 spw_phy0 : grspw_phy
445 GENERIC MAP(
445 GENERIC MAP(
446 tech => apa3e,
446 tech => apa3e,
447 rxclkbuftype => 1,
447 rxclkbuftype => 1,
448 scantest => 0)
448 scantest => 0)
449 PORT MAP(
449 PORT MAP(
450 rxrst => swno.rxrst,
450 rxrst => swno.rxrst,
451 di => dtmp(j),
451 di => dtmp(j),
452 si => stmp(j),
452 si => stmp(j),
453 rxclko => spw_rxclk(j),
453 rxclko => spw_rxclk(j),
454 do => swni.d(j),
454 do => swni.d(j),
455 ndo => swni.nd(j*5+4 DOWNTO j*5),
455 ndo => swni.nd(j*5+4 DOWNTO j*5),
456 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
456 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
457 END GENERATE spw_inputloop;
457 END GENERATE spw_inputloop;
458
458
459 swni.rmapnodeaddr <= (OTHERS => '0');
459 swni.rmapnodeaddr <= (OTHERS => '0');
460
460
461 -- SPW core
461 -- SPW core
462 sw0 : grspwm GENERIC MAP(
462 sw0 : grspwm GENERIC MAP(
463 tech => apa3e,
463 tech => apa3e,
464 hindex => 1,
464 hindex => 1,
465 pindex => 5,
465 pindex => 5,
466 paddr => 5,
466 paddr => 5,
467 pirq => 11,
467 pirq => 11,
468 sysfreq => 25000, -- CPU_FREQ
468 sysfreq => 25000, -- CPU_FREQ
469 rmap => 1,
469 rmap => 1,
470 rmapcrc => 1,
470 rmapcrc => 1,
471 fifosize1 => 16,
471 fifosize1 => 16,
472 fifosize2 => 16,
472 fifosize2 => 16,
473 rxclkbuftype => 1,
473 rxclkbuftype => 1,
474 rxunaligned => 0,
474 rxunaligned => 0,
475 rmapbufs => 4,
475 rmapbufs => 4,
476 ft => 0,
476 ft => 0,
477 netlist => 0,
477 netlist => 0,
478 ports => 2,
478 ports => 2,
479 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
479 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
480 memtech => apa3e,
480 memtech => apa3e,
481 destkey => 2,
481 destkey => 2,
482 spwcore => 1
482 spwcore => 1
483 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
483 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
484 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
484 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
485 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
485 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
486 )
486 )
487 PORT MAP(rstn_25, clk_25, spw_rxclk(0),
487 PORT MAP(rstn_25, clk_25, spw_rxclk(0),
488 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
488 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
489 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
489 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
490 swni, swno);
490 swni, swno);
491
491
492 swni.tickin <= '0';
492 swni.tickin <= '0';
493 swni.rmapen <= '1';
493 swni.rmapen <= '1';
494 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
494 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
495 swni.tickinraw <= '0';
495 swni.tickinraw <= '0';
496 swni.timein <= (OTHERS => '0');
496 swni.timein <= (OTHERS => '0');
497 swni.dcrstval <= (OTHERS => '0');
497 swni.dcrstval <= (OTHERS => '0');
498 swni.timerrstval <= (OTHERS => '0');
498 swni.timerrstval <= (OTHERS => '0');
499
499
500 -------------------------------------------------------------------------------
500 -------------------------------------------------------------------------------
501 -- LFR ------------------------------------------------------------------------
501 -- LFR ------------------------------------------------------------------------
502 -------------------------------------------------------------------------------
502 -------------------------------------------------------------------------------
503
503
504
504
505 LFR_rstn <= LFR_soft_rstn AND rstn_25;
505 LFR_rstn <= LFR_soft_rstn AND rstn_25;
506 --LFR_rstn <= rstn_25;
506 --LFR_rstn <= rstn_25;
507
507
508 lpp_lfr_1 : lpp_lfr
508 lpp_lfr_1 : lpp_lfr
509 GENERIC MAP (
509 GENERIC MAP (
510 Mem_use => use_RAM,
510 Mem_use => use_RAM,
511 nb_data_by_buffer_size => 32,
511 nb_data_by_buffer_size => 32,
512 nb_snapshot_param_size => 32,
512 nb_snapshot_param_size => 32,
513 delta_vector_size => 32,
513 delta_vector_size => 32,
514 delta_vector_size_f0_2 => 7, -- log2(96)
514 delta_vector_size_f0_2 => 7, -- log2(96)
515 pindex => 15,
515 pindex => 15,
516 paddr => 15,
516 paddr => 15,
517 pmask => 16#fff#,
517 pmask => 16#fff#,
518 pirq_ms => 6,
518 pirq_ms => 6,
519 pirq_wfp => 14,
519 pirq_wfp => 14,
520 hindex => 2,
520 hindex => 2,
521 top_lfr_version => X"000135") -- aa.bb.cc version
521 top_lfr_version => X"000135") -- aa.bb.cc version
522 PORT MAP (
522 PORT MAP (
523 clk => clk_25,
523 clk => clk_25,
524 rstn => LFR_rstn,
524 rstn => LFR_rstn,
525 sample_B => sample_s(2 DOWNTO 0),
525 sample_B => sample_s(2 DOWNTO 0),
526 sample_E => sample_s(7 DOWNTO 3),
526 sample_E => sample_s(7 DOWNTO 3),
527 sample_val => sample_val,
527 sample_val => sample_val,
528 apbi => apbi_ext,
528 apbi => apbi_ext,
529 apbo => apbo_ext(15),
529 apbo => apbo_ext(15),
530 ahbi => ahbi_m_ext,
530 ahbi => ahbi_m_ext,
531 ahbo => ahbo_m_ext(2),
531 ahbo => ahbo_m_ext(2),
532 coarse_time => coarse_time,
532 coarse_time => coarse_time,
533 fine_time => fine_time,
533 fine_time => fine_time,
534 data_shaping_BW => bias_fail_sw_sig,
534 data_shaping_BW => bias_fail_sw_sig,
535 debug_vector => lfr_debug_vector,
535 debug_vector => lfr_debug_vector,
536 debug_vector_ms => lfr_debug_vector_ms
536 debug_vector_ms => lfr_debug_vector_ms
537 );
537 );
538
538
539 observation_reg(11 DOWNTO 0) <= lfr_debug_vector;
539 observation_reg(11 DOWNTO 0) <= lfr_debug_vector;
540 observation_reg(31 DOWNTO 12) <= (OTHERS => '0');
540 observation_reg(31 DOWNTO 12) <= (OTHERS => '0');
541 observation_vector_0(11 DOWNTO 0) <= lfr_debug_vector;
541 observation_vector_0(11 DOWNTO 0) <= lfr_debug_vector;
542 observation_vector_1(11 DOWNTO 0) <= lfr_debug_vector;
542 observation_vector_1(11 DOWNTO 0) <= lfr_debug_vector;
543 IO0 <= rstn_25;
543 IO0 <= rstn_25;
544 IO1 <= lfr_debug_vector_ms(0); -- LFR MS FFT data_valid
544 IO1 <= lfr_debug_vector_ms(0); -- LFR MS FFT data_valid
545 IO2 <= lfr_debug_vector_ms(0); -- LFR MS FFT ready
545 IO2 <= lfr_debug_vector_ms(0); -- LFR MS FFT ready
546 IO3 <= lfr_debug_vector(0); -- LFR APBREG error_buffer_full
546 IO3 <= lfr_debug_vector(0); -- LFR APBREG error_buffer_full
547 IO4 <= lfr_debug_vector(1); -- LFR APBREG reg_sp.status_error_buffer_full
547 IO4 <= lfr_debug_vector(1); -- LFR APBREG reg_sp.status_error_buffer_full
548 IO5 <= lfr_debug_vector(8); -- LFR APBREG ready_matrix_f2
548 IO5 <= lfr_debug_vector(8); -- LFR APBREG ready_matrix_f2
549 IO6 <= lfr_debug_vector(9); -- LFR APBREG reg0_ready_matrix_f2
549 IO6 <= lfr_debug_vector(9); -- LFR APBREG reg0_ready_matrix_f2
550 IO7 <= lfr_debug_vector(10); -- LFR APBREG reg0_ready_matrix_f2
550 IO7 <= lfr_debug_vector(10); -- LFR APBREG reg0_ready_matrix_f2
551
551
552 all_sample : FOR I IN 7 DOWNTO 0 GENERATE
552 all_sample : FOR I IN 7 DOWNTO 0 GENERATE
553 sample_s(I) <= sample(I)(11 DOWNTO 0) & '0' & '0' & '0' & '0';
553 sample_s(I) <= sample(I)(11 DOWNTO 0) & '0' & '0' & '0' & '0';
554 END GENERATE all_sample;
554 END GENERATE all_sample;
555
555
556 top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2
556 top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2
557 GENERIC MAP(
557 GENERIC MAP(
558 ChannelCount => 8,
558 ChannelCount => 8,
559 SampleNbBits => 14,
559 SampleNbBits => 14,
560 ncycle_cnv_high => 40, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 /2 = 31.5
560 ncycle_cnv_high => 40, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 /2 = 31.5
561 ncycle_cnv => 249) -- 49 152 000 / 98304 /2
561 ncycle_cnv => 249) -- 49 152 000 / 98304 /2
562 PORT MAP (
562 PORT MAP (
563 -- CONV
563 -- CONV
564 cnv_clk => clk_24,
564 cnv_clk => clk_24,
565 cnv_rstn => rstn_25,
565 cnv_rstn => rstn_25,
566 cnv => ADC_nCS_sig,
566 cnv => ADC_nCS_sig,
567 -- DATA
567 -- DATA
568 clk => clk_25,
568 clk => clk_25,
569 rstn => rstn_25,
569 rstn => rstn_25,
570 sck => ADC_CLK_sig,
570 sck => ADC_CLK_sig,
571 sdo => ADC_SDO_sig,
571 sdo => ADC_SDO_sig,
572 -- SAMPLE
572 -- SAMPLE
573 sample => sample,
573 sample => sample,
574 sample_val => sample_val);
574 sample_val => sample_val);
575
575
576 --IO10 <= ADC_SDO_sig(5);
576 --IO10 <= ADC_SDO_sig(5);
577 --IO9 <= ADC_SDO_sig(4);
577 --IO9 <= ADC_SDO_sig(4);
578 --IO8 <= ADC_SDO_sig(3);
578 --IO8 <= ADC_SDO_sig(3);
579
579
580 ADC_nCS <= ADC_nCS_sig;
580 ADC_nCS <= ADC_nCS_sig;
581 ADC_CLK <= ADC_CLK_sig;
581 ADC_CLK <= ADC_CLK_sig;
582 ADC_SDO_sig <= ADC_SDO;
582 ADC_SDO_sig <= ADC_SDO;
583
583
584 sample_hk <= "0001000100010001" WHEN HK_SEL = "00" ELSE
584 sample_hk <= "0001000100010001" WHEN HK_SEL = "00" ELSE
585 "0010001000100010" WHEN HK_SEL = "10" ELSE
585 "0010001000100010" WHEN HK_SEL = "01" ELSE
586 "0100010001000100" WHEN HK_SEL = "11" ELSE
586 "0100010001000100" WHEN HK_SEL = "10" ELSE
587 (OTHERS => '0');
587 (OTHERS => '0');
588
588
589
589
590 ----------------------------------------------------------------------
590 ----------------------------------------------------------------------
591 --- GPIO -----------------------------------------------------------
591 --- GPIO -----------------------------------------------------------
592 ----------------------------------------------------------------------
592 ----------------------------------------------------------------------
593
593
594 grgpio0 : grgpio
594 grgpio0 : grgpio
595 GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8)
595 GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8)
596 PORT MAP(rstn_25, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo);
596 PORT MAP(rstn_25, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo);
597
597
598 gpioi.sig_en <= (OTHERS => '0');
598 gpioi.sig_en <= (OTHERS => '0');
599 gpioi.sig_in <= (OTHERS => '0');
599 gpioi.sig_in <= (OTHERS => '0');
600 gpioi.din <= (OTHERS => '0');
600 gpioi.din <= (OTHERS => '0');
601 --pio_pad_0 : iopad
601 --pio_pad_0 : iopad
602 -- GENERIC MAP (tech => CFG_PADTECH)
602 -- GENERIC MAP (tech => CFG_PADTECH)
603 -- PORT MAP (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0));
603 -- PORT MAP (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0));
604 --pio_pad_1 : iopad
604 --pio_pad_1 : iopad
605 -- GENERIC MAP (tech => CFG_PADTECH)
605 -- GENERIC MAP (tech => CFG_PADTECH)
606 -- PORT MAP (IO1, gpioo.dout(1), gpioo.oen(1), gpioi.din(1));
606 -- PORT MAP (IO1, gpioo.dout(1), gpioo.oen(1), gpioi.din(1));
607 --pio_pad_2 : iopad
607 --pio_pad_2 : iopad
608 -- GENERIC MAP (tech => CFG_PADTECH)
608 -- GENERIC MAP (tech => CFG_PADTECH)
609 -- PORT MAP (IO2, gpioo.dout(2), gpioo.oen(2), gpioi.din(2));
609 -- PORT MAP (IO2, gpioo.dout(2), gpioo.oen(2), gpioi.din(2));
610 --pio_pad_3 : iopad
610 --pio_pad_3 : iopad
611 -- GENERIC MAP (tech => CFG_PADTECH)
611 -- GENERIC MAP (tech => CFG_PADTECH)
612 -- PORT MAP (IO3, gpioo.dout(3), gpioo.oen(3), gpioi.din(3));
612 -- PORT MAP (IO3, gpioo.dout(3), gpioo.oen(3), gpioi.din(3));
613 --pio_pad_4 : iopad
613 --pio_pad_4 : iopad
614 -- GENERIC MAP (tech => CFG_PADTECH)
614 -- GENERIC MAP (tech => CFG_PADTECH)
615 -- PORT MAP (IO4, gpioo.dout(4), gpioo.oen(4), gpioi.din(4));
615 -- PORT MAP (IO4, gpioo.dout(4), gpioo.oen(4), gpioi.din(4));
616 --pio_pad_5 : iopad
616 --pio_pad_5 : iopad
617 -- GENERIC MAP (tech => CFG_PADTECH)
617 -- GENERIC MAP (tech => CFG_PADTECH)
618 -- PORT MAP (IO5, gpioo.dout(5), gpioo.oen(5), gpioi.din(5));
618 -- PORT MAP (IO5, gpioo.dout(5), gpioo.oen(5), gpioi.din(5));
619 --pio_pad_6 : iopad
619 --pio_pad_6 : iopad
620 -- GENERIC MAP (tech => CFG_PADTECH)
620 -- GENERIC MAP (tech => CFG_PADTECH)
621 -- PORT MAP (IO6, gpioo.dout(6), gpioo.oen(6), gpioi.din(6));
621 -- PORT MAP (IO6, gpioo.dout(6), gpioo.oen(6), gpioi.din(6));
622 --pio_pad_7 : iopad
622 --pio_pad_7 : iopad
623 -- GENERIC MAP (tech => CFG_PADTECH)
623 -- GENERIC MAP (tech => CFG_PADTECH)
624 -- PORT MAP (IO7, gpioo.dout(7), gpioo.oen(7), gpioi.din(7));
624 -- PORT MAP (IO7, gpioo.dout(7), gpioo.oen(7), gpioi.din(7));
625
625
626 PROCESS (clk_25, rstn_25)
626 PROCESS (clk_25, rstn_25)
627 BEGIN -- PROCESS
627 BEGIN -- PROCESS
628 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
628 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
629 -- --IO0 <= '0';
629 -- --IO0 <= '0';
630 -- IO1 <= '0';
630 -- IO1 <= '0';
631 -- IO2 <= '0';
631 -- IO2 <= '0';
632 -- IO3 <= '0';
632 -- IO3 <= '0';
633 -- IO4 <= '0';
633 -- IO4 <= '0';
634 -- IO5 <= '0';
634 -- IO5 <= '0';
635 -- IO6 <= '0';
635 -- IO6 <= '0';
636 -- IO7 <= '0';
636 -- IO7 <= '0';
637 IO8 <= '0';
637 IO8 <= '0';
638 IO9 <= '0';
638 IO9 <= '0';
639 IO10 <= '0';
639 IO10 <= '0';
640 IO11 <= '0';
640 IO11 <= '0';
641 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
641 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
642 CASE gpioo.dout(2 DOWNTO 0) IS
642 CASE gpioo.dout(2 DOWNTO 0) IS
643 WHEN "011" =>
643 WHEN "011" =>
644 -- --IO0 <= observation_reg(0 );
644 -- --IO0 <= observation_reg(0 );
645 -- IO1 <= observation_reg(1 );
645 -- IO1 <= observation_reg(1 );
646 -- IO2 <= observation_reg(2 );
646 -- IO2 <= observation_reg(2 );
647 -- IO3 <= observation_reg(3 );
647 -- IO3 <= observation_reg(3 );
648 -- IO4 <= observation_reg(4 );
648 -- IO4 <= observation_reg(4 );
649 -- IO5 <= observation_reg(5 );
649 -- IO5 <= observation_reg(5 );
650 -- IO6 <= observation_reg(6 );
650 -- IO6 <= observation_reg(6 );
651 -- IO7 <= observation_reg(7 );
651 -- IO7 <= observation_reg(7 );
652 IO8 <= observation_reg(8);
652 IO8 <= observation_reg(8);
653 IO9 <= observation_reg(9);
653 IO9 <= observation_reg(9);
654 IO10 <= observation_reg(10);
654 IO10 <= observation_reg(10);
655 IO11 <= observation_reg(11);
655 IO11 <= observation_reg(11);
656 WHEN "001" =>
656 WHEN "001" =>
657 -- --IO0 <= observation_reg(0 + 12);
657 -- --IO0 <= observation_reg(0 + 12);
658 -- IO1 <= observation_reg(1 + 12);
658 -- IO1 <= observation_reg(1 + 12);
659 -- IO2 <= observation_reg(2 + 12);
659 -- IO2 <= observation_reg(2 + 12);
660 -- IO3 <= observation_reg(3 + 12);
660 -- IO3 <= observation_reg(3 + 12);
661 -- IO4 <= observation_reg(4 + 12);
661 -- IO4 <= observation_reg(4 + 12);
662 -- IO5 <= observation_reg(5 + 12);
662 -- IO5 <= observation_reg(5 + 12);
663 -- IO6 <= observation_reg(6 + 12);
663 -- IO6 <= observation_reg(6 + 12);
664 -- IO7 <= observation_reg(7 + 12);
664 -- IO7 <= observation_reg(7 + 12);
665 IO8 <= observation_reg(8 + 12);
665 IO8 <= observation_reg(8 + 12);
666 IO9 <= observation_reg(9 + 12);
666 IO9 <= observation_reg(9 + 12);
667 IO10 <= observation_reg(10 + 12);
667 IO10 <= observation_reg(10 + 12);
668 IO11 <= observation_reg(11 + 12);
668 IO11 <= observation_reg(11 + 12);
669 WHEN "010" =>
669 WHEN "010" =>
670 -- --IO0 <= observation_reg(0 + 12 + 12);
670 -- --IO0 <= observation_reg(0 + 12 + 12);
671 -- IO1 <= observation_reg(1 + 12 + 12);
671 -- IO1 <= observation_reg(1 + 12 + 12);
672 -- IO2 <= observation_reg(2 + 12 + 12);
672 -- IO2 <= observation_reg(2 + 12 + 12);
673 -- IO3 <= observation_reg(3 + 12 + 12);
673 -- IO3 <= observation_reg(3 + 12 + 12);
674 -- IO4 <= observation_reg(4 + 12 + 12);
674 -- IO4 <= observation_reg(4 + 12 + 12);
675 -- IO5 <= observation_reg(5 + 12 + 12);
675 -- IO5 <= observation_reg(5 + 12 + 12);
676 -- IO6 <= observation_reg(6 + 12 + 12);
676 -- IO6 <= observation_reg(6 + 12 + 12);
677 -- IO7 <= observation_reg(7 + 12 + 12);
677 -- IO7 <= observation_reg(7 + 12 + 12);
678 IO8 <= '0';
678 IO8 <= '0';
679 IO9 <= '0';
679 IO9 <= '0';
680 IO10 <= '0';
680 IO10 <= '0';
681 IO11 <= '0';
681 IO11 <= '0';
682 WHEN "000" =>
682 WHEN "000" =>
683 -- --IO0 <= observation_vector_0(0 );
683 -- --IO0 <= observation_vector_0(0 );
684 -- IO1 <= observation_vector_0(1 );
684 -- IO1 <= observation_vector_0(1 );
685 -- IO2 <= observation_vector_0(2 );
685 -- IO2 <= observation_vector_0(2 );
686 -- IO3 <= observation_vector_0(3 );
686 -- IO3 <= observation_vector_0(3 );
687 -- IO4 <= observation_vector_0(4 );
687 -- IO4 <= observation_vector_0(4 );
688 -- IO5 <= observation_vector_0(5 );
688 -- IO5 <= observation_vector_0(5 );
689 -- IO6 <= observation_vector_0(6 );
689 -- IO6 <= observation_vector_0(6 );
690 -- IO7 <= observation_vector_0(7 );
690 -- IO7 <= observation_vector_0(7 );
691 IO8 <= observation_vector_0(8);
691 IO8 <= observation_vector_0(8);
692 IO9 <= observation_vector_0(9);
692 IO9 <= observation_vector_0(9);
693 IO10 <= observation_vector_0(10);
693 IO10 <= observation_vector_0(10);
694 IO11 <= observation_vector_0(11);
694 IO11 <= observation_vector_0(11);
695 WHEN "100" =>
695 WHEN "100" =>
696 -- --IO0 <= observation_vector_1(0 );
696 -- --IO0 <= observation_vector_1(0 );
697 -- IO1 <= observation_vector_1(1 );
697 -- IO1 <= observation_vector_1(1 );
698 -- IO2 <= observation_vector_1(2 );
698 -- IO2 <= observation_vector_1(2 );
699 -- IO3 <= observation_vector_1(3 );
699 -- IO3 <= observation_vector_1(3 );
700 -- IO4 <= observation_vector_1(4 );
700 -- IO4 <= observation_vector_1(4 );
701 -- IO5 <= observation_vector_1(5 );
701 -- IO5 <= observation_vector_1(5 );
702 -- IO6 <= observation_vector_1(6 );
702 -- IO6 <= observation_vector_1(6 );
703 -- IO7 <= observation_vector_1(7 );
703 -- IO7 <= observation_vector_1(7 );
704 IO8 <= observation_vector_1(8);
704 IO8 <= observation_vector_1(8);
705 IO9 <= observation_vector_1(9);
705 IO9 <= observation_vector_1(9);
706 IO10 <= observation_vector_1(10);
706 IO10 <= observation_vector_1(10);
707 IO11 <= observation_vector_1(11);
707 IO11 <= observation_vector_1(11);
708 WHEN OTHERS => NULL;
708 WHEN OTHERS => NULL;
709 END CASE;
709 END CASE;
710
710
711 END IF;
711 END IF;
712 END PROCESS;
712 END PROCESS;
713 -----------------------------------------------------------------------------
713 -----------------------------------------------------------------------------
714 --
714 --
715 -----------------------------------------------------------------------------
715 -----------------------------------------------------------------------------
716 all_apbo_ext : FOR I IN NB_APB_SLAVE-1+5 DOWNTO 5 GENERATE
716 all_apbo_ext : FOR I IN NB_APB_SLAVE-1+5 DOWNTO 5 GENERATE
717 apbo_ext_not_used : IF I /= 5 AND I /= 6 AND I /= 11 AND I /= 15 GENERATE
717 apbo_ext_not_used : IF I /= 5 AND I /= 6 AND I /= 11 AND I /= 15 GENERATE
718 apbo_ext(I) <= apb_none;
718 apbo_ext(I) <= apb_none;
719 END GENERATE apbo_ext_not_used;
719 END GENERATE apbo_ext_not_used;
720 END GENERATE all_apbo_ext;
720 END GENERATE all_apbo_ext;
721
721
722
722
723 all_ahbo_ext : FOR I IN NB_AHB_SLAVE-1+3 DOWNTO 3 GENERATE
723 all_ahbo_ext : FOR I IN NB_AHB_SLAVE-1+3 DOWNTO 3 GENERATE
724 ahbo_s_ext(I) <= ahbs_none;
724 ahbo_s_ext(I) <= ahbs_none;
725 END GENERATE all_ahbo_ext;
725 END GENERATE all_ahbo_ext;
726
726
727 all_ahbo_m_ext : FOR I IN NB_AHB_MASTER-1+1 DOWNTO 1 GENERATE
727 all_ahbo_m_ext : FOR I IN NB_AHB_MASTER-1+1 DOWNTO 1 GENERATE
728 ahbo_m_ext_not_used : IF I /= 1 AND I /= 2 GENERATE
728 ahbo_m_ext_not_used : IF I /= 1 AND I /= 2 GENERATE
729 ahbo_m_ext(I) <= ahbm_none;
729 ahbo_m_ext(I) <= ahbm_none;
730 END GENERATE ahbo_m_ext_not_used;
730 END GENERATE ahbo_m_ext_not_used;
731 END GENERATE all_ahbo_m_ext;
731 END GENERATE all_ahbo_m_ext;
732
732
733 END beh;
733 END beh;
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@@ -1,299 +1,326
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 ----------------------------------------------------------------------------
21 ----------------------------------------------------------------------------
22 LIBRARY ieee;
22 LIBRARY ieee;
23 USE ieee.std_logic_1164.ALL;
23 USE ieee.std_logic_1164.ALL;
24 LIBRARY grlib;
24 LIBRARY grlib;
25 USE grlib.amba.ALL;
25 USE grlib.amba.ALL;
26 USE grlib.stdlib.ALL;
26 USE grlib.stdlib.ALL;
27 USE grlib.devices.ALL;
27 USE grlib.devices.ALL;
28
28
29
29
30
30
31
31
32 PACKAGE iir_filter IS
32 PACKAGE iir_filter IS
33
33
34
34
35 --===========================================================|
35 --===========================================================|
36 --================A L U C O N T R O L======================|
36 --================A L U C O N T R O L======================|
37 --===========================================================|
37 --===========================================================|
38 CONSTANT IDLE : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0000";
38 CONSTANT IDLE : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0000";
39 CONSTANT MAC_op : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0001";
39 CONSTANT MAC_op : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0001";
40 CONSTANT MULT : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0010";
40 CONSTANT MULT : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0010";
41 CONSTANT ADD : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0011";
41 CONSTANT ADD : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0011";
42 CONSTANT clr_mac : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0100";
42 CONSTANT clr_mac : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0100";
43 CONSTANT MULT_with_clear_ADD : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0101";
43 CONSTANT MULT_with_clear_ADD : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0101";
44
44
45 --____
45 --____
46 --RAM |
46 --RAM |
47 --____|
47 --____|
48 CONSTANT use_RAM : INTEGER := 1;
48 CONSTANT use_RAM : INTEGER := 1;
49 CONSTANT use_CEL : INTEGER := 0;
49 CONSTANT use_CEL : INTEGER := 0;
50
50
51
51
52 --===========================================================|
52 --===========================================================|
53 --=============C O E F S ====================================|
53 --=============C O E F S ====================================|
54 --===========================================================|
54 --===========================================================|
55 -- create a specific type of data for coefs to avoid errors |
55 -- create a specific type of data for coefs to avoid errors |
56 --===========================================================|
56 --===========================================================|
57
57
58 TYPE scaleValT IS ARRAY(NATURAL RANGE <>) OF INTEGER;
58 TYPE scaleValT IS ARRAY(NATURAL RANGE <>) OF INTEGER;
59
59
60 TYPE samplT IS ARRAY(NATURAL RANGE <>, NATURAL RANGE <>) OF STD_LOGIC;
60 TYPE samplT IS ARRAY(NATURAL RANGE <>, NATURAL RANGE <>) OF STD_LOGIC;
61
61
62 TYPE in_IIR_CEL_reg IS RECORD
62 TYPE in_IIR_CEL_reg IS RECORD
63 config : STD_LOGIC_VECTOR(31 DOWNTO 0);
63 config : STD_LOGIC_VECTOR(31 DOWNTO 0);
64 virgPos : STD_LOGIC_VECTOR(4 DOWNTO 0);
64 virgPos : STD_LOGIC_VECTOR(4 DOWNTO 0);
65 END RECORD;
65 END RECORD;
66
66
67 TYPE out_IIR_CEL_reg IS RECORD
67 TYPE out_IIR_CEL_reg IS RECORD
68 config : STD_LOGIC_VECTOR(31 DOWNTO 0);
68 config : STD_LOGIC_VECTOR(31 DOWNTO 0);
69 status : STD_LOGIC_VECTOR(31 DOWNTO 0);
69 status : STD_LOGIC_VECTOR(31 DOWNTO 0);
70 END RECORD;
70 END RECORD;
71
71
72
72
73 COMPONENT APB_IIR_CEL IS
73 COMPONENT APB_IIR_CEL IS
74 GENERIC (
74 GENERIC (
75 tech : INTEGER := 0;
75 tech : INTEGER := 0;
76 pindex : INTEGER := 0;
76 pindex : INTEGER := 0;
77 paddr : INTEGER := 0;
77 paddr : INTEGER := 0;
78 pmask : INTEGER := 16#fff#;
78 pmask : INTEGER := 16#fff#;
79 pirq : INTEGER := 0;
79 pirq : INTEGER := 0;
80 abits : INTEGER := 8;
80 abits : INTEGER := 8;
81 Sample_SZ : INTEGER := 16;
81 Sample_SZ : INTEGER := 16;
82 ChanelsCount : INTEGER := 6;
82 ChanelsCount : INTEGER := 6;
83 Coef_SZ : INTEGER := 9;
83 Coef_SZ : INTEGER := 9;
84 CoefCntPerCel : INTEGER := 6;
84 CoefCntPerCel : INTEGER := 6;
85 Cels_count : INTEGER := 5;
85 Cels_count : INTEGER := 5;
86 virgPos : INTEGER := 7;
86 virgPos : INTEGER := 7;
87 Mem_use : INTEGER := use_RAM
87 Mem_use : INTEGER := use_RAM
88 );
88 );
89 PORT (
89 PORT (
90 rst : IN STD_LOGIC;
90 rst : IN STD_LOGIC;
91 clk : IN STD_LOGIC;
91 clk : IN STD_LOGIC;
92 apbi : IN apb_slv_in_type;
92 apbi : IN apb_slv_in_type;
93 apbo : OUT apb_slv_out_type;
93 apbo : OUT apb_slv_out_type;
94 sample_clk : IN STD_LOGIC;
94 sample_clk : IN STD_LOGIC;
95 sample_clk_out : OUT STD_LOGIC;
95 sample_clk_out : OUT STD_LOGIC;
96 sample_in : IN samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
96 sample_in : IN samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
97 sample_out : OUT samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
97 sample_out : OUT samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
98 CoefsInitVal : IN STD_LOGIC_VECTOR((Cels_count*CoefCntPerCel*Coef_SZ)-1 DOWNTO 0) := (OTHERS => '1')
98 CoefsInitVal : IN STD_LOGIC_VECTOR((Cels_count*CoefCntPerCel*Coef_SZ)-1 DOWNTO 0) := (OTHERS => '1')
99 );
99 );
100 END COMPONENT;
100 END COMPONENT;
101
101
102
102
103 COMPONENT Top_IIR IS
103 COMPONENT Top_IIR IS
104 GENERIC(
104 GENERIC(
105 Sample_SZ : INTEGER := 18;
105 Sample_SZ : INTEGER := 18;
106 ChanelsCount : INTEGER := 1;
106 ChanelsCount : INTEGER := 1;
107 Coef_SZ : INTEGER := 9;
107 Coef_SZ : INTEGER := 9;
108 CoefCntPerCel : INTEGER := 6;
108 CoefCntPerCel : INTEGER := 6;
109 Cels_count : INTEGER := 5);
109 Cels_count : INTEGER := 5);
110 PORT(
110 PORT(
111 reset : IN STD_LOGIC;
111 reset : IN STD_LOGIC;
112 clk : IN STD_LOGIC;
112 clk : IN STD_LOGIC;
113 sample_clk : IN STD_LOGIC;
113 sample_clk : IN STD_LOGIC;
114 -- BP : in std_logic;
114 -- BP : in std_logic;
115 -- BPinput : in std_logic_vector(3 downto 0);
115 -- BPinput : in std_logic_vector(3 downto 0);
116 LVLinput : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
116 LVLinput : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
117 INsample : OUT samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
117 INsample : OUT samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
118 OUTsample : OUT samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0)
118 OUTsample : OUT samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0)
119 );
119 );
120 END COMPONENT;
120 END COMPONENT;
121
121
122 COMPONENT IIR_CEL_CTRLR_v2
122 COMPONENT IIR_CEL_CTRLR_v2
123 GENERIC (
123 GENERIC (
124 tech : INTEGER;
124 tech : INTEGER;
125 Mem_use : INTEGER;
125 Mem_use : INTEGER;
126 Sample_SZ : INTEGER;
126 Sample_SZ : INTEGER;
127 Coef_SZ : INTEGER;
127 Coef_SZ : INTEGER;
128 Coef_Nb : INTEGER;
128 Coef_Nb : INTEGER;
129 Coef_sel_SZ : INTEGER;
129 Coef_sel_SZ : INTEGER;
130 Cels_count : INTEGER;
130 Cels_count : INTEGER;
131 ChanelsCount : INTEGER);
131 ChanelsCount : INTEGER);
132 PORT (
132 PORT (
133 rstn : IN STD_LOGIC;
133 rstn : IN STD_LOGIC;
134 clk : IN STD_LOGIC;
134 clk : IN STD_LOGIC;
135 virg_pos : IN INTEGER;
135 virg_pos : IN INTEGER;
136 coefs : IN STD_LOGIC_VECTOR((Coef_SZ*Coef_Nb)-1 DOWNTO 0);
136 coefs : IN STD_LOGIC_VECTOR((Coef_SZ*Coef_Nb)-1 DOWNTO 0);
137 sample_in_val : IN STD_LOGIC;
137 sample_in_val : IN STD_LOGIC;
138 sample_in : IN samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
138 sample_in : IN samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
139 sample_out_val : OUT STD_LOGIC;
139 sample_out_val : OUT STD_LOGIC;
140 sample_out : OUT samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0));
140 sample_out : OUT samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0));
141 END COMPONENT;
141 END COMPONENT;
142
143 COMPONENT IIR_CEL_CTRLR_v3
144 GENERIC (
145 tech : INTEGER;
146 Mem_use : INTEGER;
147 Sample_SZ : INTEGER;
148 Coef_SZ : INTEGER;
149 Coef_Nb : INTEGER;
150 Coef_sel_SZ : INTEGER;
151 Cels_count : INTEGER;
152 ChanelsCount : INTEGER);
153 PORT (
154 rstn : IN STD_LOGIC;
155 clk : IN STD_LOGIC;
156 virg_pos : IN INTEGER;
157 coefs : IN STD_LOGIC_VECTOR((Coef_SZ*Coef_Nb)-1 DOWNTO 0);
158 sample_in1_val : IN STD_LOGIC;
159 sample_in1 : IN samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
160 sample_in2_val : IN STD_LOGIC;
161 sample_in2 : IN samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
162 sample_out1_val : OUT STD_LOGIC;
163 sample_out1 : OUT samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
164 sample_out2_val : OUT STD_LOGIC;
165 sample_out2 : OUT samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0));
166 END COMPONENT;
142
167
143
168
169
170
144 --component FilterCTRLR is
171 --component FilterCTRLR is
145 --port(
172 --port(
146 -- reset : in std_logic;
173 -- reset : in std_logic;
147 -- clk : in std_logic;
174 -- clk : in std_logic;
148 -- sample_clk : in std_logic;
175 -- sample_clk : in std_logic;
149 -- ALU_Ctrl : out std_logic_vector(3 downto 0);
176 -- ALU_Ctrl : out std_logic_vector(3 downto 0);
150 -- sample_in : in samplT;
177 -- sample_in : in samplT;
151 -- coef : out std_logic_vector(Coef_SZ-1 downto 0);
178 -- coef : out std_logic_vector(Coef_SZ-1 downto 0);
152 -- sample : out std_logic_vector(Smpl_SZ-1 downto 0)
179 -- sample : out std_logic_vector(Smpl_SZ-1 downto 0)
153 --);
180 --);
154 --end component;
181 --end component;
155
182
156
183
157 --component FILTER_RAM_CTRLR is
184 --component FILTER_RAM_CTRLR is
158 --port(
185 --port(
159 -- reset : in std_logic;
186 -- reset : in std_logic;
160 -- clk : in std_logic;
187 -- clk : in std_logic;
161 -- run : in std_logic;
188 -- run : in std_logic;
162 -- GO_0 : in std_logic;
189 -- GO_0 : in std_logic;
163 -- B_A : in std_logic;
190 -- B_A : in std_logic;
164 -- writeForce : in std_logic;
191 -- writeForce : in std_logic;
165 -- next_blk : in std_logic;
192 -- next_blk : in std_logic;
166 -- sample_in : in std_logic_vector(Smpl_SZ-1 downto 0);
193 -- sample_in : in std_logic_vector(Smpl_SZ-1 downto 0);
167 -- sample_out : out std_logic_vector(Smpl_SZ-1 downto 0)
194 -- sample_out : out std_logic_vector(Smpl_SZ-1 downto 0)
168 --);
195 --);
169 --end component;
196 --end component;
170
197
171
198
172 COMPONENT IIR_CEL_CTRLR IS
199 COMPONENT IIR_CEL_CTRLR IS
173 GENERIC(
200 GENERIC(
174 tech : INTEGER := 0;
201 tech : INTEGER := 0;
175 Sample_SZ : INTEGER := 16;
202 Sample_SZ : INTEGER := 16;
176 ChanelsCount : INTEGER := 1;
203 ChanelsCount : INTEGER := 1;
177 Coef_SZ : INTEGER := 9;
204 Coef_SZ : INTEGER := 9;
178 CoefCntPerCel : INTEGER := 3;
205 CoefCntPerCel : INTEGER := 3;
179 Cels_count : INTEGER := 5;
206 Cels_count : INTEGER := 5;
180 Mem_use : INTEGER := use_RAM
207 Mem_use : INTEGER := use_RAM
181 );
208 );
182 PORT(
209 PORT(
183 reset : IN STD_LOGIC;
210 reset : IN STD_LOGIC;
184 clk : IN STD_LOGIC;
211 clk : IN STD_LOGIC;
185 sample_clk : IN STD_LOGIC;
212 sample_clk : IN STD_LOGIC;
186 sample_in : IN samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
213 sample_in : IN samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
187 sample_out : OUT samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
214 sample_out : OUT samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
188 virg_pos : IN INTEGER;
215 virg_pos : IN INTEGER;
189 GOtest : OUT STD_LOGIC;
216 GOtest : OUT STD_LOGIC;
190 coefs : IN STD_LOGIC_VECTOR(Coef_SZ*CoefCntPerCel*Cels_count-1 DOWNTO 0)
217 coefs : IN STD_LOGIC_VECTOR(Coef_SZ*CoefCntPerCel*Cels_count-1 DOWNTO 0)
191 );
218 );
192 END COMPONENT;
219 END COMPONENT;
193
220
194
221
195 COMPONENT RAM IS
222 COMPONENT RAM IS
196 GENERIC(
223 GENERIC(
197 Input_SZ_1 : INTEGER := 8
224 Input_SZ_1 : INTEGER := 8
198 );
225 );
199 PORT(WD : IN STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0); RD : OUT
226 PORT(WD : IN STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0); RD : OUT
200 STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0); WEN, REN : IN STD_LOGIC;
227 STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0); WEN, REN : IN STD_LOGIC;
201 WADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0); RADDR : IN
228 WADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0); RADDR : IN
202 STD_LOGIC_VECTOR(7 DOWNTO 0); RWCLK, RESET : IN STD_LOGIC
229 STD_LOGIC_VECTOR(7 DOWNTO 0); RWCLK, RESET : IN STD_LOGIC
203 ) ;
230 ) ;
204 END COMPONENT;
231 END COMPONENT;
205
232
206 COMPONENT RAM_CEL is
233 COMPONENT RAM_CEL is
207 generic(DataSz : integer range 1 to 32 := 8;
234 generic(DataSz : integer range 1 to 32 := 8;
208 abits : integer range 2 to 12 := 8);
235 abits : integer range 2 to 12 := 8);
209 port( WD : in std_logic_vector(DataSz-1 downto 0); RD : out
236 port( WD : in std_logic_vector(DataSz-1 downto 0); RD : out
210 std_logic_vector(DataSz-1 downto 0);WEN, REN : in std_logic;
237 std_logic_vector(DataSz-1 downto 0);WEN, REN : in std_logic;
211 WADDR : in std_logic_vector(abits-1 downto 0); RADDR : in
238 WADDR : in std_logic_vector(abits-1 downto 0); RADDR : in
212 std_logic_vector(abits-1 downto 0);RWCLK, RESET : in std_logic
239 std_logic_vector(abits-1 downto 0);RWCLK, RESET : in std_logic
213 ) ;
240 ) ;
214 end COMPONENT;
241 end COMPONENT;
215
242
216 COMPONENT RAM_CEL_N
243 COMPONENT RAM_CEL_N
217 GENERIC (
244 GENERIC (
218 size : INTEGER);
245 size : INTEGER);
219 PORT (
246 PORT (
220 WD : IN STD_LOGIC_VECTOR(size-1 DOWNTO 0);
247 WD : IN STD_LOGIC_VECTOR(size-1 DOWNTO 0);
221 RD : OUT STD_LOGIC_VECTOR(size-1 DOWNTO 0);
248 RD : OUT STD_LOGIC_VECTOR(size-1 DOWNTO 0);
222 WEN, REN : IN STD_LOGIC;
249 WEN, REN : IN STD_LOGIC;
223 WADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
250 WADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
224 RADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
251 RADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
225 RWCLK, RESET : IN STD_LOGIC);
252 RWCLK, RESET : IN STD_LOGIC);
226 END COMPONENT;
253 END COMPONENT;
227
254
228 COMPONENT IIR_CEL_FILTER IS
255 COMPONENT IIR_CEL_FILTER IS
229 GENERIC(
256 GENERIC(
230 tech : INTEGER := 0;
257 tech : INTEGER := 0;
231 Sample_SZ : INTEGER := 16;
258 Sample_SZ : INTEGER := 16;
232 ChanelsCount : INTEGER := 1;
259 ChanelsCount : INTEGER := 1;
233 Coef_SZ : INTEGER := 9;
260 Coef_SZ : INTEGER := 9;
234 CoefCntPerCel : INTEGER := 3;
261 CoefCntPerCel : INTEGER := 3;
235 Cels_count : INTEGER := 5;
262 Cels_count : INTEGER := 5;
236 Mem_use : INTEGER := use_RAM);
263 Mem_use : INTEGER := use_RAM);
237 PORT(
264 PORT(
238 reset : IN STD_LOGIC;
265 reset : IN STD_LOGIC;
239 clk : IN STD_LOGIC;
266 clk : IN STD_LOGIC;
240 sample_clk : IN STD_LOGIC;
267 sample_clk : IN STD_LOGIC;
241 regs_in : IN in_IIR_CEL_reg;
268 regs_in : IN in_IIR_CEL_reg;
242 regs_out : IN out_IIR_CEL_reg;
269 regs_out : IN out_IIR_CEL_reg;
243 sample_in : IN samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
270 sample_in : IN samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
244 sample_out : OUT samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
271 sample_out : OUT samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
245 GOtest : OUT STD_LOGIC;
272 GOtest : OUT STD_LOGIC;
246 coefs : IN STD_LOGIC_VECTOR(Coef_SZ*CoefCntPerCel*Cels_count-1 DOWNTO 0)
273 coefs : IN STD_LOGIC_VECTOR(Coef_SZ*CoefCntPerCel*Cels_count-1 DOWNTO 0)
247
274
248 );
275 );
249 END COMPONENT;
276 END COMPONENT;
250
277
251
278
252 COMPONENT RAM_CTRLR2 IS
279 COMPONENT RAM_CTRLR2 IS
253 GENERIC(
280 GENERIC(
254 tech : INTEGER := 0;
281 tech : INTEGER := 0;
255 Input_SZ_1 : INTEGER := 16;
282 Input_SZ_1 : INTEGER := 16;
256 Mem_use : INTEGER := use_RAM
283 Mem_use : INTEGER := use_RAM
257 );
284 );
258 PORT(
285 PORT(
259 reset : IN STD_LOGIC;
286 reset : IN STD_LOGIC;
260 clk : IN STD_LOGIC;
287 clk : IN STD_LOGIC;
261 WD_sel : IN STD_LOGIC;
288 WD_sel : IN STD_LOGIC;
262 Read : IN STD_LOGIC;
289 Read : IN STD_LOGIC;
263 WADDR_sel : IN STD_LOGIC;
290 WADDR_sel : IN STD_LOGIC;
264 count : IN STD_LOGIC;
291 count : IN STD_LOGIC;
265 SVG_ADDR : IN STD_LOGIC;
292 SVG_ADDR : IN STD_LOGIC;
266 Write : IN STD_LOGIC;
293 Write : IN STD_LOGIC;
267 GO_0 : IN STD_LOGIC;
294 GO_0 : IN STD_LOGIC;
268 sample_in : IN STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0);
295 sample_in : IN STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0);
269 sample_out : OUT STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0)
296 sample_out : OUT STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0)
270 );
297 );
271 END COMPONENT;
298 END COMPONENT;
272
299
273 COMPONENT APB_IIR_Filter IS
300 COMPONENT APB_IIR_Filter IS
274 GENERIC (
301 GENERIC (
275 tech : INTEGER := 0;
302 tech : INTEGER := 0;
276 pindex : INTEGER := 0;
303 pindex : INTEGER := 0;
277 paddr : INTEGER := 0;
304 paddr : INTEGER := 0;
278 pmask : INTEGER := 16#fff#;
305 pmask : INTEGER := 16#fff#;
279 pirq : INTEGER := 0;
306 pirq : INTEGER := 0;
280 abits : INTEGER := 8;
307 abits : INTEGER := 8;
281 Sample_SZ : INTEGER := 16;
308 Sample_SZ : INTEGER := 16;
282 ChanelsCount : INTEGER := 1;
309 ChanelsCount : INTEGER := 1;
283 Coef_SZ : INTEGER := 9;
310 Coef_SZ : INTEGER := 9;
284 CoefCntPerCel : INTEGER := 6;
311 CoefCntPerCel : INTEGER := 6;
285 Cels_count : INTEGER := 5;
312 Cels_count : INTEGER := 5;
286 virgPos : INTEGER := 3;
313 virgPos : INTEGER := 3;
287 Mem_use : INTEGER := use_RAM
314 Mem_use : INTEGER := use_RAM
288 );
315 );
289 PORT (
316 PORT (
290 rst : IN STD_LOGIC;
317 rst : IN STD_LOGIC;
291 clk : IN STD_LOGIC;
318 clk : IN STD_LOGIC;
292 apbi : IN apb_slv_in_type;
319 apbi : IN apb_slv_in_type;
293 apbo : OUT apb_slv_out_type;
320 apbo : OUT apb_slv_out_type;
294 sample_clk_out : OUT STD_LOGIC;
321 sample_clk_out : OUT STD_LOGIC;
295 GOtest : OUT STD_LOGIC;
322 GOtest : OUT STD_LOGIC;
296 CoefsInitVal : IN STD_LOGIC_VECTOR((Cels_count*CoefCntPerCel*Coef_SZ)-1 DOWNTO 0) := (OTHERS => '1')
323 CoefsInitVal : IN STD_LOGIC_VECTOR((Cels_count*CoefCntPerCel*Coef_SZ)-1 DOWNTO 0) := (OTHERS => '1')
297 );
324 );
298 END COMPONENT;
325 END COMPONENT;
299 END;
326 END;
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@@ -1,8 +1,10
1 iir_filter.vhd
1 iir_filter.vhd
2 FILTERcfg.vhd
2 FILTERcfg.vhd
3 RAM.vhd
3 RAM.vhd
4 RAM_CEL.vhd
4 RAM_CEL.vhd
5 RAM_CTRLR_v2.vhd
5 RAM_CTRLR_v2.vhd
6 IIR_CEL_CTRLR_v2_CONTROL.vhd
6 IIR_CEL_CTRLR_v2_CONTROL.vhd
7 IIR_CEL_CTRLR_v2_DATAFLOW.vhd
7 IIR_CEL_CTRLR_v2_DATAFLOW.vhd
8 IIR_CEL_CTRLR_v2.vhd
8 IIR_CEL_CTRLR_v2.vhd
9 IIR_CEL_CTRLR_v3_DATAFLOW.vhd
10 IIR_CEL_CTRLR_v3.vhd
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@@ -1,825 +1,825
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- jean-christophe.pellion@easii-ic.com
21 -- jean-christophe.pellion@easii-ic.com
22 -------------------------------------------------------------------------------
22 -------------------------------------------------------------------------------
23 LIBRARY ieee;
23 LIBRARY ieee;
24 USE ieee.std_logic_1164.ALL;
24 USE ieee.std_logic_1164.ALL;
25 USE ieee.numeric_std.ALL;
25 USE ieee.numeric_std.ALL;
26
26
27 LIBRARY grlib;
27 LIBRARY grlib;
28 USE grlib.amba.ALL;
28 USE grlib.amba.ALL;
29 USE grlib.stdlib.ALL;
29 USE grlib.stdlib.ALL;
30 USE grlib.devices.ALL;
30 USE grlib.devices.ALL;
31
31
32 LIBRARY lpp;
32 LIBRARY lpp;
33 USE lpp.lpp_lfr_pkg.ALL;
33 USE lpp.lpp_lfr_pkg.ALL;
34 USE lpp.apb_devices_list.ALL;
34 USE lpp.apb_devices_list.ALL;
35 USE lpp.lpp_memory.ALL;
35 USE lpp.lpp_memory.ALL;
36 USE lpp.lpp_lfr_apbreg_pkg.ALL;
36 USE lpp.lpp_lfr_apbreg_pkg.ALL;
37
37
38 LIBRARY techmap;
38 LIBRARY techmap;
39 USE techmap.gencomp.ALL;
39 USE techmap.gencomp.ALL;
40
40
41 ENTITY lpp_lfr_apbreg IS
41 ENTITY lpp_lfr_apbreg IS
42 GENERIC (
42 GENERIC (
43 nb_data_by_buffer_size : INTEGER := 11;
43 nb_data_by_buffer_size : INTEGER := 11;
44 nb_snapshot_param_size : INTEGER := 11;
44 nb_snapshot_param_size : INTEGER := 11;
45 delta_vector_size : INTEGER := 20;
45 delta_vector_size : INTEGER := 20;
46 delta_vector_size_f0_2 : INTEGER := 3;
46 delta_vector_size_f0_2 : INTEGER := 3;
47
47
48 pindex : INTEGER := 4;
48 pindex : INTEGER := 4;
49 paddr : INTEGER := 4;
49 paddr : INTEGER := 4;
50 pmask : INTEGER := 16#fff#;
50 pmask : INTEGER := 16#fff#;
51 pirq_ms : INTEGER := 0;
51 pirq_ms : INTEGER := 0;
52 pirq_wfp : INTEGER := 1;
52 pirq_wfp : INTEGER := 1;
53 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) := X"000000");
53 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) := X"000000");
54 PORT (
54 PORT (
55 -- AMBA AHB system signals
55 -- AMBA AHB system signals
56 HCLK : IN STD_ULOGIC;
56 HCLK : IN STD_ULOGIC;
57 HRESETn : IN STD_ULOGIC;
57 HRESETn : IN STD_ULOGIC;
58
58
59 -- AMBA APB Slave Interface
59 -- AMBA APB Slave Interface
60 apbi : IN apb_slv_in_type;
60 apbi : IN apb_slv_in_type;
61 apbo : OUT apb_slv_out_type;
61 apbo : OUT apb_slv_out_type;
62
62
63 ---------------------------------------------------------------------------
63 ---------------------------------------------------------------------------
64 -- Spectral Matrix Reg
64 -- Spectral Matrix Reg
65 run_ms : OUT STD_LOGIC;
65 run_ms : OUT STD_LOGIC;
66 -- IN
66 -- IN
67 ready_matrix_f0 : IN STD_LOGIC;
67 ready_matrix_f0 : IN STD_LOGIC;
68 ready_matrix_f1 : IN STD_LOGIC;
68 ready_matrix_f1 : IN STD_LOGIC;
69 ready_matrix_f2 : IN STD_LOGIC;
69 ready_matrix_f2 : IN STD_LOGIC;
70
70
71 -- error_bad_component_error : IN STD_LOGIC;
71 -- error_bad_component_error : IN STD_LOGIC;
72 error_buffer_full : IN STD_LOGIC; -- TODO
72 error_buffer_full : IN STD_LOGIC; -- TODO
73 error_input_fifo_write : IN STD_LOGIC_VECTOR(2 DOWNTO 0); -- TODO
73 error_input_fifo_write : IN STD_LOGIC_VECTOR(2 DOWNTO 0); -- TODO
74
74
75 -- debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
75 -- debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
76
76
77 -- OUT
77 -- OUT
78 status_ready_matrix_f0 : OUT STD_LOGIC;
78 status_ready_matrix_f0 : OUT STD_LOGIC;
79 status_ready_matrix_f1 : OUT STD_LOGIC;
79 status_ready_matrix_f1 : OUT STD_LOGIC;
80 status_ready_matrix_f2 : OUT STD_LOGIC;
80 status_ready_matrix_f2 : OUT STD_LOGIC;
81
81
82 --config_active_interruption_onNewMatrix : OUT STD_LOGIC;
82 --config_active_interruption_onNewMatrix : OUT STD_LOGIC;
83 --config_active_interruption_onError : OUT STD_LOGIC;
83 --config_active_interruption_onError : OUT STD_LOGIC;
84
84
85 addr_matrix_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
85 addr_matrix_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
86 addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
86 addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
87 addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
87 addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
88
88
89 length_matrix_f0 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
89 length_matrix_f0 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
90 length_matrix_f1 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
90 length_matrix_f1 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
91 length_matrix_f2 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
91 length_matrix_f2 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
92
92
93 matrix_time_f0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
93 matrix_time_f0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
94 matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
94 matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
95 matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
95 matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
96
96
97 ---------------------------------------------------------------------------
97 ---------------------------------------------------------------------------
98 ---------------------------------------------------------------------------
98 ---------------------------------------------------------------------------
99 -- WaveForm picker Reg
99 -- WaveForm picker Reg
100 --status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
100 --status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
101 --status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
101 --status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
102 --status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
102 --status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
103 status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
103 status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
104
104
105 -- OUT
105 -- OUT
106 data_shaping_BW : OUT STD_LOGIC;
106 data_shaping_BW : OUT STD_LOGIC;
107 data_shaping_SP0 : OUT STD_LOGIC;
107 data_shaping_SP0 : OUT STD_LOGIC;
108 data_shaping_SP1 : OUT STD_LOGIC;
108 data_shaping_SP1 : OUT STD_LOGIC;
109 data_shaping_R0 : OUT STD_LOGIC;
109 data_shaping_R0 : OUT STD_LOGIC;
110 data_shaping_R1 : OUT STD_LOGIC;
110 data_shaping_R1 : OUT STD_LOGIC;
111 data_shaping_R2 : OUT STD_LOGIC;
111 data_shaping_R2 : OUT STD_LOGIC;
112
112
113 delta_snapshot : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
113 delta_snapshot : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
114 delta_f0 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
114 delta_f0 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
115 delta_f0_2 : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
115 delta_f0_2 : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
116 delta_f1 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
116 delta_f1 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
117 delta_f2 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
117 delta_f2 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
118 nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
118 nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
119 --nb_word_by_buffer : OUT STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
119 --nb_word_by_buffer : OUT STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
120 nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
120 nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
121
121
122 enable_f0 : OUT STD_LOGIC;
122 enable_f0 : OUT STD_LOGIC;
123 enable_f1 : OUT STD_LOGIC;
123 enable_f1 : OUT STD_LOGIC;
124 enable_f2 : OUT STD_LOGIC;
124 enable_f2 : OUT STD_LOGIC;
125 enable_f3 : OUT STD_LOGIC;
125 enable_f3 : OUT STD_LOGIC;
126
126
127 burst_f0 : OUT STD_LOGIC;
127 burst_f0 : OUT STD_LOGIC;
128 burst_f1 : OUT STD_LOGIC;
128 burst_f1 : OUT STD_LOGIC;
129 burst_f2 : OUT STD_LOGIC;
129 burst_f2 : OUT STD_LOGIC;
130
130
131 run : OUT STD_LOGIC;
131 run : OUT STD_LOGIC;
132
132
133 start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0);
133 start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0);
134
134
135 wfp_status_buffer_ready : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
135 wfp_status_buffer_ready : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
136 wfp_addr_buffer : OUT STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
136 wfp_addr_buffer : OUT STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
137 wfp_length_buffer : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
137 wfp_length_buffer : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
138 wfp_ready_buffer : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
138 wfp_ready_buffer : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
139 wfp_buffer_time : IN STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
139 wfp_buffer_time : IN STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
140 wfp_error_buffer_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
140 wfp_error_buffer_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
141 ---------------------------------------------------------------------------
141 ---------------------------------------------------------------------------
142 sample_f3_v : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
142 sample_f3_v : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
143 sample_f3_e1 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
143 sample_f3_e1 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
144 sample_f3_e2 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
144 sample_f3_e2 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
145 sample_f3_valid : IN STD_LOGIC;
145 sample_f3_valid : IN STD_LOGIC;
146 ---------------------------------------------------------------------------
146 ---------------------------------------------------------------------------
147 debug_vector : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
147 debug_vector : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
148
148
149 );
149 );
150
150
151 END lpp_lfr_apbreg;
151 END lpp_lfr_apbreg;
152
152
153 ARCHITECTURE beh OF lpp_lfr_apbreg IS
153 ARCHITECTURE beh OF lpp_lfr_apbreg IS
154
154
155 CONSTANT REVISION : INTEGER := 1;
155 CONSTANT REVISION : INTEGER := 1;
156
156
157 CONSTANT pconfig : apb_config_type := (
157 CONSTANT pconfig : apb_config_type := (
158 0 => ahb_device_reg (lpp.apb_devices_list.VENDOR_LPP, lpp.apb_devices_list.LPP_LFR, 0, REVISION, pirq_wfp),
158 0 => ahb_device_reg (lpp.apb_devices_list.VENDOR_LPP, lpp.apb_devices_list.LPP_LFR, 0, REVISION, pirq_wfp),
159 1 => apb_iobar(paddr, pmask));
159 1 => apb_iobar(paddr, pmask));
160
160
161 --CONSTANT pconfig : apb_config_type := (
161 --CONSTANT pconfig : apb_config_type := (
162 -- 0 => ahb_device_reg (16#19#, 16#19#, 0, REVISION, pirq_wfp),
162 -- 0 => ahb_device_reg (16#19#, 16#19#, 0, REVISION, pirq_wfp),
163 -- 1 => apb_iobar(paddr, pmask));
163 -- 1 => apb_iobar(paddr, pmask));
164
164
165 TYPE lpp_SpectralMatrix_regs IS RECORD
165 TYPE lpp_SpectralMatrix_regs IS RECORD
166 config_active_interruption_onNewMatrix : STD_LOGIC;
166 config_active_interruption_onNewMatrix : STD_LOGIC;
167 config_active_interruption_onError : STD_LOGIC;
167 config_active_interruption_onError : STD_LOGIC;
168 config_ms_run : STD_LOGIC;
168 config_ms_run : STD_LOGIC;
169 status_ready_matrix_f0_0 : STD_LOGIC;
169 status_ready_matrix_f0_0 : STD_LOGIC;
170 status_ready_matrix_f1_0 : STD_LOGIC;
170 status_ready_matrix_f1_0 : STD_LOGIC;
171 status_ready_matrix_f2_0 : STD_LOGIC;
171 status_ready_matrix_f2_0 : STD_LOGIC;
172 status_ready_matrix_f0_1 : STD_LOGIC;
172 status_ready_matrix_f0_1 : STD_LOGIC;
173 status_ready_matrix_f1_1 : STD_LOGIC;
173 status_ready_matrix_f1_1 : STD_LOGIC;
174 status_ready_matrix_f2_1 : STD_LOGIC;
174 status_ready_matrix_f2_1 : STD_LOGIC;
175 -- status_error_bad_component_error : STD_LOGIC;
175 -- status_error_bad_component_error : STD_LOGIC;
176 status_error_buffer_full : STD_LOGIC;
176 status_error_buffer_full : STD_LOGIC;
177 status_error_input_fifo_write : STD_LOGIC_VECTOR(2 DOWNTO 0);
177 status_error_input_fifo_write : STD_LOGIC_VECTOR(2 DOWNTO 0);
178
178
179 addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
179 addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
180 addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
180 addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
181 addr_matrix_f1_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
181 addr_matrix_f1_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
182 addr_matrix_f1_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
182 addr_matrix_f1_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
183 addr_matrix_f2_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
183 addr_matrix_f2_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
184 addr_matrix_f2_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
184 addr_matrix_f2_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
185
185
186 length_matrix : STD_LOGIC_VECTOR(25 DOWNTO 0);
186 length_matrix : STD_LOGIC_VECTOR(25 DOWNTO 0);
187
187
188 time_matrix_f0_0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
188 time_matrix_f0_0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
189 time_matrix_f0_1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
189 time_matrix_f0_1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
190 time_matrix_f1_0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
190 time_matrix_f1_0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
191 time_matrix_f1_1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
191 time_matrix_f1_1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
192 time_matrix_f2_0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
192 time_matrix_f2_0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
193 time_matrix_f2_1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
193 time_matrix_f2_1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
194 END RECORD;
194 END RECORD;
195 SIGNAL reg_sp : lpp_SpectralMatrix_regs;
195 SIGNAL reg_sp : lpp_SpectralMatrix_regs;
196
196
197 TYPE lpp_WaveformPicker_regs IS RECORD
197 TYPE lpp_WaveformPicker_regs IS RECORD
198 -- status_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
198 -- status_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
199 -- status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
199 -- status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
200 status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
200 status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
201 data_shaping_BW : STD_LOGIC;
201 data_shaping_BW : STD_LOGIC;
202 data_shaping_SP0 : STD_LOGIC;
202 data_shaping_SP0 : STD_LOGIC;
203 data_shaping_SP1 : STD_LOGIC;
203 data_shaping_SP1 : STD_LOGIC;
204 data_shaping_R0 : STD_LOGIC;
204 data_shaping_R0 : STD_LOGIC;
205 data_shaping_R1 : STD_LOGIC;
205 data_shaping_R1 : STD_LOGIC;
206 data_shaping_R2 : STD_LOGIC;
206 data_shaping_R2 : STD_LOGIC;
207 delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
207 delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
208 delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
208 delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
209 delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
209 delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
210 delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
210 delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
211 delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
211 delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
212 nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
212 nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
213 -- nb_word_by_buffer : STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
213 -- nb_word_by_buffer : STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
214 nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
214 nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
215 enable_f0 : STD_LOGIC;
215 enable_f0 : STD_LOGIC;
216 enable_f1 : STD_LOGIC;
216 enable_f1 : STD_LOGIC;
217 enable_f2 : STD_LOGIC;
217 enable_f2 : STD_LOGIC;
218 enable_f3 : STD_LOGIC;
218 enable_f3 : STD_LOGIC;
219 burst_f0 : STD_LOGIC;
219 burst_f0 : STD_LOGIC;
220 burst_f1 : STD_LOGIC;
220 burst_f1 : STD_LOGIC;
221 burst_f2 : STD_LOGIC;
221 burst_f2 : STD_LOGIC;
222 run : STD_LOGIC;
222 run : STD_LOGIC;
223 status_ready_buffer_f : STD_LOGIC_VECTOR(4*2-1 DOWNTO 0);
223 status_ready_buffer_f : STD_LOGIC_VECTOR(4*2-1 DOWNTO 0);
224 addr_buffer_f : STD_LOGIC_VECTOR(4*2*32-1 DOWNTO 0);
224 addr_buffer_f : STD_LOGIC_VECTOR(4*2*32-1 DOWNTO 0);
225 time_buffer_f : STD_LOGIC_VECTOR(4*2*48-1 DOWNTO 0);
225 time_buffer_f : STD_LOGIC_VECTOR(4*2*48-1 DOWNTO 0);
226 length_buffer : STD_LOGIC_VECTOR(25 DOWNTO 0);
226 length_buffer : STD_LOGIC_VECTOR(25 DOWNTO 0);
227 error_buffer_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
227 error_buffer_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
228 start_date : STD_LOGIC_VECTOR(30 DOWNTO 0);
228 start_date : STD_LOGIC_VECTOR(30 DOWNTO 0);
229 END RECORD;
229 END RECORD;
230 SIGNAL reg_wp : lpp_WaveformPicker_regs;
230 SIGNAL reg_wp : lpp_WaveformPicker_regs;
231
231
232 SIGNAL prdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
232 SIGNAL prdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
233
233
234 -----------------------------------------------------------------------------
234 -----------------------------------------------------------------------------
235 -- IRQ
235 -- IRQ
236 -----------------------------------------------------------------------------
236 -----------------------------------------------------------------------------
237 CONSTANT IRQ_WFP_SIZE : INTEGER := 12;
237 CONSTANT IRQ_WFP_SIZE : INTEGER := 12;
238 SIGNAL irq_wfp_ZERO : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
238 SIGNAL irq_wfp_ZERO : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
239 SIGNAL irq_wfp_reg_s : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
239 SIGNAL irq_wfp_reg_s : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
240 SIGNAL irq_wfp_reg : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
240 SIGNAL irq_wfp_reg : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
241 SIGNAL irq_wfp : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
241 SIGNAL irq_wfp : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
242 SIGNAL ored_irq_wfp : STD_LOGIC;
242 SIGNAL ored_irq_wfp : STD_LOGIC;
243
243
244 -----------------------------------------------------------------------------
244 -----------------------------------------------------------------------------
245 --
245 --
246 -----------------------------------------------------------------------------
246 -----------------------------------------------------------------------------
247 SIGNAL reg0_ready_matrix_f0 : STD_LOGIC;
247 SIGNAL reg0_ready_matrix_f0 : STD_LOGIC;
248 -- SIGNAL reg0_addr_matrix_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
248 -- SIGNAL reg0_addr_matrix_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
249 -- SIGNAL reg0_matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
249 -- SIGNAL reg0_matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
250
250
251 SIGNAL reg1_ready_matrix_f0 : STD_LOGIC;
251 SIGNAL reg1_ready_matrix_f0 : STD_LOGIC;
252 -- SIGNAL reg1_addr_matrix_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
252 -- SIGNAL reg1_addr_matrix_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
253 -- SIGNAL reg1_matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
253 -- SIGNAL reg1_matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
254
254
255 SIGNAL reg0_ready_matrix_f1 : STD_LOGIC;
255 SIGNAL reg0_ready_matrix_f1 : STD_LOGIC;
256 -- SIGNAL reg0_addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
256 -- SIGNAL reg0_addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
257 -- SIGNAL reg0_matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
257 -- SIGNAL reg0_matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
258
258
259 SIGNAL reg1_ready_matrix_f1 : STD_LOGIC;
259 SIGNAL reg1_ready_matrix_f1 : STD_LOGIC;
260 -- SIGNAL reg1_addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
260 -- SIGNAL reg1_addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
261 -- SIGNAL reg1_matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
261 -- SIGNAL reg1_matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
262
262
263 SIGNAL reg0_ready_matrix_f2 : STD_LOGIC;
263 SIGNAL reg0_ready_matrix_f2 : STD_LOGIC;
264 -- SIGNAL reg0_addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
264 -- SIGNAL reg0_addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
265 -- SIGNAL reg0_matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
265 -- SIGNAL reg0_matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
266
266
267 SIGNAL reg1_ready_matrix_f2 : STD_LOGIC;
267 SIGNAL reg1_ready_matrix_f2 : STD_LOGIC;
268 -- SIGNAL reg1_addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
268 -- SIGNAL reg1_addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
269 -- SIGNAL reg1_matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
269 -- SIGNAL reg1_matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
270 SIGNAL apbo_irq_ms : STD_LOGIC;
270 SIGNAL apbo_irq_ms : STD_LOGIC;
271 SIGNAL apbo_irq_wfp : STD_LOGIC;
271 SIGNAL apbo_irq_wfp : STD_LOGIC;
272 -----------------------------------------------------------------------------
272 -----------------------------------------------------------------------------
273 SIGNAL reg_ready_buffer_f : STD_LOGIC_VECTOR( 2*4-1 DOWNTO 0);
273 SIGNAL reg_ready_buffer_f : STD_LOGIC_VECTOR(2*4-1 DOWNTO 0);
274
274
275 SIGNAL pirq_temp : STD_LOGIC_VECTOR(31 DOWNTO 0);
275 SIGNAL pirq_temp : STD_LOGIC_VECTOR(31 DOWNTO 0);
276
276
277 SIGNAL sample_f3_v_reg : STD_LOGIC_VECTOR(15 DOWNTO 0);
277 SIGNAL sample_f3_v_reg : STD_LOGIC_VECTOR(15 DOWNTO 0);
278 SIGNAL sample_f3_e1_reg : STD_LOGIC_VECTOR(15 DOWNTO 0);
278 SIGNAL sample_f3_e1_reg : STD_LOGIC_VECTOR(15 DOWNTO 0);
279 SIGNAL sample_f3_e2_reg : STD_LOGIC_VECTOR(15 DOWNTO 0);
279 SIGNAL sample_f3_e2_reg : STD_LOGIC_VECTOR(15 DOWNTO 0);
280
280
281 BEGIN -- beh
281 BEGIN -- beh
282
282
283 debug_vector(0) <= error_buffer_full;
283 debug_vector(0) <= error_buffer_full;
284 debug_vector(1) <= reg_sp.status_error_buffer_full;
284 debug_vector(1) <= reg_sp.status_error_buffer_full;
285 debug_vector(4 DOWNTO 2) <= error_input_fifo_write;
285 debug_vector(4 DOWNTO 2) <= error_input_fifo_write;
286 debug_vector(7 DOWNTO 5) <= reg_sp.status_error_input_fifo_write;
286 debug_vector(7 DOWNTO 5) <= reg_sp.status_error_input_fifo_write;
287 debug_vector(8) <= ready_matrix_f2;
287 debug_vector(8) <= ready_matrix_f2;
288 debug_vector(9) <= reg0_ready_matrix_f2;
288 debug_vector(9) <= reg0_ready_matrix_f2;
289 debug_vector(10) <= reg1_ready_matrix_f2;
289 debug_vector(10) <= reg1_ready_matrix_f2;
290 debug_vector(11) <= HRESETn;
290 debug_vector(11) <= HRESETn;
291
291
292 -- status_ready_matrix_f0 <= reg_sp.status_ready_matrix_f0;
292 -- status_ready_matrix_f0 <= reg_sp.status_ready_matrix_f0;
293 -- status_ready_matrix_f1 <= reg_sp.status_ready_matrix_f1;
293 -- status_ready_matrix_f1 <= reg_sp.status_ready_matrix_f1;
294 -- status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2;
294 -- status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2;
295
295
296 -- config_active_interruption_onNewMatrix <= reg_sp.config_active_interruption_onNewMatrix;
296 -- config_active_interruption_onNewMatrix <= reg_sp.config_active_interruption_onNewMatrix;
297 -- config_active_interruption_onError <= reg_sp.config_active_interruption_onError;
297 -- config_active_interruption_onError <= reg_sp.config_active_interruption_onError;
298
298
299
299
300 -- addr_matrix_f0 <= reg_sp.addr_matrix_f0;
300 -- addr_matrix_f0 <= reg_sp.addr_matrix_f0;
301 -- addr_matrix_f1 <= reg_sp.addr_matrix_f1;
301 -- addr_matrix_f1 <= reg_sp.addr_matrix_f1;
302 -- addr_matrix_f2 <= reg_sp.addr_matrix_f2;
302 -- addr_matrix_f2 <= reg_sp.addr_matrix_f2;
303
303
304
304
305 data_shaping_BW <= NOT reg_wp.data_shaping_BW;
305 data_shaping_BW <= NOT reg_wp.data_shaping_BW;
306 data_shaping_SP0 <= reg_wp.data_shaping_SP0;
306 data_shaping_SP0 <= reg_wp.data_shaping_SP0;
307 data_shaping_SP1 <= reg_wp.data_shaping_SP1;
307 data_shaping_SP1 <= reg_wp.data_shaping_SP1;
308 data_shaping_R0 <= reg_wp.data_shaping_R0;
308 data_shaping_R0 <= reg_wp.data_shaping_R0;
309 data_shaping_R1 <= reg_wp.data_shaping_R1;
309 data_shaping_R1 <= reg_wp.data_shaping_R1;
310 data_shaping_R2 <= reg_wp.data_shaping_R2;
310 data_shaping_R2 <= reg_wp.data_shaping_R2;
311
311
312 delta_snapshot <= reg_wp.delta_snapshot;
312 delta_snapshot <= reg_wp.delta_snapshot;
313 delta_f0 <= reg_wp.delta_f0;
313 delta_f0 <= reg_wp.delta_f0;
314 delta_f0_2 <= reg_wp.delta_f0_2;
314 delta_f0_2 <= reg_wp.delta_f0_2;
315 delta_f1 <= reg_wp.delta_f1;
315 delta_f1 <= reg_wp.delta_f1;
316 delta_f2 <= reg_wp.delta_f2;
316 delta_f2 <= reg_wp.delta_f2;
317 nb_data_by_buffer <= reg_wp.nb_data_by_buffer;
317 nb_data_by_buffer <= reg_wp.nb_data_by_buffer;
318 nb_snapshot_param <= reg_wp.nb_snapshot_param;
318 nb_snapshot_param <= reg_wp.nb_snapshot_param;
319
319
320 enable_f0 <= reg_wp.enable_f0;
320 enable_f0 <= reg_wp.enable_f0;
321 enable_f1 <= reg_wp.enable_f1;
321 enable_f1 <= reg_wp.enable_f1;
322 enable_f2 <= reg_wp.enable_f2;
322 enable_f2 <= reg_wp.enable_f2;
323 enable_f3 <= reg_wp.enable_f3;
323 enable_f3 <= reg_wp.enable_f3;
324
324
325 burst_f0 <= reg_wp.burst_f0;
325 burst_f0 <= reg_wp.burst_f0;
326 burst_f1 <= reg_wp.burst_f1;
326 burst_f1 <= reg_wp.burst_f1;
327 burst_f2 <= reg_wp.burst_f2;
327 burst_f2 <= reg_wp.burst_f2;
328
328
329 run <= reg_wp.run;
329 run <= reg_wp.run;
330
330
331 --addr_data_f0 <= reg_wp.addr_data_f0;
331 --addr_data_f0 <= reg_wp.addr_data_f0;
332 --addr_data_f1 <= reg_wp.addr_data_f1;
332 --addr_data_f1 <= reg_wp.addr_data_f1;
333 --addr_data_f2 <= reg_wp.addr_data_f2;
333 --addr_data_f2 <= reg_wp.addr_data_f2;
334 --addr_data_f3 <= reg_wp.addr_data_f3;
334 --addr_data_f3 <= reg_wp.addr_data_f3;
335
335
336 start_date <= reg_wp.start_date;
336 start_date <= reg_wp.start_date;
337
337
338 length_matrix_f0 <= reg_sp.length_matrix;
338 length_matrix_f0 <= reg_sp.length_matrix;
339 length_matrix_f1 <= reg_sp.length_matrix;
339 length_matrix_f1 <= reg_sp.length_matrix;
340 length_matrix_f2 <= reg_sp.length_matrix;
340 length_matrix_f2 <= reg_sp.length_matrix;
341 wfp_length_buffer <= reg_wp.length_buffer;
341 wfp_length_buffer <= reg_wp.length_buffer;
342
342
343
343
344
344
345 PROCESS (HCLK, HRESETn)
345 PROCESS (HCLK, HRESETn)
346 BEGIN -- PROCESS
346 BEGIN -- PROCESS
347 IF HRESETn = '0' THEN -- asynchronous reset (active low)
347 IF HRESETn = '0' THEN -- asynchronous reset (active low)
348 sample_f3_v_reg <= (OTHERS => '0');
348 sample_f3_v_reg <= (OTHERS => '0');
349 sample_f3_e1_reg <= (OTHERS => '0');
349 sample_f3_e1_reg <= (OTHERS => '0');
350 sample_f3_e2_reg <= (OTHERS => '0');
350 sample_f3_e2_reg <= (OTHERS => '0');
351 ELSIF HCLK'event AND HCLK = '1' THEN -- rising clock edge
351 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
352 IF sample_f3_valid = '1' THEN
352 IF sample_f3_valid = '1' THEN
353 sample_f3_v_reg <= sample_f3_v;
353 sample_f3_v_reg <= sample_f3_v;
354 sample_f3_e1_reg <= sample_f3_e1;
354 sample_f3_e1_reg <= sample_f3_e1;
355 sample_f3_e2_reg <= sample_f3_e2;
355 sample_f3_e2_reg <= sample_f3_e2;
356 END IF;
356 END IF;
357 END IF;
357 END IF;
358 END PROCESS;
358 END PROCESS;
359
359
360
360
361 lpp_lfr_apbreg : PROCESS (HCLK, HRESETn)
361 lpp_lfr_apbreg : PROCESS (HCLK, HRESETn)
362 VARIABLE paddr : STD_LOGIC_VECTOR(7 DOWNTO 2);
362 VARIABLE paddr : STD_LOGIC_VECTOR(7 DOWNTO 2);
363 BEGIN -- PROCESS lpp_dma_top
363 BEGIN -- PROCESS lpp_dma_top
364 IF HRESETn = '0' THEN -- asynchronous reset (active low)
364 IF HRESETn = '0' THEN -- asynchronous reset (active low)
365 reg_sp.config_active_interruption_onNewMatrix <= '0';
365 reg_sp.config_active_interruption_onNewMatrix <= '0';
366 reg_sp.config_active_interruption_onError <= '0';
366 reg_sp.config_active_interruption_onError <= '0';
367 reg_sp.config_ms_run <= '0';
367 reg_sp.config_ms_run <= '0';
368 reg_sp.status_ready_matrix_f0_0 <= '0';
368 reg_sp.status_ready_matrix_f0_0 <= '0';
369 reg_sp.status_ready_matrix_f1_0 <= '0';
369 reg_sp.status_ready_matrix_f1_0 <= '0';
370 reg_sp.status_ready_matrix_f2_0 <= '0';
370 reg_sp.status_ready_matrix_f2_0 <= '0';
371 reg_sp.status_ready_matrix_f0_1 <= '0';
371 reg_sp.status_ready_matrix_f0_1 <= '0';
372 reg_sp.status_ready_matrix_f1_1 <= '0';
372 reg_sp.status_ready_matrix_f1_1 <= '0';
373 reg_sp.status_ready_matrix_f2_1 <= '0';
373 reg_sp.status_ready_matrix_f2_1 <= '0';
374 reg_sp.status_error_buffer_full <= '0';
374 reg_sp.status_error_buffer_full <= '0';
375 reg_sp.status_error_input_fifo_write <= (OTHERS => '0');
375 reg_sp.status_error_input_fifo_write <= (OTHERS => '0');
376
376
377 reg_sp.addr_matrix_f0_0 <= (OTHERS => '0');
377 reg_sp.addr_matrix_f0_0 <= (OTHERS => '0');
378 reg_sp.addr_matrix_f1_0 <= (OTHERS => '0');
378 reg_sp.addr_matrix_f1_0 <= (OTHERS => '0');
379 reg_sp.addr_matrix_f2_0 <= (OTHERS => '0');
379 reg_sp.addr_matrix_f2_0 <= (OTHERS => '0');
380
380
381 reg_sp.addr_matrix_f0_1 <= (OTHERS => '0');
381 reg_sp.addr_matrix_f0_1 <= (OTHERS => '0');
382 reg_sp.addr_matrix_f1_1 <= (OTHERS => '0');
382 reg_sp.addr_matrix_f1_1 <= (OTHERS => '0');
383 reg_sp.addr_matrix_f2_1 <= (OTHERS => '0');
383 reg_sp.addr_matrix_f2_1 <= (OTHERS => '0');
384
384
385 reg_sp.length_matrix <= (OTHERS => '0');
385 reg_sp.length_matrix <= (OTHERS => '0');
386
386
387 -- reg_sp.time_matrix_f0_0 <= (OTHERS => '0'); -- ok
387 -- reg_sp.time_matrix_f0_0 <= (OTHERS => '0'); -- ok
388 -- reg_sp.time_matrix_f1_0 <= (OTHERS => '0'); -- ok
388 -- reg_sp.time_matrix_f1_0 <= (OTHERS => '0'); -- ok
389 -- reg_sp.time_matrix_f2_0 <= (OTHERS => '0'); -- ok
389 -- reg_sp.time_matrix_f2_0 <= (OTHERS => '0'); -- ok
390
390
391 -- reg_sp.time_matrix_f0_1 <= (OTHERS => '0'); -- ok
391 -- reg_sp.time_matrix_f0_1 <= (OTHERS => '0'); -- ok
392 --reg_sp.time_matrix_f1_1 <= (OTHERS => '0'); -- ok
392 --reg_sp.time_matrix_f1_1 <= (OTHERS => '0'); -- ok
393 -- reg_sp.time_matrix_f2_1 <= (OTHERS => '0'); -- ok
393 -- reg_sp.time_matrix_f2_1 <= (OTHERS => '0'); -- ok
394
394
395 prdata <= (OTHERS => '0');
395 prdata <= (OTHERS => '0');
396
396
397
397
398 apbo_irq_ms <= '0';
398 apbo_irq_ms <= '0';
399 apbo_irq_wfp <= '0';
399 apbo_irq_wfp <= '0';
400
400
401
401
402 -- status_full_ack <= (OTHERS => '0');
402 -- status_full_ack <= (OTHERS => '0');
403
403
404 reg_wp.data_shaping_BW <= '0';
404 reg_wp.data_shaping_BW <= '0';
405 reg_wp.data_shaping_SP0 <= '0';
405 reg_wp.data_shaping_SP0 <= '0';
406 reg_wp.data_shaping_SP1 <= '0';
406 reg_wp.data_shaping_SP1 <= '0';
407 reg_wp.data_shaping_R0 <= '0';
407 reg_wp.data_shaping_R0 <= '0';
408 reg_wp.data_shaping_R1 <= '0';
408 reg_wp.data_shaping_R1 <= '0';
409 reg_wp.data_shaping_R2 <= '0';
409 reg_wp.data_shaping_R2 <= '0';
410 reg_wp.enable_f0 <= '0';
410 reg_wp.enable_f0 <= '0';
411 reg_wp.enable_f1 <= '0';
411 reg_wp.enable_f1 <= '0';
412 reg_wp.enable_f2 <= '0';
412 reg_wp.enable_f2 <= '0';
413 reg_wp.enable_f3 <= '0';
413 reg_wp.enable_f3 <= '0';
414 reg_wp.burst_f0 <= '0';
414 reg_wp.burst_f0 <= '0';
415 reg_wp.burst_f1 <= '0';
415 reg_wp.burst_f1 <= '0';
416 reg_wp.burst_f2 <= '0';
416 reg_wp.burst_f2 <= '0';
417 reg_wp.run <= '0';
417 reg_wp.run <= '0';
418 -- reg_wp.status_full <= (OTHERS => '0');
418 -- reg_wp.status_full <= (OTHERS => '0');
419 -- reg_wp.status_full_err <= (OTHERS => '0');
419 -- reg_wp.status_full_err <= (OTHERS => '0');
420 reg_wp.status_new_err <= (OTHERS => '0');
420 reg_wp.status_new_err <= (OTHERS => '0');
421 reg_wp.error_buffer_full <= (OTHERS => '0');
421 reg_wp.error_buffer_full <= (OTHERS => '0');
422 reg_wp.delta_snapshot <= (OTHERS => '0');
422 reg_wp.delta_snapshot <= (OTHERS => '0');
423 reg_wp.delta_f0 <= (OTHERS => '0');
423 reg_wp.delta_f0 <= (OTHERS => '0');
424 reg_wp.delta_f0_2 <= (OTHERS => '0');
424 reg_wp.delta_f0_2 <= (OTHERS => '0');
425 reg_wp.delta_f1 <= (OTHERS => '0');
425 reg_wp.delta_f1 <= (OTHERS => '0');
426 reg_wp.delta_f2 <= (OTHERS => '0');
426 reg_wp.delta_f2 <= (OTHERS => '0');
427 reg_wp.nb_data_by_buffer <= (OTHERS => '0');
427 reg_wp.nb_data_by_buffer <= (OTHERS => '0');
428 reg_wp.nb_snapshot_param <= (OTHERS => '0');
428 reg_wp.nb_snapshot_param <= (OTHERS => '0');
429 reg_wp.start_date <= (OTHERS => '1');
429 reg_wp.start_date <= (OTHERS => '1');
430
430
431 reg_wp.status_ready_buffer_f <= (OTHERS => '0');
431 reg_wp.status_ready_buffer_f <= (OTHERS => '0');
432 reg_wp.length_buffer <= (OTHERS => '0');
432 reg_wp.length_buffer <= (OTHERS => '0');
433
433
434 pirq_temp <= (OTHERS => '0');
434 pirq_temp <= (OTHERS => '0');
435
435
436 reg_wp.addr_buffer_f <= (OTHERS => '0');
436 reg_wp.addr_buffer_f <= (OTHERS => '0');
437
437
438 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
438 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
439
439
440 -- status_full_ack <= (OTHERS => '0');
440 -- status_full_ack <= (OTHERS => '0');
441
441
442 reg_sp.status_ready_matrix_f0_0 <= reg_sp.status_ready_matrix_f0_0 OR reg0_ready_matrix_f0;
442 reg_sp.status_ready_matrix_f0_0 <= reg_sp.status_ready_matrix_f0_0 OR reg0_ready_matrix_f0;
443 reg_sp.status_ready_matrix_f1_0 <= reg_sp.status_ready_matrix_f1_0 OR reg0_ready_matrix_f1;
443 reg_sp.status_ready_matrix_f1_0 <= reg_sp.status_ready_matrix_f1_0 OR reg0_ready_matrix_f1;
444 reg_sp.status_ready_matrix_f2_0 <= reg_sp.status_ready_matrix_f2_0 OR reg0_ready_matrix_f2;
444 reg_sp.status_ready_matrix_f2_0 <= reg_sp.status_ready_matrix_f2_0 OR reg0_ready_matrix_f2;
445
445
446 reg_sp.status_ready_matrix_f0_1 <= reg_sp.status_ready_matrix_f0_1 OR reg1_ready_matrix_f0;
446 reg_sp.status_ready_matrix_f0_1 <= reg_sp.status_ready_matrix_f0_1 OR reg1_ready_matrix_f0;
447 reg_sp.status_ready_matrix_f1_1 <= reg_sp.status_ready_matrix_f1_1 OR reg1_ready_matrix_f1;
447 reg_sp.status_ready_matrix_f1_1 <= reg_sp.status_ready_matrix_f1_1 OR reg1_ready_matrix_f1;
448 reg_sp.status_ready_matrix_f2_1 <= reg_sp.status_ready_matrix_f2_1 OR reg1_ready_matrix_f2;
448 reg_sp.status_ready_matrix_f2_1 <= reg_sp.status_ready_matrix_f2_1 OR reg1_ready_matrix_f2;
449
449
450 all_status_ready_buffer_bit: FOR I IN 4*2-1 DOWNTO 0 LOOP
450 all_status_ready_buffer_bit : FOR I IN 4*2-1 DOWNTO 0 LOOP
451 reg_wp.status_ready_buffer_f(I) <= reg_wp.status_ready_buffer_f(I) OR reg_ready_buffer_f(I);
451 reg_wp.status_ready_buffer_f(I) <= reg_wp.status_ready_buffer_f(I) OR reg_ready_buffer_f(I);
452 END LOOP all_status_ready_buffer_bit;
452 END LOOP all_status_ready_buffer_bit;
453
453
454
454
455 reg_sp.status_error_buffer_full <= reg_sp.status_error_buffer_full OR error_buffer_full;
455 reg_sp.status_error_buffer_full <= reg_sp.status_error_buffer_full OR error_buffer_full;
456 reg_sp.status_error_input_fifo_write(0) <= reg_sp.status_error_input_fifo_write(0) OR error_input_fifo_write(0);
456 reg_sp.status_error_input_fifo_write(0) <= reg_sp.status_error_input_fifo_write(0) OR error_input_fifo_write(0);
457 reg_sp.status_error_input_fifo_write(1) <= reg_sp.status_error_input_fifo_write(1) OR error_input_fifo_write(1);
457 reg_sp.status_error_input_fifo_write(1) <= reg_sp.status_error_input_fifo_write(1) OR error_input_fifo_write(1);
458 reg_sp.status_error_input_fifo_write(2) <= reg_sp.status_error_input_fifo_write(2) OR error_input_fifo_write(2);
458 reg_sp.status_error_input_fifo_write(2) <= reg_sp.status_error_input_fifo_write(2) OR error_input_fifo_write(2);
459
459
460
460
461
461
462 all_status : FOR I IN 3 DOWNTO 0 LOOP
462 all_status : FOR I IN 3 DOWNTO 0 LOOP
463 reg_wp.error_buffer_full(I) <= reg_wp.error_buffer_full(I) OR wfp_error_buffer_full(I);
463 reg_wp.error_buffer_full(I) <= reg_wp.error_buffer_full(I) OR wfp_error_buffer_full(I);
464 reg_wp.status_new_err(I) <= reg_wp.status_new_err(I) OR status_new_err(I);
464 reg_wp.status_new_err(I) <= reg_wp.status_new_err(I) OR status_new_err(I);
465 END LOOP all_status;
465 END LOOP all_status;
466
466
467 paddr := "000000";
467 paddr := "000000";
468 paddr(7 DOWNTO 2) := apbi.paddr(7 DOWNTO 2);
468 paddr(7 DOWNTO 2) := apbi.paddr(7 DOWNTO 2);
469 prdata <= (OTHERS => '0');
469 prdata <= (OTHERS => '0');
470 IF apbi.psel(pindex) = '1' THEN
470 IF apbi.psel(pindex) = '1' THEN
471 -- APB DMA READ --
471 -- APB DMA READ --
472 CASE paddr(7 DOWNTO 2) IS
472 CASE paddr(7 DOWNTO 2) IS
473
473
474 WHEN ADDR_LFR_SM_CONFIG =>
474 WHEN ADDR_LFR_SM_CONFIG =>
475 prdata(0) <= reg_sp.config_active_interruption_onNewMatrix;
475 prdata(0) <= reg_sp.config_active_interruption_onNewMatrix;
476 prdata(1) <= reg_sp.config_active_interruption_onError;
476 prdata(1) <= reg_sp.config_active_interruption_onError;
477 prdata(2) <= reg_sp.config_ms_run;
477 prdata(2) <= reg_sp.config_ms_run;
478
478
479 WHEN ADDR_LFR_SM_STATUS =>
479 WHEN ADDR_LFR_SM_STATUS =>
480 prdata(0) <= reg_sp.status_ready_matrix_f0_0;
480 prdata(0) <= reg_sp.status_ready_matrix_f0_0;
481 prdata(1) <= reg_sp.status_ready_matrix_f0_1;
481 prdata(1) <= reg_sp.status_ready_matrix_f0_1;
482 prdata(2) <= reg_sp.status_ready_matrix_f1_0;
482 prdata(2) <= reg_sp.status_ready_matrix_f1_0;
483 prdata(3) <= reg_sp.status_ready_matrix_f1_1;
483 prdata(3) <= reg_sp.status_ready_matrix_f1_1;
484 prdata(4) <= reg_sp.status_ready_matrix_f2_0;
484 prdata(4) <= reg_sp.status_ready_matrix_f2_0;
485 prdata(5) <= reg_sp.status_ready_matrix_f2_1;
485 prdata(5) <= reg_sp.status_ready_matrix_f2_1;
486 -- prdata(6) <= reg_sp.status_error_bad_component_error;
486 -- prdata(6) <= reg_sp.status_error_bad_component_error;
487 prdata(7) <= reg_sp.status_error_buffer_full;
487 prdata(7) <= reg_sp.status_error_buffer_full;
488 prdata(8) <= reg_sp.status_error_input_fifo_write(0);
488 prdata(8) <= reg_sp.status_error_input_fifo_write(0);
489 prdata(9) <= reg_sp.status_error_input_fifo_write(1);
489 prdata(9) <= reg_sp.status_error_input_fifo_write(1);
490 prdata(10) <= reg_sp.status_error_input_fifo_write(2);
490 prdata(10) <= reg_sp.status_error_input_fifo_write(2);
491
491
492 WHEN ADDR_LFR_SM_F0_0_ADDR => prdata <= reg_sp.addr_matrix_f0_0;
492 WHEN ADDR_LFR_SM_F0_0_ADDR => prdata <= reg_sp.addr_matrix_f0_0;
493 WHEN ADDR_LFR_SM_F0_1_ADDR => prdata <= reg_sp.addr_matrix_f0_1;
493 WHEN ADDR_LFR_SM_F0_1_ADDR => prdata <= reg_sp.addr_matrix_f0_1;
494 WHEN ADDR_LFR_SM_F1_0_ADDR => prdata <= reg_sp.addr_matrix_f1_0;
494 WHEN ADDR_LFR_SM_F1_0_ADDR => prdata <= reg_sp.addr_matrix_f1_0;
495 WHEN ADDR_LFR_SM_F1_1_ADDR => prdata <= reg_sp.addr_matrix_f1_1;
495 WHEN ADDR_LFR_SM_F1_1_ADDR => prdata <= reg_sp.addr_matrix_f1_1;
496 WHEN ADDR_LFR_SM_F2_0_ADDR => prdata <= reg_sp.addr_matrix_f2_0;
496 WHEN ADDR_LFR_SM_F2_0_ADDR => prdata <= reg_sp.addr_matrix_f2_0;
497 WHEN ADDR_LFR_SM_F2_1_ADDR => prdata <= reg_sp.addr_matrix_f2_1;
497 WHEN ADDR_LFR_SM_F2_1_ADDR => prdata <= reg_sp.addr_matrix_f2_1;
498 WHEN ADDR_LFR_SM_F0_0_TIME_COARSE => prdata <= reg_sp.time_matrix_f0_0(47 DOWNTO 16);
498 WHEN ADDR_LFR_SM_F0_0_TIME_COARSE => prdata <= reg_sp.time_matrix_f0_0(47 DOWNTO 16);
499 WHEN ADDR_LFR_SM_F0_0_TIME_FINE => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f0_0(15 DOWNTO 0);
499 WHEN ADDR_LFR_SM_F0_0_TIME_FINE => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f0_0(15 DOWNTO 0);
500 WHEN ADDR_LFR_SM_F0_1_TIME_COARSE => prdata <= reg_sp.time_matrix_f0_1(47 DOWNTO 16);
500 WHEN ADDR_LFR_SM_F0_1_TIME_COARSE => prdata <= reg_sp.time_matrix_f0_1(47 DOWNTO 16);
501 WHEN ADDR_LFR_SM_F0_1_TIME_FINE => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f0_1(15 DOWNTO 0);
501 WHEN ADDR_LFR_SM_F0_1_TIME_FINE => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f0_1(15 DOWNTO 0);
502 WHEN ADDR_LFR_SM_F1_0_TIME_COARSE => prdata <= reg_sp.time_matrix_f1_0(47 DOWNTO 16);
502 WHEN ADDR_LFR_SM_F1_0_TIME_COARSE => prdata <= reg_sp.time_matrix_f1_0(47 DOWNTO 16);
503 WHEN ADDR_LFR_SM_F1_0_TIME_FINE => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f1_0(15 DOWNTO 0);
503 WHEN ADDR_LFR_SM_F1_0_TIME_FINE => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f1_0(15 DOWNTO 0);
504 WHEN ADDR_LFR_SM_F1_1_TIME_COARSE => prdata <= reg_sp.time_matrix_f1_1(47 DOWNTO 16);
504 WHEN ADDR_LFR_SM_F1_1_TIME_COARSE => prdata <= reg_sp.time_matrix_f1_1(47 DOWNTO 16);
505 WHEN ADDR_LFR_SM_F1_1_TIME_FINE => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f1_1(15 DOWNTO 0);
505 WHEN ADDR_LFR_SM_F1_1_TIME_FINE => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f1_1(15 DOWNTO 0);
506 WHEN ADDR_LFR_SM_F2_0_TIME_COARSE => prdata <= reg_sp.time_matrix_f2_0(47 DOWNTO 16);
506 WHEN ADDR_LFR_SM_F2_0_TIME_COARSE => prdata <= reg_sp.time_matrix_f2_0(47 DOWNTO 16);
507 WHEN ADDR_LFR_SM_F2_0_TIME_FINE => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f2_0(15 DOWNTO 0);
507 WHEN ADDR_LFR_SM_F2_0_TIME_FINE => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f2_0(15 DOWNTO 0);
508 WHEN ADDR_LFR_SM_F2_1_TIME_COARSE => prdata <= reg_sp.time_matrix_f2_1(47 DOWNTO 16);
508 WHEN ADDR_LFR_SM_F2_1_TIME_COARSE => prdata <= reg_sp.time_matrix_f2_1(47 DOWNTO 16);
509 WHEN ADDR_LFR_SM_F2_1_TIME_FINE => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f2_1(15 DOWNTO 0);
509 WHEN ADDR_LFR_SM_F2_1_TIME_FINE => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f2_1(15 DOWNTO 0);
510 WHEN ADDR_LFR_SM_LENGTH => prdata(25 DOWNTO 0) <= reg_sp.length_matrix;
510 WHEN ADDR_LFR_SM_LENGTH => prdata(25 DOWNTO 0) <= reg_sp.length_matrix;
511 ---------------------------------------------------------------------
511 ---------------------------------------------------------------------
512 WHEN ADDR_LFR_WP_DATASHAPING =>
512 WHEN ADDR_LFR_WP_DATASHAPING =>
513 prdata(0) <= reg_wp.data_shaping_BW;
513 prdata(0) <= reg_wp.data_shaping_BW;
514 prdata(1) <= reg_wp.data_shaping_SP0;
514 prdata(1) <= reg_wp.data_shaping_SP0;
515 prdata(2) <= reg_wp.data_shaping_SP1;
515 prdata(2) <= reg_wp.data_shaping_SP1;
516 prdata(3) <= reg_wp.data_shaping_R0;
516 prdata(3) <= reg_wp.data_shaping_R0;
517 prdata(4) <= reg_wp.data_shaping_R1;
517 prdata(4) <= reg_wp.data_shaping_R1;
518 prdata(5) <= reg_wp.data_shaping_R2;
518 prdata(5) <= reg_wp.data_shaping_R2;
519 WHEN ADDR_LFR_WP_CONTROL =>
519 WHEN ADDR_LFR_WP_CONTROL =>
520 prdata(0) <= reg_wp.enable_f0;
520 prdata(0) <= reg_wp.enable_f0;
521 prdata(1) <= reg_wp.enable_f1;
521 prdata(1) <= reg_wp.enable_f1;
522 prdata(2) <= reg_wp.enable_f2;
522 prdata(2) <= reg_wp.enable_f2;
523 prdata(3) <= reg_wp.enable_f3;
523 prdata(3) <= reg_wp.enable_f3;
524 prdata(4) <= reg_wp.burst_f0;
524 prdata(4) <= reg_wp.burst_f0;
525 prdata(5) <= reg_wp.burst_f1;
525 prdata(5) <= reg_wp.burst_f1;
526 prdata(6) <= reg_wp.burst_f2;
526 prdata(6) <= reg_wp.burst_f2;
527 prdata(7) <= reg_wp.run;
527 prdata(7) <= reg_wp.run;
528 WHEN ADDR_LFR_WP_F0_0_ADDR => prdata <= reg_wp.addr_buffer_f(32*1-1 DOWNTO 32*0);--0
528 WHEN ADDR_LFR_WP_F0_0_ADDR => prdata <= reg_wp.addr_buffer_f(32*1-1 DOWNTO 32*0); --0
529 WHEN ADDR_LFR_WP_F0_1_ADDR => prdata <= reg_wp.addr_buffer_f(32*2-1 DOWNTO 32*1);
529 WHEN ADDR_LFR_WP_F0_1_ADDR => prdata <= reg_wp.addr_buffer_f(32*2-1 DOWNTO 32*1);
530 WHEN ADDR_LFR_WP_F1_0_ADDR => prdata <= reg_wp.addr_buffer_f(32*3-1 DOWNTO 32*2);--1
530 WHEN ADDR_LFR_WP_F1_0_ADDR => prdata <= reg_wp.addr_buffer_f(32*3-1 DOWNTO 32*2); --1
531 WHEN ADDR_LFR_WP_F1_1_ADDR => prdata <= reg_wp.addr_buffer_f(32*4-1 DOWNTO 32*3);
531 WHEN ADDR_LFR_WP_F1_1_ADDR => prdata <= reg_wp.addr_buffer_f(32*4-1 DOWNTO 32*3);
532 WHEN ADDR_LFR_WP_F2_0_ADDR => prdata <= reg_wp.addr_buffer_f(32*5-1 DOWNTO 32*4);--2
532 WHEN ADDR_LFR_WP_F2_0_ADDR => prdata <= reg_wp.addr_buffer_f(32*5-1 DOWNTO 32*4); --2
533 WHEN ADDR_LFR_WP_F2_1_ADDR => prdata <= reg_wp.addr_buffer_f(32*6-1 DOWNTO 32*5);
533 WHEN ADDR_LFR_WP_F2_1_ADDR => prdata <= reg_wp.addr_buffer_f(32*6-1 DOWNTO 32*5);
534 WHEN ADDR_LFR_WP_F3_0_ADDR => prdata <= reg_wp.addr_buffer_f(32*7-1 DOWNTO 32*6);--3
534 WHEN ADDR_LFR_WP_F3_0_ADDR => prdata <= reg_wp.addr_buffer_f(32*7-1 DOWNTO 32*6); --3
535 WHEN ADDR_LFR_WP_F3_1_ADDR => prdata <= reg_wp.addr_buffer_f(32*8-1 DOWNTO 32*7);
535 WHEN ADDR_LFR_WP_F3_1_ADDR => prdata <= reg_wp.addr_buffer_f(32*8-1 DOWNTO 32*7);
536
536
537 WHEN ADDR_LFR_WP_STATUS =>
537 WHEN ADDR_LFR_WP_STATUS =>
538 prdata(7 DOWNTO 0) <= reg_wp.status_ready_buffer_f;
538 prdata(7 DOWNTO 0) <= reg_wp.status_ready_buffer_f;
539 prdata(11 DOWNTO 8) <= reg_wp.error_buffer_full;
539 prdata(11 DOWNTO 8) <= reg_wp.error_buffer_full;
540 prdata(15 DOWNTO 12) <= reg_wp.status_new_err;
540 prdata(15 DOWNTO 12) <= reg_wp.status_new_err;
541
541
542 WHEN ADDR_LFR_WP_DELTASNAPSHOT => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_snapshot;
542 WHEN ADDR_LFR_WP_DELTASNAPSHOT => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_snapshot;
543 WHEN ADDR_LFR_WP_DELTA_F0 => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f0;
543 WHEN ADDR_LFR_WP_DELTA_F0 => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f0;
544 WHEN ADDR_LFR_WP_DELTA_F0_2 => prdata(delta_vector_size_f0_2-1 DOWNTO 0) <= reg_wp.delta_f0_2;
544 WHEN ADDR_LFR_WP_DELTA_F0_2 => prdata(delta_vector_size_f0_2-1 DOWNTO 0) <= reg_wp.delta_f0_2;
545 WHEN ADDR_LFR_WP_DELTA_F1 => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f1;
545 WHEN ADDR_LFR_WP_DELTA_F1 => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f1;
546 WHEN ADDR_LFR_WP_DELTA_F2 => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f2;
546 WHEN ADDR_LFR_WP_DELTA_F2 => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f2;
547 WHEN ADDR_LFR_WP_DATA_IN_BUFFER => prdata(nb_data_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_data_by_buffer;
547 WHEN ADDR_LFR_WP_DATA_IN_BUFFER => prdata(nb_data_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_data_by_buffer;
548 WHEN ADDR_LFR_WP_NBSNAPSHOT => prdata(nb_snapshot_param_size-1 DOWNTO 0) <= reg_wp.nb_snapshot_param;
548 WHEN ADDR_LFR_WP_NBSNAPSHOT => prdata(nb_snapshot_param_size-1 DOWNTO 0) <= reg_wp.nb_snapshot_param;
549 WHEN ADDR_LFR_WP_START_DATE => prdata(30 DOWNTO 0) <= reg_wp.start_date;
549 WHEN ADDR_LFR_WP_START_DATE => prdata(30 DOWNTO 0) <= reg_wp.start_date;
550
550
551 WHEN ADDR_LFR_WP_F0_0_TIME_COARSE => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*0 + 31 DOWNTO 48*0);
551 WHEN ADDR_LFR_WP_F0_0_TIME_COARSE => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*0 + 31 DOWNTO 48*0);
552 WHEN ADDR_LFR_WP_F0_0_TIME_FINE => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*0 + 47 DOWNTO 48*0 + 32);
552 WHEN ADDR_LFR_WP_F0_0_TIME_FINE => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*0 + 47 DOWNTO 48*0 + 32);
553 WHEN ADDR_LFR_WP_F0_1_TIME_COARSE => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*1 + 31 DOWNTO 48*1);
553 WHEN ADDR_LFR_WP_F0_1_TIME_COARSE => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*1 + 31 DOWNTO 48*1);
554 WHEN ADDR_LFR_WP_F0_1_TIME_FINE => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*1 + 47 DOWNTO 48*1 + 32);
554 WHEN ADDR_LFR_WP_F0_1_TIME_FINE => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*1 + 47 DOWNTO 48*1 + 32);
555
555
556 WHEN ADDR_LFR_WP_F1_0_TIME_COARSE => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*2 + 31 DOWNTO 48*2);
556 WHEN ADDR_LFR_WP_F1_0_TIME_COARSE => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*2 + 31 DOWNTO 48*2);
557 WHEN ADDR_LFR_WP_F1_0_TIME_FINE => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*2 + 47 DOWNTO 48*2 + 32);
557 WHEN ADDR_LFR_WP_F1_0_TIME_FINE => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*2 + 47 DOWNTO 48*2 + 32);
558 WHEN ADDR_LFR_WP_F1_1_TIME_COARSE => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*3 + 31 DOWNTO 48*3);
558 WHEN ADDR_LFR_WP_F1_1_TIME_COARSE => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*3 + 31 DOWNTO 48*3);
559 WHEN ADDR_LFR_WP_F1_1_TIME_FINE => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*3 + 47 DOWNTO 48*3 + 32);
559 WHEN ADDR_LFR_WP_F1_1_TIME_FINE => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*3 + 47 DOWNTO 48*3 + 32);
560
560
561 WHEN ADDR_LFR_WP_F2_0_TIME_COARSE => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*4 + 31 DOWNTO 48*4);
561 WHEN ADDR_LFR_WP_F2_0_TIME_COARSE => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*4 + 31 DOWNTO 48*4);
562 WHEN ADDR_LFR_WP_F2_0_TIME_FINE => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*4 + 47 DOWNTO 48*4 + 32);
562 WHEN ADDR_LFR_WP_F2_0_TIME_FINE => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*4 + 47 DOWNTO 48*4 + 32);
563 WHEN ADDR_LFR_WP_F2_1_TIME_COARSE => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*5 + 31 DOWNTO 48*5);
563 WHEN ADDR_LFR_WP_F2_1_TIME_COARSE => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*5 + 31 DOWNTO 48*5);
564 WHEN ADDR_LFR_WP_F2_1_TIME_FINE => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*5 + 47 DOWNTO 48*5 + 32);
564 WHEN ADDR_LFR_WP_F2_1_TIME_FINE => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*5 + 47 DOWNTO 48*5 + 32);
565
565
566 WHEN ADDR_LFR_WP_F3_0_TIME_COARSE => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*6 + 31 DOWNTO 48*6);
566 WHEN ADDR_LFR_WP_F3_0_TIME_COARSE => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*6 + 31 DOWNTO 48*6);
567 WHEN ADDR_LFR_WP_F3_0_TIME_FINE => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*6 + 47 DOWNTO 48*6 + 32);
567 WHEN ADDR_LFR_WP_F3_0_TIME_FINE => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*6 + 47 DOWNTO 48*6 + 32);
568 WHEN ADDR_LFR_WP_F3_1_TIME_COARSE => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*7 + 31 DOWNTO 48*7);
568 WHEN ADDR_LFR_WP_F3_1_TIME_COARSE => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*7 + 31 DOWNTO 48*7);
569 WHEN ADDR_LFR_WP_F3_1_TIME_FINE => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*7 + 47 DOWNTO 48*7 + 32);
569 WHEN ADDR_LFR_WP_F3_1_TIME_FINE => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*7 + 47 DOWNTO 48*7 + 32);
570
570
571 WHEN ADDR_LFR_WP_LENGTH => prdata(25 DOWNTO 0) <= reg_wp.length_buffer;
571 WHEN ADDR_LFR_WP_LENGTH => prdata(25 DOWNTO 0) <= reg_wp.length_buffer;
572
572
573 WHEN ADDR_LFR_WP_F3_V => prdata(15 DOWNTO 0) <= sample_f3_v_reg;
573 WHEN ADDR_LFR_WP_F3_V => prdata(15 DOWNTO 0) <= sample_f3_v_reg;
574 prdata(31 DOWNTO 16) <= (OTHERS => '0');
574 prdata(31 DOWNTO 16) <= (OTHERS => '0');
575 WHEN ADDR_LFR_WP_F3_E1 => prdata(15 DOWNTO 0) <= sample_f3_e1_reg;
575 WHEN ADDR_LFR_WP_F3_E1 => prdata(15 DOWNTO 0) <= sample_f3_e1_reg;
576 prdata(31 DOWNTO 16) <= (OTHERS => '0');
576 prdata(31 DOWNTO 16) <= (OTHERS => '0');
577 WHEN ADDR_LFR_WP_F3_E2 => prdata(15 DOWNTO 0) <= sample_f3_e2_reg;
577 WHEN ADDR_LFR_WP_F3_E2 => prdata(15 DOWNTO 0) <= sample_f3_e2_reg;
578 prdata(31 DOWNTO 16) <= (OTHERS => '0');
578 prdata(31 DOWNTO 16) <= (OTHERS => '0');
579 ---------------------------------------------------------------------
579 ---------------------------------------------------------------------
580 WHEN ADDR_LFR_VERSION => prdata(23 DOWNTO 0) <= top_lfr_version(23 DOWNTO 0);
580 WHEN ADDR_LFR_VERSION => prdata(23 DOWNTO 0) <= top_lfr_version(23 DOWNTO 0);
581 WHEN OTHERS => NULL;
581 WHEN OTHERS => NULL;
582
582
583 END CASE;
583 END CASE;
584 IF (apbi.pwrite AND apbi.penable) = '1' THEN
584 IF (apbi.pwrite AND apbi.penable) = '1' THEN
585 -- APB DMA WRITE --
585 -- APB DMA WRITE --
586 CASE paddr(7 DOWNTO 2) IS
586 CASE paddr(7 DOWNTO 2) IS
587 --
587 --
588 WHEN ADDR_LFR_SM_CONFIG =>
588 WHEN ADDR_LFR_SM_CONFIG =>
589 reg_sp.config_active_interruption_onNewMatrix <= apbi.pwdata(0);
589 reg_sp.config_active_interruption_onNewMatrix <= apbi.pwdata(0);
590 reg_sp.config_active_interruption_onError <= apbi.pwdata(1);
590 reg_sp.config_active_interruption_onError <= apbi.pwdata(1);
591 reg_sp.config_ms_run <= apbi.pwdata(2);
591 reg_sp.config_ms_run <= apbi.pwdata(2);
592
592
593 WHEN ADDR_LFR_SM_STATUS =>
593 WHEN ADDR_LFR_SM_STATUS =>
594 reg_sp.status_ready_matrix_f0_0 <= ((NOT apbi.pwdata(0) ) AND reg_sp.status_ready_matrix_f0_0 ) OR reg0_ready_matrix_f0;
594 reg_sp.status_ready_matrix_f0_0 <= ((NOT apbi.pwdata(0)) AND reg_sp.status_ready_matrix_f0_0) OR reg0_ready_matrix_f0;
595 reg_sp.status_ready_matrix_f0_1 <= ((NOT apbi.pwdata(1) ) AND reg_sp.status_ready_matrix_f0_1 ) OR reg1_ready_matrix_f0;
595 reg_sp.status_ready_matrix_f0_1 <= ((NOT apbi.pwdata(1)) AND reg_sp.status_ready_matrix_f0_1) OR reg1_ready_matrix_f0;
596 reg_sp.status_ready_matrix_f1_0 <= ((NOT apbi.pwdata(2) ) AND reg_sp.status_ready_matrix_f1_0 ) OR reg0_ready_matrix_f1;
596 reg_sp.status_ready_matrix_f1_0 <= ((NOT apbi.pwdata(2)) AND reg_sp.status_ready_matrix_f1_0) OR reg0_ready_matrix_f1;
597 reg_sp.status_ready_matrix_f1_1 <= ((NOT apbi.pwdata(3) ) AND reg_sp.status_ready_matrix_f1_1 ) OR reg1_ready_matrix_f1;
597 reg_sp.status_ready_matrix_f1_1 <= ((NOT apbi.pwdata(3)) AND reg_sp.status_ready_matrix_f1_1) OR reg1_ready_matrix_f1;
598 reg_sp.status_ready_matrix_f2_0 <= ((NOT apbi.pwdata(4) ) AND reg_sp.status_ready_matrix_f2_0 ) OR reg0_ready_matrix_f2;
598 reg_sp.status_ready_matrix_f2_0 <= ((NOT apbi.pwdata(4)) AND reg_sp.status_ready_matrix_f2_0) OR reg0_ready_matrix_f2;
599 reg_sp.status_ready_matrix_f2_1 <= ((NOT apbi.pwdata(5) ) AND reg_sp.status_ready_matrix_f2_1 ) OR reg1_ready_matrix_f2;
599 reg_sp.status_ready_matrix_f2_1 <= ((NOT apbi.pwdata(5)) AND reg_sp.status_ready_matrix_f2_1) OR reg1_ready_matrix_f2;
600 reg_sp.status_error_buffer_full <= ((NOT apbi.pwdata(7) ) AND reg_sp.status_error_buffer_full ) OR error_buffer_full;
600 reg_sp.status_error_buffer_full <= ((NOT apbi.pwdata(7)) AND reg_sp.status_error_buffer_full) OR error_buffer_full;
601 reg_sp.status_error_input_fifo_write(0) <= ((NOT apbi.pwdata(8) ) AND reg_sp.status_error_input_fifo_write(0)) OR error_input_fifo_write(0);
601 reg_sp.status_error_input_fifo_write(0) <= ((NOT apbi.pwdata(8)) AND reg_sp.status_error_input_fifo_write(0)) OR error_input_fifo_write(0);
602 reg_sp.status_error_input_fifo_write(1) <= ((NOT apbi.pwdata(9) ) AND reg_sp.status_error_input_fifo_write(1)) OR error_input_fifo_write(1);
602 reg_sp.status_error_input_fifo_write(1) <= ((NOT apbi.pwdata(9)) AND reg_sp.status_error_input_fifo_write(1)) OR error_input_fifo_write(1);
603 reg_sp.status_error_input_fifo_write(2) <= ((NOT apbi.pwdata(10)) AND reg_sp.status_error_input_fifo_write(2)) OR error_input_fifo_write(2);
603 reg_sp.status_error_input_fifo_write(2) <= ((NOT apbi.pwdata(10)) AND reg_sp.status_error_input_fifo_write(2)) OR error_input_fifo_write(2);
604 WHEN ADDR_LFR_SM_F0_0_ADDR => reg_sp.addr_matrix_f0_0 <= apbi.pwdata;
604 WHEN ADDR_LFR_SM_F0_0_ADDR => reg_sp.addr_matrix_f0_0 <= apbi.pwdata;
605 WHEN ADDR_LFR_SM_F0_1_ADDR => reg_sp.addr_matrix_f0_1 <= apbi.pwdata;
605 WHEN ADDR_LFR_SM_F0_1_ADDR => reg_sp.addr_matrix_f0_1 <= apbi.pwdata;
606 WHEN ADDR_LFR_SM_F1_0_ADDR => reg_sp.addr_matrix_f1_0 <= apbi.pwdata;
606 WHEN ADDR_LFR_SM_F1_0_ADDR => reg_sp.addr_matrix_f1_0 <= apbi.pwdata;
607 WHEN ADDR_LFR_SM_F1_1_ADDR => reg_sp.addr_matrix_f1_1 <= apbi.pwdata;
607 WHEN ADDR_LFR_SM_F1_1_ADDR => reg_sp.addr_matrix_f1_1 <= apbi.pwdata;
608 WHEN ADDR_LFR_SM_F2_0_ADDR => reg_sp.addr_matrix_f2_0 <= apbi.pwdata;
608 WHEN ADDR_LFR_SM_F2_0_ADDR => reg_sp.addr_matrix_f2_0 <= apbi.pwdata;
609 WHEN ADDR_LFR_SM_F2_1_ADDR => reg_sp.addr_matrix_f2_1 <= apbi.pwdata;
609 WHEN ADDR_LFR_SM_F2_1_ADDR => reg_sp.addr_matrix_f2_1 <= apbi.pwdata;
610
610
611 WHEN ADDR_LFR_SM_LENGTH => reg_sp.length_matrix <= apbi.pwdata(25 DOWNTO 0);
611 WHEN ADDR_LFR_SM_LENGTH => reg_sp.length_matrix <= apbi.pwdata(25 DOWNTO 0);
612 ---------------------------------------------------------------------
612 ---------------------------------------------------------------------
613 WHEN ADDR_LFR_WP_DATASHAPING =>
613 WHEN ADDR_LFR_WP_DATASHAPING =>
614 reg_wp.data_shaping_BW <= apbi.pwdata(0);
614 reg_wp.data_shaping_BW <= apbi.pwdata(0);
615 reg_wp.data_shaping_SP0 <= apbi.pwdata(1);
615 reg_wp.data_shaping_SP0 <= apbi.pwdata(1);
616 reg_wp.data_shaping_SP1 <= apbi.pwdata(2);
616 reg_wp.data_shaping_SP1 <= apbi.pwdata(2);
617 reg_wp.data_shaping_R0 <= apbi.pwdata(3);
617 reg_wp.data_shaping_R0 <= apbi.pwdata(3);
618 reg_wp.data_shaping_R1 <= apbi.pwdata(4);
618 reg_wp.data_shaping_R1 <= apbi.pwdata(4);
619 reg_wp.data_shaping_R2 <= apbi.pwdata(5);
619 reg_wp.data_shaping_R2 <= apbi.pwdata(5);
620 WHEN ADDR_LFR_WP_CONTROL =>
620 WHEN ADDR_LFR_WP_CONTROL =>
621 reg_wp.enable_f0 <= apbi.pwdata(0);
621 reg_wp.enable_f0 <= apbi.pwdata(0);
622 reg_wp.enable_f1 <= apbi.pwdata(1);
622 reg_wp.enable_f1 <= apbi.pwdata(1);
623 reg_wp.enable_f2 <= apbi.pwdata(2);
623 reg_wp.enable_f2 <= apbi.pwdata(2);
624 reg_wp.enable_f3 <= apbi.pwdata(3);
624 reg_wp.enable_f3 <= apbi.pwdata(3);
625 reg_wp.burst_f0 <= apbi.pwdata(4);
625 reg_wp.burst_f0 <= apbi.pwdata(4);
626 reg_wp.burst_f1 <= apbi.pwdata(5);
626 reg_wp.burst_f1 <= apbi.pwdata(5);
627 reg_wp.burst_f2 <= apbi.pwdata(6);
627 reg_wp.burst_f2 <= apbi.pwdata(6);
628 reg_wp.run <= apbi.pwdata(7);
628 reg_wp.run <= apbi.pwdata(7);
629 WHEN ADDR_LFR_WP_F0_0_ADDR => reg_wp.addr_buffer_f(32*1-1 DOWNTO 32*0) <= apbi.pwdata;
629 WHEN ADDR_LFR_WP_F0_0_ADDR => reg_wp.addr_buffer_f(32*1-1 DOWNTO 32*0) <= apbi.pwdata;
630 WHEN ADDR_LFR_WP_F0_1_ADDR => reg_wp.addr_buffer_f(32*2-1 DOWNTO 32*1) <= apbi.pwdata;
630 WHEN ADDR_LFR_WP_F0_1_ADDR => reg_wp.addr_buffer_f(32*2-1 DOWNTO 32*1) <= apbi.pwdata;
631 WHEN ADDR_LFR_WP_F1_0_ADDR => reg_wp.addr_buffer_f(32*3-1 DOWNTO 32*2) <= apbi.pwdata;
631 WHEN ADDR_LFR_WP_F1_0_ADDR => reg_wp.addr_buffer_f(32*3-1 DOWNTO 32*2) <= apbi.pwdata;
632 WHEN ADDR_LFR_WP_F1_1_ADDR => reg_wp.addr_buffer_f(32*4-1 DOWNTO 32*3) <= apbi.pwdata;
632 WHEN ADDR_LFR_WP_F1_1_ADDR => reg_wp.addr_buffer_f(32*4-1 DOWNTO 32*3) <= apbi.pwdata;
633 WHEN ADDR_LFR_WP_F2_0_ADDR => reg_wp.addr_buffer_f(32*5-1 DOWNTO 32*4) <= apbi.pwdata;
633 WHEN ADDR_LFR_WP_F2_0_ADDR => reg_wp.addr_buffer_f(32*5-1 DOWNTO 32*4) <= apbi.pwdata;
634 WHEN ADDR_LFR_WP_F2_1_ADDR => reg_wp.addr_buffer_f(32*6-1 DOWNTO 32*5) <= apbi.pwdata;
634 WHEN ADDR_LFR_WP_F2_1_ADDR => reg_wp.addr_buffer_f(32*6-1 DOWNTO 32*5) <= apbi.pwdata;
635 WHEN ADDR_LFR_WP_F3_0_ADDR => reg_wp.addr_buffer_f(32*7-1 DOWNTO 32*6) <= apbi.pwdata;
635 WHEN ADDR_LFR_WP_F3_0_ADDR => reg_wp.addr_buffer_f(32*7-1 DOWNTO 32*6) <= apbi.pwdata;
636 WHEN ADDR_LFR_WP_F3_1_ADDR => reg_wp.addr_buffer_f(32*8-1 DOWNTO 32*7) <= apbi.pwdata;
636 WHEN ADDR_LFR_WP_F3_1_ADDR => reg_wp.addr_buffer_f(32*8-1 DOWNTO 32*7) <= apbi.pwdata;
637 WHEN ADDR_LFR_WP_STATUS =>
637 WHEN ADDR_LFR_WP_STATUS =>
638 all_reg_wp_status_bit: FOR I IN 3 DOWNTO 0 LOOP
638 all_reg_wp_status_bit : FOR I IN 3 DOWNTO 0 LOOP
639 reg_wp.status_ready_buffer_f(I*2) <= ((NOT apbi.pwdata(I*2) ) AND reg_wp.status_ready_buffer_f(I*2) ) OR reg_ready_buffer_f(I*2);
639 reg_wp.status_ready_buffer_f(I*2) <= ((NOT apbi.pwdata(I*2)) AND reg_wp.status_ready_buffer_f(I*2)) OR reg_ready_buffer_f(I*2);
640 reg_wp.status_ready_buffer_f(I*2+1) <= ((NOT apbi.pwdata(I*2+1)) AND reg_wp.status_ready_buffer_f(I*2+1)) OR reg_ready_buffer_f(I*2+1);
640 reg_wp.status_ready_buffer_f(I*2+1) <= ((NOT apbi.pwdata(I*2+1)) AND reg_wp.status_ready_buffer_f(I*2+1)) OR reg_ready_buffer_f(I*2+1);
641 reg_wp.error_buffer_full(I) <= ((NOT apbi.pwdata(I+8) ) AND reg_wp.error_buffer_full(I) ) OR wfp_error_buffer_full(I);
641 reg_wp.error_buffer_full(I) <= ((NOT apbi.pwdata(I+8)) AND reg_wp.error_buffer_full(I)) OR wfp_error_buffer_full(I);
642 reg_wp.status_new_err(I) <= ((NOT apbi.pwdata(I+12) ) AND reg_wp.status_new_err(I) ) OR status_new_err(I);
642 reg_wp.status_new_err(I) <= ((NOT apbi.pwdata(I+12)) AND reg_wp.status_new_err(I)) OR status_new_err(I);
643 END LOOP all_reg_wp_status_bit;
643 END LOOP all_reg_wp_status_bit;
644
644
645 WHEN ADDR_LFR_WP_DELTASNAPSHOT => reg_wp.delta_snapshot <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
645 WHEN ADDR_LFR_WP_DELTASNAPSHOT => reg_wp.delta_snapshot <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
646 WHEN ADDR_LFR_WP_DELTA_F0 => reg_wp.delta_f0 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
646 WHEN ADDR_LFR_WP_DELTA_F0 => reg_wp.delta_f0 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
647 WHEN ADDR_LFR_WP_DELTA_F0_2 => reg_wp.delta_f0_2 <= apbi.pwdata(delta_vector_size_f0_2-1 DOWNTO 0);
647 WHEN ADDR_LFR_WP_DELTA_F0_2 => reg_wp.delta_f0_2 <= apbi.pwdata(delta_vector_size_f0_2-1 DOWNTO 0);
648 WHEN ADDR_LFR_WP_DELTA_F1 => reg_wp.delta_f1 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
648 WHEN ADDR_LFR_WP_DELTA_F1 => reg_wp.delta_f1 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
649 WHEN ADDR_LFR_WP_DELTA_F2 => reg_wp.delta_f2 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
649 WHEN ADDR_LFR_WP_DELTA_F2 => reg_wp.delta_f2 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
650 WHEN ADDR_LFR_WP_DATA_IN_BUFFER => reg_wp.nb_data_by_buffer <= apbi.pwdata(nb_data_by_buffer_size-1 DOWNTO 0);
650 WHEN ADDR_LFR_WP_DATA_IN_BUFFER => reg_wp.nb_data_by_buffer <= apbi.pwdata(nb_data_by_buffer_size-1 DOWNTO 0);
651 WHEN ADDR_LFR_WP_NBSNAPSHOT => reg_wp.nb_snapshot_param <= apbi.pwdata(nb_snapshot_param_size-1 DOWNTO 0);
651 WHEN ADDR_LFR_WP_NBSNAPSHOT => reg_wp.nb_snapshot_param <= apbi.pwdata(nb_snapshot_param_size-1 DOWNTO 0);
652 WHEN ADDR_LFR_WP_START_DATE => reg_wp.start_date <= apbi.pwdata(30 DOWNTO 0);
652 WHEN ADDR_LFR_WP_START_DATE => reg_wp.start_date <= apbi.pwdata(30 DOWNTO 0);
653
654 WHEN ADDR_LFR_WP_LENGTH => reg_wp.length_buffer <= apbi.pwdata(25 DOWNTO 0);
655
653
656 WHEN OTHERS => NULL;
654 WHEN ADDR_LFR_WP_LENGTH => reg_wp.length_buffer <= apbi.pwdata(25 DOWNTO 0);
655
656 WHEN OTHERS => NULL;
657 END CASE;
657 END CASE;
658 END IF;
658 END IF;
659 END IF;
659 END IF;
660 --apbo.pirq(pirq_ms) <=
660 --apbo.pirq(pirq_ms) <=
661 pirq_temp( pirq_ms) <= apbo_irq_ms;
661 pirq_temp(pirq_ms) <= apbo_irq_ms;
662 pirq_temp(pirq_wfp) <= apbo_irq_wfp;
662 pirq_temp(pirq_wfp) <= apbo_irq_wfp;
663 apbo_irq_ms <= ((reg_sp.config_active_interruption_onNewMatrix AND (ready_matrix_f0 OR
663 apbo_irq_ms <= ((reg_sp.config_active_interruption_onNewMatrix AND (ready_matrix_f0 OR
664 ready_matrix_f1 OR
664 ready_matrix_f1 OR
665 ready_matrix_f2)
665 ready_matrix_f2)
666 )
666 )
667 OR
667 OR
668 (reg_sp.config_active_interruption_onError AND (
668 (reg_sp.config_active_interruption_onError AND (
669 -- error_bad_component_error OR
669 -- error_bad_component_error OR
670 error_buffer_full
670 error_buffer_full
671 OR error_input_fifo_write(0)
671 OR error_input_fifo_write(0)
672 OR error_input_fifo_write(1)
672 OR error_input_fifo_write(1)
673 OR error_input_fifo_write(2))
673 OR error_input_fifo_write(2))
674 ));
674 ));
675 -- apbo.pirq(pirq_wfp)
675 -- apbo.pirq(pirq_wfp)
676 apbo_irq_wfp<= ored_irq_wfp;
676 apbo_irq_wfp <= ored_irq_wfp;
677
677
678 END IF;
678 END IF;
679 END PROCESS lpp_lfr_apbreg;
679 END PROCESS lpp_lfr_apbreg;
680
680
681 apbo.pirq <= pirq_temp;
681 apbo.pirq <= pirq_temp;
682
682
683
683
684 --all_irq: FOR I IN 31 DOWNTO 0 GENERATE
684 --all_irq: FOR I IN 31 DOWNTO 0 GENERATE
685 -- IRQ_is_PIRQ_MS: IF I = pirq_ms GENERATE
685 -- IRQ_is_PIRQ_MS: IF I = pirq_ms GENERATE
686 -- apbo.pirq(I) <= apbo_irq_ms;
686 -- apbo.pirq(I) <= apbo_irq_ms;
687 -- END GENERATE IRQ_is_PIRQ_MS;
687 -- END GENERATE IRQ_is_PIRQ_MS;
688 -- IRQ_is_PIRQ_WFP: IF I = pirq_wfp GENERATE
688 -- IRQ_is_PIRQ_WFP: IF I = pirq_wfp GENERATE
689 -- apbo.pirq(I) <= apbo_irq_wfp;
689 -- apbo.pirq(I) <= apbo_irq_wfp;
690 -- END GENERATE IRQ_is_PIRQ_WFP;
690 -- END GENERATE IRQ_is_PIRQ_WFP;
691 -- IRQ_OTHERS: IF I /= pirq_ms AND pirq_wfp /= pirq_wfp GENERATE
691 -- IRQ_OTHERS: IF I /= pirq_ms AND pirq_wfp /= pirq_wfp GENERATE
692 -- apbo.pirq(I) <= '0';
692 -- apbo.pirq(I) <= '0';
693 -- END GENERATE IRQ_OTHERS;
693 -- END GENERATE IRQ_OTHERS;
694
694
695 --END GENERATE all_irq;
695 --END GENERATE all_irq;
696
696
697
697
698
698
699 apbo.pindex <= pindex;
699 apbo.pindex <= pindex;
700 apbo.pconfig <= pconfig;
700 apbo.pconfig <= pconfig;
701 apbo.prdata <= prdata;
701 apbo.prdata <= prdata;
702
702
703 -----------------------------------------------------------------------------
703 -----------------------------------------------------------------------------
704 -- IRQ
704 -- IRQ
705 -----------------------------------------------------------------------------
705 -----------------------------------------------------------------------------
706 irq_wfp_reg_s <= wfp_ready_buffer & wfp_error_buffer_full & status_new_err;
706 irq_wfp_reg_s <= wfp_ready_buffer & wfp_error_buffer_full & status_new_err;
707
707
708 PROCESS (HCLK, HRESETn)
708 PROCESS (HCLK, HRESETn)
709 BEGIN -- PROCESS
709 BEGIN -- PROCESS
710 IF HRESETn = '0' THEN -- asynchronous reset (active low)
710 IF HRESETn = '0' THEN -- asynchronous reset (active low)
711 irq_wfp_reg <= (OTHERS => '0');
711 irq_wfp_reg <= (OTHERS => '0');
712 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
712 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
713 irq_wfp_reg <= irq_wfp_reg_s;
713 irq_wfp_reg <= irq_wfp_reg_s;
714 END IF;
714 END IF;
715 END PROCESS;
715 END PROCESS;
716
716
717 all_irq_wfp : FOR I IN IRQ_WFP_SIZE-1 DOWNTO 0 GENERATE
717 all_irq_wfp : FOR I IN IRQ_WFP_SIZE-1 DOWNTO 0 GENERATE
718 irq_wfp(I) <= (NOT irq_wfp_reg(I)) AND irq_wfp_reg_s(I);
718 irq_wfp(I) <= (NOT irq_wfp_reg(I)) AND irq_wfp_reg_s(I);
719 END GENERATE all_irq_wfp;
719 END GENERATE all_irq_wfp;
720
720
721 irq_wfp_ZERO <= (OTHERS => '0');
721 irq_wfp_ZERO <= (OTHERS => '0');
722 ored_irq_wfp <= '0' WHEN irq_wfp = irq_wfp_ZERO ELSE '1';
722 ored_irq_wfp <= '0' WHEN irq_wfp = irq_wfp_ZERO ELSE '1';
723
723
724 run_ms <= reg_sp.config_ms_run;
724 run_ms <= reg_sp.config_ms_run;
725
725
726 -----------------------------------------------------------------------------
726 -----------------------------------------------------------------------------
727 --
727 --
728 -----------------------------------------------------------------------------
728 -----------------------------------------------------------------------------
729 lpp_apbreg_ms_pointer_f0 : lpp_apbreg_ms_pointer
729 lpp_apbreg_ms_pointer_f0 : lpp_apbreg_ms_pointer
730 PORT MAP (
730 PORT MAP (
731 clk => HCLK,
731 clk => HCLK,
732 rstn => HRESETn,
732 rstn => HRESETn,
733
733
734 run => '1',--reg_sp.config_ms_run,
734 run => '1', --reg_sp.config_ms_run,
735
735
736 reg0_status_ready_matrix => reg_sp.status_ready_matrix_f0_0,
736 reg0_status_ready_matrix => reg_sp.status_ready_matrix_f0_0,
737 reg0_ready_matrix => reg0_ready_matrix_f0,
737 reg0_ready_matrix => reg0_ready_matrix_f0,
738 reg0_addr_matrix => reg_sp.addr_matrix_f0_0, --reg0_addr_matrix_f0,
738 reg0_addr_matrix => reg_sp.addr_matrix_f0_0, --reg0_addr_matrix_f0,
739 reg0_matrix_time => reg_sp.time_matrix_f0_0, --reg0_matrix_time_f0,
739 reg0_matrix_time => reg_sp.time_matrix_f0_0, --reg0_matrix_time_f0,
740
740
741 reg1_status_ready_matrix => reg_sp.status_ready_matrix_f0_1,
741 reg1_status_ready_matrix => reg_sp.status_ready_matrix_f0_1,
742 reg1_ready_matrix => reg1_ready_matrix_f0,
742 reg1_ready_matrix => reg1_ready_matrix_f0,
743 reg1_addr_matrix => reg_sp.addr_matrix_f0_1, --reg1_addr_matrix_f0,
743 reg1_addr_matrix => reg_sp.addr_matrix_f0_1, --reg1_addr_matrix_f0,
744 reg1_matrix_time => reg_sp.time_matrix_f0_1, --reg1_matrix_time_f0,
744 reg1_matrix_time => reg_sp.time_matrix_f0_1, --reg1_matrix_time_f0,
745
745
746 ready_matrix => ready_matrix_f0,
746 ready_matrix => ready_matrix_f0,
747 status_ready_matrix => status_ready_matrix_f0,
747 status_ready_matrix => status_ready_matrix_f0,
748 addr_matrix => addr_matrix_f0,
748 addr_matrix => addr_matrix_f0,
749 matrix_time => matrix_time_f0);
749 matrix_time => matrix_time_f0);
750
750
751 lpp_apbreg_ms_pointer_f1 : lpp_apbreg_ms_pointer
751 lpp_apbreg_ms_pointer_f1 : lpp_apbreg_ms_pointer
752 PORT MAP (
752 PORT MAP (
753 clk => HCLK,
753 clk => HCLK,
754 rstn => HRESETn,
754 rstn => HRESETn,
755
755
756 run => '1',--reg_sp.config_ms_run,
756 run => '1', --reg_sp.config_ms_run,
757
757
758 reg0_status_ready_matrix => reg_sp.status_ready_matrix_f1_0,
758 reg0_status_ready_matrix => reg_sp.status_ready_matrix_f1_0,
759 reg0_ready_matrix => reg0_ready_matrix_f1,
759 reg0_ready_matrix => reg0_ready_matrix_f1,
760 reg0_addr_matrix => reg_sp.addr_matrix_f1_0, --reg0_addr_matrix_f1,
760 reg0_addr_matrix => reg_sp.addr_matrix_f1_0, --reg0_addr_matrix_f1,
761 reg0_matrix_time => reg_sp.time_matrix_f1_0, --reg0_matrix_time_f1,
761 reg0_matrix_time => reg_sp.time_matrix_f1_0, --reg0_matrix_time_f1,
762
762
763 reg1_status_ready_matrix => reg_sp.status_ready_matrix_f1_1,
763 reg1_status_ready_matrix => reg_sp.status_ready_matrix_f1_1,
764 reg1_ready_matrix => reg1_ready_matrix_f1,
764 reg1_ready_matrix => reg1_ready_matrix_f1,
765 reg1_addr_matrix => reg_sp.addr_matrix_f1_1, --reg1_addr_matrix_f1,
765 reg1_addr_matrix => reg_sp.addr_matrix_f1_1, --reg1_addr_matrix_f1,
766 reg1_matrix_time => reg_sp.time_matrix_f1_1, --reg1_matrix_time_f1,
766 reg1_matrix_time => reg_sp.time_matrix_f1_1, --reg1_matrix_time_f1,
767
767
768 ready_matrix => ready_matrix_f1,
768 ready_matrix => ready_matrix_f1,
769 status_ready_matrix => status_ready_matrix_f1,
769 status_ready_matrix => status_ready_matrix_f1,
770 addr_matrix => addr_matrix_f1,
770 addr_matrix => addr_matrix_f1,
771 matrix_time => matrix_time_f1);
771 matrix_time => matrix_time_f1);
772
772
773 lpp_apbreg_ms_pointer_f2 : lpp_apbreg_ms_pointer
773 lpp_apbreg_ms_pointer_f2 : lpp_apbreg_ms_pointer
774 PORT MAP (
774 PORT MAP (
775 clk => HCLK,
775 clk => HCLK,
776 rstn => HRESETn,
776 rstn => HRESETn,
777
777
778 run => '1',--reg_sp.config_ms_run,
778 run => '1', --reg_sp.config_ms_run,
779
779
780 reg0_status_ready_matrix => reg_sp.status_ready_matrix_f2_0,
780 reg0_status_ready_matrix => reg_sp.status_ready_matrix_f2_0,
781 reg0_ready_matrix => reg0_ready_matrix_f2,
781 reg0_ready_matrix => reg0_ready_matrix_f2,
782 reg0_addr_matrix => reg_sp.addr_matrix_f2_0, --reg0_addr_matrix_f2,
782 reg0_addr_matrix => reg_sp.addr_matrix_f2_0, --reg0_addr_matrix_f2,
783 reg0_matrix_time => reg_sp.time_matrix_f2_0, --reg0_matrix_time_f2,
783 reg0_matrix_time => reg_sp.time_matrix_f2_0, --reg0_matrix_time_f2,
784
784
785 reg1_status_ready_matrix => reg_sp.status_ready_matrix_f2_1,
785 reg1_status_ready_matrix => reg_sp.status_ready_matrix_f2_1,
786 reg1_ready_matrix => reg1_ready_matrix_f2,
786 reg1_ready_matrix => reg1_ready_matrix_f2,
787 reg1_addr_matrix => reg_sp.addr_matrix_f2_1, --reg1_addr_matrix_f2,
787 reg1_addr_matrix => reg_sp.addr_matrix_f2_1, --reg1_addr_matrix_f2,
788 reg1_matrix_time => reg_sp.time_matrix_f2_1, --reg1_matrix_time_f2,
788 reg1_matrix_time => reg_sp.time_matrix_f2_1, --reg1_matrix_time_f2,
789
789
790 ready_matrix => ready_matrix_f2,
790 ready_matrix => ready_matrix_f2,
791 status_ready_matrix => status_ready_matrix_f2,
791 status_ready_matrix => status_ready_matrix_f2,
792 addr_matrix => addr_matrix_f2,
792 addr_matrix => addr_matrix_f2,
793 matrix_time => matrix_time_f2);
793 matrix_time => matrix_time_f2);
794
794
795 -----------------------------------------------------------------------------
795 -----------------------------------------------------------------------------
796 all_wfp_pointer: FOR I IN 3 DOWNTO 0 GENERATE
796 all_wfp_pointer : FOR I IN 3 DOWNTO 0 GENERATE
797 lpp_apbreg_wfp_pointer_fi : lpp_apbreg_ms_pointer
797 lpp_apbreg_wfp_pointer_fi : lpp_apbreg_ms_pointer
798 PORT MAP (
798 PORT MAP (
799 clk => HCLK,
799 clk => HCLK,
800 rstn => HRESETn,
800 rstn => HRESETn,
801
801
802 run => '1',--reg_wp.run,
802 run => '1', --reg_wp.run,
803
803
804 reg0_status_ready_matrix => reg_wp.status_ready_buffer_f(2*I),
804 reg0_status_ready_matrix => reg_wp.status_ready_buffer_f(2*I),
805 reg0_ready_matrix => reg_ready_buffer_f(2*I),
805 reg0_ready_matrix => reg_ready_buffer_f(2*I),
806 reg0_addr_matrix => reg_wp.addr_buffer_f((2*I+1)*32-1 DOWNTO (2*I)*32),
806 reg0_addr_matrix => reg_wp.addr_buffer_f((2*I+1)*32-1 DOWNTO (2*I)*32),
807 reg0_matrix_time => reg_wp.time_buffer_f((2*I+1)*48-1 DOWNTO (2*I)*48),
807 reg0_matrix_time => reg_wp.time_buffer_f((2*I+1)*48-1 DOWNTO (2*I)*48),
808
808
809 reg1_status_ready_matrix => reg_wp.status_ready_buffer_f(2*I+1),
809 reg1_status_ready_matrix => reg_wp.status_ready_buffer_f(2*I+1),
810 reg1_ready_matrix => reg_ready_buffer_f(2*I+1),
810 reg1_ready_matrix => reg_ready_buffer_f(2*I+1),
811 reg1_addr_matrix => reg_wp.addr_buffer_f((2*I+2)*32-1 DOWNTO (2*I+1)*32),
811 reg1_addr_matrix => reg_wp.addr_buffer_f((2*I+2)*32-1 DOWNTO (2*I+1)*32),
812 reg1_matrix_time => reg_wp.time_buffer_f((2*I+2)*48-1 DOWNTO (2*I+1)*48),
812 reg1_matrix_time => reg_wp.time_buffer_f((2*I+2)*48-1 DOWNTO (2*I+1)*48),
813
813
814 ready_matrix => wfp_ready_buffer(I),
814 ready_matrix => wfp_ready_buffer(I),
815 status_ready_matrix => wfp_status_buffer_ready(I),
815 status_ready_matrix => wfp_status_buffer_ready(I),
816 addr_matrix => wfp_addr_buffer((I+1)*32-1 DOWNTO I*32),
816 addr_matrix => wfp_addr_buffer((I+1)*32-1 DOWNTO I*32),
817 matrix_time => wfp_buffer_time((I+1)*48-1 DOWNTO I*48)
817 matrix_time => wfp_buffer_time((I+1)*48-1 DOWNTO I*48)
818 );
818 );
819
819
820 END GENERATE all_wfp_pointer;
820 END GENERATE all_wfp_pointer;
821 -----------------------------------------------------------------------------
821 -----------------------------------------------------------------------------
822
822
823 END beh;
823 END beh;
824
824
825 ------------------------------------------------------------------------------
825 ------------------------------------------------------------------------------
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