# HG changeset patch # User pellion # Date 2015-01-28 16:41:56 # Node ID 4ecb2a44355972628549ced321f78640592f4632 # Parent 7d6d07e76b74e34914057567a755c1545e3023ca add filter (f2,f3) diff --git a/designs/LFR-em-WFP_MS/LFR-em.vhd b/designs/LFR-em-WFP_MS/LFR-em.vhd --- a/designs/LFR-em-WFP_MS/LFR-em.vhd +++ b/designs/LFR-em-WFP_MS/LFR-em.vhd @@ -379,7 +379,7 @@ BEGIN -- beh pirq_ms => 6, pirq_wfp => 14, hindex => 2, - top_lfr_version => X"010131") -- aa.bb.cc version + top_lfr_version => X"010135") -- aa.bb.cc version -- AA : BOARD NUMBER -- 0 => MINI_LFR -- 1 => EM diff --git a/designs/MINI-LFR_WFP_MS/MINI_LFR_top.vhd b/designs/MINI-LFR_WFP_MS/MINI_LFR_top.vhd --- a/designs/MINI-LFR_WFP_MS/MINI_LFR_top.vhd +++ b/designs/MINI-LFR_WFP_MS/MINI_LFR_top.vhd @@ -582,8 +582,8 @@ BEGIN -- beh ADC_SDO_sig <= ADC_SDO; sample_hk <= "0001000100010001" WHEN HK_SEL = "00" ELSE - "0010001000100010" WHEN HK_SEL = "10" ELSE - "0100010001000100" WHEN HK_SEL = "11" ELSE + "0010001000100010" WHEN HK_SEL = "01" ELSE + "0100010001000100" WHEN HK_SEL = "10" ELSE (OTHERS => '0'); diff --git a/lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR_v3.vhd b/lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR_v3.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR_v3.vhd @@ -0,0 +1,442 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Jean-christophe PELLION +-- Mail : jean-christophe.pellion@lpp.polytechnique.fr +------------------------------------------------------------------------------- + +LIBRARY IEEE; +USE IEEE.numeric_std.ALL; +USE IEEE.std_logic_1164.ALL; + +LIBRARY techmap; +USE techmap.gencomp.ALL; + +LIBRARY lpp; +USE lpp.iir_filter.ALL; +USE lpp.general_purpose.ALL; + +ENTITY IIR_CEL_CTRLR_v3 IS + GENERIC ( + tech : INTEGER := 0; + Mem_use : INTEGER := use_RAM; + Sample_SZ : INTEGER := 18; + Coef_SZ : INTEGER := 9; + Coef_Nb : INTEGER := 25; + Coef_sel_SZ : INTEGER := 5; + Cels_count : INTEGER := 5; + ChanelsCount : INTEGER := 8); + PORT ( + rstn : IN STD_LOGIC; + clk : IN STD_LOGIC; + + virg_pos : IN INTEGER; + coefs : IN STD_LOGIC_VECTOR((Coef_SZ*Coef_Nb)-1 DOWNTO 0); + + sample_in1_val : IN STD_LOGIC; + sample_in1 : IN samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0); + sample_in2_val : IN STD_LOGIC; + sample_in2 : IN samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0); + + sample_out1_val : OUT STD_LOGIC; + sample_out1 : OUT samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0); + sample_out2_val : OUT STD_LOGIC; + sample_out2 : OUT samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0)); +END IIR_CEL_CTRLR_v3; + +ARCHITECTURE ar_IIR_CEL_CTRLR_v3 OF IIR_CEL_CTRLR_v3 IS + + COMPONENT RAM_CTRLR_v2 + GENERIC ( + tech : INTEGER; + Input_SZ_1 : INTEGER; + Mem_use : INTEGER); + PORT ( + rstn : IN STD_LOGIC; + clk : IN STD_LOGIC; + ram_write : IN STD_LOGIC; + ram_read : IN STD_LOGIC; + raddr_rst : IN STD_LOGIC; + raddr_add1 : IN STD_LOGIC; + waddr_previous : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + sample_in : IN STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0); + sample_out : OUT STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0)); + END COMPONENT; + + COMPONENT IIR_CEL_CTRLR_v3_DATAFLOW + GENERIC ( + Sample_SZ : INTEGER; + Coef_SZ : INTEGER; + Coef_Nb : INTEGER; + Coef_sel_SZ : INTEGER); + PORT ( + rstn : IN STD_LOGIC; + clk : IN STD_LOGIC; + virg_pos : IN INTEGER; + coefs : IN STD_LOGIC_VECTOR((Coef_SZ*Coef_Nb)-1 DOWNTO 0); + in_sel_src : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + ram_sel_Wdata : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + ram_input : OUT STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0); + ram_output : IN STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0); + alu_sel_input : IN STD_LOGIC; + alu_sel_coeff : IN STD_LOGIC_VECTOR(Coef_sel_SZ-1 DOWNTO 0); + alu_ctrl : IN STD_LOGIC_VECTOR(2 DOWNTO 0); + alu_comp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + sample_in : IN STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0); + sample_out : OUT STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0)); + END COMPONENT; + + COMPONENT IIR_CEL_CTRLR_v2_CONTROL + GENERIC ( + Coef_sel_SZ : INTEGER; + Cels_count : INTEGER; + ChanelsCount : INTEGER); + PORT ( + rstn : IN STD_LOGIC; + clk : IN STD_LOGIC; + sample_in_val : IN STD_LOGIC; + sample_in_rot : OUT STD_LOGIC; + sample_out_val : OUT STD_LOGIC; + sample_out_rot : OUT STD_LOGIC; + in_sel_src : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + ram_sel_Wdata : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + ram_write : OUT STD_LOGIC; + ram_read : OUT STD_LOGIC; + raddr_rst : OUT STD_LOGIC; + raddr_add1 : OUT STD_LOGIC; + waddr_previous : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + alu_sel_input : OUT STD_LOGIC; + alu_sel_coeff : OUT STD_LOGIC_VECTOR(Coef_sel_SZ-1 DOWNTO 0); + alu_ctrl : OUT STD_LOGIC_VECTOR(2 DOWNTO 0)); + END COMPONENT; + + SIGNAL in_sel_src : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL ram_sel_Wdata : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL ram_write : STD_LOGIC; + SIGNAL ram_read : STD_LOGIC; + SIGNAL raddr_rst : STD_LOGIC; + SIGNAL raddr_add1 : STD_LOGIC; + SIGNAL waddr_previous : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL alu_sel_input : STD_LOGIC; + SIGNAL alu_sel_coeff : STD_LOGIC_VECTOR(Coef_sel_SZ-1 DOWNTO 0); + SIGNAL alu_ctrl : STD_LOGIC_VECTOR(2 DOWNTO 0); + + SIGNAL sample_in_buf : samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0); + SIGNAL sample_in_rotate : STD_LOGIC; + SIGNAL sample_in_s : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0); + SIGNAL sample_out_val_s : STD_LOGIC; + SIGNAL sample_out_val_s2 : STD_LOGIC; + SIGNAL sample_out_rot_s : STD_LOGIC; + SIGNAL sample_out_s : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0); + + SIGNAL sample_out_s2 : samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0); + + SIGNAL ram_input : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0); + SIGNAL ram_output : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0); + -- + SIGNAL sample_in_val : STD_LOGIC; + SIGNAL sample_in : samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0); + SIGNAL sample_out_val : STD_LOGIC; + SIGNAL sample_out : samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0); + + ----------------------------------------------------------------------------- + -- + ----------------------------------------------------------------------------- + SIGNAL CHANNEL_SEL : STD_LOGIC; + + SIGNAL ram_output_1 : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0); + SIGNAL ram_output_2 : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0); + + SIGNAL ram_write_1 : STD_LOGIC; + SIGNAL ram_read_1 : STD_LOGIC; + SIGNAL raddr_rst_1 : STD_LOGIC; + SIGNAL raddr_add1_1 : STD_LOGIC; + SIGNAL waddr_previous_1 : STD_LOGIC_VECTOR(1 DOWNTO 0); + + SIGNAL ram_write_2 : STD_LOGIC; + SIGNAL ram_read_2 : STD_LOGIC; + SIGNAL raddr_rst_2 : STD_LOGIC; + SIGNAL raddr_add1_2 : STD_LOGIC; + SIGNAL waddr_previous_2 : STD_LOGIC_VECTOR(1 DOWNTO 0); + ----------------------------------------------------------------------------- + SIGNAL channel_ready : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL channel_val : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL channel_done : STD_LOGIC_VECTOR(1 DOWNTO 0); + ----------------------------------------------------------------------------- + TYPE FSM_CHANNEL_SELECTION IS (IDLE, ONGOING_1, ONGOING_2, WAIT_STATE); + SIGNAL state_channel_selection : FSM_CHANNEL_SELECTION; + + SIGNAL sample_out_zero : samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0); + +BEGIN + + ----------------------------------------------------------------------------- + channel_val(0) <= sample_in1_val; + channel_val(1) <= sample_in2_val; + all_channel_input_valid: FOR I IN 1 DOWNTO 0 GENERATE + PROCESS (clk, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + channel_ready(I) <= '0'; + ELSIF clk'event AND clk = '1' THEN -- rising clock edge + IF channel_val(I) = '1' THEN + channel_ready(I) <= '1'; + ELSIF channel_done(I) = '1' THEN + channel_ready(I) <= '0'; + END IF; + END IF; + END PROCESS; + END GENERATE all_channel_input_valid; + ----------------------------------------------------------------------------- + all_channel_sample_out: FOR I IN ChanelsCount-1 DOWNTO 0 GENERATE + all_bit: FOR J IN Sample_SZ-1 DOWNTO 0 GENERATE + sample_out_zero(I,J) <= '0'; + END GENERATE all_bit; + END GENERATE all_channel_sample_out; + + PROCESS (clk, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + state_channel_selection <= IDLE; + CHANNEL_SEL <= '0'; + sample_in_val <= '0'; + sample_out1_val <= '0'; + sample_out2_val <= '0'; + sample_out1 <= sample_out_zero; + sample_out2 <= sample_out_zero; + channel_done <= "00"; + + ELSIF clk'event AND clk = '1' THEN -- rising clock edge + CASE state_channel_selection IS + WHEN IDLE => + CHANNEL_SEL <= '0'; + sample_in_val <= '0'; + sample_out1_val <= '0'; + sample_out2_val <= '0'; + channel_done <= "00"; + IF channel_ready(0) = '1' THEN + state_channel_selection <= ONGOING_1; + CHANNEL_SEL <= '0'; + sample_in_val <= '1'; + ELSIF channel_ready(1) = '1' THEN + state_channel_selection <= ONGOING_2; + CHANNEL_SEL <= '1'; + sample_in_val <= '1'; + END IF; + WHEN ONGOING_1 => + sample_in_val <= '0'; + IF sample_out_val = '1' THEN + state_channel_selection <= WAIT_STATE; + sample_out1 <= sample_out; + sample_out1_val <= '1'; + channel_done(0) <= '1'; + END IF; + WHEN ONGOING_2 => + sample_in_val <= '0'; + IF sample_out_val = '1' THEN + state_channel_selection <= WAIT_STATE; + sample_out2 <= sample_out; + sample_out2_val <= '1'; + channel_done(1) <= '1'; + END IF; + WHEN WAIT_STATE => + state_channel_selection <= IDLE; + CHANNEL_SEL <= '0'; + sample_in_val <= '0'; + sample_out1_val <= '0'; + sample_out2_val <= '0'; + channel_done <= "00"; + + WHEN OTHERS => NULL; + END CASE; + + END IF; + END PROCESS; + + sample_in <= sample_in1 WHEN CHANNEL_SEL = '0' ELSE sample_in2; + ----------------------------------------------------------------------------- + ram_output <= ram_output_1 WHEN CHANNEL_SEL = '0' ELSE + ram_output_2; + + ram_write_1 <= ram_write WHEN CHANNEL_SEL = '0' ELSE '0'; + ram_read_1 <= ram_read WHEN CHANNEL_SEL = '0' ELSE '0'; + raddr_rst_1 <= raddr_rst WHEN CHANNEL_SEL = '0' ELSE '1'; + raddr_add1_1 <= raddr_add1 WHEN CHANNEL_SEL = '0' ELSE '0'; + waddr_previous_1 <= waddr_previous WHEN CHANNEL_SEL = '0' ELSE "00"; + + ram_write_2 <= ram_write WHEN CHANNEL_SEL = '1' ELSE '0'; + ram_read_2 <= ram_read WHEN CHANNEL_SEL = '1' ELSE '0'; + raddr_rst_2 <= raddr_rst WHEN CHANNEL_SEL = '1' ELSE '1'; + raddr_add1_2 <= raddr_add1 WHEN CHANNEL_SEL = '1' ELSE '0'; + waddr_previous_2 <= waddr_previous WHEN CHANNEL_SEL = '1' ELSE "00"; + + RAM_CTRLR_v2_1: RAM_CTRLR_v2 + GENERIC MAP ( + tech => tech, + Input_SZ_1 => Sample_SZ, + Mem_use => Mem_use) + PORT MAP ( + clk => clk, + rstn => rstn, + ram_write => ram_write_1, + ram_read => ram_read_1, + raddr_rst => raddr_rst_1, + raddr_add1 => raddr_add1_1, + waddr_previous => waddr_previous_1, + sample_in => ram_input, + sample_out => ram_output_1); + + RAM_CTRLR_v2_2: RAM_CTRLR_v2 + GENERIC MAP ( + tech => tech, + Input_SZ_1 => Sample_SZ, + Mem_use => Mem_use) + PORT MAP ( + clk => clk, + rstn => rstn, + ram_write => ram_write_2, + ram_read => ram_read_2, + raddr_rst => raddr_rst_2, + raddr_add1 => raddr_add1_2, + waddr_previous => waddr_previous_2, + sample_in => ram_input, + sample_out => ram_output_2); + ----------------------------------------------------------------------------- + + IIR_CEL_CTRLR_v3_DATAFLOW_1 : IIR_CEL_CTRLR_v3_DATAFLOW + GENERIC MAP ( + Sample_SZ => Sample_SZ, + Coef_SZ => Coef_SZ, + Coef_Nb => Coef_Nb, + Coef_sel_SZ => Coef_sel_SZ) + PORT MAP ( + rstn => rstn, + clk => clk, + virg_pos => virg_pos, + coefs => coefs, + --CTRL + in_sel_src => in_sel_src, + ram_sel_Wdata => ram_sel_Wdata, + -- + ram_input => ram_input, + ram_output => ram_output, + -- + alu_sel_input => alu_sel_input, + alu_sel_coeff => alu_sel_coeff, + alu_ctrl => alu_ctrl, + alu_comp => "00", + --DATA + sample_in => sample_in_s, + sample_out => sample_out_s); + ----------------------------------------------------------------------------- + + + IIR_CEL_CTRLR_v3_CONTROL_1 : IIR_CEL_CTRLR_v2_CONTROL + GENERIC MAP ( + Coef_sel_SZ => Coef_sel_SZ, + Cels_count => Cels_count, + ChanelsCount => ChanelsCount) + PORT MAP ( + rstn => rstn, + clk => clk, + sample_in_val => sample_in_val, + sample_in_rot => sample_in_rotate, + sample_out_val => sample_out_val_s, + sample_out_rot => sample_out_rot_s, + + in_sel_src => in_sel_src, + ram_sel_Wdata => ram_sel_Wdata, + ram_write => ram_write, + ram_read => ram_read, + raddr_rst => raddr_rst, + raddr_add1 => raddr_add1, + waddr_previous => waddr_previous, + alu_sel_input => alu_sel_input, + alu_sel_coeff => alu_sel_coeff, + alu_ctrl => alu_ctrl); + + ----------------------------------------------------------------------------- + -- SAMPLE IN + ----------------------------------------------------------------------------- + loop_all_sample : FOR J IN Sample_SZ-1 DOWNTO 0 GENERATE + + loop_all_chanel : FOR I IN ChanelsCount-1 DOWNTO 0 GENERATE + PROCESS (clk, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + sample_in_buf(I, J) <= '0'; + ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge + IF sample_in_val = '1' THEN + sample_in_buf(I, J) <= sample_in(I, J); + ELSIF sample_in_rotate = '1' THEN + sample_in_buf(I, J) <= sample_in_buf((I+1) MOD ChanelsCount, J); + END IF; + END IF; + END PROCESS; + END GENERATE loop_all_chanel; + + sample_in_s(J) <= sample_in(0, J) WHEN sample_in_val = '1' ELSE sample_in_buf(0, J); + + END GENERATE loop_all_sample; + + ----------------------------------------------------------------------------- + -- SAMPLE OUT + ----------------------------------------------------------------------------- + PROCESS (clk, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + sample_out_val <= '0'; + sample_out_val_s2 <= '0'; + ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge + sample_out_val <= sample_out_val_s2; + sample_out_val_s2 <= sample_out_val_s; + END IF; + END PROCESS; + + chanel_HIGH : FOR I IN Sample_SZ-1 DOWNTO 0 GENERATE + PROCESS (clk, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + sample_out_s2(ChanelsCount-1, I) <= '0'; + ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge + IF sample_out_rot_s = '1' THEN + sample_out_s2(ChanelsCount-1, I) <= sample_out_s(I); + END IF; + END IF; + END PROCESS; + END GENERATE chanel_HIGH; + + chanel_more : IF ChanelsCount > 1 GENERATE + all_chanel : FOR J IN ChanelsCount-1 DOWNTO 1 GENERATE + all_bit : FOR I IN Sample_SZ-1 DOWNTO 0 GENERATE + PROCESS (clk, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + sample_out_s2(J-1, I) <= '0'; + ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge + IF sample_out_rot_s = '1' THEN + sample_out_s2(J-1, I) <= sample_out_s2(J, I); + END IF; + END IF; + END PROCESS; + END GENERATE all_bit; + END GENERATE all_chanel; + END GENERATE chanel_more; + + sample_out <= sample_out_s2; +END ar_IIR_CEL_CTRLR_v3; diff --git a/lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR_v3_DATAFLOW.vhd b/lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR_v3_DATAFLOW.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR_v3_DATAFLOW.vhd @@ -0,0 +1,213 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Jean-christophe PELLION +-- Mail : jean-christophe.pellion@lpp.polytechnique.fr +------------------------------------------------------------------------------- +LIBRARY IEEE; +USE IEEE.numeric_std.ALL; +USE IEEE.std_logic_1164.ALL; +LIBRARY lpp; +USE lpp.iir_filter.ALL; +USE lpp.general_purpose.ALL; + + + +ENTITY IIR_CEL_CTRLR_v3_DATAFLOW IS + GENERIC( + Sample_SZ : INTEGER := 16; + Coef_SZ : INTEGER := 9; + Coef_Nb : INTEGER := 30; + Coef_sel_SZ : INTEGER := 5 + ); + PORT( + rstn : IN STD_LOGIC; + clk : IN STD_LOGIC; + -- PARAMETER + virg_pos : IN INTEGER; + coefs : IN STD_LOGIC_VECTOR((Coef_SZ*Coef_Nb)-1 DOWNTO 0); + -- CONTROL + in_sel_src : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + -- + ram_sel_Wdata : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + -- + ram_input : OUT STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0); + ram_output : IN STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0); + + -- + alu_sel_input : IN STD_LOGIC; + alu_sel_coeff : IN STD_LOGIC_VECTOR(Coef_sel_SZ-1 DOWNTO 0); + alu_ctrl : IN STD_LOGIC_VECTOR(2 DOWNTO 0);--(MAC_op, MULT_with_clear_ADD, IDLE) + alu_comp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + -- DATA + sample_in : IN STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0); + sample_out : OUT STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0) + ); +END IIR_CEL_CTRLR_v3_DATAFLOW; + +ARCHITECTURE ar_IIR_CEL_CTRLR_v3_DATAFLOW OF IIR_CEL_CTRLR_v3_DATAFLOW IS + + SIGNAL reg_sample_in : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0); + SIGNAL alu_output : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0); + SIGNAL alu_sample : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0); + SIGNAL alu_output_s : STD_LOGIC_VECTOR(Sample_SZ+Coef_SZ-1 DOWNTO 0); + + SIGNAL arrayCoeff : MUX_INPUT_TYPE(0 TO (2**Coef_sel_SZ)-1,Coef_SZ-1 DOWNTO 0); + SIGNAL alu_coef_s : MUX_OUTPUT_TYPE(Coef_SZ-1 DOWNTO 0); + + SIGNAL alu_coef : STD_LOGIC_VECTOR(Coef_SZ-1 DOWNTO 0); + +BEGIN + + ----------------------------------------------------------------------------- + -- INPUT + ----------------------------------------------------------------------------- + PROCESS (clk, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + reg_sample_in <= (OTHERS => '0'); + ELSIF clk'event AND clk = '1' THEN -- rising clock edge + CASE in_sel_src IS + WHEN "00" => reg_sample_in <= reg_sample_in; + WHEN "01" => reg_sample_in <= sample_in; + WHEN "10" => reg_sample_in <= ram_output; + WHEN "11" => reg_sample_in <= alu_output; + WHEN OTHERS => NULL; + END CASE; + END IF; + END PROCESS; + + + ----------------------------------------------------------------------------- + -- RAM + CTRL + ----------------------------------------------------------------------------- + + ram_input <= reg_sample_in WHEN ram_sel_Wdata = "00" ELSE + alu_output WHEN ram_sel_Wdata = "01" ELSE + ram_output; + + ----------------------------------------------------------------------------- + -- MAC_ACC + ----------------------------------------------------------------------------- + -- Control : mac_ctrl (MAC_op, MULT_with_clear_ADD, IDLE) + -- Data In : mac_sample, mac_coef + -- Data Out: mac_output + + alu_sample <= reg_sample_in WHEN alu_sel_input = '0' ELSE ram_output; + + coefftable: FOR I IN 0 TO (2**Coef_sel_SZ)-1 GENERATE + coeff_in: IF I < Coef_Nb GENERATE + all_bit: FOR J IN Coef_SZ-1 DOWNTO 0 GENERATE + arrayCoeff(I,J) <= coefs(Coef_SZ*I+J); + END GENERATE all_bit; + END GENERATE coeff_in; + coeff_null: IF I > (Coef_Nb -1) GENERATE + all_bit: FOR J IN Coef_SZ-1 DOWNTO 0 GENERATE + arrayCoeff(I,J) <= '0'; + END GENERATE all_bit; + END GENERATE coeff_null; + END GENERATE coefftable; + + Coeff_Mux : MUXN + GENERIC MAP ( + Input_SZ => Coef_SZ, + NbStage => Coef_sel_SZ) + PORT MAP ( + sel => alu_sel_coeff, + INPUT => arrayCoeff, + RES => alu_coef_s); + + + all_bit: FOR J IN Coef_SZ-1 DOWNTO 0 GENERATE + alu_coef(J) <= alu_coef_s(J); + END GENERATE all_bit; + + ----------------------------------------------------------------------------- + -- TODO : just for Synthesis test + + --PROCESS (clk, rstn) + --BEGIN + -- IF rstn = '0' THEN + -- alu_coef <= (OTHERS => '0'); + -- ELSIF clk'event AND clk = '1' THEN + -- all_bit: FOR J IN Coef_SZ-1 DOWNTO 0 LOOP + -- alu_coef(J) <= alu_coef_s(J); + -- END LOOP all_bit; + -- END IF; + --END PROCESS; + + ----------------------------------------------------------------------------- + + + ALU_1: ALU + GENERIC MAP ( + Arith_en => 1, + Input_SZ_1 => Sample_SZ, + Input_SZ_2 => Coef_SZ, + COMP_EN => 1) + PORT MAP ( + clk => clk, + reset => rstn, + ctrl => alu_ctrl, + comp => alu_comp, + OP1 => alu_sample, + OP2 => alu_coef, + RES => alu_output_s); + + alu_output <= alu_output_s(Sample_SZ+virg_pos-1 DOWNTO virg_pos); + + sample_out <= alu_output; + +END ar_IIR_CEL_CTRLR_v3_DATAFLOW; + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/lib/lpp/dsp/iir_filter/iir_filter.vhd b/lib/lpp/dsp/iir_filter/iir_filter.vhd --- a/lib/lpp/dsp/iir_filter/iir_filter.vhd +++ b/lib/lpp/dsp/iir_filter/iir_filter.vhd @@ -139,8 +139,35 @@ PACKAGE iir_filter IS sample_out_val : OUT STD_LOGIC; sample_out : OUT samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0)); END COMPONENT; + + COMPONENT IIR_CEL_CTRLR_v3 + GENERIC ( + tech : INTEGER; + Mem_use : INTEGER; + Sample_SZ : INTEGER; + Coef_SZ : INTEGER; + Coef_Nb : INTEGER; + Coef_sel_SZ : INTEGER; + Cels_count : INTEGER; + ChanelsCount : INTEGER); + PORT ( + rstn : IN STD_LOGIC; + clk : IN STD_LOGIC; + virg_pos : IN INTEGER; + coefs : IN STD_LOGIC_VECTOR((Coef_SZ*Coef_Nb)-1 DOWNTO 0); + sample_in1_val : IN STD_LOGIC; + sample_in1 : IN samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0); + sample_in2_val : IN STD_LOGIC; + sample_in2 : IN samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0); + sample_out1_val : OUT STD_LOGIC; + sample_out1 : OUT samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0); + sample_out2_val : OUT STD_LOGIC; + sample_out2 : OUT samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0)); + END COMPONENT; + + --component FilterCTRLR is --port( -- reset : in std_logic; diff --git a/lib/lpp/dsp/iir_filter/vhdlsyn.txt b/lib/lpp/dsp/iir_filter/vhdlsyn.txt --- a/lib/lpp/dsp/iir_filter/vhdlsyn.txt +++ b/lib/lpp/dsp/iir_filter/vhdlsyn.txt @@ -6,3 +6,5 @@ RAM_CTRLR_v2.vhd IIR_CEL_CTRLR_v2_CONTROL.vhd IIR_CEL_CTRLR_v2_DATAFLOW.vhd IIR_CEL_CTRLR_v2.vhd +IIR_CEL_CTRLR_v3_DATAFLOW.vhd +IIR_CEL_CTRLR_v3.vhd diff --git a/lib/lpp/lpp_top_lfr/lpp_lfr_apbreg.vhd b/lib/lpp/lpp_top_lfr/lpp_lfr_apbreg.vhd --- a/lib/lpp/lpp_top_lfr/lpp_lfr_apbreg.vhd +++ b/lib/lpp/lpp_top_lfr/lpp_lfr_apbreg.vhd @@ -69,8 +69,8 @@ ENTITY lpp_lfr_apbreg IS ready_matrix_f2 : IN STD_LOGIC; -- error_bad_component_error : IN STD_LOGIC; - error_buffer_full : IN STD_LOGIC; -- TODO - error_input_fifo_write : IN STD_LOGIC_VECTOR(2 DOWNTO 0); -- TODO + error_buffer_full : IN STD_LOGIC; -- TODO + error_input_fifo_write : IN STD_LOGIC_VECTOR(2 DOWNTO 0); -- TODO -- debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0); @@ -100,8 +100,8 @@ ENTITY lpp_lfr_apbreg IS --status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0); --status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); --status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0); - status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0); - + status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + -- OUT data_shaping_BW : OUT STD_LOGIC; data_shaping_SP0 : OUT STD_LOGIC; @@ -130,22 +130,22 @@ ENTITY lpp_lfr_apbreg IS run : OUT STD_LOGIC; - start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0); - + start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0); + wfp_status_buffer_ready : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); wfp_addr_buffer : OUT STD_LOGIC_VECTOR(32*4-1 DOWNTO 0); wfp_length_buffer : OUT STD_LOGIC_VECTOR(25 DOWNTO 0); - wfp_ready_buffer : IN STD_LOGIC_VECTOR(3 DOWNTO 0); - wfp_buffer_time : IN STD_LOGIC_VECTOR(48*4-1 DOWNTO 0); - wfp_error_buffer_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + wfp_ready_buffer : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + wfp_buffer_time : IN STD_LOGIC_VECTOR(48*4-1 DOWNTO 0); + wfp_error_buffer_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0); --------------------------------------------------------------------------- - sample_f3_v : IN STD_LOGIC_VECTOR(15 DOWNTO 0); - sample_f3_e1 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); - sample_f3_e2 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); - sample_f3_valid : IN STD_LOGIC; + sample_f3_v : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + sample_f3_e1 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + sample_f3_e2 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + sample_f3_valid : IN STD_LOGIC; --------------------------------------------------------------------------- - debug_vector : OUT STD_LOGIC_VECTOR(11 DOWNTO 0) - + debug_vector : OUT STD_LOGIC_VECTOR(11 DOWNTO 0) + ); END lpp_lfr_apbreg; @@ -197,35 +197,35 @@ ARCHITECTURE beh OF lpp_lfr_apbreg IS TYPE lpp_WaveformPicker_regs IS RECORD -- status_full : STD_LOGIC_VECTOR(3 DOWNTO 0); -- status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0); - status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0); - data_shaping_BW : STD_LOGIC; - data_shaping_SP0 : STD_LOGIC; - data_shaping_SP1 : STD_LOGIC; - data_shaping_R0 : STD_LOGIC; - data_shaping_R1 : STD_LOGIC; - data_shaping_R2 : STD_LOGIC; - delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); - delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); - delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0); - delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); - delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); - nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); + status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0); + data_shaping_BW : STD_LOGIC; + data_shaping_SP0 : STD_LOGIC; + data_shaping_SP1 : STD_LOGIC; + data_shaping_R0 : STD_LOGIC; + data_shaping_R1 : STD_LOGIC; + data_shaping_R2 : STD_LOGIC; + delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); + delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); + delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0); + delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); + delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); + nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); -- nb_word_by_buffer : STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0); - nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); - enable_f0 : STD_LOGIC; - enable_f1 : STD_LOGIC; - enable_f2 : STD_LOGIC; - enable_f3 : STD_LOGIC; - burst_f0 : STD_LOGIC; - burst_f1 : STD_LOGIC; - burst_f2 : STD_LOGIC; - run : STD_LOGIC; - status_ready_buffer_f : STD_LOGIC_VECTOR(4*2-1 DOWNTO 0); - addr_buffer_f : STD_LOGIC_VECTOR(4*2*32-1 DOWNTO 0); - time_buffer_f : STD_LOGIC_VECTOR(4*2*48-1 DOWNTO 0); + nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); + enable_f0 : STD_LOGIC; + enable_f1 : STD_LOGIC; + enable_f2 : STD_LOGIC; + enable_f3 : STD_LOGIC; + burst_f0 : STD_LOGIC; + burst_f1 : STD_LOGIC; + burst_f2 : STD_LOGIC; + run : STD_LOGIC; + status_ready_buffer_f : STD_LOGIC_VECTOR(4*2-1 DOWNTO 0); + addr_buffer_f : STD_LOGIC_VECTOR(4*2*32-1 DOWNTO 0); + time_buffer_f : STD_LOGIC_VECTOR(4*2*48-1 DOWNTO 0); length_buffer : STD_LOGIC_VECTOR(25 DOWNTO 0); - error_buffer_full : STD_LOGIC_VECTOR(3 DOWNTO 0); - start_date : STD_LOGIC_VECTOR(30 DOWNTO 0); + error_buffer_full : STD_LOGIC_VECTOR(3 DOWNTO 0); + start_date : STD_LOGIC_VECTOR(30 DOWNTO 0); END RECORD; SIGNAL reg_wp : lpp_WaveformPicker_regs; @@ -267,16 +267,16 @@ ARCHITECTURE beh OF lpp_lfr_apbreg IS SIGNAL reg1_ready_matrix_f2 : STD_LOGIC; -- SIGNAL reg1_addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); -- SIGNAL reg1_matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0); - SIGNAL apbo_irq_ms : STD_LOGIC; - SIGNAL apbo_irq_wfp : STD_LOGIC; + SIGNAL apbo_irq_ms : STD_LOGIC; + SIGNAL apbo_irq_wfp : STD_LOGIC; ----------------------------------------------------------------------------- - SIGNAL reg_ready_buffer_f : STD_LOGIC_VECTOR( 2*4-1 DOWNTO 0); + SIGNAL reg_ready_buffer_f : STD_LOGIC_VECTOR(2*4-1 DOWNTO 0); - SIGNAL pirq_temp : STD_LOGIC_VECTOR(31 DOWNTO 0); - - SIGNAL sample_f3_v_reg : STD_LOGIC_VECTOR(15 DOWNTO 0); - SIGNAL sample_f3_e1_reg : STD_LOGIC_VECTOR(15 DOWNTO 0); - SIGNAL sample_f3_e2_reg : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL pirq_temp : STD_LOGIC_VECTOR(31 DOWNTO 0); + + SIGNAL sample_f3_v_reg : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL sample_f3_e1_reg : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL sample_f3_e2_reg : STD_LOGIC_VECTOR(15 DOWNTO 0); BEGIN -- beh @@ -288,7 +288,7 @@ BEGIN -- beh debug_vector(9) <= reg0_ready_matrix_f2; debug_vector(10) <= reg1_ready_matrix_f2; debug_vector(11) <= HRESETn; - + -- status_ready_matrix_f0 <= reg_sp.status_ready_matrix_f0; -- status_ready_matrix_f1 <= reg_sp.status_ready_matrix_f1; -- status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2; @@ -335,20 +335,20 @@ BEGIN -- beh start_date <= reg_wp.start_date; - length_matrix_f0 <= reg_sp.length_matrix; - length_matrix_f1 <= reg_sp.length_matrix; - length_matrix_f2 <= reg_sp.length_matrix; + length_matrix_f0 <= reg_sp.length_matrix; + length_matrix_f1 <= reg_sp.length_matrix; + length_matrix_f2 <= reg_sp.length_matrix; wfp_length_buffer <= reg_wp.length_buffer; - + PROCESS (HCLK, HRESETn) BEGIN -- PROCESS - IF HRESETn = '0' THEN -- asynchronous reset (active low) + IF HRESETn = '0' THEN -- asynchronous reset (active low) sample_f3_v_reg <= (OTHERS => '0'); sample_f3_e1_reg <= (OTHERS => '0'); sample_f3_e2_reg <= (OTHERS => '0'); - ELSIF HCLK'event AND HCLK = '1' THEN -- rising clock edge + ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge IF sample_f3_valid = '1' THEN sample_f3_v_reg <= sample_f3_v; sample_f3_e1_reg <= sample_f3_e1; @@ -356,7 +356,7 @@ BEGIN -- beh END IF; END IF; END PROCESS; - + lpp_lfr_apbreg : PROCESS (HCLK, HRESETn) VARIABLE paddr : STD_LOGIC_VECTOR(7 DOWNTO 2); @@ -383,7 +383,7 @@ BEGIN -- beh reg_sp.addr_matrix_f2_1 <= (OTHERS => '0'); reg_sp.length_matrix <= (OTHERS => '0'); - + -- reg_sp.time_matrix_f0_0 <= (OTHERS => '0'); -- ok -- reg_sp.time_matrix_f1_0 <= (OTHERS => '0'); -- ok -- reg_sp.time_matrix_f2_0 <= (OTHERS => '0'); -- ok @@ -394,10 +394,10 @@ BEGIN -- beh prdata <= (OTHERS => '0'); - - apbo_irq_ms <= '0'; + + apbo_irq_ms <= '0'; apbo_irq_wfp <= '0'; - + -- status_full_ack <= (OTHERS => '0'); @@ -427,14 +427,14 @@ BEGIN -- beh reg_wp.nb_data_by_buffer <= (OTHERS => '0'); reg_wp.nb_snapshot_param <= (OTHERS => '0'); reg_wp.start_date <= (OTHERS => '1'); - + reg_wp.status_ready_buffer_f <= (OTHERS => '0'); - reg_wp.length_buffer <= (OTHERS => '0'); + reg_wp.length_buffer <= (OTHERS => '0'); pirq_temp <= (OTHERS => '0'); - + reg_wp.addr_buffer_f <= (OTHERS => '0'); - + ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge -- status_full_ack <= (OTHERS => '0'); @@ -447,7 +447,7 @@ BEGIN -- beh reg_sp.status_ready_matrix_f1_1 <= reg_sp.status_ready_matrix_f1_1 OR reg1_ready_matrix_f1; reg_sp.status_ready_matrix_f2_1 <= reg_sp.status_ready_matrix_f2_1 OR reg1_ready_matrix_f2; - all_status_ready_buffer_bit: FOR I IN 4*2-1 DOWNTO 0 LOOP + all_status_ready_buffer_bit : FOR I IN 4*2-1 DOWNTO 0 LOOP reg_wp.status_ready_buffer_f(I) <= reg_wp.status_ready_buffer_f(I) OR reg_ready_buffer_f(I); END LOOP all_status_ready_buffer_bit; @@ -460,8 +460,8 @@ BEGIN -- beh all_status : FOR I IN 3 DOWNTO 0 LOOP - reg_wp.error_buffer_full(I) <= reg_wp.error_buffer_full(I) OR wfp_error_buffer_full(I); - reg_wp.status_new_err(I) <= reg_wp.status_new_err(I) OR status_new_err(I); + reg_wp.error_buffer_full(I) <= reg_wp.error_buffer_full(I) OR wfp_error_buffer_full(I); + reg_wp.status_new_err(I) <= reg_wp.status_new_err(I) OR status_new_err(I); END LOOP all_status; paddr := "000000"; @@ -477,7 +477,7 @@ BEGIN -- beh prdata(2) <= reg_sp.config_ms_run; WHEN ADDR_LFR_SM_STATUS => - prdata(0) <= reg_sp.status_ready_matrix_f0_0; + prdata(0) <= reg_sp.status_ready_matrix_f0_0; prdata(1) <= reg_sp.status_ready_matrix_f0_1; prdata(2) <= reg_sp.status_ready_matrix_f1_0; prdata(3) <= reg_sp.status_ready_matrix_f1_1; @@ -508,8 +508,8 @@ BEGIN -- beh WHEN ADDR_LFR_SM_F2_1_TIME_COARSE => prdata <= reg_sp.time_matrix_f2_1(47 DOWNTO 16); WHEN ADDR_LFR_SM_F2_1_TIME_FINE => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f2_1(15 DOWNTO 0); WHEN ADDR_LFR_SM_LENGTH => prdata(25 DOWNTO 0) <= reg_sp.length_matrix; - --------------------------------------------------------------------- - WHEN ADDR_LFR_WP_DATASHAPING => + --------------------------------------------------------------------- + WHEN ADDR_LFR_WP_DATASHAPING => prdata(0) <= reg_wp.data_shaping_BW; prdata(1) <= reg_wp.data_shaping_SP0; prdata(2) <= reg_wp.data_shaping_SP1; @@ -525,60 +525,60 @@ BEGIN -- beh prdata(5) <= reg_wp.burst_f1; prdata(6) <= reg_wp.burst_f2; prdata(7) <= reg_wp.run; - WHEN ADDR_LFR_WP_F0_0_ADDR => prdata <= reg_wp.addr_buffer_f(32*1-1 DOWNTO 32*0);--0 - WHEN ADDR_LFR_WP_F0_1_ADDR => prdata <= reg_wp.addr_buffer_f(32*2-1 DOWNTO 32*1); - WHEN ADDR_LFR_WP_F1_0_ADDR => prdata <= reg_wp.addr_buffer_f(32*3-1 DOWNTO 32*2);--1 - WHEN ADDR_LFR_WP_F1_1_ADDR => prdata <= reg_wp.addr_buffer_f(32*4-1 DOWNTO 32*3); - WHEN ADDR_LFR_WP_F2_0_ADDR => prdata <= reg_wp.addr_buffer_f(32*5-1 DOWNTO 32*4);--2 - WHEN ADDR_LFR_WP_F2_1_ADDR => prdata <= reg_wp.addr_buffer_f(32*6-1 DOWNTO 32*5); - WHEN ADDR_LFR_WP_F3_0_ADDR => prdata <= reg_wp.addr_buffer_f(32*7-1 DOWNTO 32*6);--3 - WHEN ADDR_LFR_WP_F3_1_ADDR => prdata <= reg_wp.addr_buffer_f(32*8-1 DOWNTO 32*7); - + WHEN ADDR_LFR_WP_F0_0_ADDR => prdata <= reg_wp.addr_buffer_f(32*1-1 DOWNTO 32*0); --0 + WHEN ADDR_LFR_WP_F0_1_ADDR => prdata <= reg_wp.addr_buffer_f(32*2-1 DOWNTO 32*1); + WHEN ADDR_LFR_WP_F1_0_ADDR => prdata <= reg_wp.addr_buffer_f(32*3-1 DOWNTO 32*2); --1 + WHEN ADDR_LFR_WP_F1_1_ADDR => prdata <= reg_wp.addr_buffer_f(32*4-1 DOWNTO 32*3); + WHEN ADDR_LFR_WP_F2_0_ADDR => prdata <= reg_wp.addr_buffer_f(32*5-1 DOWNTO 32*4); --2 + WHEN ADDR_LFR_WP_F2_1_ADDR => prdata <= reg_wp.addr_buffer_f(32*6-1 DOWNTO 32*5); + WHEN ADDR_LFR_WP_F3_0_ADDR => prdata <= reg_wp.addr_buffer_f(32*7-1 DOWNTO 32*6); --3 + WHEN ADDR_LFR_WP_F3_1_ADDR => prdata <= reg_wp.addr_buffer_f(32*8-1 DOWNTO 32*7); + WHEN ADDR_LFR_WP_STATUS => - prdata(7 DOWNTO 0) <= reg_wp.status_ready_buffer_f; - prdata(11 DOWNTO 8) <= reg_wp.error_buffer_full; + prdata(7 DOWNTO 0) <= reg_wp.status_ready_buffer_f; + prdata(11 DOWNTO 8) <= reg_wp.error_buffer_full; prdata(15 DOWNTO 12) <= reg_wp.status_new_err; - WHEN ADDR_LFR_WP_DELTASNAPSHOT => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_snapshot; - WHEN ADDR_LFR_WP_DELTA_F0 => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f0; - WHEN ADDR_LFR_WP_DELTA_F0_2 => prdata(delta_vector_size_f0_2-1 DOWNTO 0) <= reg_wp.delta_f0_2; - WHEN ADDR_LFR_WP_DELTA_F1 => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f1; - WHEN ADDR_LFR_WP_DELTA_F2 => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f2; + WHEN ADDR_LFR_WP_DELTASNAPSHOT => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_snapshot; + WHEN ADDR_LFR_WP_DELTA_F0 => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f0; + WHEN ADDR_LFR_WP_DELTA_F0_2 => prdata(delta_vector_size_f0_2-1 DOWNTO 0) <= reg_wp.delta_f0_2; + WHEN ADDR_LFR_WP_DELTA_F1 => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f1; + WHEN ADDR_LFR_WP_DELTA_F2 => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f2; WHEN ADDR_LFR_WP_DATA_IN_BUFFER => prdata(nb_data_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_data_by_buffer; WHEN ADDR_LFR_WP_NBSNAPSHOT => prdata(nb_snapshot_param_size-1 DOWNTO 0) <= reg_wp.nb_snapshot_param; WHEN ADDR_LFR_WP_START_DATE => prdata(30 DOWNTO 0) <= reg_wp.start_date; - WHEN ADDR_LFR_WP_F0_0_TIME_COARSE => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*0 + 31 DOWNTO 48*0); + WHEN ADDR_LFR_WP_F0_0_TIME_COARSE => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*0 + 31 DOWNTO 48*0); WHEN ADDR_LFR_WP_F0_0_TIME_FINE => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*0 + 47 DOWNTO 48*0 + 32); WHEN ADDR_LFR_WP_F0_1_TIME_COARSE => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*1 + 31 DOWNTO 48*1); WHEN ADDR_LFR_WP_F0_1_TIME_FINE => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*1 + 47 DOWNTO 48*1 + 32); - + WHEN ADDR_LFR_WP_F1_0_TIME_COARSE => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*2 + 31 DOWNTO 48*2); WHEN ADDR_LFR_WP_F1_0_TIME_FINE => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*2 + 47 DOWNTO 48*2 + 32); WHEN ADDR_LFR_WP_F1_1_TIME_COARSE => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*3 + 31 DOWNTO 48*3); WHEN ADDR_LFR_WP_F1_1_TIME_FINE => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*3 + 47 DOWNTO 48*3 + 32); - + WHEN ADDR_LFR_WP_F2_0_TIME_COARSE => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*4 + 31 DOWNTO 48*4); WHEN ADDR_LFR_WP_F2_0_TIME_FINE => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*4 + 47 DOWNTO 48*4 + 32); WHEN ADDR_LFR_WP_F2_1_TIME_COARSE => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*5 + 31 DOWNTO 48*5); WHEN ADDR_LFR_WP_F2_1_TIME_FINE => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*5 + 47 DOWNTO 48*5 + 32); - + WHEN ADDR_LFR_WP_F3_0_TIME_COARSE => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*6 + 31 DOWNTO 48*6); WHEN ADDR_LFR_WP_F3_0_TIME_FINE => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*6 + 47 DOWNTO 48*6 + 32); WHEN ADDR_LFR_WP_F3_1_TIME_COARSE => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*7 + 31 DOWNTO 48*7); WHEN ADDR_LFR_WP_F3_1_TIME_FINE => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*7 + 47 DOWNTO 48*7 + 32); WHEN ADDR_LFR_WP_LENGTH => prdata(25 DOWNTO 0) <= reg_wp.length_buffer; - - WHEN ADDR_LFR_WP_F3_V => prdata(15 DOWNTO 0) <= sample_f3_v_reg; - prdata(31 DOWNTO 16) <= (OTHERS => '0'); - WHEN ADDR_LFR_WP_F3_E1 => prdata(15 DOWNTO 0) <= sample_f3_e1_reg; - prdata(31 DOWNTO 16) <= (OTHERS => '0'); - WHEN ADDR_LFR_WP_F3_E2 => prdata(15 DOWNTO 0) <= sample_f3_e2_reg; - prdata(31 DOWNTO 16) <= (OTHERS => '0'); - --------------------------------------------------------------------- - WHEN ADDR_LFR_VERSION => prdata(23 DOWNTO 0) <= top_lfr_version(23 DOWNTO 0); - WHEN OTHERS => NULL; + + WHEN ADDR_LFR_WP_F3_V => prdata(15 DOWNTO 0) <= sample_f3_v_reg; + prdata(31 DOWNTO 16) <= (OTHERS => '0'); + WHEN ADDR_LFR_WP_F3_E1 => prdata(15 DOWNTO 0) <= sample_f3_e1_reg; + prdata(31 DOWNTO 16) <= (OTHERS => '0'); + WHEN ADDR_LFR_WP_F3_E2 => prdata(15 DOWNTO 0) <= sample_f3_e2_reg; + prdata(31 DOWNTO 16) <= (OTHERS => '0'); + --------------------------------------------------------------------- + WHEN ADDR_LFR_VERSION => prdata(23 DOWNTO 0) <= top_lfr_version(23 DOWNTO 0); + WHEN OTHERS => NULL; END CASE; IF (apbi.pwrite AND apbi.penable) = '1' THEN @@ -589,17 +589,17 @@ BEGIN -- beh reg_sp.config_active_interruption_onNewMatrix <= apbi.pwdata(0); reg_sp.config_active_interruption_onError <= apbi.pwdata(1); reg_sp.config_ms_run <= apbi.pwdata(2); - + WHEN ADDR_LFR_SM_STATUS => - reg_sp.status_ready_matrix_f0_0 <= ((NOT apbi.pwdata(0) ) AND reg_sp.status_ready_matrix_f0_0 ) OR reg0_ready_matrix_f0; - reg_sp.status_ready_matrix_f0_1 <= ((NOT apbi.pwdata(1) ) AND reg_sp.status_ready_matrix_f0_1 ) OR reg1_ready_matrix_f0; - reg_sp.status_ready_matrix_f1_0 <= ((NOT apbi.pwdata(2) ) AND reg_sp.status_ready_matrix_f1_0 ) OR reg0_ready_matrix_f1; - reg_sp.status_ready_matrix_f1_1 <= ((NOT apbi.pwdata(3) ) AND reg_sp.status_ready_matrix_f1_1 ) OR reg1_ready_matrix_f1; - reg_sp.status_ready_matrix_f2_0 <= ((NOT apbi.pwdata(4) ) AND reg_sp.status_ready_matrix_f2_0 ) OR reg0_ready_matrix_f2; - reg_sp.status_ready_matrix_f2_1 <= ((NOT apbi.pwdata(5) ) AND reg_sp.status_ready_matrix_f2_1 ) OR reg1_ready_matrix_f2; - reg_sp.status_error_buffer_full <= ((NOT apbi.pwdata(7) ) AND reg_sp.status_error_buffer_full ) OR error_buffer_full; - reg_sp.status_error_input_fifo_write(0) <= ((NOT apbi.pwdata(8) ) AND reg_sp.status_error_input_fifo_write(0)) OR error_input_fifo_write(0); - reg_sp.status_error_input_fifo_write(1) <= ((NOT apbi.pwdata(9) ) AND reg_sp.status_error_input_fifo_write(1)) OR error_input_fifo_write(1); + reg_sp.status_ready_matrix_f0_0 <= ((NOT apbi.pwdata(0)) AND reg_sp.status_ready_matrix_f0_0) OR reg0_ready_matrix_f0; + reg_sp.status_ready_matrix_f0_1 <= ((NOT apbi.pwdata(1)) AND reg_sp.status_ready_matrix_f0_1) OR reg1_ready_matrix_f0; + reg_sp.status_ready_matrix_f1_0 <= ((NOT apbi.pwdata(2)) AND reg_sp.status_ready_matrix_f1_0) OR reg0_ready_matrix_f1; + reg_sp.status_ready_matrix_f1_1 <= ((NOT apbi.pwdata(3)) AND reg_sp.status_ready_matrix_f1_1) OR reg1_ready_matrix_f1; + reg_sp.status_ready_matrix_f2_0 <= ((NOT apbi.pwdata(4)) AND reg_sp.status_ready_matrix_f2_0) OR reg0_ready_matrix_f2; + reg_sp.status_ready_matrix_f2_1 <= ((NOT apbi.pwdata(5)) AND reg_sp.status_ready_matrix_f2_1) OR reg1_ready_matrix_f2; + reg_sp.status_error_buffer_full <= ((NOT apbi.pwdata(7)) AND reg_sp.status_error_buffer_full) OR error_buffer_full; + reg_sp.status_error_input_fifo_write(0) <= ((NOT apbi.pwdata(8)) AND reg_sp.status_error_input_fifo_write(0)) OR error_input_fifo_write(0); + reg_sp.status_error_input_fifo_write(1) <= ((NOT apbi.pwdata(9)) AND reg_sp.status_error_input_fifo_write(1)) OR error_input_fifo_write(1); reg_sp.status_error_input_fifo_write(2) <= ((NOT apbi.pwdata(10)) AND reg_sp.status_error_input_fifo_write(2)) OR error_input_fifo_write(2); WHEN ADDR_LFR_SM_F0_0_ADDR => reg_sp.addr_matrix_f0_0 <= apbi.pwdata; WHEN ADDR_LFR_SM_F0_1_ADDR => reg_sp.addr_matrix_f0_1 <= apbi.pwdata; @@ -608,8 +608,8 @@ BEGIN -- beh WHEN ADDR_LFR_SM_F2_0_ADDR => reg_sp.addr_matrix_f2_0 <= apbi.pwdata; WHEN ADDR_LFR_SM_F2_1_ADDR => reg_sp.addr_matrix_f2_1 <= apbi.pwdata; - WHEN ADDR_LFR_SM_LENGTH => reg_sp.length_matrix <= apbi.pwdata(25 DOWNTO 0); - --------------------------------------------------------------------- + WHEN ADDR_LFR_SM_LENGTH => reg_sp.length_matrix <= apbi.pwdata(25 DOWNTO 0); + --------------------------------------------------------------------- WHEN ADDR_LFR_WP_DATASHAPING => reg_wp.data_shaping_BW <= apbi.pwdata(0); reg_wp.data_shaping_SP0 <= apbi.pwdata(1); @@ -617,7 +617,7 @@ BEGIN -- beh reg_wp.data_shaping_R0 <= apbi.pwdata(3); reg_wp.data_shaping_R1 <= apbi.pwdata(4); reg_wp.data_shaping_R2 <= apbi.pwdata(5); - WHEN ADDR_LFR_WP_CONTROL => + WHEN ADDR_LFR_WP_CONTROL => reg_wp.enable_f0 <= apbi.pwdata(0); reg_wp.enable_f1 <= apbi.pwdata(1); reg_wp.enable_f2 <= apbi.pwdata(2); @@ -634,12 +634,12 @@ BEGIN -- beh WHEN ADDR_LFR_WP_F2_1_ADDR => reg_wp.addr_buffer_f(32*6-1 DOWNTO 32*5) <= apbi.pwdata; WHEN ADDR_LFR_WP_F3_0_ADDR => reg_wp.addr_buffer_f(32*7-1 DOWNTO 32*6) <= apbi.pwdata; WHEN ADDR_LFR_WP_F3_1_ADDR => reg_wp.addr_buffer_f(32*8-1 DOWNTO 32*7) <= apbi.pwdata; - WHEN ADDR_LFR_WP_STATUS => - all_reg_wp_status_bit: FOR I IN 3 DOWNTO 0 LOOP - reg_wp.status_ready_buffer_f(I*2) <= ((NOT apbi.pwdata(I*2) ) AND reg_wp.status_ready_buffer_f(I*2) ) OR reg_ready_buffer_f(I*2); + WHEN ADDR_LFR_WP_STATUS => + all_reg_wp_status_bit : FOR I IN 3 DOWNTO 0 LOOP + reg_wp.status_ready_buffer_f(I*2) <= ((NOT apbi.pwdata(I*2)) AND reg_wp.status_ready_buffer_f(I*2)) OR reg_ready_buffer_f(I*2); reg_wp.status_ready_buffer_f(I*2+1) <= ((NOT apbi.pwdata(I*2+1)) AND reg_wp.status_ready_buffer_f(I*2+1)) OR reg_ready_buffer_f(I*2+1); - reg_wp.error_buffer_full(I) <= ((NOT apbi.pwdata(I+8) ) AND reg_wp.error_buffer_full(I) ) OR wfp_error_buffer_full(I); - reg_wp.status_new_err(I) <= ((NOT apbi.pwdata(I+12) ) AND reg_wp.status_new_err(I) ) OR status_new_err(I); + reg_wp.error_buffer_full(I) <= ((NOT apbi.pwdata(I+8)) AND reg_wp.error_buffer_full(I)) OR wfp_error_buffer_full(I); + reg_wp.status_new_err(I) <= ((NOT apbi.pwdata(I+12)) AND reg_wp.status_new_err(I)) OR status_new_err(I); END LOOP all_reg_wp_status_bit; WHEN ADDR_LFR_WP_DELTASNAPSHOT => reg_wp.delta_snapshot <= apbi.pwdata(delta_vector_size-1 DOWNTO 0); @@ -650,37 +650,37 @@ BEGIN -- beh WHEN ADDR_LFR_WP_DATA_IN_BUFFER => reg_wp.nb_data_by_buffer <= apbi.pwdata(nb_data_by_buffer_size-1 DOWNTO 0); WHEN ADDR_LFR_WP_NBSNAPSHOT => reg_wp.nb_snapshot_param <= apbi.pwdata(nb_snapshot_param_size-1 DOWNTO 0); WHEN ADDR_LFR_WP_START_DATE => reg_wp.start_date <= apbi.pwdata(30 DOWNTO 0); - - WHEN ADDR_LFR_WP_LENGTH => reg_wp.length_buffer <= apbi.pwdata(25 DOWNTO 0); - WHEN OTHERS => NULL; + WHEN ADDR_LFR_WP_LENGTH => reg_wp.length_buffer <= apbi.pwdata(25 DOWNTO 0); + + WHEN OTHERS => NULL; END CASE; END IF; END IF; --apbo.pirq(pirq_ms) <= - pirq_temp( pirq_ms) <= apbo_irq_ms; + pirq_temp(pirq_ms) <= apbo_irq_ms; pirq_temp(pirq_wfp) <= apbo_irq_wfp; apbo_irq_ms <= ((reg_sp.config_active_interruption_onNewMatrix AND (ready_matrix_f0 OR - ready_matrix_f1 OR - ready_matrix_f2) - ) - OR - (reg_sp.config_active_interruption_onError AND ( + ready_matrix_f1 OR + ready_matrix_f2) + ) + OR + (reg_sp.config_active_interruption_onError AND ( -- error_bad_component_error OR - error_buffer_full - OR error_input_fifo_write(0) - OR error_input_fifo_write(1) - OR error_input_fifo_write(2)) - )); + error_buffer_full + OR error_input_fifo_write(0) + OR error_input_fifo_write(1) + OR error_input_fifo_write(2)) + )); -- apbo.pirq(pirq_wfp) - apbo_irq_wfp<= ored_irq_wfp; + apbo_irq_wfp <= ored_irq_wfp; END IF; END PROCESS lpp_lfr_apbreg; apbo.pirq <= pirq_temp; - + --all_irq: FOR I IN 31 DOWNTO 0 GENERATE -- IRQ_is_PIRQ_MS: IF I = pirq_ms GENERATE -- apbo.pirq(I) <= apbo_irq_ms; @@ -691,11 +691,11 @@ BEGIN -- beh -- IRQ_OTHERS: IF I /= pirq_ms AND pirq_wfp /= pirq_wfp GENERATE -- apbo.pirq(I) <= '0'; -- END GENERATE IRQ_OTHERS; - + --END GENERATE all_irq; - + - + apbo.pindex <= pindex; apbo.pconfig <= pconfig; apbo.prdata <= prdata; @@ -731,8 +731,8 @@ BEGIN -- beh clk => HCLK, rstn => HRESETn, - run => '1',--reg_sp.config_ms_run, - + run => '1', --reg_sp.config_ms_run, + reg0_status_ready_matrix => reg_sp.status_ready_matrix_f0_0, reg0_ready_matrix => reg0_ready_matrix_f0, reg0_addr_matrix => reg_sp.addr_matrix_f0_0, --reg0_addr_matrix_f0, @@ -753,7 +753,7 @@ BEGIN -- beh clk => HCLK, rstn => HRESETn, - run => '1',--reg_sp.config_ms_run, + run => '1', --reg_sp.config_ms_run, reg0_status_ready_matrix => reg_sp.status_ready_matrix_f1_0, reg0_ready_matrix => reg0_ready_matrix_f1, @@ -775,7 +775,7 @@ BEGIN -- beh clk => HCLK, rstn => HRESETn, - run => '1',--reg_sp.config_ms_run, + run => '1', --reg_sp.config_ms_run, reg0_status_ready_matrix => reg_sp.status_ready_matrix_f2_0, reg0_ready_matrix => reg0_ready_matrix_f2, @@ -793,33 +793,33 @@ BEGIN -- beh matrix_time => matrix_time_f2); ----------------------------------------------------------------------------- - all_wfp_pointer: FOR I IN 3 DOWNTO 0 GENERATE + all_wfp_pointer : FOR I IN 3 DOWNTO 0 GENERATE lpp_apbreg_wfp_pointer_fi : lpp_apbreg_ms_pointer PORT MAP ( clk => HCLK, rstn => HRESETn, - run => '1',--reg_wp.run, + run => '1', --reg_wp.run, reg0_status_ready_matrix => reg_wp.status_ready_buffer_f(2*I), reg0_ready_matrix => reg_ready_buffer_f(2*I), reg0_addr_matrix => reg_wp.addr_buffer_f((2*I+1)*32-1 DOWNTO (2*I)*32), - reg0_matrix_time => reg_wp.time_buffer_f((2*I+1)*48-1 DOWNTO (2*I)*48), + reg0_matrix_time => reg_wp.time_buffer_f((2*I+1)*48-1 DOWNTO (2*I)*48), reg1_status_ready_matrix => reg_wp.status_ready_buffer_f(2*I+1), reg1_ready_matrix => reg_ready_buffer_f(2*I+1), reg1_addr_matrix => reg_wp.addr_buffer_f((2*I+2)*32-1 DOWNTO (2*I+1)*32), - reg1_matrix_time => reg_wp.time_buffer_f((2*I+2)*48-1 DOWNTO (2*I+1)*48), + reg1_matrix_time => reg_wp.time_buffer_f((2*I+2)*48-1 DOWNTO (2*I+1)*48), ready_matrix => wfp_ready_buffer(I), status_ready_matrix => wfp_status_buffer_ready(I), addr_matrix => wfp_addr_buffer((I+1)*32-1 DOWNTO I*32), matrix_time => wfp_buffer_time((I+1)*48-1 DOWNTO I*48) ); - - END GENERATE all_wfp_pointer; + + END GENERATE all_wfp_pointer; ----------------------------------------------------------------------------- - + END beh; ------------------------------------------------------------------------------