HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib Commit - r547:4e22970f1b7e

minor update (cleaning file)

pellion -

r547:4e22970f1b7e JC

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r547:4e22970f1b7e

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lib/lpp/general_purpose/general_counter.vhd +7 -7

             LIBRARY IEEE;
             USE IEEE.STD_LOGIC_1164.ALL;
-            USE IEEE.std_logic_arith.ALL;
+            USE IEEE.NUMERIC_STD.ALL;
-            USE IEEE.std_logic_unsigned.ALL;
             ENTITY general_counter IS
               GENERIC (
                 CYCLIC          : STD_LOGIC := '1';
-                NB_BITS_COUNTER : INTEGER   := 9
+                NB_BITS_COUNTER : INTEGER   := 9;
+                RST_VALUE       : INTEGER   := 0
                 );
               PORT (
                 clk       : IN  STD_LOGIC;
                 rstn      : IN  STD_LOGIC;
                 --
-                RST_VALUE  : IN STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0) := (OTHERS => '0');
                 MAX_VALUE : IN  STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0) := (OTHERS => '1');
                 --
                 set       : IN  STD_LOGIC;
             END general_counter;
             ARCHITECTURE beh OF general_counter IS
+              CONSTANT RST_VALUE_v : STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0) := STD_LOGIC_VECTOR(to_unsigned(RST_VALUE, NB_BITS_COUNTER));
               SIGNAL   counter_s   : STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0);
             BEGIN  -- beh
               PROCESS (clk, rstn)
               BEGIN  -- PROCESS
                 IF rstn = '0' THEN                  -- asynchronous reset (active low)
-                  counter_s <= RST_VALUE;
+                  counter_s <= RST_VALUE_v;
-                ELSIF clk'event AND clk = '1' THEN  -- rising clock edge
+                ELSIF clk'EVENT AND clk = '1' THEN  -- rising clock edge
                   IF set = '1' THEN
                     counter_s <= set_value;
                   ELSIF add1 = '1' THEN
                     IF counter_s < MAX_VALUE THEN
-                      counter_s <= counter_s + 1;
+                      counter_s <= STD_LOGIC_VECTOR((UNSIGNED(counter_s) + 1));
                     ELSE
                       IF CYCLIC = '1' THEN
                         counter_s <= (OTHERS => '0');

lib/lpp/general_purpose/general_purpose.vhd +2 -2

               COMPONENT general_counter
                 GENERIC (
                   CYCLIC          : STD_LOGIC;
-                  NB_BITS_COUNTER : INTEGER);
+                  NB_BITS_COUNTER : INTEGER;
+                  RST_VALUE       : INTEGER);
                 PORT (
                   clk       : IN  STD_LOGIC;
                   rstn      : IN  STD_LOGIC;
-                  RST_VALUE : IN STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0);
                   MAX_VALUE : IN  STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0);
                   set       : IN  STD_LOGIC;
                   set_value : IN  STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0);

lib/lpp/lfr_management/coarse_time_counter.vhd +6 -5

               counter_1 : general_counter
                 GENERIC MAP (
                   CYCLIC => '1',
-                  NB_BITS_COUNTER => 31)
+                  NB_BITS_COUNTER => 31,
+                  RST_VALUE => 0)
                 PORT MAP (
                   clk       => clk,
                   rstn      => rstn,
-                  RST_VALUE => (OTHERS => '0'),
                   MAX_VALUE => "111" & X"FFFFFFF" ,
                   set       => set_TCU,
                   set_value => set_TCU_value(30 DOWNTO 0),
               counter_2 : general_counter
                 GENERIC MAP (
                   CYCLIC          => '0',
-                  NB_BITS_COUNTER => 6)
+                  NB_BITS_COUNTER => 6,
+                  RST_VALUE       => NB_SECOND_DESYNC
+                  )
                 PORT MAP (
                   clk       => clk,
                   rstn      => rstn,
-                  RST_VALUE => STD_LOGIC_VECTOR(to_unsigned(NB_SECOND_DESYNC, 6)),
                   MAX_VALUE => STD_LOGIC_VECTOR(to_unsigned(NB_SECOND_DESYNC, 6)),
                   set       => set_synchronized,
                   set_value => set_synchronized_value,
                 END IF;
               END PROCESS;
-            END beh;
+            END beh;
  No newline at end of file

lib/lpp/lfr_management/fine_time_counter.vhd +6 -5

               counter_1 : general_counter
                 GENERIC MAP (
                   CYCLIC          => '1',
-                  NB_BITS_COUNTER => 9)
+                  NB_BITS_COUNTER => 9,
+                  RST_VALUE       => 0
+                  )
                 PORT MAP (
                   clk       => clk,
                   rstn      => rstn,
-                  RST_VALUE => (OTHERS => '0'),
                   MAX_VALUE => STD_LOGIC_VECTOR(to_unsigned(FIRST_DIVISION, 9)),
                   set       => tick,
                   set_value => (OTHERS => '0'),
               counter_2 : general_counter
                 GENERIC MAP (
                   CYCLIC          => '1',
-                  NB_BITS_COUNTER => 16)
+                  NB_BITS_COUNTER => 16,
+                  RST_VALUE       => 0
+                  )
                 PORT MAP (
                   clk       => clk,
                   rstn      => rstn,
-                  RST_VALUE => (OTHERS => '0'),
                   MAX_VALUE => X"FFFF",
                   set       => tick,
                   set_value => (OTHERS => '0'),
               END PROCESS;
             END beh;

lib/lpp/lpp_cna/RAM_READER.vhd +2 -2

             architecture Behavioral of RAM_READER is
             CONSTANT interleaved_sz   : integer := dacresolution/(datawidth-dacresolution);
-            signal ADDRESS_R             :  STD_LOGIC_VECTOR (abits-1 downto 0):=(others=>'0');
+            signal ADDRESS_R             :  STD_LOGIC_VECTOR (abits-1 downto 0);--:=(others=>'0');
             signal SAMPLE_R              :  STD_LOGIC_VECTOR (dacresolution-1 downto 0):=(others=>'0');
             signal INTERLEAVED_SAMPLE_R  :  STD_LOGIC_VECTOR (dacresolution-1 downto 0):=(others=>'0');
             signal SMP_CLK_R             :  STD_LOGIC;
                 end if;
             end process;
-            end Behavioral;
+            end Behavioral;
  No newline at end of file

lib/lpp/lpp_cna/SPI_DAC_DRIVER.vhd 0 -4

               SIGNAL SMP_CLK_R  : STD_LOGIC                              := '0';
               SIGNAL shiftcnt   : INTEGER                                := 0;
               SIGNAL shifting   : STD_LOGIC                              := '0';
-              SIGNAL shifting_R : STD_LOGIC                              := '0';
             BEGIN
               PROCESS(clk, rstn)
               BEGIN
                 IF rstn = '0' THEN
-            --      shifting_R <= '0';
                   SMP_CLK_R <= '0';
                 ELSIF clk'EVENT AND clk = '1' THEN
                   SMP_CLK_R <= SMP_CLK;
-            --      shifting_R <= shifting;
                 END IF;
               END PROCESS;
             END ARCHITECTURE behav;

lib/lpp/lpp_cna/dynamic_freq_div.vhd +2 -2

             constant prescaller_reg_sz : integer := 2**PRESZ;
             constant PREMAX_max        : STD_LOGIC_VECTOR(PRESZ-1 downto 0):=(others => '1');
             signal cpt_reg             : std_logic_vector(CPTSZ-1 downto 0):=(others => '0');
-            signal prescaller_reg      : std_logic_vector(prescaller_reg_sz-1 downto 0):=(others => '0');
+            signal prescaller_reg      : std_logic_vector(prescaller_reg_sz-1 downto 0);--:=(others => '0');
             signal internal_clk        : std_logic:='0';
             signal internal_clk_reg    : std_logic:='0';
             signal clk_out_reg         : std_logic:='0';
             end if;
             end process;
-            end Behavioral;
+            end Behavioral;
  No newline at end of file

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