diff --git a/lib/lpp/general_purpose/general_counter.vhd b/lib/lpp/general_purpose/general_counter.vhd --- a/lib/lpp/general_purpose/general_counter.vhd +++ b/lib/lpp/general_purpose/general_counter.vhd @@ -1,21 +1,20 @@ LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; -USE IEEE.std_logic_arith.ALL; -USE IEEE.std_logic_unsigned.ALL; +USE IEEE.NUMERIC_STD.ALL; ENTITY general_counter IS GENERIC ( CYCLIC : STD_LOGIC := '1'; - NB_BITS_COUNTER : INTEGER := 9 + NB_BITS_COUNTER : INTEGER := 9; + RST_VALUE : INTEGER := 0 ); PORT ( clk : IN STD_LOGIC; rstn : IN STD_LOGIC; -- - RST_VALUE : IN STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0) := (OTHERS => '0'); - MAX_VALUE : IN STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0) := (OTHERS => '1'); + MAX_VALUE : IN STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0) := (OTHERS => '1'); -- set : IN STD_LOGIC; set_value : IN STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0); @@ -26,20 +25,21 @@ ENTITY general_counter IS END general_counter; ARCHITECTURE beh OF general_counter IS - SIGNAL counter_s : STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0); + CONSTANT RST_VALUE_v : STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0) := STD_LOGIC_VECTOR(to_unsigned(RST_VALUE, NB_BITS_COUNTER)); + SIGNAL counter_s : STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0); BEGIN -- beh PROCESS (clk, rstn) BEGIN -- PROCESS - IF rstn = '0' THEN -- asynchronous reset (active low) - counter_s <= RST_VALUE; - ELSIF clk'event AND clk = '1' THEN -- rising clock edge + IF rstn = '0' THEN -- asynchronous reset (active low) + counter_s <= RST_VALUE_v; + ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge IF set = '1' THEN counter_s <= set_value; ELSIF add1 = '1' THEN IF counter_s < MAX_VALUE THEN - counter_s <= counter_s + 1; + counter_s <= STD_LOGIC_VECTOR((UNSIGNED(counter_s) + 1)); ELSE IF CYCLIC = '1' THEN counter_s <= (OTHERS => '0'); @@ -50,5 +50,5 @@ BEGIN -- beh END PROCESS; counter <= counter_s; - + END beh; diff --git a/lib/lpp/general_purpose/general_purpose.vhd b/lib/lpp/general_purpose/general_purpose.vhd --- a/lib/lpp/general_purpose/general_purpose.vhd +++ b/lib/lpp/general_purpose/general_purpose.vhd @@ -32,16 +32,16 @@ USE IEEE.NUMERIC_STD.ALL; PACKAGE general_purpose IS - + COMPONENT general_counter GENERIC ( CYCLIC : STD_LOGIC; - NB_BITS_COUNTER : INTEGER); + NB_BITS_COUNTER : INTEGER; + RST_VALUE : INTEGER); PORT ( clk : IN STD_LOGIC; rstn : IN STD_LOGIC; - RST_VALUE : IN STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0); - MAX_VALUE : IN STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0); + MAX_VALUE : IN STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0); set : IN STD_LOGIC; set_value : IN STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0); add1 : IN STD_LOGIC; diff --git a/lib/lpp/lfr_management/coarse_time_counter.vhd b/lib/lpp/lfr_management/coarse_time_counter.vhd --- a/lib/lpp/lfr_management/coarse_time_counter.vhd +++ b/lib/lpp/lfr_management/coarse_time_counter.vhd @@ -48,11 +48,11 @@ BEGIN -- beh counter_1 : general_counter GENERIC MAP ( CYCLIC => '1', - NB_BITS_COUNTER => 31) + NB_BITS_COUNTER => 31, + RST_VALUE => 0) PORT MAP ( clk => clk, rstn => rstn, - RST_VALUE => (OTHERS => '0'), MAX_VALUE => "111" & X"FFFFFFF" , set => set_TCU, set_value => set_TCU_value(30 DOWNTO 0), @@ -75,11 +75,12 @@ BEGIN -- beh counter_2 : general_counter GENERIC MAP ( CYCLIC => '0', - NB_BITS_COUNTER => 6) + NB_BITS_COUNTER => 6, + RST_VALUE => NB_SECOND_DESYNC + ) PORT MAP ( clk => clk, rstn => rstn, - RST_VALUE => STD_LOGIC_VECTOR(to_unsigned(NB_SECOND_DESYNC, 6)), MAX_VALUE => STD_LOGIC_VECTOR(to_unsigned(NB_SECOND_DESYNC, 6)), set => set_synchronized, set_value => set_synchronized_value, @@ -105,4 +106,4 @@ BEGIN -- beh END IF; END PROCESS; -END beh; +END beh; \ No newline at end of file diff --git a/lib/lpp/lfr_management/fine_time_counter.vhd b/lib/lpp/lfr_management/fine_time_counter.vhd --- a/lib/lpp/lfr_management/fine_time_counter.vhd +++ b/lib/lpp/lfr_management/fine_time_counter.vhd @@ -43,11 +43,12 @@ BEGIN -- beh counter_1 : general_counter GENERIC MAP ( CYCLIC => '1', - NB_BITS_COUNTER => 9) + NB_BITS_COUNTER => 9, + RST_VALUE => 0 + ) PORT MAP ( clk => clk, rstn => rstn, - RST_VALUE => (OTHERS => '0'), MAX_VALUE => STD_LOGIC_VECTOR(to_unsigned(FIRST_DIVISION, 9)), set => tick, set_value => (OTHERS => '0'), @@ -59,11 +60,12 @@ BEGIN -- beh counter_2 : general_counter GENERIC MAP ( CYCLIC => '1', - NB_BITS_COUNTER => 16) + NB_BITS_COUNTER => 16, + RST_VALUE => 0 + ) PORT MAP ( clk => clk, rstn => rstn, - RST_VALUE => (OTHERS => '0'), MAX_VALUE => X"FFFF", set => tick, set_value => (OTHERS => '0'), @@ -90,4 +92,3 @@ BEGIN -- beh END PROCESS; END beh; - diff --git a/lib/lpp/lpp_cna/RAM_READER.vhd b/lib/lpp/lpp_cna/RAM_READER.vhd --- a/lib/lpp/lpp_cna/RAM_READER.vhd +++ b/lib/lpp/lpp_cna/RAM_READER.vhd @@ -44,7 +44,7 @@ end RAM_READER; architecture Behavioral of RAM_READER is CONSTANT interleaved_sz : integer := dacresolution/(datawidth-dacresolution); -signal ADDRESS_R : STD_LOGIC_VECTOR (abits-1 downto 0):=(others=>'0'); +signal ADDRESS_R : STD_LOGIC_VECTOR (abits-1 downto 0);--:=(others=>'0'); signal SAMPLE_R : STD_LOGIC_VECTOR (dacresolution-1 downto 0):=(others=>'0'); signal INTERLEAVED_SAMPLE_R : STD_LOGIC_VECTOR (dacresolution-1 downto 0):=(others=>'0'); signal SMP_CLK_R : STD_LOGIC; @@ -114,4 +114,4 @@ begin end if; end process; -end Behavioral; +end Behavioral; \ No newline at end of file diff --git a/lib/lpp/lpp_cna/SPI_DAC_DRIVER.vhd b/lib/lpp/lpp_cna/SPI_DAC_DRIVER.vhd --- a/lib/lpp/lpp_cna/SPI_DAC_DRIVER.vhd +++ b/lib/lpp/lpp_cna/SPI_DAC_DRIVER.vhd @@ -47,7 +47,6 @@ ARCHITECTURE behav OF SPI_DAC_DRIVER IS SIGNAL SMP_CLK_R : STD_LOGIC := '0'; SIGNAL shiftcnt : INTEGER := 0; SIGNAL shifting : STD_LOGIC := '0'; - SIGNAL shifting_R : STD_LOGIC := '0'; BEGIN @@ -64,11 +63,9 @@ BEGIN PROCESS(clk, rstn) BEGIN IF rstn = '0' THEN --- shifting_R <= '0'; SMP_CLK_R <= '0'; ELSIF clk'EVENT AND clk = '1' THEN SMP_CLK_R <= SMP_CLK; --- shifting_R <= shifting; END IF; END PROCESS; @@ -104,4 +101,3 @@ BEGIN END ARCHITECTURE behav; - diff --git a/lib/lpp/lpp_cna/dynamic_freq_div.vhd b/lib/lpp/lpp_cna/dynamic_freq_div.vhd --- a/lib/lpp/lpp_cna/dynamic_freq_div.vhd +++ b/lib/lpp/lpp_cna/dynamic_freq_div.vhd @@ -43,7 +43,7 @@ architecture Behavioral of dynamic_freq_ constant prescaller_reg_sz : integer := 2**PRESZ; constant PREMAX_max : STD_LOGIC_VECTOR(PRESZ-1 downto 0):=(others => '1'); signal cpt_reg : std_logic_vector(CPTSZ-1 downto 0):=(others => '0'); -signal prescaller_reg : std_logic_vector(prescaller_reg_sz-1 downto 0):=(others => '0'); +signal prescaller_reg : std_logic_vector(prescaller_reg_sz-1 downto 0);--:=(others => '0'); signal internal_clk : std_logic:='0'; signal internal_clk_reg : std_logic:='0'; signal clk_out_reg : std_logic:='0'; @@ -96,4 +96,4 @@ elsif clk'event and clk = '1' then end if; end process; -end Behavioral; +end Behavioral; \ No newline at end of file