HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib Commit - r547:4e22970f1b7e

minor update (cleaning file)

pellion -

r547:4e22970f1b7e JC

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r547:4e22970f1b7e

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lib/lpp/general_purpose/general_counter.vhd +11 -11

             LIBRARY IEEE;
             USE IEEE.STD_LOGIC_1164.ALL;
-            USE IEEE.std_logic_arith.ALL;
+            USE IEEE.NUMERIC_STD.ALL;
-            USE IEEE.std_logic_unsigned.ALL;
             ENTITY general_counter IS
               GENERIC (
                 CYCLIC          : STD_LOGIC := '1';
-                NB_BITS_COUNTER : INTEGER   := 9
+                NB_BITS_COUNTER : INTEGER   := 9;
+                RST_VALUE       : INTEGER   := 0
                 );
               PORT (
                 clk       : IN  STD_LOGIC;
                 rstn      : IN  STD_LOGIC;
                 --
-                RST_VALUE  : IN STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0) := (OTHERS => '0');
+                MAX_VALUE : IN  STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0) := (OTHERS => '1');
-                MAX_VALUE  : IN STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0) := (OTHERS => '1');
                 --
                 set       : IN  STD_LOGIC;
                 set_value : IN  STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0);
                 add1      : IN  STD_LOGIC;
                 counter   : OUT STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0)
                 );
             END general_counter;
             ARCHITECTURE beh OF general_counter IS
-              SIGNAL counter_s : STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0);
+              CONSTANT RST_VALUE_v : STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0) := STD_LOGIC_VECTOR(to_unsigned(RST_VALUE, NB_BITS_COUNTER));
+              SIGNAL   counter_s   : STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0);
             BEGIN  -- beh
               PROCESS (clk, rstn)
               BEGIN  -- PROCESS
-                IF rstn = '0' THEN  -- asynchronous reset (active low)
+                IF rstn = '0' THEN                  -- asynchronous reset (active low)
-                  counter_s <= RST_VALUE;
+                  counter_s <= RST_VALUE_v;
-                ELSIF clk'event AND clk = '1' THEN  -- rising clock edge
+                ELSIF clk'EVENT AND clk = '1' THEN  -- rising clock edge
                   IF set = '1' THEN
                     counter_s <= set_value;
                   ELSIF add1 = '1' THEN
                     IF counter_s < MAX_VALUE THEN
-                      counter_s <= counter_s + 1;
+                      counter_s <= STD_LOGIC_VECTOR((UNSIGNED(counter_s) + 1));
                     ELSE
                       IF CYCLIC = '1' THEN
                         counter_s <= (OTHERS => '0');
                       END IF;
                     END IF;
                   END IF;
                 END IF;
               END PROCESS;
               counter <= counter_s;
             END beh;

lib/lpp/general_purpose/general_purpose.vhd +4 -4

             ------------------------------------------------------------------------------
             --  This file is a part of the LPP VHDL IP LIBRARY
             --  Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
             --
             --  This program is free software; you can redistribute it and/or modify
             --  it under the terms of the GNU General Public License as published by
             --  the Free Software Foundation; either version 3 of the License, or
             --  (at your option) any later version.
             --
             --  This program is distributed in the hope that it will be useful,
             --  but WITHOUT ANY WARRANTY; without even the implied warranty of
             --  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
             --  GNU General Public License for more details.
             --
             --  You should have received a copy of the GNU General Public License
             --  along with this program; if not, write to the Free Software
             --  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
             -------------------------------------------------------------------------------
             --                    Author : Alexis Jeandet
             --                     Mail : alexis.jeandet@lpp.polytechnique.fr
             ----------------------------------------------------------------------------
             --UPDATE
             -------------------------------------------------------------------------------
             -- 14-03-2013 - Jean-christophe Pellion
             -- ADD MUXN (a parametric multiplexor (N stage of MUX2))
             -------------------------------------------------------------------------------
             LIBRARY ieee;
             USE ieee.std_logic_1164.ALL;
             USE IEEE.NUMERIC_STD.ALL;
             PACKAGE general_purpose IS
               COMPONENT general_counter
                 GENERIC (
                   CYCLIC          : STD_LOGIC;
-                  NB_BITS_COUNTER : INTEGER);
+                  NB_BITS_COUNTER : INTEGER;
+                  RST_VALUE       : INTEGER);
                 PORT (
                   clk       : IN  STD_LOGIC;
                   rstn      : IN  STD_LOGIC;
-                  RST_VALUE : IN STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0);
+                  MAX_VALUE : IN  STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0);
-                  MAX_VALUE : IN STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0);
                   set       : IN  STD_LOGIC;
                   set_value : IN  STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0);
                   add1      : IN  STD_LOGIC;
                   counter   : OUT STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0));
               END COMPONENT;
               COMPONENT Clk_divider IS
                 GENERIC(OSC_freqHz    : INTEGER := 50000000;
                         TargetFreq_Hz : INTEGER := 50000);
                 PORT (clk          : IN  STD_LOGIC;
                        reset       : IN  STD_LOGIC;
                        clk_divided : OUT STD_LOGIC);
               END COMPONENT;
               COMPONENT Clk_divider2 IS
                 generic(N : integer := 16);
                 port(
                 clk_in  :   in  std_logic;
                 clk_out :   out std_logic);
               END COMPONENT;
               COMPONENT Adder IS
                 GENERIC(
                   Input_SZ_A : INTEGER := 16;
                   Input_SZ_B : INTEGER := 16
                   );
                 PORT(
                   clk   : IN  STD_LOGIC;
                   reset : IN  STD_LOGIC;
                   clr   : IN  STD_LOGIC;
                   load  : IN STD_LOGIC;
                   add   : IN  STD_LOGIC;
                   OP1   : IN  STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
                   OP2   : IN  STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
                   RES   : OUT STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0)
                   );
               END COMPONENT;
             COMPONENT Adder_V0 is
             generic(
                 Input_SZ_A     :   integer := 16;
                 Input_SZ_B     :   integer := 16
             );
             port(
                 clk     :   in  std_logic;
                 reset   :   in  std_logic;
                 clr     :   in  std_logic;
                 add     :   in  std_logic;
                 OP1     :   in  std_logic_vector(Input_SZ_A-1 downto 0);
                 OP2     :   in  std_logic_vector(Input_SZ_B-1 downto 0);
                 RES     :   out std_logic_vector(Input_SZ_A-1 downto 0)
             );
             end COMPONENT;
               COMPONENT ADDRcntr IS
                 PORT(
                   clk   : IN  STD_LOGIC;
                   reset : IN  STD_LOGIC;
                   count : IN  STD_LOGIC;
                   clr   : IN  STD_LOGIC;
                   Q     : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
                   );
               END COMPONENT;
               COMPONENT ALU IS
                 GENERIC(
                   Arith_en   : INTEGER := 1;
                   Logic_en   : INTEGER := 1;
                   Input_SZ_1 : INTEGER := 16;
                   Input_SZ_2 : INTEGER := 9;
                   COMP_EN    : INTEGER := 0 -- 1 =>  No Comp
                   );
                 PORT(
                   clk   : IN  STD_LOGIC;
                   reset : IN  STD_LOGIC;
                   ctrl  : IN  STD_LOGIC_VECTOR(2 downto 0);
                   comp  : IN  STD_LOGIC_VECTOR(1 downto 0);
                   OP1   : IN  STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0);
                   OP2   : IN  STD_LOGIC_VECTOR(Input_SZ_2-1 DOWNTO 0);
                   RES   : OUT STD_LOGIC_VECTOR(Input_SZ_1+Input_SZ_2-1 DOWNTO 0)
                   );
               END COMPONENT;
             COMPONENT ALU_V0 IS
               GENERIC(
                 Arith_en   : INTEGER := 1;
                 Logic_en   : INTEGER := 1;
                 Input_SZ_1 : INTEGER := 16;
                 Input_SZ_2 : INTEGER := 9
                 );
               PORT(
                 clk   : IN  STD_LOGIC;
                 reset : IN  STD_LOGIC;
                 ctrl  : IN  STD_LOGIC_VECTOR(3 DOWNTO 0);
                 OP1   : IN  STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0);
                 OP2   : IN  STD_LOGIC_VECTOR(Input_SZ_2-1 DOWNTO 0);
                 RES   : OUT STD_LOGIC_VECTOR(Input_SZ_1+Input_SZ_2-1 DOWNTO 0)
                 );
             END COMPONENT;
             COMPONENT MAC_V0 is
             generic(
                 Input_SZ_A     :   integer := 8;
                 Input_SZ_B     :   integer := 8
             );
             port(
                 clk     :   in  std_logic;
                 reset   :   in  std_logic;
                 clr_MAC :   in  std_logic;
                 MAC_MUL_ADD :   in  std_logic_vector(1 downto 0);
                 OP1     :   in  std_logic_vector(Input_SZ_A-1 downto 0);
                 OP2     :   in  std_logic_vector(Input_SZ_B-1 downto 0);
                 RES     :   out std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0)
             );
             end COMPONENT;
             ---------------------------------------------------------
             -------- // Sélection grace a l'entrée "ctrl" \\ --------
             ---------------------------------------------------------
             Constant ctrl_IDLE   : std_logic_vector(2 downto 0) := "000";
             Constant ctrl_MAC    : std_logic_vector(2 downto 0) := "001";
             Constant ctrl_MULT   : std_logic_vector(2 downto 0) := "010";
             Constant ctrl_ADD    : std_logic_vector(2 downto 0) := "011";
             Constant ctrl_CLRMAC : std_logic_vector(2 downto 0) := "100";
             Constant IDLE_V0    : std_logic_vector(3 downto 0) := "0000";
             Constant MAC_op_V0  : std_logic_vector(3 downto 0) := "0001";
             Constant MULT_V0    : std_logic_vector(3 downto 0) := "0010";
             Constant ADD_V0     : std_logic_vector(3 downto 0) := "0011";
             Constant CLR_MAC_V0 : std_logic_vector(3 downto 0) := "0100";
             ---------------------------------------------------------
               COMPONENT MAC IS
                 GENERIC(
                   Input_SZ_A : INTEGER := 8;
                   Input_SZ_B : INTEGER := 8;
                   COMP_EN    : INTEGER := 0 -- 1 =>  No Comp
                   );
                 PORT(
                   clk         : IN  STD_LOGIC;
                   reset       : IN  STD_LOGIC;
                   clr_MAC     : IN  STD_LOGIC;
                   MAC_MUL_ADD : IN  STD_LOGIC_VECTOR(1 DOWNTO 0);
                   Comp_2C     : IN  STD_LOGIC_VECTOR(1 DOWNTO 0);
                   OP1         : IN  STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
                   OP2         : IN  STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
                   RES         : OUT STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0)
                   );
               END COMPONENT;
               COMPONENT TwoComplementer is
               generic(
                   Input_SZ : integer := 16);
               port(
                   clk     : in  std_logic;                                --! Horloge du composant
                   reset   : in  std_logic;                                --! Reset general du composant
                   clr     : in  std_logic;                                --! Un reset spécifique au programme
                   TwoComp : in  std_logic;                                --! Autorise l'utilisation du complément
                   OP      : in  std_logic_vector(Input_SZ-1 downto 0);    --! Opérande d'entrée
                   RES     : out std_logic_vector(Input_SZ-1 downto 0)     --! Résultat, opérande complémenté ou non
               );
               end COMPONENT;
               COMPONENT MAC_CONTROLER IS
                 PORT(
                   ctrl        : IN  STD_LOGIC_VECTOR(1 DOWNTO 0);
                   MULT        : OUT STD_LOGIC;
                   ADD         : OUT STD_LOGIC;
             --      LOAD_ADDER  : out std_logic;
                   MACMUX_sel  : OUT STD_LOGIC;
                   MACMUX2_sel : OUT STD_LOGIC
                   );
               END COMPONENT;
               COMPONENT MAC_MUX IS
                 GENERIC(
                   Input_SZ_A : INTEGER := 16;
                   Input_SZ_B : INTEGER := 16
                   );
                 PORT(
                   sel  : IN  STD_LOGIC;
                   INA1 : IN  STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
                   INA2 : IN  STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
                   INB1 : IN  STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
                   INB2 : IN  STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
                   OUTA : OUT STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
                   OUTB : OUT STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0)
                   );
               END COMPONENT;
               COMPONENT MAC_MUX2 IS
                 GENERIC(Input_SZ : INTEGER := 16);
                 PORT(
                   sel  : IN  STD_LOGIC;
                   RES1 : IN  STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0);
                   RES2 : IN  STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0);
                   RES  : OUT STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0)
                   );
               END COMPONENT;
               COMPONENT MAC_REG IS
                 GENERIC(size : INTEGER := 16);
                 PORT(
                   reset : IN  STD_LOGIC;
                   clk   : IN  STD_LOGIC;
                   D     : IN  STD_LOGIC_VECTOR(size-1 DOWNTO 0);
                   Q     : OUT STD_LOGIC_VECTOR(size-1 DOWNTO 0)
                   );
               END COMPONENT;
               COMPONENT MUX2 IS
                 GENERIC(Input_SZ : INTEGER := 16);
                 PORT(
                   sel : IN  STD_LOGIC;
                   IN1 : IN  STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0);
                   IN2 : IN  STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0);
                   RES : OUT STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0)
                   );
               END COMPONENT;
               TYPE MUX_INPUT_TYPE IS ARRAY (NATURAL RANGE <>, NATURAL RANGE <>) OF STD_LOGIC;
               TYPE MUX_OUTPUT_TYPE IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC;
               COMPONENT MUXN
                 GENERIC (
                   Input_SZ : INTEGER;
                   NbStage  : INTEGER);
                 PORT (
                   sel   : IN  STD_LOGIC_VECTOR(NbStage-1 DOWNTO 0);
                   INPUT : IN  MUX_INPUT_TYPE(0 TO (2**NbStage)-1,Input_SZ-1 DOWNTO 0);
                   --INPUT : IN  ARRAY (0 TO (2**NbStage)-1) OF STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0);
                   RES   : OUT MUX_OUTPUT_TYPE(Input_SZ-1 DOWNTO 0));
               END COMPONENT;
               COMPONENT Multiplier IS
                 GENERIC(
                   Input_SZ_A : INTEGER := 16;
                   Input_SZ_B : INTEGER := 16
                   );
                 PORT(
                   clk   : IN  STD_LOGIC;
                   reset : IN  STD_LOGIC;
                   mult  : IN  STD_LOGIC;
                   OP1   : IN  STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
                   OP2   : IN  STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
                   RES   : OUT STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0)
                   );
               END COMPONENT;
               COMPONENT REG IS
                 GENERIC(size : INTEGER := 16; initial_VALUE : INTEGER := 0);
                 PORT(
                   reset : IN  STD_LOGIC;
                   clk   : IN  STD_LOGIC;
                   D     : IN  STD_LOGIC_VECTOR(size-1 DOWNTO 0);
                   Q     : OUT STD_LOGIC_VECTOR(size-1 DOWNTO 0)
                   );
               END COMPONENT;
               COMPONENT RShifter IS
                 GENERIC(
                   Input_SZ : INTEGER := 16;
                   shift_SZ : INTEGER := 4
                   );
                 PORT(
                   clk   : IN  STD_LOGIC;
                   reset : IN  STD_LOGIC;
                   shift : IN  STD_LOGIC;
                   OP    : IN  STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0);
                   cnt   : IN  STD_LOGIC_VECTOR(shift_SZ-1 DOWNTO 0);
                   RES   : OUT STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0)
                   );
               END COMPONENT;
               COMPONENT SYNC_FF
                 GENERIC (
                   NB_FF_OF_SYNC : INTEGER);
                 PORT (
                   clk    : IN  STD_LOGIC;
                   rstn   : IN  STD_LOGIC;
                   A      : IN  STD_LOGIC;
                   A_sync : OUT STD_LOGIC);
               END COMPONENT;
               COMPONENT lpp_front_to_level
                 PORT (
                   clk  : IN  STD_LOGIC;
                   rstn : IN  STD_LOGIC;
                   sin  : IN  STD_LOGIC;
                   sout : OUT STD_LOGIC);
               END COMPONENT;
               COMPONENT lpp_front_detection
                 PORT (
                   clk  : IN  STD_LOGIC;
                   rstn : IN  STD_LOGIC;
                   sin  : IN  STD_LOGIC;
                   sout : OUT STD_LOGIC);
               END COMPONENT;
               COMPONENT lpp_front_positive_detection
                 PORT (
                   clk  : IN  STD_LOGIC;
                   rstn : IN  STD_LOGIC;
                   sin  : IN  STD_LOGIC;
                   sout : OUT STD_LOGIC);
               END COMPONENT;
               COMPONENT SYNC_VALID_BIT
                 GENERIC (
                   NB_FF_OF_SYNC : INTEGER);
                 PORT (
                   clk_in  : IN  STD_LOGIC;
                   clk_out : IN  STD_LOGIC;
                   rstn : IN  STD_LOGIC;
                   sin  : IN  STD_LOGIC;
                   sout : OUT STD_LOGIC);
               END COMPONENT;
               COMPONENT RR_Arbiter_4
                 PORT (
                   clk       : IN  STD_LOGIC;
                   rstn      : IN  STD_LOGIC;
                   in_valid  : IN  STD_LOGIC_VECTOR(3 DOWNTO 0);
                   out_grant : OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
               END COMPONENT;
             COMPONENT Clock_Divider is
             generic(N :integer := 10);
             port(
                 clk, rst   : in std_logic;
                 sclk       : out std_logic);
             end COMPONENT;
             END;

lib/lpp/lfr_management/coarse_time_counter.vhd +6 -5

             LIBRARY IEEE;
             USE IEEE.STD_LOGIC_1164.ALL;
             USE IEEE.NUMERIC_STD.ALL;
             LIBRARY lpp;
             USE lpp.general_purpose.ALL;
             ENTITY coarse_time_counter IS
               GENERIC (
                 NB_SECOND_DESYNC : INTEGER := 60);
               PORT (
                 clk           : IN STD_LOGIC;
                 rstn          : IN STD_LOGIC;
                 tick          : IN STD_LOGIC;
                 set_TCU       : IN STD_LOGIC;
                 new_TCU       : IN STD_LOGIC;
                 set_TCU_value : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
                 CT_add1       : IN STD_LOGIC;
                 fsm_desync    : IN STD_LOGIC;
                 FT_max        : IN STD_LOGIC;
                 coarse_time   : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                 coarse_time_new   : OUT STD_LOGIC
                 );
             END coarse_time_counter;
             ARCHITECTURE beh OF coarse_time_counter IS
               SIGNAL add1_bit31 : STD_LOGIC;
               SIGNAL nb_second_counter : STD_LOGIC_VECTOR(5 DOWNTO 0);
               SIGNAL coarse_time_new_counter : STD_LOGIC;
               SIGNAL coarse_time_31 : STD_LOGIC;
               SIGNAL coarse_time_31_reg : STD_LOGIC;
               SIGNAL set_synchronized       : STD_LOGIC;
               SIGNAL set_synchronized_value : STD_LOGIC_VECTOR(5 DOWNTO 0);
               --CONSTANT NB_SECOND_DESYNC : INTEGER := 4; -- TODO : 60
             BEGIN  -- beh
               -----------------------------------------------------------------------------
               -- COARSE_TIME( 30 DOWNTO 0)
               -----------------------------------------------------------------------------
               counter_1 : general_counter
                 GENERIC MAP (
                   CYCLIC => '1',
-                  NB_BITS_COUNTER => 31)
+                  NB_BITS_COUNTER => 31,
+                  RST_VALUE => 0)
                 PORT MAP (
                   clk       => clk,
                   rstn      => rstn,
-                  RST_VALUE => (OTHERS => '0'),
                   MAX_VALUE => "111" & X"FFFFFFF" ,
                   set       => set_TCU,
                   set_value => set_TCU_value(30 DOWNTO 0),
                   add1      => CT_add1,
                   counter   => coarse_time(30 DOWNTO 0));
               add1_bit31 <= '1' WHEN fsm_desync = '1' AND FT_max = '1' ELSE '0';
               -----------------------------------------------------------------------------
               -- COARSE_TIME(31)
               -----------------------------------------------------------------------------
               --set_synchronized       <= (tick AND (NOT coarse_time_31)) OR (coarse_time_31 AND set_TCU);
               --set_synchronized_value <= STD_LOGIC_VECTOR(to_unsigned(NB_SECOND_DESYNC, 6)) WHEN (set_TCU AND set_TCU_value(31)) =  '1' ELSE
               --                          (OTHERS => '0');
               set_synchronized       <= tick AND ((NOT coarse_time_31) OR (coarse_time_31 AND new_TCU));
               set_synchronized_value <= (OTHERS => '0');
               counter_2 : general_counter
                 GENERIC MAP (
                   CYCLIC          => '0',
-                  NB_BITS_COUNTER => 6)
+                  NB_BITS_COUNTER => 6,
+                  RST_VALUE       => NB_SECOND_DESYNC
+                  )
                 PORT MAP (
                   clk       => clk,
                   rstn      => rstn,
-                  RST_VALUE => STD_LOGIC_VECTOR(to_unsigned(NB_SECOND_DESYNC, 6)),
                   MAX_VALUE => STD_LOGIC_VECTOR(to_unsigned(NB_SECOND_DESYNC, 6)),
                   set       => set_synchronized,
                   set_value => set_synchronized_value,
                   add1      => add1_bit31,
                   counter   => nb_second_counter);
               coarse_time_31 <= '1' WHEN nb_second_counter = STD_LOGIC_VECTOR(to_unsigned(NB_SECOND_DESYNC, 6))  ELSE '0';
               coarse_time(31) <= coarse_time_31;
               coarse_time_new <= coarse_time_new_counter OR (coarse_time_31 XOR coarse_time_31_reg);
               PROCESS (clk, rstn)
               BEGIN  -- PROCESS
                 IF rstn = '0' THEN                  -- asynchronous reset (active low)
                   coarse_time_new_counter <= '0';
                   coarse_time_31_reg <= '0';
                 ELSIF clk'event AND clk = '1' THEN  -- rising clock edge
                   coarse_time_31_reg <= coarse_time_31;
                   IF set_TCU = '1' OR CT_add1 = '1' THEN
                     coarse_time_new_counter <= '1';
                   ELSE
                     coarse_time_new_counter <= '0';
                   END IF;
                 END IF;
               END PROCESS;
-            END beh;
+            END beh;
  No newline at end of file

lib/lpp/lfr_management/fine_time_counter.vhd +6 -5

             LIBRARY IEEE;
             USE IEEE.STD_LOGIC_1164.ALL;
             USE IEEE.NUMERIC_STD.ALL;
             LIBRARY lpp;
             USE lpp.general_purpose.ALL;
             ENTITY fine_time_counter IS
               GENERIC (
                 WAITING_TIME : STD_LOGIC_VECTOR(15 DOWNTO 0) := X"0040";
                 FIRST_DIVISION : INTEGER := 374
                 );
               PORT (
                 clk            : IN STD_LOGIC;
                 rstn           : IN STD_LOGIC;
                 --
                 tick           : IN STD_LOGIC;
                 fsm_transition : IN STD_LOGIC;
                 FT_max        : OUT STD_LOGIC;
                 FT_half       : OUT STD_LOGIC;
                 FT_wait       : OUT STD_LOGIC;
                 fine_time     : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
                 fine_time_new : OUT STD_LOGIC
                 );
             END fine_time_counter;
             ARCHITECTURE beh OF fine_time_counter IS
               SIGNAL new_ft_counter    : STD_LOGIC_VECTOR(8 DOWNTO 0);
               SIGNAL new_ft            : STD_LOGIC;
               SIGNAL fine_time_counter : STD_LOGIC_VECTOR(15 DOWNTO 0);
             --  CONSTANT FIRST_DIVISION : INTEGER := 20; -- TODO : 374
             BEGIN  -- beh
               counter_1 : general_counter
                 GENERIC MAP (
                   CYCLIC          => '1',
-                  NB_BITS_COUNTER => 9)
+                  NB_BITS_COUNTER => 9,
+                  RST_VALUE       => 0
+                  )
                 PORT MAP (
                   clk       => clk,
                   rstn      => rstn,
-                  RST_VALUE => (OTHERS => '0'),
                   MAX_VALUE => STD_LOGIC_VECTOR(to_unsigned(FIRST_DIVISION, 9)),
                   set       => tick,
                   set_value => (OTHERS => '0'),
                   add1      => '1',
                   counter   => new_ft_counter);
               new_ft <= '1' WHEN new_ft_counter = STD_LOGIC_VECTOR(to_unsigned(FIRST_DIVISION, 9)) ELSE '0';
               counter_2 : general_counter
                 GENERIC MAP (
                   CYCLIC          => '1',
-                  NB_BITS_COUNTER => 16)
+                  NB_BITS_COUNTER => 16,
+                  RST_VALUE       => 0
+                  )
                 PORT MAP (
                   clk       => clk,
                   rstn      => rstn,
-                  RST_VALUE => (OTHERS => '0'),
                   MAX_VALUE => X"FFFF",
                   set       => tick,
                   set_value => (OTHERS => '0'),
                   add1      => new_ft,
                   counter   => fine_time_counter);
               FT_max  <= '1' WHEN new_ft = '1' AND fine_time_counter = X"FFFF" ELSE '0';
               FT_half <= '1' WHEN fine_time_counter > X"7FFF"                  ELSE '0';
               FT_wait <= '1' WHEN fine_time_counter > WAITING_TIME             ELSE '0';
               fine_time <= X"FFFF" WHEN fsm_transition = '1' ELSE fine_time_counter;
               PROCESS (clk, rstn)
               BEGIN  -- PROCESS
                 IF rstn = '0' THEN                  -- asynchronous reset (active low)
                   fine_time_new <= '0';
                 ELSIF clk'EVENT AND clk = '1' THEN  -- rising clock edge
                   IF (new_ft = '1' AND fsm_transition = '0') OR tick = '1' THEN
                     fine_time_new <= '1';
                   ELSE
                     fine_time_new <= '0';
                   END IF;
                 END IF;
               END PROCESS;
             END beh;

lib/lpp/lpp_cna/RAM_READER.vhd +2 -2

             ------------------------------------------------------------------------------
             --  This file is a part of the LPP VHDL IP LIBRARY
             --  Copyright (C) 2009 - 2015, Laboratory of Plasmas Physic - CNRS
             --
             --  This program is free software; you can redistribute it and/or modify
             --  it under the terms of the GNU General Public License as published by
             --  the Free Software Foundation; either version 3 of the License, or
             --  (at your option) any later version.
             --
             --  This program is distributed in the hope that it will be useful,
             --  but WITHOUT ANY WARRANTY; without even the implied warranty of
             --  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
             --  GNU General Public License for more details.
             --
             --  You should have received a copy of the GNU General Public License
             --  along with this program; if not, write to the Free Software
             --  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
             ------------------------------------------------------------------------------
             --                    Author : Alexis Jeandet
             --                     Mail : alexis.jeandet@member.fsf.org
             ------------------------------------------------------------------------------
             library IEEE;
             use IEEE.STD_LOGIC_1164.ALL;
             use IEEE.NUMERIC_STD.ALL;
             entity RAM_READER is
                 Generic(
                     datawidth     : integer := 18;
                     dacresolution : integer := 12;
                     abits         : integer := 8
                 );
                 Port (
                     clk         : in  STD_LOGIC;                                    --! clock input
                     rstn        : in  STD_LOGIC;                                    --! Active low restet input
                     DATA_IN     : in  STD_LOGIC_VECTOR (datawidth-1 downto 0);      --! DATA input vector -> connect to RAM DATA output
                     ADDRESS     : out STD_LOGIC_VECTOR (abits-1 downto 0);          --! ADDRESS output vector -> connect to RAM read ADDRESS input
                     REN         : out STD_LOGIC;                                    --! Active low read enable -> connect to RAM read enable
                     DATA_OUT    : out STD_LOGIC_VECTOR (dacresolution-1 downto 0);  --! DATA output vector
                     SMP_CLK     : in  STD_LOGIC;                                    --! Sampling clock input, each rising edge will provide a DATA to the output and read a new one in RAM
                     INTERLEAVED : in  STD_LOGIC                                     --! When 1, interleaved mode is actived.
                           );
             end RAM_READER;
             architecture Behavioral of RAM_READER is
             CONSTANT interleaved_sz   : integer := dacresolution/(datawidth-dacresolution);
-            signal ADDRESS_R             :  STD_LOGIC_VECTOR (abits-1 downto 0):=(others=>'0');
+            signal ADDRESS_R             :  STD_LOGIC_VECTOR (abits-1 downto 0);--:=(others=>'0');
             signal SAMPLE_R              :  STD_LOGIC_VECTOR (dacresolution-1 downto 0):=(others=>'0');
             signal INTERLEAVED_SAMPLE_R  :  STD_LOGIC_VECTOR (dacresolution-1 downto 0):=(others=>'0');
             signal SMP_CLK_R             :  STD_LOGIC;
             signal interleavedCNTR       :  integer range 0 to interleaved_sz;
             signal REN_R                 :  STD_LOGIC:='1';
             signal interleave            :  STD_LOGIC:='0';
             signal loadEvent             :  STD_LOGIC:='0';
             signal loadEvent_R           :  STD_LOGIC:='0';
             signal loadEvent_R2          :  STD_LOGIC:='0';
             begin
             REN         <=  REN_R;
             DATA_OUT    <=  SAMPLE_R;
             ADDRESS     <=  ADDRESS_R;
             interleave  <= '1' when interleavedCNTR=interleaved_sz else '0';
             loadEvent   <= SMP_CLK and not SMP_CLK_R ;
             process(clk,rstn)
             begin
                 if rstn='0' then
                     SMP_CLK_R               <= '0';
                     loadEvent_R             <= '0';
                     loadEvent_R2            <= '0';
                 elsif clk'event and clk='1' then
                     SMP_CLK_R    <= SMP_CLK;
                     loadEvent_R  <= loadEvent;
                     loadEvent_R2 <= loadEvent_R;
                 end if;
             end process;
             process(clk,rstn)
             begin
                 if rstn='0' then
                     ADDRESS_R               <= (others=>'0');
                     SAMPLE_R                <= (others=>'0');
                     INTERLEAVED_SAMPLE_R    <= (others=>'0');
                     REN_R                   <= '1';
                     interleavedCNTR 		<= 0;
                 elsif clk'event and clk='1' then
                     if loadEvent = '1' then
                         if(interleave='0') then
                             REN_R           <= '0';
                         end if;
                     else
                         REN_R   <= '1';
                     end if;
                     if REN_R = '0' then
                         ADDRESS_R       <= std_logic_vector(UNSIGNED(ADDRESS_R) + 1); --Automatic increment on each read
                     end if;
                     if loadEvent_R2='1' then
                         if(interleave='1') then
                             interleavedCNTR <= 0;
                             SAMPLE_R        <= INTERLEAVED_SAMPLE_R;
                         else
                             if interleaved='1' then
                                 interleavedCNTR     <= interleavedCNTR + 1;
                             else
                                 interleavedCNTR     <= 0;
                             end if;
                             SAMPLE_R            <= DATA_IN(dacresolution-1 downto 0);
                             INTERLEAVED_SAMPLE_R(dacresolution-1 downto 0) <= INTERLEAVED_SAMPLE_R(datawidth-dacresolution-1 downto 0) & DATA_IN(datawidth-1 downto dacresolution);
                         end if;
                     end if;
                 end if;
             end process;
-            end Behavioral;
+            end Behavioral;
  No newline at end of file

lib/lpp/lpp_cna/SPI_DAC_DRIVER.vhd 0 -4

             ------------------------------------------------------------------------------
             --  This file is a part of the LPP VHDL IP LIBRARY
             --  Copyright (C) 2009 - 2015, Laboratory of Plasmas Physic - CNRS
             --
             --  This program is free software; you can redistribute it and/or modify
             --  it under the terms of the GNU General Public License as published by
             --  the Free Software Foundation; either version 3 of the License, or
             --  (at your option) any later version.
             --
             --  This program is distributed in the hope that it will be useful,
             --  but WITHOUT ANY WARRANTY; without even the implied warranty of
             --  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
             --  GNU General Public License for more details.
             --
             --  You should have received a copy of the GNU General Public License
             --  along with this program; if not, write to the Free Software
             --  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
             ------------------------------------------------------------------------------
             --                    Author : Alexis Jeandet
             --                     Mail : alexis.jeandet@member.fsf.org
             ------------------------------------------------------------------------------
             LIBRARY IEEE;
             USE IEEE.STD_LOGIC_1164.ALL;
             USE IEEE.NUMERIC_STD.ALL;
             ENTITY SPI_DAC_DRIVER IS
               GENERIC(
                 datawidth : INTEGER := 16;
                 MSBFIRST  : INTEGER := 1
                 );
               PORT (
                 clk     : IN  STD_LOGIC;
                 rstn    : IN  STD_LOGIC;
                 DATA    : IN  STD_LOGIC_VECTOR(datawidth-1 DOWNTO 0);
                 SMP_CLK : IN  STD_LOGIC;
                 SYNC    : OUT STD_LOGIC;
                 DOUT    : OUT STD_LOGIC;
                 SCLK    : OUT STD_LOGIC
                 );
             END ENTITY SPI_DAC_DRIVER;
             ARCHITECTURE behav OF SPI_DAC_DRIVER IS
               SIGNAL SHIFTREG   : STD_LOGIC_VECTOR(datawidth-1 DOWNTO 0) := (OTHERS => '0');
               SIGNAL INPUTREG   : STD_LOGIC_VECTOR(datawidth-1 DOWNTO 0) := (OTHERS => '0');
               SIGNAL SMP_CLK_R  : STD_LOGIC                              := '0';
               SIGNAL shiftcnt   : INTEGER                                := 0;
               SIGNAL shifting   : STD_LOGIC                              := '0';
-              SIGNAL shifting_R : STD_LOGIC                              := '0';
             BEGIN
               MSB : IF MSBFIRST = 1 GENERATE
                 INPUTREG <= DATA;
               END GENERATE;
               LSB : IF MSBFIRST = 0 GENERATE
                 INPUTREG(datawidth-1 DOWNTO 0) <= DATA(0 TO datawidth-1);
               END GENERATE;
               SCLK <= clk;
               PROCESS(clk, rstn)
               BEGIN
                 IF rstn = '0' THEN
-            --      shifting_R <= '0';
                   SMP_CLK_R <= '0';
                 ELSIF clk'EVENT AND clk = '1' THEN
                   SMP_CLK_R <= SMP_CLK;
-            --      shifting_R <= shifting;
                 END IF;
               END PROCESS;
               PROCESS(clk, rstn)
               BEGIN
                 IF rstn = '0' THEN
                   shifting <= '0';
                   SHIFTREG <= (OTHERS => '0');
                   SYNC     <= '0';
                   shiftcnt <= 0;
                   DOUT     <= '0';
                 ELSIF clk'EVENT AND clk = '1' THEN
                   DOUT <= SHIFTREG(datawidth-1);
                   IF(SMP_CLK = '1' AND SMP_CLK_R = '0') THEN
                     SYNC     <= '1';
                     shifting <= '1';
                   ELSE
                     SYNC <= '0';
                     IF shiftcnt = datawidth-1 THEN
                       shifting <= '0';
                     END IF;
                   END IF;
                   IF shifting = '1' THEN
                     shiftcnt <= shiftcnt + 1;
                     SHIFTREG <= SHIFTREG (datawidth-2 DOWNTO 0) & '0';
                   ELSE
                     SHIFTREG <= INPUTREG;
                     shiftcnt <= 0;
                   END IF;
                 END IF;
               END PROCESS;
             END ARCHITECTURE behav;

lib/lpp/lpp_cna/dynamic_freq_div.vhd +2 -2

             ------------------------------------------------------------------------------
             --  This file is a part of the LPP VHDL IP LIBRARY
             --  Copyright (C) 2009 - 2015, Laboratory of Plasmas Physic - CNRS
             --
             --  This program is free software; you can redistribute it and/or modify
             --  it under the terms of the GNU General Public License as published by
             --  the Free Software Foundation; either version 3 of the License, or
             --  (at your option) any later version.
             --
             --  This program is distributed in the hope that it will be useful,
             --  but WITHOUT ANY WARRANTY; without even the implied warranty of
             --  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
             --  GNU General Public License for more details.
             --
             --  You should have received a copy of the GNU General Public License
             --  along with this program; if not, write to the Free Software
             --  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
             ------------------------------------------------------------------------------
             --                    Author : Alexis Jeandet
             --                     Mail : alexis.jeandet@member.fsf.org
             ------------------------------------------------------------------------------
             library IEEE;
             use IEEE.STD_LOGIC_1164.ALL;
             use IEEE.NUMERIC_STD.ALL;
             entity dynamic_freq_div is
                 generic(
                     PRESZ  :  integer range 1 to 32:=4;
                     PREMAX :  integer := 16#FFFFFF#;
                     CPTSZ  :  integer range 1 to 32:=16
                  );
                 Port (
                     clk     : in  STD_LOGIC;
                     rstn    : in  STD_LOGIC;
                     pre     : in  STD_LOGIC_VECTOR(PRESZ-1 downto 0);
                     N       : in  STD_LOGIC_VECTOR(CPTSZ-1 downto 0);
                     Reload  : in  std_logic;
                     clk_out : out STD_LOGIC
                     );
             end dynamic_freq_div;
             architecture Behavioral of dynamic_freq_div is
             constant prescaller_reg_sz : integer := 2**PRESZ;
             constant PREMAX_max        : STD_LOGIC_VECTOR(PRESZ-1 downto 0):=(others => '1');
             signal cpt_reg             : std_logic_vector(CPTSZ-1 downto 0):=(others => '0');
-            signal prescaller_reg      : std_logic_vector(prescaller_reg_sz-1 downto 0):=(others => '0');
+            signal prescaller_reg      : std_logic_vector(prescaller_reg_sz-1 downto 0);--:=(others => '0');
             signal internal_clk        : std_logic:='0';
             signal internal_clk_reg    : std_logic:='0';
             signal clk_out_reg         : std_logic:='0';
             begin
             max0: if (UNSIGNED(PREMAX_max) < PREMAX) generate
             internal_clk <= prescaller_reg(to_integer(unsigned(pre))) when (to_integer(unsigned(pre))<=UNSIGNED(PREMAX_max)) else
                                 prescaller_reg(to_integer(UNSIGNED(PREMAX_max)));
             end generate;
             max1: if UNSIGNED(PREMAX_max) > PREMAX generate
             internal_clk <= prescaller_reg(to_integer(unsigned(pre))) when (to_integer(unsigned(pre))<=PREMAX) else
                                 prescaller_reg(PREMAX);
             end generate;
             prescaller: process(rstn, clk)
             begin
             if rstn='0' then
                 prescaller_reg    <= (others => '0');
             elsif clk'event and clk = '1' then
                 prescaller_reg <= std_logic_vector(UNSIGNED(prescaller_reg) + 1);
             end if;
             end process;
             clk_out <= clk_out_reg;
             counter: process(rstn, clk)
             begin
             if rstn='0' then
                 cpt_reg    <= (others => '0');
                 internal_clk_reg <= '0';
                 clk_out_reg <= '0';
             elsif clk'event and clk = '1' then
                 internal_clk_reg  <= internal_clk;
                 if Reload = '1' then
                     clk_out_reg <= '0';
                     cpt_reg     <= (others => '0');
                 elsif (internal_clk = '1' and internal_clk_reg = '0')  then
                     if cpt_reg = N then
                         clk_out_reg <= not clk_out_reg;
                         cpt_reg     <= (others => '0');
                     else
                         cpt_reg     <= std_logic_vector(UNSIGNED(cpt_reg) + 1);
                     end if;
                 end if;
             end if;
             end process;
-            end Behavioral;
+            end Behavioral;
  No newline at end of file

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