##// END OF EJS Templates
HG_REPOSITORIES » LPP » INSTRUMENTATION » USERS » PELLION » VHD_Lib
RSS

Clone from http://pc-instru.lpp.polytechnique.fr:5000/VHD_Lib

minor update (cleaning file)
pellion -
r547:4e22970f1b7e JC
parent child
Show More
Show file before | Show file after | Hide comments
@@ -1,21 +1,20
1 1 LIBRARY IEEE;
2 2 USE IEEE.STD_LOGIC_1164.ALL;
3 USE IEEE.std_logic_arith.ALL;
4 USE IEEE.std_logic_unsigned.ALL;
3 USE IEEE.NUMERIC_STD.ALL;
5 4
6 5 ENTITY general_counter IS
7 6
8 7 GENERIC (
9 8 CYCLIC : STD_LOGIC := '1';
10 NB_BITS_COUNTER : INTEGER := 9
9 NB_BITS_COUNTER : INTEGER := 9;
10 RST_VALUE : INTEGER := 0
11 11 );
12 12
13 13 PORT (
14 14 clk : IN STD_LOGIC;
15 15 rstn : IN STD_LOGIC;
16 16 --
17 RST_VALUE : IN STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0) := (OTHERS => '0');
18 MAX_VALUE : IN STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0) := (OTHERS => '1');
17 MAX_VALUE : IN STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0) := (OTHERS => '1');
19 18 --
20 19 set : IN STD_LOGIC;
21 20 set_value : IN STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0);
@@ -26,20 +25,21 ENTITY general_counter IS
26 25 END general_counter;
27 26
28 27 ARCHITECTURE beh OF general_counter IS
29 SIGNAL counter_s : STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0);
28 CONSTANT RST_VALUE_v : STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0) := STD_LOGIC_VECTOR(to_unsigned(RST_VALUE, NB_BITS_COUNTER));
29 SIGNAL counter_s : STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0);
30 30
31 31 BEGIN -- beh
32 32
33 33 PROCESS (clk, rstn)
34 34 BEGIN -- PROCESS
35 IF rstn = '0' THEN -- asynchronous reset (active low)
36 counter_s <= RST_VALUE;
37 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
35 IF rstn = '0' THEN -- asynchronous reset (active low)
36 counter_s <= RST_VALUE_v;
37 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
38 38 IF set = '1' THEN
39 39 counter_s <= set_value;
40 40 ELSIF add1 = '1' THEN
41 41 IF counter_s < MAX_VALUE THEN
42 counter_s <= counter_s + 1;
42 counter_s <= STD_LOGIC_VECTOR((UNSIGNED(counter_s) + 1));
43 43 ELSE
44 44 IF CYCLIC = '1' THEN
45 45 counter_s <= (OTHERS => '0');
@@ -50,5 +50,5 BEGIN -- beh
50 50 END PROCESS;
51 51
52 52 counter <= counter_s;
53
53
54 54 END beh;
Show file before | Show file after | Hide comments
@@ -32,16 +32,16 USE IEEE.NUMERIC_STD.ALL;
32 32
33 33
34 34 PACKAGE general_purpose IS
35
35
36 36 COMPONENT general_counter
37 37 GENERIC (
38 38 CYCLIC : STD_LOGIC;
39 NB_BITS_COUNTER : INTEGER);
39 NB_BITS_COUNTER : INTEGER;
40 RST_VALUE : INTEGER);
40 41 PORT (
41 42 clk : IN STD_LOGIC;
42 43 rstn : IN STD_LOGIC;
43 RST_VALUE : IN STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0);
44 MAX_VALUE : IN STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0);
44 MAX_VALUE : IN STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0);
45 45 set : IN STD_LOGIC;
46 46 set_value : IN STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0);
47 47 add1 : IN STD_LOGIC;
Show file before | Show file after | Hide comments
@@ -48,11 +48,11 BEGIN -- beh
48 48 counter_1 : general_counter
49 49 GENERIC MAP (
50 50 CYCLIC => '1',
51 NB_BITS_COUNTER => 31)
51 NB_BITS_COUNTER => 31,
52 RST_VALUE => 0)
52 53 PORT MAP (
53 54 clk => clk,
54 55 rstn => rstn,
55 RST_VALUE => (OTHERS => '0'),
56 56 MAX_VALUE => "111" & X"FFFFFFF" ,
57 57 set => set_TCU,
58 58 set_value => set_TCU_value(30 DOWNTO 0),
@@ -75,11 +75,12 BEGIN -- beh
75 75 counter_2 : general_counter
76 76 GENERIC MAP (
77 77 CYCLIC => '0',
78 NB_BITS_COUNTER => 6)
78 NB_BITS_COUNTER => 6,
79 RST_VALUE => NB_SECOND_DESYNC
80 )
79 81 PORT MAP (
80 82 clk => clk,
81 83 rstn => rstn,
82 RST_VALUE => STD_LOGIC_VECTOR(to_unsigned(NB_SECOND_DESYNC, 6)),
83 84 MAX_VALUE => STD_LOGIC_VECTOR(to_unsigned(NB_SECOND_DESYNC, 6)),
84 85 set => set_synchronized,
85 86 set_value => set_synchronized_value,
@@ -105,4 +106,4 BEGIN -- beh
105 106 END IF;
106 107 END PROCESS;
107 108
108 END beh;
109 END beh; No newline at end of file
Show file before | Show file after | Hide comments
@@ -43,11 +43,12 BEGIN -- beh
43 43 counter_1 : general_counter
44 44 GENERIC MAP (
45 45 CYCLIC => '1',
46 NB_BITS_COUNTER => 9)
46 NB_BITS_COUNTER => 9,
47 RST_VALUE => 0
48 )
47 49 PORT MAP (
48 50 clk => clk,
49 51 rstn => rstn,
50 RST_VALUE => (OTHERS => '0'),
51 52 MAX_VALUE => STD_LOGIC_VECTOR(to_unsigned(FIRST_DIVISION, 9)),
52 53 set => tick,
53 54 set_value => (OTHERS => '0'),
@@ -59,11 +60,12 BEGIN -- beh
59 60 counter_2 : general_counter
60 61 GENERIC MAP (
61 62 CYCLIC => '1',
62 NB_BITS_COUNTER => 16)
63 NB_BITS_COUNTER => 16,
64 RST_VALUE => 0
65 )
63 66 PORT MAP (
64 67 clk => clk,
65 68 rstn => rstn,
66 RST_VALUE => (OTHERS => '0'),
67 69 MAX_VALUE => X"FFFF",
68 70 set => tick,
69 71 set_value => (OTHERS => '0'),
@@ -90,4 +92,3 BEGIN -- beh
90 92 END PROCESS;
91 93
92 94 END beh;
93
Show file before | Show file after | Hide comments
@@ -44,7 +44,7 end RAM_READER;
44 44 architecture Behavioral of RAM_READER is
45 45 CONSTANT interleaved_sz : integer := dacresolution/(datawidth-dacresolution);
46 46
47 signal ADDRESS_R : STD_LOGIC_VECTOR (abits-1 downto 0):=(others=>'0');
47 signal ADDRESS_R : STD_LOGIC_VECTOR (abits-1 downto 0);--:=(others=>'0');
48 48 signal SAMPLE_R : STD_LOGIC_VECTOR (dacresolution-1 downto 0):=(others=>'0');
49 49 signal INTERLEAVED_SAMPLE_R : STD_LOGIC_VECTOR (dacresolution-1 downto 0):=(others=>'0');
50 50 signal SMP_CLK_R : STD_LOGIC;
@@ -114,4 +114,4 begin
114 114 end if;
115 115 end process;
116 116
117 end Behavioral;
117 end Behavioral; No newline at end of file
Show file before | Show file after | Hide comments
@@ -47,7 +47,6 ARCHITECTURE behav OF SPI_DAC_DRIVER IS
47 47 SIGNAL SMP_CLK_R : STD_LOGIC := '0';
48 48 SIGNAL shiftcnt : INTEGER := 0;
49 49 SIGNAL shifting : STD_LOGIC := '0';
50 SIGNAL shifting_R : STD_LOGIC := '0';
51 50 BEGIN
52 51
53 52
@@ -64,11 +63,9 BEGIN
64 63 PROCESS(clk, rstn)
65 64 BEGIN
66 65 IF rstn = '0' THEN
67 -- shifting_R <= '0';
68 66 SMP_CLK_R <= '0';
69 67 ELSIF clk'EVENT AND clk = '1' THEN
70 68 SMP_CLK_R <= SMP_CLK;
71 -- shifting_R <= shifting;
72 69 END IF;
73 70 END PROCESS;
74 71
@@ -104,4 +101,3 BEGIN
104 101
105 102 END ARCHITECTURE behav;
106 103
107
Show file before | Show file after | Hide comments
@@ -43,7 +43,7 architecture Behavioral of dynamic_freq_
43 43 constant prescaller_reg_sz : integer := 2**PRESZ;
44 44 constant PREMAX_max : STD_LOGIC_VECTOR(PRESZ-1 downto 0):=(others => '1');
45 45 signal cpt_reg : std_logic_vector(CPTSZ-1 downto 0):=(others => '0');
46 signal prescaller_reg : std_logic_vector(prescaller_reg_sz-1 downto 0):=(others => '0');
46 signal prescaller_reg : std_logic_vector(prescaller_reg_sz-1 downto 0);--:=(others => '0');
47 47 signal internal_clk : std_logic:='0';
48 48 signal internal_clk_reg : std_logic:='0';
49 49 signal clk_out_reg : std_logic:='0';
@@ -96,4 +96,4 elsif clk'event and clk = '1' then
96 96 end if;
97 97 end process;
98 98
99 end Behavioral;
99 end Behavioral; No newline at end of file
General Comments 0
You need to be logged in to leave comments. Login now