HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib Commit - r29:4c437dd190b1

lib/lpp/lpp_cna/Systeme_Clock.vhd created 644 +40 0

			@@ -0,0 +1,40
		1	-- Systeme_Clock.vhd
		2	library IEEE;
		3	use IEEE.std_logic_1164.all;
		4	use IEEE.numeric_std.all;
		5
		6	--! Programme qui va permetre de g�n�rer l'horloge systeme (sclk)
		7
		8	entity Systeme_Clock is
		9	generic(N :integer := 695); --! G�n�rique contenant le r�sultat de la division clk/sclk
		10	port(
		11	clk, raz : in std_logic; --! Horloge et Reset globale
		12	sclk : out std_logic --! Horloge Systeme g�n�r�e
		13	);
		14	end Systeme_Clock;
		15
		16	--! @details Fonctionne a base d'un compteur (countint) qui va permetre de diviser l'horloge N fois
		17	architecture ar_Systeme_Clock of Systeme_Clock is
		18
		19	signal clockint : std_logic;
		20	signal countint : integer range 0 to N/2-1;
		21
		22	begin
		23	process (clk,raz)
		24	begin
		25	if(raz = '0') then
		26	countint <= 0;
		27	clockint <= '0';
		28	elsif (clk' event and clk='1') then
		29	if (countint = N/2-1) then
		30	countint <= 0;
		31	clockint <= not clockint;
		32	else
		33	countint <= countint+1;
		34	end if;
		35	end if;
		36	end process;
		37
		38	sclk <= clockint;
		39
		40	end ar_Systeme_Clock; No newline at end of file

lib/lpp/dirs.txt 0 -1

              ./lpp_ad_Conv
              ./lpp_amba
              ./lpp_cna
-             ./lpp_CNA_amba
              ./lpp_uart

lib/lpp/lpp_amba/APB_MULTI_DIODE.vhd +6 -5

              end record;
              signal r : LEDregs;
+             signal Rdata     : std_logic_vector(31 downto 0);
              begin
                  if rst = '0' then
                      LED <=  "000";
                      r.DATAin <= (others => '0');
-                     apbo.prdata <= (others => '0');
-                 elsif clk'event and clk = '1' then
                          LED <= r.DATAin(2 downto 0);
                      end if;
              --APB READ OP
-                     if (apbi.psel(pindex) and apbi.penable and (not apbi.pwrite)) = '1' then
+                     if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
                          case apbi.paddr(abits-1 downto 2) is
                              when "000000" =>
-                                 apbo.prdata <= r.DATAin;
+                                 Rdata <= r.DATAin;
                              when others =>
-                                 apbo.prdata <= r.DATAout;
+                                 Rdata <= r.DATAout;
                          end case;
                      end if;
                  apbo.pconfig <= pconfig;
              end process;
+             apbo.prdata     <=   Rdata when apbi.penable = '1';
              end ar_APB_MULTI_DIODE;

lib/lpp/lpp_amba/APB_SIMPLE_DIODE.vhd +6 -6

              end record;
              signal r : LEDregs;
+             signal Rdata     : std_logic_vector(31 downto 0);
              begin
                  if rst = '0' then
                      LED <=  '0';
                      r.DATAin <= (others => '0');
-                     apbo.prdata <= (others => '0');
-                 elsif clk'event and clk = '1' then
                          LED <= r.DATAin(0);
                      end if;
              --APB READ OP
-                     if (apbi.psel(pindex) and apbi.penable and (not apbi.pwrite)) = '1' then
+                     if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
                          case apbi.paddr(abits-1 downto 2) is
                              when "000000" =>
-                                 apbo.prdata <= r.DATAin;
+                                 Rdata <= r.DATAin;
                              when others =>
-                                 apbo.prdata <= r.DATAout;
+                                 Rdata <= r.DATAout;
                          end case;
                      end if;
                  apbo.pconfig <= pconfig;
              end process;
+             apbo.prdata     <=   Rdata when apbi.penable = '1';
              -- pragma translate_off
              --    bootmsg : report_version

lib/lpp/lpp_cna/CNA_TabloC.vhd +1 -1

                  port map(A => rst, Y => raz);
-             SystemCLK : entity work.Clock_Serie
+             SystemCLK : entity work.Systeme_Clock
                  generic map (nb_serial)
                  port map (clk,raz,s_SCLK);

lib/lpp/lpp_cna/lpp_cna.vhd +1 -1

              end component;
-             component Clock_Serie is
+             component Systeme_Clock is
                  generic(N :integer := 695);
                  port(
                      clk, raz   : in std_logic ;

lib/lpp/lpp_uart/APB_UART.vhd +11 -8

              end record;
              signal Rec : UART_ctrlr_Reg;
+             signal Rdata     : std_logic_vector(31 downto 0);
              begin
                  begin
                      if(rst='0')then
                          Rec.UART_Wdata <=  (others => '0');
-                         apbo.prdata <= (others => '0');
-                     elsif(clk'event and clk='1')then
                          end if;
                  --APB READ OP
-                         if (apbi.psel(pindex) and apbi.penable and (not apbi.pwrite)) = '1' then
+                         if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
                              case apbi.paddr(abits-1 downto 2) is
                                  when "000000" =>
-                                     apbo.prdata(31 downto 27) <= Rec.UART_Cfg;
-                                     apbo.prdata(26 downto 12) <= (others => '0');
-                                     apbo.prdata(11 downto 0) <= Rec.UART_BTrig;
+                                     Rdata(31 downto 27) <= Rec.UART_Cfg;
+                                     Rdata(26 downto 12) <= (others => '0');
+                                     Rdata(11 downto 0) <= Rec.UART_BTrig;
                                  when "000001" =>
-                                     apbo.prdata(7 downto 0) <= Rec.UART_Wdata;
+                                     Rdata(7 downto 0) <= Rec.UART_Wdata;
                                  when "000010" =>
-                                     apbo.prdata(7 downto 0) <= Rec.UART_Rdata;
+                                     Rdata(7 downto 0) <= Rec.UART_Rdata;
                                  when others =>
-                                     apbo.prdata <= (others => '0');
+                                     Rdata <= (others => '0');
                              end case;
                          end if;
                      apbo.pconfig <= pconfig;
                  end process;
+                 apbo.prdata     <=   Rdata when apbi.penable = '1';
              end ar_APB_UART;

lib/lpp/lpp_CNA_amba/APB_CNA.vhd removed 0 -118

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lib/lpp/lpp_CNA_amba/CNA_TabloC.vhd removed 0 -88

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lib/lpp/lpp_CNA_amba/Convertisseur_config.vhd removed 0 -41

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lib/lpp/lpp_CNA_amba/GeneSYNC_flag.vhd removed 0 -111

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lib/lpp/lpp_CNA_amba/Serialize.vhd removed 0 -103

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lib/lpp/lpp_CNA_amba/clock.vhd removed 0 -58

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lib/lpp/lpp_CNA_amba/lpp_CNA_amba.vhd removed 0 -51

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