##// END OF EJS Templates
HG_REPOSITORIES » LPP » INSTRUMENTATION » USERS » PELLION » VHD_Lib
RSS

Clone from http://pc-instru.lpp.polytechnique.fr:5000/VHD_Lib

GRLIB changes
martin -
r29:4c437dd190b1 default
parent child
Show More
Show file before | Show file after | Hide comments
@@ -0,0 +1,40
1 -- Systeme_Clock.vhd
2 library IEEE;
3 use IEEE.std_logic_1164.all;
4 use IEEE.numeric_std.all;
5
6 --! Programme qui va permetre de g�n�rer l'horloge systeme (sclk)
7
8 entity Systeme_Clock is
9 generic(N :integer := 695); --! G�n�rique contenant le r�sultat de la division clk/sclk
10 port(
11 clk, raz : in std_logic; --! Horloge et Reset globale
12 sclk : out std_logic --! Horloge Systeme g�n�r�e
13 );
14 end Systeme_Clock;
15
16 --! @details Fonctionne a base d'un compteur (countint) qui va permetre de diviser l'horloge N fois
17 architecture ar_Systeme_Clock of Systeme_Clock is
18
19 signal clockint : std_logic;
20 signal countint : integer range 0 to N/2-1;
21
22 begin
23 process (clk,raz)
24 begin
25 if(raz = '0') then
26 countint <= 0;
27 clockint <= '0';
28 elsif (clk' event and clk='1') then
29 if (countint = N/2-1) then
30 countint <= 0;
31 clockint <= not clockint;
32 else
33 countint <= countint+1;
34 end if;
35 end if;
36 end process;
37
38 sclk <= clockint;
39
40 end ar_Systeme_Clock; No newline at end of file
Show file before | Show file after | Hide comments
@@ -4,5 +4,4
4 ./lpp_ad_Conv
4 ./lpp_ad_Conv
5 ./lpp_amba
5 ./lpp_amba
6 ./lpp_cna
6 ./lpp_cna
7 ./lpp_CNA_amba
8 ./lpp_uart
7 ./lpp_uart
Show file before | Show file after | Hide comments
@@ -60,6 +60,7 type LEDregs is record
60 end record;
60 end record;
61
61
62 signal r : LEDregs;
62 signal r : LEDregs;
63 signal Rdata : std_logic_vector(31 downto 0);
63
64
64
65
65 begin
66 begin
@@ -71,7 +72,7 begin
71 if rst = '0' then
72 if rst = '0' then
72 LED <= "000";
73 LED <= "000";
73 r.DATAin <= (others => '0');
74 r.DATAin <= (others => '0');
74 apbo.prdata <= (others => '0');
75
75 elsif clk'event and clk = '1' then
76 elsif clk'event and clk = '1' then
76
77
77 LED <= r.DATAin(2 downto 0);
78 LED <= r.DATAin(2 downto 0);
@@ -87,12 +88,12 begin
87 end if;
88 end if;
88
89
89 --APB READ OP
90 --APB READ OP
90 if (apbi.psel(pindex) and apbi.penable and (not apbi.pwrite)) = '1' then
91 if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
91 case apbi.paddr(abits-1 downto 2) is
92 case apbi.paddr(abits-1 downto 2) is
92 when "000000" =>
93 when "000000" =>
93 apbo.prdata <= r.DATAin;
94 Rdata <= r.DATAin;
94 when others =>
95 when others =>
95 apbo.prdata <= r.DATAout;
96 Rdata <= r.DATAout;
96 end case;
97 end case;
97 end if;
98 end if;
98
99
@@ -100,5 +101,5 begin
100 apbo.pconfig <= pconfig;
101 apbo.pconfig <= pconfig;
101 end process;
102 end process;
102
103
103
104 apbo.prdata <= Rdata when apbi.penable = '1';
104 end ar_APB_MULTI_DIODE;
105 end ar_APB_MULTI_DIODE;
Show file before | Show file after | Hide comments
@@ -60,7 +60,7 type LEDregs is record
60 end record;
60 end record;
61
61
62 signal r : LEDregs;
62 signal r : LEDregs;
63
63 signal Rdata : std_logic_vector(31 downto 0);
64
64
65 begin
65 begin
66
66
@@ -71,7 +71,7 begin
71 if rst = '0' then
71 if rst = '0' then
72 LED <= '0';
72 LED <= '0';
73 r.DATAin <= (others => '0');
73 r.DATAin <= (others => '0');
74 apbo.prdata <= (others => '0');
74
75 elsif clk'event and clk = '1' then
75 elsif clk'event and clk = '1' then
76
76
77 LED <= r.DATAin(0);
77 LED <= r.DATAin(0);
@@ -87,12 +87,12 begin
87 end if;
87 end if;
88
88
89 --APB READ OP
89 --APB READ OP
90 if (apbi.psel(pindex) and apbi.penable and (not apbi.pwrite)) = '1' then
90 if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
91 case apbi.paddr(abits-1 downto 2) is
91 case apbi.paddr(abits-1 downto 2) is
92 when "000000" =>
92 when "000000" =>
93 apbo.prdata <= r.DATAin;
93 Rdata <= r.DATAin;
94 when others =>
94 when others =>
95 apbo.prdata <= r.DATAout;
95 Rdata <= r.DATAout;
96 end case;
96 end case;
97 end if;
97 end if;
98
98
@@ -100,7 +100,7 begin
100 apbo.pconfig <= pconfig;
100 apbo.pconfig <= pconfig;
101 end process;
101 end process;
102
102
103
103 apbo.prdata <= Rdata when apbi.penable = '1';
104
104
105 -- pragma translate_off
105 -- pragma translate_off
106 -- bootmsg : report_version
106 -- bootmsg : report_version
Show file before | Show file after | Hide comments
@@ -44,7 +44,7 CLKINT_1 : CLKINT
44 port map(A => rst, Y => raz);
44 port map(A => rst, Y => raz);
45
45
46
46
47 SystemCLK : entity work.Clock_Serie
47 SystemCLK : entity work.Systeme_Clock
48 generic map (nb_serial)
48 generic map (nb_serial)
49 port map (clk,raz,s_SCLK);
49 port map (clk,raz,s_SCLK);
50
50
Show file before | Show file after | Hide comments
@@ -46,7 +46,7 component CNA_TabloC is
46 end component;
46 end component;
47
47
48
48
49 component Clock_Serie is
49 component Systeme_Clock is
50 generic(N :integer := 695);
50 generic(N :integer := 695);
51 port(
51 port(
52 clk, raz : in std_logic ;
52 clk, raz : in std_logic ;
Show file before | Show file after | Hide comments
@@ -67,6 +67,7 type UART_ctrlr_Reg is record
67 end record;
67 end record;
68
68
69 signal Rec : UART_ctrlr_Reg;
69 signal Rec : UART_ctrlr_Reg;
70 signal Rdata : std_logic_vector(31 downto 0);
70
71
71 begin
72 begin
72
73
@@ -86,7 +87,7 Rec.UART_Cfg(4) <= NwData;
86 begin
87 begin
87 if(rst='0')then
88 if(rst='0')then
88 Rec.UART_Wdata <= (others => '0');
89 Rec.UART_Wdata <= (others => '0');
89 apbo.prdata <= (others => '0');
90
90
91
91 elsif(clk'event and clk='1')then
92 elsif(clk'event and clk='1')then
92
93
@@ -104,18 +105,18 Rec.UART_Cfg(4) <= NwData;
104 end if;
105 end if;
105
106
106 --APB READ OP
107 --APB READ OP
107 if (apbi.psel(pindex) and apbi.penable and (not apbi.pwrite)) = '1' then
108 if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
108 case apbi.paddr(abits-1 downto 2) is
109 case apbi.paddr(abits-1 downto 2) is
109 when "000000" =>
110 when "000000" =>
110 apbo.prdata(31 downto 27) <= Rec.UART_Cfg;
111 Rdata(31 downto 27) <= Rec.UART_Cfg;
111 apbo.prdata(26 downto 12) <= (others => '0');
112 Rdata(26 downto 12) <= (others => '0');
112 apbo.prdata(11 downto 0) <= Rec.UART_BTrig;
113 Rdata(11 downto 0) <= Rec.UART_BTrig;
113 when "000001" =>
114 when "000001" =>
114 apbo.prdata(7 downto 0) <= Rec.UART_Wdata;
115 Rdata(7 downto 0) <= Rec.UART_Wdata;
115 when "000010" =>
116 when "000010" =>
116 apbo.prdata(7 downto 0) <= Rec.UART_Rdata;
117 Rdata(7 downto 0) <= Rec.UART_Rdata;
117 when others =>
118 when others =>
118 apbo.prdata <= (others => '0');
119 Rdata <= (others => '0');
119 end case;
120 end case;
120 end if;
121 end if;
121
122
@@ -123,4 +124,6 Rec.UART_Cfg(4) <= NwData;
123 apbo.pconfig <= pconfig;
124 apbo.pconfig <= pconfig;
124 end process;
125 end process;
125
126
127 apbo.prdata <= Rdata when apbi.penable = '1';
128
126 end ar_APB_UART;
129 end ar_APB_UART;
Show file before | Show file after | Hide comments
1 NO CONTENT: file was removed
NO CONTENT: file was removed
Show file before | Show file after | Hide comments
1 NO CONTENT: file was removed
NO CONTENT: file was removed
Show file before | Show file after | Hide comments
1 NO CONTENT: file was removed
NO CONTENT: file was removed
Show file before | Show file after | Hide comments
1 NO CONTENT: file was removed
NO CONTENT: file was removed
Show file before | Show file after | Hide comments
1 NO CONTENT: file was removed
NO CONTENT: file was removed
Show file before | Show file after | Hide comments
1 NO CONTENT: file was removed
NO CONTENT: file was removed
Show file before | Show file after | Hide comments
1 NO CONTENT: file was removed
NO CONTENT: file was removed
General Comments 0
You need to be logged in to leave comments. Login now