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DAC CAL input data via Registre_data Driver C
martin -
r261:489b6615789a martin
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@@ -0,0 +1,53
1 -- Bridge.vhd
2 library IEEE;
3 use IEEE.std_logic_1164.all;
4 use IEEE.numeric_std.all;
5
6 entity Bridge is
7 port(
8 clk : in std_logic;
9 raz : in std_logic;
10 EmptyUp : in std_logic;
11 FullDwn : in std_logic;
12 WriteDwn : out std_logic;
13 ReadUp : out std_logic
14 );
15 end entity;
16
17
18 architecture ar_Bridge of Bridge is
19
20 type etat is (e0,e1);
21 signal ect : etat;
22
23 begin
24
25 process(clk,raz)
26 begin
27 if(raz='0')then
28 WriteDwn <= '1';
29 ReadUp <= '1';
30 ect <= e0;
31
32 elsif(clk'event and clk='1')then
33
34 case ect is
35
36 when e0 =>
37 WriteDwn <= '1';
38 if(EmptyUp='0' and FullDwn='0')then
39 ReadUp <= '0';
40 ect <= e1;
41 end if;
42
43 when e1 =>
44 ReadUp <= '1';
45 WriteDwn <= '0';
46 ect <= e0;
47
48 end case;
49
50 end if;
51 end process;
52
53 end architecture; No newline at end of file
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@@ -45,9 +45,7 entity APB_DAC is
45 45 rst : in std_logic; --! Reset general du composant
46 46 apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus
47 47 apbo : out apb_slv_out_type; --! Registre de gestion des sorties du bus
48 DataIN : in std_logic_vector(15 downto 0);
49 48 Cal_EN : out std_logic; --! Signal Enable du multiplex pour la CAL
50 Readn : out std_logic;
51 49 SYNC : out std_logic; --! Signal de synchronisation du convertisseur
52 50 SCLK : out std_logic; --! Horloge systeme du convertisseur
53 51 DATA : out std_logic --! Donn�e num�rique s�rialis�
@@ -66,11 +64,11 constant pconfig : apb_config_type := (
66 64 1 => apb_iobar(paddr, pmask));
67 65
68 66 signal enable : std_logic;
69 --signal flag_sd : std_logic;
67 signal Ready : std_logic;
70 68
71 69 type DAC_ctrlr_Reg is record
72 DAC_Enable : std_logic_vector(0 downto 0);
73 -- DAC_Data : std_logic_vector(15 downto 0);
70 DAC_Cfg : std_logic_vector(1 downto 0);
71 DAC_Data : std_logic_vector(15 downto 0);
74 72 end record;
75 73
76 74 signal Rec : DAC_ctrlr_Reg;
@@ -78,19 +76,18 signal Rdata : std_logic_vector(31 d
78 76
79 77 begin
80 78
81 enable <= Rec.DAC_Enable(0);
82 --Rec.DAC_Cfg(1) <= flag_sd;
79 enable <= Rec.DAC_Cfg(0);
80 Rec.DAC_Cfg(1) <= Ready;
83 81
84 82 CONV0 : DacDriver
85 generic map(cpt_serial)
86 port map(clk,rst,enable,DataIN,SYNC,SCLK,Readn,Data);
83 generic map (cpt_serial)
84 port map(clk,rst,enable,Rec.DAC_Data,SYNC,SCLK,Ready,Data);
87 85
88 86
89 87 process(rst,clk)
90 88 begin
91 89 if(rst='0')then
92 --Rec.DAC_Data <= (others => '0');
93 Rec.DAC_Enable(0) <= '0';
90 Rec.DAC_Data <= (others => '0');
94 91
95 92 elsif(clk'event and clk='1')then
96 93
@@ -99,9 +96,9 enable <= Rec.DAC_Enable(0);
99 96 if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
100 97 case apbi.paddr(abits-1 downto 2) is
101 98 when "000000" =>
102 Rec.DAC_Enable(0) <= apbi.pwdata(0);
103 -- when "000001" =>
104 -- Rec.DAC_Data <= apbi.pwdata(15 downto 0);
99 Rec.DAC_Cfg(0) <= apbi.pwdata(0);
100 when "000001" =>
101 Rec.DAC_Data <= apbi.pwdata(15 downto 0);
105 102 when others =>
106 103 null;
107 104 end case;
@@ -111,11 +108,11 enable <= Rec.DAC_Enable(0);
111 108 if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
112 109 case apbi.paddr(abits-1 downto 2) is
113 110 when "000000" =>
114 Rdata(31 downto 1) <= (others => '0');--X"ABCDEF5" & "00";
115 Rdata(0 downto 0) <= Rec.DAC_Enable;
116 -- when "000001" =>
117 -- Rdata(31 downto 16) <= X"FD18";
118 -- Rdata(15 downto 0) <= Rec.DAC_Data;
111 Rdata(31 downto 2) <= X"ABCDEF5" & "00";
112 Rdata(1 downto 0) <= Rec.DAC_Cfg;
113 when "000001" =>
114 Rdata(31 downto 16) <= X"FD18";
115 Rdata(15 downto 0) <= Rec.DAC_Data;
119 116 when others =>
120 117 Rdata <= (others => '0');
121 118 end case;
@@ -126,5 +123,5 enable <= Rec.DAC_Enable(0);
126 123 end process;
127 124
128 125 apbo.prdata <= Rdata when apbi.penable = '1';
129 Cal_EN <= Rec.DAC_Enable(0);
126 Cal_EN <= enable;
130 127 end architecture; No newline at end of file
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@@ -27,15 +27,15 use lpp.lpp_cna.all;
27 27 --! Programme du Convertisseur Num�rique/Analogique
28 28
29 29 entity DacDriver is
30 generic(cpt_serial : integer := 6); --! G�n�rique contenant le r�sultat de la division clk/sclk !!! clk=25Mhz
30 generic(cpt_serial : integer := 6); --! G�n�rique contenant le r�sultat de la division clk/sclk !!! clk=25Mhz
31 31 port(
32 32 clk : in std_logic; --! Horloge du composant
33 33 rst : in std_logic; --! Reset general du composant
34 34 enable : in std_logic; --! Autorise ou non l'utilisation du composant
35 Data_reg : in std_logic_vector(15 downto 0); --! Donn�e Num�rique d'entr�e sur 16 bits
35 Data_C : in std_logic_vector(15 downto 0); --! Donn�e Num�rique d'entr�e sur 16 bits
36 36 SYNC : out std_logic; --! Signal de synchronisation du convertisseur
37 37 SCLK : out std_logic; --! Horloge systeme du convertisseur
38 Readn : out std_logic;
38 Ready : out std_logic; --! Flag, signale la fin de la s�rialisation d'une donn�e
39 39 Data : out std_logic --! Donn�e num�rique s�rialis�
40 40 );
41 41 end entity;
@@ -46,7 +46,7 end entity;
46 46 architecture ar_DacDriver of DacDriver is
47 47
48 48 signal s_SCLK : std_logic;
49 signal s_SYNC : std_logic;
49 signal Sended : std_logic;
50 50
51 51 begin
52 52
@@ -56,16 +56,13 SystemCLK : Systeme_Clock
56 56
57 57
58 58 Signal_sync : Gene_SYNC
59 port map (s_SCLK,rst,enable,s_SYNC);
59 port map (s_SCLK,rst,enable,Sended,SYNC);
60 60
61 61
62 62 Serial : serialize
63 port map (clk,rst,s_SCLK,Data_reg,s_SYNC,Data);
63 port map (clk,rst,s_SCLK,Data_C,Sended,Ready,Data);
64 64
65 RenGEN : ReadFifo_GEN
66 port map (clk,rst,s_SYNC,Readn);
67 65
68 66 SCLK <= s_SCLK;
69 SYNC <= s_SYNC;
70 67
71 68 end architecture; No newline at end of file
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@@ -29,7 +29,7 entity Gene_SYNC is
29 29 port(
30 30 SCLK,raz : in std_logic; --! Horloge systeme et Reset du composant
31 31 enable : in std_logic; --! Autorise ou non l'utilisation du composant
32 -- OKAI_send : out std_logic; --! Flag, Autorise l'envoi (s�rialisation) d'une nouvelle donn�e
32 Sended : out std_logic; --! Flag, Autorise l'envoi (s�rialisation) d'une nouvelle donn�e
33 33 SYNC : out std_logic --! Signal de synchronisation du convertisseur g�n�r�
34 34 );
35 35 end Gene_SYNC;
@@ -46,22 +46,21 begin
46 46 if(raz='0')then
47 47 SYNC <= '0';
48 48 count <= 14;
49 -- OKAI_send <= '0';
49 Sended <= '0';
50 50
51 51 elsif(SCLK' event and SCLK='1')then
52 52 if(enable='1')then
53 53
54 54 if(count=15)then
55 55 SYNC <= '1';
56 -- count <= count+1;
57 -- elsif(count=16)then
56 count <= count+1;
57 elsif(count=16)then
58 58 count <= 0;
59 -- SYNC <= '0';
60 -- OKAI_send <= '1';
59 SYNC <= '0';
60 Sended <= '1';
61 61 else
62 62 count <= count+1;
63 SYNC <= '0';
64 -- OKAI_send <= '0';
63 Sended <= '0';
65 64 end if;
66 65
67 66 end if;
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@@ -31,7 +31,7 entity Serialize is
31 31 sclk : in std_logic; --! Horloge Systeme
32 32 vectin : in std_logic_vector(15 downto 0); --! Vecteur d'entr�e
33 33 send : in std_logic; --! Flag, Une nouvelle donn�e est pr�sente
34 -- sended : out std_logic; --! Flag, La donn�e a �t� s�rialis�e
34 sended : out std_logic; --! Flag, La donn�e a �t� s�rialis�e
35 35 Data : out std_logic --! Donn�e num�rique s�rialis�
36 36 );
37 37 end Serialize;
@@ -39,7 +39,7 end Serialize;
39 39
40 40 architecture ar_Serialize of Serialize is
41 41
42 type etat is (attente,serialize,reg);
42 type etat is (attente,serialize);
43 43 signal ect : etat;
44 44
45 45 signal vector_int : std_logic_vector(16 downto 0);
@@ -47,7 +47,6 signal vectin_reg : std_logic_vector(1
47 47 signal load : std_logic;
48 48 signal N : integer range 0 to 16;
49 49 signal CPT_ended : std_logic:='0';
50 signal i : std_logic;
51 50
52 51 begin
53 52 process(clk,raz)
@@ -56,8 +55,7 begin
56 55 ect <= attente;
57 56 vectin_reg <= (others=> '0');
58 57 load <= '0';
59 i <= '1';
60 -- sended <= '1';
58 sended <= '1';
61 59
62 60 elsif(clk'event and clk='1')then
63 61 vectin_reg <= vectin;
@@ -65,25 +63,18 begin
65 63 case ect is
66 64 when attente =>
67 65 if (send='1') then
68 -- sended <= '0';
69 if(i='1')then
70 i <= '0';
71 ect <= reg;
72 else
73 load <= '1';
74 ect <= serialize;
75 end if;
66 sended <= '0';
67 load <= '1';
68 ect <= serialize;
69 else
70 ect <= attente;
76 71 end if;
77 72
78 when reg =>
79 load <= '1';
80 ect <= serialize;
81
82 73 when serialize =>
83 74 load <= '0';
84 75 if(CPT_ended='1')then
85 76 ect <= attente;
86 -- sended <= '1';
77 sended <= '1';
87 78 end if;
88 79
89 80 end case;
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@@ -1,108 +1,96
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
22 library ieee;
23 use ieee.std_logic_1164.all;
24 library grlib;
25 use grlib.amba.all;
26 use std.textio.all;
27 library lpp;
28 use lpp.lpp_amba.all;
29
30 --! Package contenant tous les programmes qui forment le composant int�gr� dans le l�on
31
32 package lpp_cna is
33
34 component APB_DAC is
35 generic (
36 pindex : integer := 0;
37 paddr : integer := 0;
38 pmask : integer := 16#fff#;
39 pirq : integer := 0;
40 abits : integer := 8;
41 cpt_serial : integer := 6);
42 port (
43 clk : in std_logic;
44 rst : in std_logic;
45 apbi : in apb_slv_in_type;
46 apbo : out apb_slv_out_type;
47 DataIN : in std_logic_vector(15 downto 0);
48 Cal_EN : out std_logic;
49 Readn : out std_logic;
50 SYNC : out std_logic;
51 SCLK : out std_logic;
52 DATA : out std_logic
53 );
54 end component;
55
56
57 component DacDriver is
58 generic(cpt_serial : integer := 6);
59 port(
60 clk : in std_logic;
61 rst : in std_logic;
62 enable : in std_logic;
63 Data_reg : in std_logic_vector(15 downto 0);
64 SYNC : out std_logic;
65 SCLK : out std_logic;
66 Readn : out std_logic;
67 Data : out std_logic
68 );
69 end component;
70
71
72 component Systeme_Clock is
73 generic(N :integer := 695);
74 port(
75 clk, raz : in std_logic ;
76 clock : out std_logic);
77 end component;
78
79
80 component Gene_SYNC is
81 port(
82 SCLK,raz : in std_logic; --! Horloge systeme et Reset du composant
83 enable : in std_logic; --! Autorise ou non l'utilisation du composant
84 -- OKAI_send : out std_logic; --! Flag, Autorise l'envoi (s�rialisation) d'une nouvelle donn�e
85 SYNC : out std_logic --! Signal de synchronisation du convertisseur g�n�r�
86 );
87 end component;
88
89
90 component Serialize is
91 port(
92 clk,raz : in std_logic;
93 sclk : in std_logic;
94 vectin : in std_logic_vector(15 downto 0);
95 send : in std_logic;
96 -- sended : out std_logic;
97 Data : out std_logic);
98 end component;
99
100 component ReadFifo_GEN is
101 port(
102 clk,raz : in std_logic;
103 SYNC : in std_logic;
104 Readn : out std_logic
105 );
106 end component;
107
108 end;
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
22 library ieee;
23 use ieee.std_logic_1164.all;
24 library grlib;
25 use grlib.amba.all;
26 use std.textio.all;
27 library lpp;
28 use lpp.lpp_amba.all;
29
30 --! Package contenant tous les programmes qui forment le composant int�gr� dans le l�on
31
32 package lpp_cna is
33
34 component APB_DAC is
35 generic (
36 pindex : integer := 0;
37 paddr : integer := 0;
38 pmask : integer := 16#fff#;
39 pirq : integer := 0;
40 abits : integer := 8);
41 port (
42 clk : in std_logic;
43 rst : in std_logic;
44 apbi : in apb_slv_in_type;
45 apbo : out apb_slv_out_type;
46 Cal_EN : out std_logic;
47 SYNC : out std_logic;
48 SCLK : out std_logic;
49 DATA : out std_logic
50 );
51 end component;
52
53
54 component DacDriver is
55 generic(cpt_serial : integer := 6); --! G�n�rique contenant le r�sultat de la division clk/sclk !!! clk=25Mhz
56 port(
57 clk : in std_logic;
58 rst : in std_logic;
59 enable : in std_logic;
60 Data_C : in std_logic_vector(15 downto 0);
61 SYNC : out std_logic;
62 SCLK : out std_logic;
63 Ready : out std_logic;
64 Data : out std_logic
65 );
66 end component;
67
68
69 component Systeme_Clock is
70 generic(N :integer := 695);
71 port(
72 clk, raz : in std_logic ;
73 sclk : out std_logic);
74 end component;
75
76
77 component Gene_SYNC is
78 port(
79 SCLK,raz : in std_logic; --! Horloge systeme et Reset du composant
80 enable : in std_logic; --! Autorise ou non l'utilisation du composant
81 Sended : out std_logic; --! Flag, Autorise l'envoi (s�rialisation) d'une nouvelle donn�e
82 SYNC : out std_logic); --! Signal de synchronisation du convertisseur g�n�r�
83 end component;
84
85
86 component Serialize is
87 port(
88 clk,raz : in std_logic;
89 sclk : in std_logic;
90 vectin : in std_logic_vector(15 downto 0);
91 send : in std_logic;
92 sended : out std_logic;
93 Data : out std_logic);
94 end component;
95
96 end; No newline at end of file
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@@ -135,6 +135,17 port(
135 135 );
136 136 end component;
137 137
138 component Bridge is
139 port(
140 clk : in std_logic;
141 raz : in std_logic;
142 EmptyUp : in std_logic;
143 FullDwn : in std_logic;
144 WriteDwn : out std_logic;
145 ReadUp : out std_logic
146 );
147 end component;
148
138 149 component ssram_plugin is
139 150 generic (tech : integer := 0);
140 151 port
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@@ -1,8 +1,10
1 1 lpp_memory.vhd
2 2 lpp_FIFO.vhd
3 3 FillFifo.vhd
4 Bridge.vhd
4 5 APB_FIFO.vhd
5 6 Bridge.vhd
6 7 SSRAM_plugin.vhd
7 8 lppFIFOx5.vhd
8 9 lppFIFOxN.vhd
10
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