# HG changeset patch
# User martin
# Date 2013-12-03 13:35:32
# Node ID 489b6615789aa60f4dcc761994a312814524107e
# Parent  d170a7fb48c0e1e91d0fe393bdd68bafb85ce149

DAC CAL input data via Registre_data Driver C

diff --git a/lib/lpp/lpp_cna/APB_DAC.vhd b/lib/lpp/lpp_cna/APB_DAC.vhd
--- a/lib/lpp/lpp_cna/APB_DAC.vhd
+++ b/lib/lpp/lpp_cna/APB_DAC.vhd
@@ -45,9 +45,7 @@ entity APB_DAC is
     rst     : in  std_logic;           --! Reset general du composant
     apbi    : in  apb_slv_in_type;     --! Registre de gestion des entr�es du bus
     apbo    : out apb_slv_out_type;    --! Registre de gestion des sorties du bus
-    DataIN : in std_logic_vector(15 downto 0);
     Cal_EN  : out std_logic;           --! Signal Enable du multiplex pour la CAL
-    Readn   : out std_logic;
     SYNC    : out std_logic;           --! Signal de synchronisation du convertisseur
     SCLK    : out std_logic;           --! Horloge systeme du convertisseur
     DATA    : out std_logic            --! Donn�e num�rique s�rialis�
@@ -66,11 +64,11 @@ constant pconfig : apb_config_type := (
   1 => apb_iobar(paddr, pmask));
 
 signal enable   : std_logic;
---signal flag_sd : std_logic;
+signal Ready : std_logic;
 
 type DAC_ctrlr_Reg is record
-     DAC_Enable  : std_logic_vector(0 downto 0);
---     DAC_Data : std_logic_vector(15 downto 0);
+     DAC_Cfg  : std_logic_vector(1 downto 0);
+     DAC_Data : std_logic_vector(15 downto 0);
 end record;
 
 signal Rec : DAC_ctrlr_Reg;
@@ -78,19 +76,18 @@ signal Rdata     : std_logic_vector(31 d
 
 begin
 
-enable <= Rec.DAC_Enable(0);
---Rec.DAC_Cfg(1) <= flag_sd;
+enable <= Rec.DAC_Cfg(0);
+Rec.DAC_Cfg(1) <= Ready;
 
     CONV0 : DacDriver
-        generic map(cpt_serial)
-        port map(clk,rst,enable,DataIN,SYNC,SCLK,Readn,Data);
+        generic map (cpt_serial)
+        port map(clk,rst,enable,Rec.DAC_Data,SYNC,SCLK,Ready,Data);
 
 
     process(rst,clk)
     begin
         if(rst='0')then
-            --Rec.DAC_Data <=  (others => '0');
-            Rec.DAC_Enable(0) <= '0';
+            Rec.DAC_Data <=  (others => '0');
 
         elsif(clk'event and clk='1')then 
         
@@ -99,9 +96,9 @@ enable <= Rec.DAC_Enable(0);
             if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
                 case apbi.paddr(abits-1 downto 2) is
                     when "000000" =>
-                        Rec.DAC_Enable(0) <= apbi.pwdata(0);
---                    when "000001" =>
---                        Rec.DAC_Data <= apbi.pwdata(15 downto 0);
+                        Rec.DAC_Cfg(0) <= apbi.pwdata(0);
+                    when "000001" =>
+                        Rec.DAC_Data <= apbi.pwdata(15 downto 0);
                     when others =>
                         null;
                 end case;
@@ -111,11 +108,11 @@ enable <= Rec.DAC_Enable(0);
             if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
                 case apbi.paddr(abits-1 downto 2) is
                     when "000000" =>
-                        Rdata(31 downto 1) <= (others => '0');--X"ABCDEF5" & "00";
-                        Rdata(0 downto 0) <= Rec.DAC_Enable;
- --                   when "000001" =>
- --                       Rdata(31 downto 16) <= X"FD18";
- --                       Rdata(15 downto 0) <= Rec.DAC_Data;
+                        Rdata(31 downto 2) <= X"ABCDEF5" & "00";
+                        Rdata(1 downto 0) <= Rec.DAC_Cfg;
+                    when "000001" =>
+                        Rdata(31 downto 16) <= X"FD18";
+                        Rdata(15 downto 0) <= Rec.DAC_Data;
                     when others =>
                         Rdata <= (others => '0');
                 end case;
@@ -126,5 +123,5 @@ enable <= Rec.DAC_Enable(0);
     end process;
 
 apbo.prdata     <=   Rdata when apbi.penable = '1';
-Cal_EN <= Rec.DAC_Enable(0);
+Cal_EN <= enable;
 end architecture;
\ No newline at end of file
diff --git a/lib/lpp/lpp_cna/DacDriver.vhd b/lib/lpp/lpp_cna/DacDriver.vhd
--- a/lib/lpp/lpp_cna/DacDriver.vhd
+++ b/lib/lpp/lpp_cna/DacDriver.vhd
@@ -27,15 +27,15 @@ use lpp.lpp_cna.all;
 --! Programme du Convertisseur Num�rique/Analogique
 
 entity DacDriver is
-  generic(cpt_serial : integer := 6);  --! G�n�rique contenant le r�sultat de la division clk/sclk  !!! clk=25Mhz
+generic(cpt_serial : integer := 6);  --! G�n�rique contenant le r�sultat de la division clk/sclk  !!! clk=25Mhz
   port(
     clk         : in std_logic;                        --! Horloge du composant
     rst         : in std_logic;                        --! Reset general du composant
     enable      : in std_logic;                        --! Autorise ou non l'utilisation du composant
-    Data_reg    : in std_logic_vector(15 downto 0);    --! Donn�e Num�rique d'entr�e sur 16 bits
+    Data_C      : in std_logic_vector(15 downto 0);    --! Donn�e Num�rique d'entr�e sur 16 bits
     SYNC        : out std_logic;                       --! Signal de synchronisation du convertisseur
     SCLK        : out std_logic;                       --! Horloge systeme du convertisseur
-    Readn       : out std_logic;                       
+    Ready     : out std_logic;                       --! Flag, signale la fin de la s�rialisation d'une donn�e
     Data        : out std_logic                        --! Donn�e num�rique s�rialis�
     );
 end entity;
@@ -46,7 +46,7 @@ end entity;
 architecture ar_DacDriver of DacDriver is
 
 signal s_SCLK      : std_logic;
-signal s_SYNC    : std_logic;
+signal Sended    : std_logic;
 
 begin
 
@@ -56,16 +56,13 @@ SystemCLK : Systeme_Clock
 
 
 Signal_sync : Gene_SYNC
-    port map (s_SCLK,rst,enable,s_SYNC);
+    port map (s_SCLK,rst,enable,Sended,SYNC);
 
 
 Serial : serialize
-    port map (clk,rst,s_SCLK,Data_reg,s_SYNC,Data);
+    port map (clk,rst,s_SCLK,Data_C,Sended,Ready,Data);
 
-RenGEN : ReadFifo_GEN
-    port map (clk,rst,s_SYNC,Readn);
 
 SCLK        <= s_SCLK;
-SYNC        <= s_SYNC;
 
 end architecture;
\ No newline at end of file
diff --git a/lib/lpp/lpp_cna/Gene_SYNC.vhd b/lib/lpp/lpp_cna/Gene_SYNC.vhd
--- a/lib/lpp/lpp_cna/Gene_SYNC.vhd
+++ b/lib/lpp/lpp_cna/Gene_SYNC.vhd
@@ -29,7 +29,7 @@ entity Gene_SYNC is
   port(
     SCLK,raz : in std_logic;     --! Horloge systeme et Reset du composant
     enable : in std_logic;       --! Autorise ou non l'utilisation du composant
---    OKAI_send : out std_logic;   --! Flag, Autorise l'envoi (s�rialisation) d'une nouvelle donn�e
+    Sended : out std_logic;   --! Flag, Autorise l'envoi (s�rialisation) d'une nouvelle donn�e
     SYNC : out std_logic         --! Signal de synchronisation du convertisseur g�n�r�
     );
 end Gene_SYNC;
@@ -46,22 +46,21 @@ begin
         if(raz='0')then
             SYNC <= '0';
             count <= 14;  
---            OKAI_send <= '0';         
+            Sended <= '0';
         
         elsif(SCLK' event and SCLK='1')then    
             if(enable='1')then
 
                 if(count=15)then
                     SYNC <= '1';
---                    count <= count+1;
---                elsif(count=16)then
+                    count <= count+1;
+                elsif(count=16)then
                     count <= 0;
---                    SYNC <= '0';
---                    OKAI_send <= '1';
+                    SYNC <= '0';
+                    Sended <= '1';
                 else
                     count <= count+1;
-                    SYNC <= '0';
---                    OKAI_send <= '0';
+                    Sended <= '0';
                 end if;
 
             end if;
diff --git a/lib/lpp/lpp_cna/ReadFifo_GEN.vhd b/lib/lpp/lpp_cna/ReadFifo_GEN.vhd
deleted file mode 100644
--- a/lib/lpp/lpp_cna/ReadFifo_GEN.vhd
+++ /dev/null
@@ -1,67 +0,0 @@
-------------------------------------------------------------------------------
---  This file is a part of the LPP VHDL IP LIBRARY
---  Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
---
---  This program is free software; you can redistribute it and/or modify
---  it under the terms of the GNU General Public License as published by
---  the Free Software Foundation; either version 3 of the License, or
---  (at your option) any later version.
---
---  This program is distributed in the hope that it will be useful,
---  but WITHOUT ANY WARRANTY; without even the implied warranty of
---  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
---  GNU General Public License for more details.
---
---  You should have received a copy of the GNU General Public License
---  along with this program; if not, write to the Free Software
---  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
-------------------------------------------------------------------------------
---                    Author : Martin Morlot
---                     Mail : martin.morlot@lpp.polytechnique.fr
-------------------------------------------------------------------------------
-library IEEE;
-use IEEE.numeric_std.all;
-use IEEE.std_logic_1164.all;
-
-entity ReadFifo_GEN is
-  port(
-    clk,raz : in std_logic;                      --! Horloge et Reset du composant
-    SYNC : in std_logic;
-    Readn : out std_logic
-    );
-end entity;
-
-
-architecture ar_ReadFifo_GEN of ReadFifo_GEN is
-
-type etat is (eX,e0);
-signal ect      : etat;
-
-signal SYNC_reg : std_logic;
-
-begin
-    process(clk,raz)
-        begin
-        if(raz='0')then           
-            ect         <= eX;
-            Readn  <= '1';           
-
-        elsif(clk'event and clk='1')then
-            SYNC_reg <= SYNC;
-          
-            case ect is
-                when eX =>                     
-                    if (SYNC_reg='0' and  SYNC='1') then 
-                        Readn    <= '0';                   
-                        ect     <= e0;                      
-                    end if;
-                
-                when e0 => 
-                    Readn <= '1';                    
-                    ect <= eX;
-
-            end case;
-        end if;
-    end process;
-
-end architecture;
\ No newline at end of file
diff --git a/lib/lpp/lpp_cna/Serialize.vhd b/lib/lpp/lpp_cna/Serialize.vhd
--- a/lib/lpp/lpp_cna/Serialize.vhd
+++ b/lib/lpp/lpp_cna/Serialize.vhd
@@ -31,7 +31,7 @@ entity Serialize is
     sclk    : in std_logic;                      --! Horloge Systeme
     vectin  : in std_logic_vector(15 downto 0);  --! Vecteur d'entr�e
     send    : in std_logic;                      --! Flag, Une nouvelle donn�e est pr�sente
---    sended  : out std_logic;                     --! Flag, La donn�e a �t� s�rialis�e
+    sended  : out std_logic;                     --! Flag, La donn�e a �t� s�rialis�e
     Data    : out std_logic                      --! Donn�e num�rique s�rialis�
     );
 end Serialize;
@@ -39,7 +39,7 @@ end Serialize;
 
 architecture ar_Serialize of Serialize is
 
-type etat is (attente,serialize,reg);
+type etat is (attente,serialize);
 signal ect      : etat;
 
 signal vector_int   : std_logic_vector(16 downto 0);
@@ -47,7 +47,6 @@ signal vectin_reg   : std_logic_vector(1
 signal load         : std_logic;
 signal N            : integer range 0 to 16;
 signal CPT_ended    : std_logic:='0';
-signal i            : std_logic;
 
 begin
     process(clk,raz)
@@ -56,8 +55,7 @@ begin
             ect         <= attente;
             vectin_reg  <= (others=> '0');
             load        <= '0';
-            i <= '1';
---            sended      <= '1';            
+            sended      <= '1';            
 
         elsif(clk'event and clk='1')then
             vectin_reg <= vectin;
@@ -65,25 +63,18 @@ begin
             case ect is
                 when attente =>                     
                     if (send='1') then 
---                        sended  <= '0';                        
-                        if(i='1')then
-                            i <= '0';
-                            ect <= reg;                  
-                        else
-                            load    <= '1';
-                            ect     <= serialize;                        
-                        end if;                        
+                        sended  <= '0'; 
+                        load    <= '1';                   
+                        ect     <= serialize;                        
+                    else
+                        ect <= attente;                       
                     end if;
                 
-                when reg =>
-                    load    <= '1';
-                    ect <= serialize;
-                
                 when serialize => 
                     load <= '0';                    
                     if(CPT_ended='1')then 
                         ect     <= attente;
---                        sended  <= '1';                        
+                        sended  <= '1';                        
                     end if;
 
             end case;
diff --git a/lib/lpp/lpp_cna/lpp_cna.vhd b/lib/lpp/lpp_cna/lpp_cna.vhd
--- a/lib/lpp/lpp_cna/lpp_cna.vhd
+++ b/lib/lpp/lpp_cna/lpp_cna.vhd
@@ -1,108 +1,96 @@
-------------------------------------------------------------------------------
---  This file is a part of the LPP VHDL IP LIBRARY
---  Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
---
---  This program is free software; you can redistribute it and/or modify
---  it under the terms of the GNU General Public License as published by
---  the Free Software Foundation; either version 3 of the License, or
---  (at your option) any later version.
---
---  This program is distributed in the hope that it will be useful,
---  but WITHOUT ANY WARRANTY; without even the implied warranty of
---  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
---  GNU General Public License for more details.
---
---  You should have received a copy of the GNU General Public License
---  along with this program; if not, write to the Free Software
---  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
-------------------------------------------------------------------------------
---                    Author : Martin Morlot
---                     Mail : martin.morlot@lpp.polytechnique.fr
-------------------------------------------------------------------------------
-library ieee;
-use ieee.std_logic_1164.all;
-library grlib;
-use grlib.amba.all;
-use std.textio.all;
-library lpp;
-use lpp.lpp_amba.all;
-
---! Package contenant tous les programmes qui forment le composant int�gr� dans le l�on
-
-package lpp_cna is
-
-component APB_DAC is
-  generic (
-    pindex   : integer := 0;
-    paddr    : integer := 0;
-    pmask    : integer := 16#fff#;
-    pirq     : integer := 0;
-    abits    : integer := 8;
-    cpt_serial : integer := 6);
-  port (
-    clk     : in  std_logic;
-    rst     : in  std_logic;
-    apbi    : in  apb_slv_in_type;
-    apbo    : out apb_slv_out_type;
-    DataIN : in std_logic_vector(15 downto 0);
-    Cal_EN  : out std_logic;
-    Readn   : out std_logic;
-    SYNC    : out std_logic;
-    SCLK    : out std_logic;
-    DATA    : out std_logic
-    );
-end component;
-
-
-component DacDriver is
-    generic(cpt_serial : integer := 6);
-    port(
-        clk       : in std_logic;
-        rst         : in std_logic;
-        enable      : in std_logic;
-        Data_reg      : in std_logic_vector(15 downto 0);
-        SYNC        : out std_logic;
-        SCLK        : out std_logic;
-        Readn     : out std_logic;
-        Data        : out std_logic
-        );
-end component;
-
-
-component Systeme_Clock is
-    generic(N :integer := 695);
-    port(
-        clk, raz   : in std_logic ;
-        clock      : out std_logic);
-end component;
-
-
-component Gene_SYNC is
-  port(
-    SCLK,raz : in std_logic;     --! Horloge systeme et Reset du composant
-    enable : in std_logic;       --! Autorise ou non l'utilisation du composant
---    OKAI_send : out std_logic;   --! Flag, Autorise l'envoi (s�rialisation) d'une nouvelle donn�e
-    SYNC : out std_logic         --! Signal de synchronisation du convertisseur g�n�r�
-    );
-end component;
-
-
-component Serialize is
-port(
-    clk,raz : in std_logic;
-    sclk    : in std_logic;
-    vectin  : in std_logic_vector(15 downto 0);
-    send    : in std_logic;
---    sended  : out std_logic;
-    Data    : out std_logic);
-end component;
-
-component ReadFifo_GEN is
-  port(
-    clk,raz : in std_logic;
-    SYNC : in std_logic;
-    Readn : out std_logic
-    );
-end component;
-
-end;
+------------------------------------------------------------------------------
+--  This file is a part of the LPP VHDL IP LIBRARY
+--  Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
+--
+--  This program is free software; you can redistribute it and/or modify
+--  it under the terms of the GNU General Public License as published by
+--  the Free Software Foundation; either version 3 of the License, or
+--  (at your option) any later version.
+--
+--  This program is distributed in the hope that it will be useful,
+--  but WITHOUT ANY WARRANTY; without even the implied warranty of
+--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+--  GNU General Public License for more details.
+--
+--  You should have received a copy of the GNU General Public License
+--  along with this program; if not, write to the Free Software
+--  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+------------------------------------------------------------------------------
+--                    Author : Martin Morlot
+--                     Mail : martin.morlot@lpp.polytechnique.fr
+------------------------------------------------------------------------------
+library ieee;
+use ieee.std_logic_1164.all;
+library grlib;
+use grlib.amba.all;
+use std.textio.all;
+library lpp;
+use lpp.lpp_amba.all;
+
+--! Package contenant tous les programmes qui forment le composant int�gr� dans le l�on
+
+package lpp_cna is
+
+component APB_DAC is
+  generic (
+    pindex   : integer := 0;
+    paddr    : integer := 0;
+    pmask    : integer := 16#fff#;
+    pirq     : integer := 0;
+    abits    : integer := 8);
+  port (
+    clk     : in  std_logic;
+    rst     : in  std_logic;
+    apbi    : in  apb_slv_in_type;
+    apbo    : out apb_slv_out_type;
+    Cal_EN  : out std_logic;
+    SYNC    : out std_logic;
+    SCLK    : out std_logic;
+    DATA    : out std_logic
+    );
+end component;
+
+
+component DacDriver is
+generic(cpt_serial : integer := 6);  --! G�n�rique contenant le r�sultat de la division clk/sclk  !!! clk=25Mhz
+    port(
+        clk       : in std_logic;
+        rst         : in std_logic;
+        enable      : in std_logic;
+        Data_C      : in std_logic_vector(15 downto 0);
+        SYNC        : out std_logic;
+        SCLK        : out std_logic;
+        Ready     : out std_logic;
+        Data        : out std_logic
+        );
+end component;
+
+
+component Systeme_Clock is
+    generic(N :integer := 695);
+    port(
+        clk, raz   : in std_logic ;
+        sclk      : out std_logic);
+end component;
+
+
+component Gene_SYNC is
+    port(
+    SCLK,raz : in std_logic;     --! Horloge systeme et Reset du composant
+    enable : in std_logic;       --! Autorise ou non l'utilisation du composant
+    Sended : out std_logic;   --! Flag, Autorise l'envoi (s�rialisation) d'une nouvelle donn�e
+    SYNC : out std_logic);         --! Signal de synchronisation du convertisseur g�n�r�
+end component;
+
+
+component Serialize is
+port(
+    clk,raz : in std_logic;
+    sclk    : in std_logic;
+    vectin  : in std_logic_vector(15 downto 0);
+    send    : in std_logic;
+    sended  : out std_logic;
+    Data    : out std_logic);
+end component;
+
+end;
\ No newline at end of file
diff --git a/lib/lpp/lpp_memory/Bridge.vhd b/lib/lpp/lpp_memory/Bridge.vhd
new file mode 100644
--- /dev/null
+++ b/lib/lpp/lpp_memory/Bridge.vhd
@@ -0,0 +1,53 @@
+-- Bridge.vhd
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity Bridge is
+    port(
+        clk         : in std_logic;
+        raz        : in std_logic;
+        EmptyUp : in std_logic;
+        FullDwn : in std_logic;
+        WriteDwn : out std_logic;
+        ReadUp : out std_logic
+        );
+end entity;
+
+
+architecture ar_Bridge of Bridge is
+
+type etat is (e0,e1);
+signal ect : etat;
+
+begin
+
+    process(clk,raz)
+    begin
+        if(raz='0')then 
+            WriteDwn    <= '1';
+            ReadUp      <= '1';
+            ect         <= e0;
+
+        elsif(clk'event and clk='1')then
+
+            case ect is
+
+                when e0 =>
+                    WriteDwn    <= '1';
+                    if(EmptyUp='0' and FullDwn='0')then
+                        ReadUp      <= '0';
+                        ect         <= e1;
+                    end if;
+
+                when e1 =>
+                    ReadUp      <= '1';
+                    WriteDwn    <= '0';
+                    ect         <= e0; 
+                           
+            end case;                
+   
+        end if;
+    end process;
+
+end architecture;
\ No newline at end of file
diff --git a/lib/lpp/lpp_memory/lpp_memory.vhd b/lib/lpp/lpp_memory/lpp_memory.vhd
--- a/lib/lpp/lpp_memory/lpp_memory.vhd
+++ b/lib/lpp/lpp_memory/lpp_memory.vhd
@@ -135,6 +135,17 @@ port(
 );
 end component;
 
+component Bridge is
+    port(
+        clk         : in std_logic;
+        raz        : in std_logic;
+        EmptyUp : in std_logic;
+        FullDwn : in std_logic;
+        WriteDwn : out std_logic;
+        ReadUp : out std_logic
+        );
+end component;
+
 component ssram_plugin is
 generic (tech : integer := 0);
 port
diff --git a/lib/lpp/lpp_memory/vhdlsyn.txt b/lib/lpp/lpp_memory/vhdlsyn.txt
--- a/lib/lpp/lpp_memory/vhdlsyn.txt
+++ b/lib/lpp/lpp_memory/vhdlsyn.txt
@@ -1,8 +1,10 @@
 lpp_memory.vhd
 lpp_FIFO.vhd
 FillFifo.vhd
+Bridge.vhd
 APB_FIFO.vhd
 Bridge.vhd
 SSRAM_plugin.vhd
 lppFIFOx5.vhd
 lppFIFOxN.vhd
+