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/!\ Unstable LFR-142200-DM-LEON3-BASE design /!\
jeandet@PC-DE-JEANDET.lpp.polytechnique.fr -
r85:439b6d5bebcc alexis
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1 #------------------------------------------------------------------------------
2 #-- This file is a part of the LPP VHDL IP LIBRARY
3 #-- Copyright (C) 2010, Laboratory of Plasmas Physic - CNRS
4 #--
5 #-- This program is free software; you can redistribute it and/or modify
6 #-- it under the terms of the GNU General Public License as published by
7 #-- the Free Software Foundation; either version 3 of the License, or
8 #-- (at your option) any later version.
9 #--
10 #-- This program is distributed in the hope that it will be useful,
11 #-- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 #-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 #-- GNU General Public License for more details.
14 #--
15 #-- You should have received a copy of the GNU General Public License
16 #-- along with this program; if not, write to the Free Software
17 #-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 #------------------------------------------------------------------------------
19
20 include ../../rules.mk
21 LIBDIR=
22 INCPATH = ../../includes
23 SCRIPTDIR=../../scripts/
24 LIBS=
25 INPUTFILE=main.c
26 EXEC=hello.bin
27 OUTBINDIR=bin/
28
29
30 .PHONY:bin
31
32 all:bin
33 @echo $(EXEC)" file created"
34
35 clean:
36 rm -f *.{o,a}
37
38
39
40 help:ruleshelp
41 @echo " all : makes an executable file called "$(EXEC)
42 @echo " in "$(OUTBINDIR)
43 @echo " clean : removes temporary files"
44
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@@ -0,0 +1,26
1 /*------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------*/
19 #include "stdio.h"
20
21
22 int main()
23 {
24 printf("hello World\n");
25 return 0;
26 }
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@@ -25,13 +25,13 DOXYFILE_ENCODING = UTF-8
25 25 # The PROJECT_NAME tag is a single word (or a sequence of words surrounded
26 26 # by quotes) that should identify the project.
27 27
28 PROJECT_NAME = "VHDL lib Drivers"
28 PROJECT_NAME = "apb lcd driver"
29 29
30 30 # The PROJECT_NUMBER tag can be used to enter a project or revision number.
31 31 # This could be handy for archiving the generated documentation or
32 32 # if some version control system is used.
33 33
34 PROJECT_NUMBER = 0.4
34 PROJECT_NUMBER = 0.1
35 35
36 36 # The OUTPUT_DIRECTORY tag is used to specify the (relative or absolute)
37 37 # base path where the generated documentation will be put.
@@ -339,7 +339,7 EXTRACT_LOCAL_METHODS = YES
339 339 # name of the file that contains the anonymous namespace. By default
340 340 # anonymous namespace are hidden.
341 341
342 EXTRACT_ANON_NSPACES = YES
342 EXTRACT_ANON_NSPACES = NO
343 343
344 344 # If the HIDE_UNDOC_MEMBERS tag is set to YES, Doxygen will hide all
345 345 # undocumented members of documented classes, files or namespaces.
@@ -497,7 +497,7 SHOW_USED_FILES = YES
497 497 # then setting the SHOW_DIRECTORIES tag to YES will show the directory hierarchy
498 498 # in the documentation. The default is NO.
499 499
500 SHOW_DIRECTORIES = YES
500 SHOW_DIRECTORIES = NO
501 501
502 502 # Set the SHOW_FILES tag to NO to disable the generation of the Files page.
503 503 # This will remove the Files entry from the Quick Index and from the
@@ -677,7 +677,7 EXCLUDE_SYMBOLS =
677 677 # directories that contain example code fragments that are included (see
678 678 # the \include command).
679 679
680 EXAMPLE_PATH = Doc/ressources/examples
680 EXAMPLE_PATH =
681 681
682 682 # If the value of the EXAMPLE_PATH tag contains directories, you can use the
683 683 # EXAMPLE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp
@@ -827,13 +827,13 HTML_FILE_EXTENSION = .html
827 827 # each generated HTML page. If it is left blank doxygen will generate a
828 828 # standard header.
829 829
830 HTML_HEADER = Doc/ressources/Header
830 HTML_HEADER =
831 831
832 832 # The HTML_FOOTER tag can be used to specify a personal HTML footer for
833 833 # each generated HTML page. If it is left blank doxygen will generate a
834 834 # standard footer.
835 835
836 HTML_FOOTER = Doc/ressources/Footer
836 HTML_FOOTER =
837 837
838 838 # The HTML_STYLESHEET tag can be used to specify a user-defined cascading
839 839 # style sheet that is used by each HTML page. It can be used to
@@ -842,7 +842,7 HTML_FOOTER = Doc/ressources/
842 842 # the style sheet file to the HTML output directory, so don't put your own
843 843 # stylesheet in the HTML output directory as well, or it will be erased!
844 844
845 HTML_STYLESHEET = Doc/ressources/doxygen.css
845 HTML_STYLESHEET =
846 846
847 847 # The HTML_COLORSTYLE_HUE tag controls the color of the HTML output.
848 848 # Doxygen will adjust the colors in the stylesheet and background images
@@ -852,7 +852,7 HTML_STYLESHEET = Doc/ressources/
852 852 # 180 is cyan, 240 is blue, 300 purple, and 360 is red again.
853 853 # The allowed range is 0 to 359.
854 854
855 HTML_COLORSTYLE_HUE = 218
855 HTML_COLORSTYLE_HUE = 220
856 856
857 857 # The HTML_COLORSTYLE_SAT tag controls the purity (or saturation) of
858 858 # the colors in the HTML output. For a value of 0 the output will use
@@ -1059,7 +1059,7 ENUM_VALUES_PER_LINE = 4
1059 1059 # JavaScript, DHTML, CSS and frames is required (i.e. any modern browser).
1060 1060 # Windows users are probably better off using the HTML help feature.
1061 1061
1062 GENERATE_TREEVIEW = YES
1062 GENERATE_TREEVIEW = NO
1063 1063
1064 1064 # By enabling USE_INLINE_TREES, doxygen will generate the Groups, Directories,
1065 1065 # and Class Hierarchy pages using a tree view instead of an ordered list.
@@ -1491,7 +1491,7 HIDE_UNDOC_RELATIONS = YES
1491 1491 # toolkit from AT&T and Lucent Bell Labs. The other options in this section
1492 1492 # have no effect if this option is set to NO (the default)
1493 1493
1494 HAVE_DOT = YES
1494 HAVE_DOT = NO
1495 1495
1496 1496 # The DOT_NUM_THREADS specifies the number of dot invocations doxygen is
1497 1497 # allowed to run in parallel. When set to 0 (the default) doxygen will
@@ -1547,7 +1547,7 GROUP_GRAPHS = YES
1547 1547 # collaboration diagrams in a style similar to the OMG's Unified Modeling
1548 1548 # Language.
1549 1549
1550 UML_LOOK = YES
1550 UML_LOOK = NO
1551 1551
1552 1552 # If set to YES, the inheritance and collaboration graphs will show the
1553 1553 # relations between templates and their instances.
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1 NO CONTENT: modified file, binary diff hidden
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@@ -1,1 +1,1
1 load bin/BenchFIFO.bin
1 load bin/hello.bin
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@@ -61,6 +61,7 Patched-dist: Patch-GRLIB
61 61
62 62
63 63 doc:
64 mkdir -p doc/html/
64 65 cp doc/ressources/*.jpg doc/html/
65 66 cp doc/ressources/doxygen.css doc/html/
66 67 make -C lib/lpp doc
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@@ -29,9 +29,9 package config is
29 29
30 30 -- Clock generator
31 31 constant CFG_CLKTECH : integer := inferred;
32 constant CFG_CLKMUL : integer := (45);
33 constant CFG_CLKDIV : integer := (9);
34 constant CFG_OCLKDIV : integer := (8);
32 constant CFG_CLKMUL : integer := (5);
33 constant CFG_CLKDIV : integer := (10);
34 constant CFG_OCLKDIV : integer := (1);
35 35 constant CFG_PCIDLL : integer := 0;
36 36 constant CFG_PCISYSCLK: integer := 0;
37 37 constant CFG_CLK_NOFB : integer := 0;
@@ -177,4 +177,4 package config is
177 177 constant CFG_DUART : integer := 0;
178 178
179 179
180 end; No newline at end of file
180 end;
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@@ -1,22 +1,23
1 ----------------------------------------------------------------------------------
2 -- Company:
3 -- Engineer:
1 -----------------------------------------------------------------------------
2 -- LEON3 Demonstration design
3 -- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 2 of the License, or
8 -- (at your option) any later version.
4 9 --
5 -- Create Date: 17:16:12 03/29/2011
6 -- Design Name:
7 -- Module Name: top - Behavioral
8 -- Project Name:
9 -- Target Devices:
10 -- Tool versions:
11 -- Description:
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
12 14 --
13 -- Dependencies:
14 --
15 -- Revision:
16 -- Revision 0.01 - File Created
17 -- Additional Comments:
18 --
19 ----------------------------------------------------------------------------------
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19
20
20 21 library ieee;
21 22 use ieee.std_logic_1164.all;
22 23 library grlib;
@@ -34,11 +35,12 use esa.memoryctrl.all;
34 35 use work.config.all;
35 36 library lpp;
36 37 use lpp.lpp_amba.all;
37 use lpp.lpp_uart.all;
38 38 use lpp.lpp_memory.all;
39 use lpp.general_purpose.all;
39 --use lpp.lpp_uart.all;
40 --use lpp.lpp_matrix.all;
41 --use lpp.lpp_usb.all;
40 42
41 entity miniamba is
43 entity leon3mp is
42 44 generic (
43 45 fabtech : integer := CFG_FABTECH;
44 46 memtech : integer := CFG_MEMTECH;
@@ -46,20 +48,24 entity miniamba is
46 48 clktech : integer := CFG_CLKTECH;
47 49 disas : integer := CFG_DISAS; -- Enable disassembly to console
48 50 dbguart : integer := CFG_DUART; -- Print UART on console
49 pclow : integer := CFG_PCLOW);
50 Port (
51 clk50MHz : in STD_LOGIC;
52 reset : in STD_LOGIC;
53 led : out std_logic_vector(1 downto 0);
54 errorn : out std_ulogic;
51 pclow : integer := CFG_PCLOW
52 );
53 port (
54 clk50MHz : in std_ulogic;
55 reset : in std_ulogic;
56 ramclk : out std_logic;
57
58 ahbrxd : in std_ulogic; -- DSU rx data
59 ahbtxd : out std_ulogic; -- DSU tx data
55 60 dsubre : in std_ulogic;
56 61 dsuact : out std_ulogic;
57 ahbrxd : in std_ulogic;
58 ahbtxd : out std_ulogic;
59 urxd1 : in std_ulogic;
60 utxd1 : out std_ulogic;
62 urxd1 : in std_ulogic; -- UART1 rx data
63 utxd1 : out std_ulogic; -- UART1 tx data
64 errorn : out std_ulogic;
65
66 address : out std_logic_vector(18 downto 0);
61 67 data : inout std_logic_vector(31 downto 0);
62 address : out std_logic_vector(18 downto 0);
68
63 69 nBWa : out std_logic;
64 70 nBWb : out std_logic;
65 71 nBWc : out std_logic;
@@ -75,12 +81,31 entity miniamba is
75 81 nOE : out std_logic;
76 82 MODE : out std_logic;
77 83 SSRAM_CLK : out std_logic;
78 ZZ : out std_logic
84 ZZ : out std_logic;
85 led : out std_logic_vector(1 downto 0)
79 86 );
80 end miniamba;
87 end;
88
89 architecture Behavioral of leon3mp is
90
91 constant maxahbmsp : integer := CFG_NCPU+CFG_AHB_UART+
92 CFG_GRETH+CFG_AHB_JTAG;
93 constant maxahbm : integer := maxahbmsp;
81 94
82 architecture Behavioral of miniamba is
83
95 --Clk & Rst g�n�
96 signal vcc : std_logic_vector(4 downto 0);
97 signal gnd : std_logic_vector(4 downto 0);
98 signal resetnl : std_ulogic;
99 signal clk2x : std_ulogic;
100 signal lclk : std_ulogic;
101 signal lclk2x : std_ulogic;
102 signal clkm : std_ulogic;
103 signal rstn : std_ulogic;
104 signal rstraw : std_ulogic;
105 signal pciclk : std_ulogic;
106 signal sdclkl : std_ulogic;
107 signal cgi : clkgen_in_type;
108 signal cgo : clkgen_out_type;
84 109 --- AHB / APB
85 110 signal apbi : apb_slv_in_type;
86 111 signal apbo : apb_slv_out_vector := (others => apb_none);
@@ -88,51 +113,49 signal ahbsi : ahb_slv_in_type;
88 113 signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
89 114 signal ahbmi : ahb_mst_in_type;
90 115 signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
91 -- AHBUART
116 --UART
92 117 signal ahbuarti: uart_in_type;
93 118 signal ahbuarto: uart_out_type;
94 119 signal apbuarti: uart_in_type;
95 120 signal apbuarto: uart_out_type;
96 signal rxd2 : std_ulogic;
97 signal rxd1 : std_ulogic;
98 signal txd1 : std_ulogic;
99
100 signal vcc : std_logic_vector(4 downto 0);
101 signal gnd : std_logic_vector(4 downto 0);
102
103 121 -- MEM CTRLR
104 122 signal memi : memory_in_type;
105 123 signal memo : memory_out_type;
124 signal wpo : wprot_out_type;
106 125 signal sdo : sdram_out_type;
107 signal sdo3 : sdctrl_out_type;
108 signal wpo : wprot_out_type;
109
110 signal clkm : std_ulogic;
111 signal resetnl : std_ulogic;
112 signal sdclkl : std_ulogic;
113 signal pciclk : std_ulogic;
114 signal lclk : std_ulogic;
115 signal rstn : std_ulogic;
116 signal clk2x : std_ulogic;
117 signal rstraw : std_logic;
118 signal rstneg : std_logic;
119 signal lock : std_logic;
120 signal cgi : clkgen_in_type;
121 signal cgo : clkgen_out_type;
122
123 -- LEON3
126 --IRQ
124 127 signal irqi : irq_in_vector(0 to CFG_NCPU-1);
125 128 signal irqo : irq_out_vector(0 to CFG_NCPU-1);
129 --Timer
130 signal gpti : gptimer_in_type;
131 signal gpto : gptimer_out_type;
132 --GPIO
133 signal gpioi : gpio_in_type;
134 signal gpioo : gpio_out_type;
135 --DSU
126 136 signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
127 137 signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
128
129 138 signal dsui : dsu_in_type;
130 139 signal dsuo : dsu_out_type;
131 signal dui : uart_in_type;
132 signal duo : uart_out_type;
140 ----------------------------------------------------------------------
141 --- AJOUT TEST ------------------------Signaux----------------------
142 ----------------------------------------------------------------------
143 -- TEST USB
144 --signal USB_Read : std_logic;
145 --signal USB_Write : std_logic;
133 146
147 -- MATRICE SPECTRALE
148 --signal Matrix_Write : std_logic;
149 --signal Matrix_Read : std_logic_vector(1 downto 0);
150 --signal Matrix_Full : std_logic_vector(1 downto 0);
151 --signal Matrix_Empty : std_logic_vector(1 downto 0);
152 --signal Matrix_Data1 : std_logic_vector(15 downto 0);
153 --signal Matrix_Data2 : std_logic_vector(15 downto 0);
154 --signal Matrix_Result : std_logic_vector(31 downto 0);
134 155
135 constant boardfreq : integer := 50000; -- input frequency in KHz
156 ---------------------------------------------------------------------
157 constant IOAEN : integer := CFG_CAN;
158 constant boardfreq : integer := 50000;
136 159
137 160 begin
138 161
@@ -140,87 +163,29 begin
140 163 --- Reset and Clock generation -------------------------------------
141 164 ----------------------------------------------------------------------
142 165
143 -- vcc <= (others => '1'); gnd <= (others => '0');
144 -- cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
145 -- rstneg <= reset;
146 --
147 -- rst0 : rstgen port map (rstneg, clkm, '1', rstn, rstraw);
148 -- lock <= cgo.clklock;
149 --
150 -- clk_pad : clkpad generic map (tech => padtech) port map (clk50MHz, lclk);
151 ----
152 ---- clkgen0 : clkgen -- clock generator MUL 4, DIV 5
153 ---- generic map (fabtech, CFG_CLKMUL, CFG_CLKDIV, 0, 0, 0, 0, 0, BOARD_FREQ, 0)
154 ---- port map (lclk, gnd(0), clkm, open, open, open, open, cgi, cgo, open, open, clk2x);
155 --
156 --process(lclk)
157 --begin
158 -- if lclk'event and lclk = '1' then
159 -- clkm <= not clkm;
160 -- end if;
161 --end process;
162 166 vcc <= (others => '1'); gnd <= (others => '0');
163 167 cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
164 168
165 clk_pad : inpad generic map (tech => 0) port map (clk50MHz, lclk);
169 rst0 : rstgen port map (reset, clkm, cgo.clklock, rstn, rstraw);
170
171
172 clk_pad : clkpad generic map (tech => padtech) port map (clk50MHz, lclk2x);
166 173
167 174 clkgen0 : clkgen -- clock generator
168 175 generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN,
169 176 CFG_CLK_NOFB, 0, 0, 0, boardfreq, 0, 0, CFG_OCLKDIV)
170 port map (lclk, lclk, clkm, open, open, open, open, cgi, cgo);
171
172 resetn_pad : inpad generic map (tech => padtech) port map (reset, resetnl);
173 rst0 : rstgen -- reset generator
174 port map (resetnl, clkm, cgo.clklock, rstn, rstraw);
175 --led(5) <= cgo.clklock;
176
177
178 --------------------------------------
179 --- CLK_DIVIDER ----------------------
180 --------------------------------------
181 clk_divider0 : Clk_divider
182 generic map (OSC_freqHz => 50000000, TargetFreq_Hz => 5)
183 Port map( clkm, rstn, led(1));
184
185 -------------------------------
186 --- AHB CONTROLLER ------------
187 -------------------------------
188 ahb0 : ahbctrl -- AHB arbiter/multiplexer
189 generic map (defmast => 0, --AHB_UART default master
190 split => CFG_SPLIT,
191 rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, ioen => 1,
192 nahbm => 3,
193 nahbs => 2)
194 port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
177 port map (lclk, lclk, clkm, open, clk2x, sdclkl, pciclk, cgi, cgo);
195 178
196
197 -------------------------------
198 --- MEMORY CONTROLLER ---------
199 -------------------------------
200 memctrlr : mctrl generic map (hindex => 0,pindex => 0, paddr => 0)
201 port map (rstn, clkm, memi, memo, ahbsi, ahbso(0),apbi,apbo(0),wpo, sdo);
202
203
204 bdr : for i in 0 to 3 generate
205 data_pad : iopadv generic map (tech => padtech, width => 8)
206 port map (data(31-i*8 downto 24-i*8), memo.data(31-i*8 downto 24-i*8),
207 memo.bdrive(i), memi.data(31-i*8 downto 24-i*8));
208 end generate;
209
210
211
212 addr_pad : outpadv generic map (width => 19, tech => padtech)
213 port map (address, memo.address(18 downto 0));
214
215
216
217 SSRAM_0:entity ssram_plugin
218 generic map (tech => padtech)
219 port map
220 (clkm,memo,SSRAM_CLK,nBWa,nBWb,nBWc,nBWd,nBWE,nADSC,nADSP,nADV,nGW,nCE1,CE2,nCE3,nOE,MODE,ZZ);
179 ramclk <= clkm;
180 process(lclk2x)
181 begin
182 if lclk2x'event and lclk2x = '1' then
183 lclk <= not lclk;
184 end if;
185 end process;
221 186
222 187 ----------------------------------------------------------------------
223 --- LEON3 processor and DSU -----------------------------------------
188 --- LEON3 processor / DSU / IRQ ------------------------------------
224 189 ----------------------------------------------------------------------
225 190
226 191 l3 : if CFG_LEON3 = 1 generate
@@ -252,43 +217,110 port map
252 217 nodsu : if CFG_DSU = 0 generate
253 218 ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
254 219 end generate;
255 nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate;
220
221 irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
222 irqctrl0 : irqmp -- interrupt controller
223 generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
224 port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
225 end generate;
226 irq3 : if CFG_IRQ3_ENABLE = 0 generate
227 x : for i in 0 to CFG_NCPU-1 generate
228 irqi(i).irl <= "0000";
229 end generate;
230 apbo(2) <= apb_none;
231 end generate;
232
233 ----------------------------------------------------------------------
234 --- Memory controllers ---------------------------------------------
235 ----------------------------------------------------------------------
236
237 memctrlr : mctrl generic map (hindex => 0,pindex => 0, paddr => 0)
238 port map (rstn, clkm, memi, memo, ahbsi, ahbso(0),apbi,apbo(0),wpo, sdo);
239
240 memi.brdyn <= '1'; memi.bexcn <= '1';
241 memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "10";
242
243 bdr : for i in 0 to 3 generate
244 data_pad : iopadv generic map (tech => padtech, width => 8)
245 port map (data(31-i*8 downto 24-i*8), memo.data(31-i*8 downto 24-i*8),
246 memo.bdrive(i), memi.data(31-i*8 downto 24-i*8));
247 end generate;
256 248
257 249
258 -------------------------------
259 --- AHBUART -------------------
260 -------------------------------
261 dcom0 : ahbuart -- AMBA AHB Serial Debug Interface
262 generic map (hindex => 1, pindex => 2, paddr => 2)
263 port map (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(2), ahbmi, ahbmo(1));
264 dsurx_pad : inpad generic map (tech => padtech) port map (ahbrxd, rxd2);
265 dsutx_pad : outpad generic map (tech => padtech) port map (ahbtxd, ahbuarto.txd);
266 ahbuarti.rxd <= rxd2;
250 addr_pad : outpadv generic map (width => 19, tech => padtech)
251 port map (address, memo.address(20 downto 2));
252
253
254 SSRAM_0:entity ssram_plugin
255 generic map (tech => padtech)
256 port map
257 (clkm,memo,SSRAM_CLK,nBWa,nBWb,nBWc,nBWd,nBWE,nADSC,nADSP,nADV,nGW,nCE1,CE2,nCE3,nOE,MODE,ZZ);
258
259 ----------------------------------------------------------------------
260 --- AHB CONTROLLER -------------------------------------------------
261 ----------------------------------------------------------------------
262
263 ahb0 : ahbctrl -- AHB arbiter/multiplexer
264 generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
265 rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
266 ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
267 port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
267 268
268 269 ----------------------------------------------------------------------
269 --- APB Bridge and various periherals --------------------------------
270 --- AHB UART -------------------------------------------------------
270 271 ----------------------------------------------------------------------
271 apb0 : apbctrl -- AHB/APB bridge
272 generic map (hindex => 3, haddr => CFG_APBADDR)
273 port map (rstn, clkm, ahbsi, ahbso(3), apbi, apbo);
272 dcomgen : if CFG_AHB_UART = 1 generate
273 dcom0: ahbuart -- Debug UART
274 generic map (hindex => CFG_NCPU, pindex => 7, paddr => 7)
275 port map (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(7), ahbmi, ahbmo(CFG_NCPU));
276 dsurx_pad : inpad generic map (tech => padtech) port map (ahbrxd, ahbuarti.rxd);
277 dsutx_pad : outpad generic map (tech => padtech) port map (ahbtxd, ahbuarto.txd);
278 -- led(0) <= not ahbuarti.rxd; led(1) <= not ahbuarto.txd;
279 end generate;
280 nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate;
281
282 ----------------------------------------------------------------------
283 --- APB Bridge -----------------------------------------------------
284 ----------------------------------------------------------------------
274 285
275 uart1 : APB_UART
276 generic map(
277 pindex => 1,
278 paddr => 1)
279 port map(
280 clk => clkm, --! Horloge du composant
281 rst => rstn, --! Reset general du composant
282 apbi => apbi, --! Registre de gestion des entr�es du bus
283 apbo => apbo(1), --! Registre de gestion des sorties du bus
284 TXD => utxd1, --! Transmission s�rie, c�t� composant
285 RXD => urxd1 --! Reception s�rie, c�t� composant
286 );
286 apb0 : apbctrl -- AHB/APB bridge
287 generic map (hindex => 1, haddr => CFG_APBADDR)
288 port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
289
290 ----------------------------------------------------------------------
291 --- GPT Timer ------------------------------------------------------
292 ----------------------------------------------------------------------
293
294 gpt : if CFG_GPT_ENABLE /= 0 generate
295 timer0 : gptimer -- timer unit
296 generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
297 sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
298 nbits => CFG_GPT_TW)
299 port map (rstn, clkm, apbi, apbo(3), gpti, gpto);
300 gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
301 -- led(4) <= gpto.wdog;
302 end generate;
303 notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
287 304
288 305
289 ----------------------------------
290 --- LED --------------------------
291 ----------------------------------
292 led(0) <= not rxd1;
306 ----------------------------------------------------------------------
307 --- APB UART -------------------------------------------------------
308 ----------------------------------------------------------------------
309
310 ua1 : if CFG_UART1_ENABLE /= 0 generate
311 uart1 : apbuart -- UART 1
312 generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
313 fifosize => CFG_UART1_FIFO)
314 port map (rstn, clkm, apbi, apbo(1), ahbuarti, apbuarto);
315 apbuarti.rxd <= urxd1; apbuarti.extclk <= '0'; utxd1 <= apbuarto.txd;
316 apbuarti.ctsn <= '0'; --rtsn1 <= apbuarto.rtsn;
317 led(0) <= not apbuarti.rxd; led(1) <= not apbuarto.txd;
318 end generate;
319 noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
320
321 ---------------------------------------------------------------------
322 --- AJOUT TEST -------------------------------------IPs------------
323 ---------------------------------------------------------------------
324
293 325
294 326 end Behavioral; No newline at end of file
Show file before | Show file after | Hide comments
@@ -17,23 +17,28
17 17 -- Additional Comments:
18 18 --
19 19 ----------------------------------------------------------------------------------
20 library IEEE;
21 use IEEE.STD_LOGIC_1164.ALL;
20 library ieee;
21 use ieee.std_logic_1164.all;
22 22 library grlib;
23 23 use grlib.amba.all;
24 use work.config.all;
24 use grlib.stdlib.all;
25 library techmap;
26 use techmap.gencomp.all;
25 27 library gaisler;
28 use gaisler.memctrl.all;
29 use gaisler.leon3.all;
26 30 use gaisler.uart.all;
27 31 use gaisler.misc.all;
28 use gaisler.leon3.all;
29 library techmap;
30 use techmap.gencomp.all;
31 use techmap.allclkgen.all;
32 library esa;
33 use esa.memoryctrl.all;
34 use work.config.all;
32 35 library lpp;
33 use lpp.general_purpose.all;
36 use lpp.lpp_amba.all;
34 37 use lpp.lpp_uart.all;
38 use lpp.lpp_memory.all;
39 use lpp.general_purpose.all;
35 40
36 entity top is
41 entity miniamba is
37 42 generic (
38 43 fabtech : integer := CFG_FABTECH;
39 44 memtech : integer := CFG_MEMTECH;
@@ -42,18 +47,36 entity top is
42 47 disas : integer := CFG_DISAS; -- Enable disassembly to console
43 48 dbguart : integer := CFG_DUART; -- Print UART on console
44 49 pclow : integer := CFG_PCLOW);
45 Port ( clk50MHz : in STD_LOGIC;
50 Port (
51 clk50MHz : in STD_LOGIC;
46 52 reset : in STD_LOGIC;
47 53 led : out std_logic_vector(1 downto 0);
48 --
49 54 ahbrxd : in std_ulogic;
50 55 ahbtxd : out std_ulogic;
51 56 urxd1 : in std_ulogic;
52 utxd1 : out std_ulogic
57 utxd1 : out std_ulogic;
58 data : inout std_logic_vector(31 downto 0);
59 address : out std_logic_vector(18 downto 0);
60 nBWa : out std_logic;
61 nBWb : out std_logic;
62 nBWc : out std_logic;
63 nBWd : out std_logic;
64 nBWE : out std_logic;
65 nADSC : out std_logic;
66 nADSP : out std_logic;
67 nADV : out std_logic;
68 nGW : out std_logic;
69 nCE1 : out std_logic;
70 CE2 : out std_logic;
71 nCE3 : out std_logic;
72 nOE : out std_logic;
73 MODE : out std_logic;
74 SSRAM_CLK : out std_logic;
75 ZZ : out std_logic
53 76 );
54 end top;
77 end miniamba;
55 78
56 architecture Behavioral of top is
79 architecture Behavioral of miniamba is
57 80
58 81 --- AHB / APB
59 82 signal apbi : apb_slv_in_type;
@@ -73,9 +96,18 signal txd1 : std_ulogic;
73 96
74 97 signal vcc : std_logic_vector(4 downto 0);
75 98 signal gnd : std_logic_vector(4 downto 0);
76 --signal LED_rotary : std_logic_vector(7 downto 0);
99
100 -- MEM CTRLR
101 signal memi : memory_in_type;
102 signal memo : memory_out_type;
103 signal sdo : sdram_out_type;
104 signal sdo3 : sdctrl_out_type;
105 signal wpo : wprot_out_type;
77 106
78 107 signal clkm : std_ulogic;
108 signal resetnl : std_ulogic;
109 signal sdclkl : std_ulogic;
110 signal pciclk : std_ulogic;
79 111 signal lclk : std_ulogic;
80 112 signal rstn : std_ulogic;
81 113 signal clk2x : std_ulogic;
@@ -85,7 +117,19 signal lock : std_logic;
85 117 signal cgi : clkgen_in_type;
86 118 signal cgo : clkgen_out_type;
87 119
88 constant BOARD_FREQ : integer := 50000; -- input frequency in KHz
120 -- LEON3
121 signal irqi : irq_in_vector(0 to CFG_NCPU-1);
122 signal irqo : irq_out_vector(0 to CFG_NCPU-1);
123 signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
124 signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
125
126 signal dsui : dsu_in_type;
127 signal dsuo : dsu_out_type;
128 signal dui : uart_in_type;
129 signal duo : uart_out_type;
130
131
132 constant boardfreq : integer := 50000; -- input frequency in KHz
89 133
90 134 begin
91 135
@@ -93,18 +137,40 begin
93 137 --- Reset and Clock generation -------------------------------------
94 138 ----------------------------------------------------------------------
95 139
140 -- vcc <= (others => '1'); gnd <= (others => '0');
141 -- cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
142 -- rstneg <= reset;
143 --
144 -- rst0 : rstgen port map (rstneg, clkm, '1', rstn, rstraw);
145 -- lock <= cgo.clklock;
146 --
147 -- clk_pad : clkpad generic map (tech => padtech) port map (clk50MHz, lclk);
148 ----
149 ---- clkgen0 : clkgen -- clock generator MUL 4, DIV 5
150 ---- generic map (fabtech, CFG_CLKMUL, CFG_CLKDIV, 0, 0, 0, 0, 0, BOARD_FREQ, 0)
151 ---- port map (lclk, gnd(0), clkm, open, open, open, open, cgi, cgo, open, open, clk2x);
152 --
153 --process(lclk)
154 --begin
155 -- if lclk'event and lclk = '1' then
156 -- clkm <= not clkm;
157 -- end if;
158 --end process;
96 159 vcc <= (others => '1'); gnd <= (others => '0');
97 160 cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
98 rstneg <= reset;
99 161
100 rst0 : rstgen port map (rstneg, clkm, lock, rstn, rstraw);
101 lock <= cgo.clklock;
162 clk_pad : inpad generic map (tech => 0) port map (clk50MHz, lclk);
102 163
103 clk_pad : clkpad generic map (tech => padtech) port map (clk50MHz, lclk);
164 clkgen0 : clkgen -- clock generator
165 generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN,
166 CFG_CLK_NOFB, 0, 0, 0, boardfreq, 0, 0, CFG_OCLKDIV)
167 port map (lclk, lclk, clkm, open, open, open, open, cgi, cgo);
104 168
105 clkgen0 : clkgen -- clock generator MUL 4, DIV 5
106 generic map (fabtech, CFG_CLKMUL, CFG_CLKDIV, 0, 0, 0, 0, 0, BOARD_FREQ, 0)
107 port map (lclk, gnd(0), clkm, open, open, open, open, cgi, cgo, open, open, clk2x);
169 resetn_pad : inpad generic map (tech => padtech) port map (reset, resetnl);
170 rst0 : rstgen -- reset generator
171 port map (resetnl, clkm, cgo.clklock, rstn, rstraw);
172 --led(5) <= cgo.clklock;
173
108 174
109 175 --------------------------------------
110 176 --- CLK_DIVIDER ----------------------
@@ -117,18 +183,45 clk_divider0 : Clk_divider
117 183 --- AHB CONTROLLER ------------
118 184 -------------------------------
119 185 ahb0 : ahbctrl -- AHB arbiter/multiplexer
120 generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
186 generic map (defmast => 0, --AHB_UART default master
187 split => CFG_SPLIT,
121 188 rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, ioen => 1,
122 nahbm => CFG_NCPU+CFG_AHB_UART,
189 nahbm => 3,
123 190 nahbs => 2)
124 191 port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
125 192
193
194 -------------------------------
195 --- MEMORY CONTROLLER ---------
196 -------------------------------
197 memctrlr : mctrl generic map (hindex => 0,pindex => 0, paddr => 0)
198 port map (rstn, clkm, memi, memo, ahbsi, ahbso(0),apbi,apbo(0),wpo, sdo);
199
200
201 bdr : for i in 0 to 3 generate
202 data_pad : iopadv generic map (tech => padtech, width => 8)
203 port map (data(31-i*8 downto 24-i*8), memo.data(31-i*8 downto 24-i*8),
204 memo.bdrive(i), memi.data(31-i*8 downto 24-i*8));
205 end generate;
206
207
208
209 addr_pad : outpadv generic map (width => 19, tech => padtech)
210 port map (address, memo.address(18 downto 0));
211
212
213
214 SSRAM_0:entity ssram_plugin
215 generic map (tech => padtech)
216 port map
217 (clkm,memo,SSRAM_CLK,nBWa,nBWb,nBWc,nBWd,nBWE,nADSC,nADSP,nADV,nGW,nCE1,CE2,nCE3,nOE,MODE,ZZ);
218
126 219 -------------------------------
127 220 --- AHBUART -------------------
128 221 -------------------------------
129 222 dcom0 : ahbuart -- AMBA AHB Serial Debug Interface
130 generic map (hindex => CFG_NCPU, pindex => 4, paddr => 7)
131 port map (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(4), ahbmi, ahbmo(CFG_NCPU));
223 generic map (hindex => 1, pindex => 2, paddr => 2)
224 port map (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(2), ahbmi, ahbmo(1));
132 225 dsurx_pad : inpad generic map (tech => padtech) port map (ahbrxd, rxd2);
133 226 dsutx_pad : outpad generic map (tech => padtech) port map (ahbtxd, ahbuarto.txd);
134 227 ahbuarti.rxd <= rxd2;
@@ -137,18 +230,18 ahbuarti.rxd <= rxd2;
137 230 --- APB Bridge and various periherals --------------------------------
138 231 ----------------------------------------------------------------------
139 232 apb0 : apbctrl -- AHB/APB bridge
140 generic map (hindex => 1, haddr => CFG_APBADDR,nslaves => 1)
141 port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
233 generic map (hindex => 3, haddr => CFG_APBADDR)
234 port map (rstn, clkm, ahbsi, ahbso(3), apbi, apbo);
142 235
143 236 uart1 : APB_UART
144 237 generic map(
145 pindex => 0,
146 paddr => 0)
238 pindex => 1,
239 paddr => 1)
147 240 port map(
148 241 clk => clkm, --! Horloge du composant
149 242 rst => rstn, --! Reset general du composant
150 243 apbi => apbi, --! Registre de gestion des entr�es du bus
151 apbo => apbo(0), --! Registre de gestion des sorties du bus
244 apbo => apbo(1), --! Registre de gestion des sorties du bus
152 245 TXD => utxd1, --! Transmission s�rie, c�t� composant
153 246 RXD => urxd1 --! Reception s�rie, c�t� composant
154 247 );
@@ -159,5 +252,4 uart1 : APB_UART
159 252 ----------------------------------
160 253 led(0) <= not rxd1;
161 254
162 end Behavioral;
163
255 end Behavioral; No newline at end of file
Show file before | Show file after | Hide comments
@@ -14,6 +14,7 CURREV=1
14 14 ENDLIST
15 15 LIST LIBRARIES
16 16 grlib
17 dw02
17 18 synplify
18 19 techmap
19 20 spw
@@ -32,6 +33,10 LIST LIBRARIES_grlib
32 33 ALIAS=grlib
33 34 COMPILE_OPTION=COMPILE
34 35 ENDLIST
36 LIST LIBRARIES_dw02
37 ALIAS=dw02
38 COMPILE_OPTION=COMPILE
39 ENDLIST
35 40 LIST LIBRARIES_synplify
36 41 ALIAS=synplify
37 42 COMPILE_OPTION=COMPILE
@@ -165,6 +170,10 VALUE "<project>/../../lib/grlib/amba/am
165 170 STATE="utd"
166 171 LIBRARY="grlib"
167 172 ENDFILE
173 VALUE "<project>/../../lib/tech/dw02/comp/DW02_components.vhd,hdl"
174 STATE="utd"
175 LIBRARY="dw02"
176 ENDFILE
168 177 VALUE "<project>/../../lib/synplify/sim/synplify.vhd,hdl"
169 178 STATE="utd"
170 179 LIBRARY="synplify"
@@ -185,6 +194,10 VALUE "<project>/../../lib/techmap/infer
185 194 STATE="utd"
186 195 LIBRARY="techmap"
187 196 ENDFILE
197 VALUE "<project>/../../lib/techmap/inferred/tap_inferred.vhd,hdl"
198 STATE="utd"
199 LIBRARY="techmap"
200 ENDFILE
188 201 VALUE "<project>/../../lib/techmap/inferred/ddr_inferred.vhd,hdl"
189 202 STATE="utd"
190 203 LIBRARY="techmap"
@@ -197,6 +210,62 VALUE "<project>/../../lib/techmap/infer
197 210 STATE="utd"
198 211 LIBRARY="techmap"
199 212 ENDFILE
213 VALUE "<project>/../../lib/techmap/dw02/mul_dw_gen.vhd,hdl"
214 STATE="utd"
215 LIBRARY="techmap"
216 ENDFILE
217 VALUE "<project>/../../lib/techmap/proasic3/a3pacomp.vhd,hdl"
218 STATE="utd"
219 LIBRARY="techmap"
220 ENDFILE
221 VALUE "<project>/../../lib/techmap/proasic3/memory_apa3.vhd,hdl"
222 STATE="utd"
223 LIBRARY="techmap"
224 ENDFILE
225 VALUE "<project>/../../lib/techmap/proasic3/buffer_apa3.vhd,hdl"
226 STATE="utd"
227 LIBRARY="techmap"
228 ENDFILE
229 VALUE "<project>/../../lib/techmap/proasic3/pads_apa3.vhd,hdl"
230 STATE="utd"
231 LIBRARY="techmap"
232 ENDFILE
233 VALUE "<project>/../../lib/techmap/proasic3/clkgen_proasic3.vhd,hdl"
234 STATE="utd"
235 LIBRARY="techmap"
236 ENDFILE
237 VALUE "<project>/../../lib/techmap/proasic3/ddr_proasic3.vhd,hdl"
238 STATE="utd"
239 LIBRARY="techmap"
240 ENDFILE
241 VALUE "<project>/../../lib/techmap/proasic3/tap_proasic3.vhd,hdl"
242 STATE="utd"
243 LIBRARY="techmap"
244 ENDFILE
245 VALUE "<project>/../../lib/techmap/proasic3/grspwc_proasic3.vhd,hdl"
246 STATE="utd"
247 LIBRARY="techmap"
248 ENDFILE
249 VALUE "<project>/../../lib/techmap/proasic3/leon3ft_proasic3.vhd,hdl"
250 STATE="utd"
251 LIBRARY="techmap"
252 ENDFILE
253 VALUE "<project>/../../lib/techmap/proasic3/leon3ft_proasic3_8_4_v8.vhd,hdl"
254 STATE="utd"
255 LIBRARY="techmap"
256 ENDFILE
257 VALUE "<project>/../../lib/techmap/proasic3/grspwc2_proasic3.vhd,hdl"
258 STATE="utd"
259 LIBRARY="techmap"
260 ENDFILE
261 VALUE "<project>/../../lib/techmap/proasic3/grspwc2_proasic3_16_16_rmap0.vhd,hdl"
262 STATE="utd"
263 LIBRARY="techmap"
264 ENDFILE
265 VALUE "<project>/../../lib/techmap/proasic3/grspwc2_proasic3_16_16_rmap1.vhd,hdl"
266 STATE="utd"
267 LIBRARY="techmap"
268 ENDFILE
200 269 VALUE "<project>/../../lib/techmap/maps/allclkgen.vhd,hdl"
201 270 STATE="utd"
202 271 LIBRARY="techmap"
@@ -1085,6 +1154,10 VALUE "<project>/../../lib/lpp/./dsp/lpp
1085 1154 STATE="utd"
1086 1155 LIBRARY="lpp"
1087 1156 ENDFILE
1157 VALUE "<project>/../../lib/lpp/./dsp/lpp_fft/Flag_Extremum.vhd,hdl"
1158 STATE="utd"
1159 LIBRARY="lpp"
1160 ENDFILE
1088 1161 VALUE "<project>/../../lib/lpp/./dsp/lpp_fft/lpp_fft.vhd,hdl"
1089 1162 STATE="utd"
1090 1163 LIBRARY="lpp"
@@ -1181,6 +1254,38 VALUE "<project>/../../lib/lpp/./lpp_amb
1181 1254 STATE="utd"
1182 1255 LIBRARY="lpp"
1183 1256 ENDFILE
1257 VALUE "<project>/../../lib/lpp/./lpp_AMR/APB_AMR.vhd,hdl"
1258 STATE="utd"
1259 LIBRARY="lpp"
1260 ENDFILE
1261 VALUE "<project>/../../lib/lpp/./lpp_AMR/Clock_multi.vhd,hdl"
1262 STATE="utd"
1263 LIBRARY="lpp"
1264 ENDFILE
1265 VALUE "<project>/../../lib/lpp/./lpp_AMR/Dephaseur.vhd,hdl"
1266 STATE="utd"
1267 LIBRARY="lpp"
1268 ENDFILE
1269 VALUE "<project>/../../lib/lpp/./lpp_AMR/Gene_Rz.vhd,hdl"
1270 STATE="utd"
1271 LIBRARY="lpp"
1272 ENDFILE
1273 VALUE "<project>/../../lib/lpp/./lpp_AMR/bclk_reg.vhd,hdl"
1274 STATE="utd"
1275 LIBRARY="lpp"
1276 ENDFILE
1277 VALUE "<project>/../../lib/lpp/./lpp_AMR/lpp_AMR.vhd,hdl"
1278 STATE="utd"
1279 LIBRARY="lpp"
1280 ENDFILE
1281 VALUE "<project>/../../lib/lpp/./lpp_balise/APB_Balise.vhd,hdl"
1282 STATE="utd"
1283 LIBRARY="lpp"
1284 ENDFILE
1285 VALUE "<project>/../../lib/lpp/./lpp_balise/lpp_balise.vhd,hdl"
1286 STATE="utd"
1287 LIBRARY="lpp"
1288 ENDFILE
1184 1289 VALUE "<project>/../../lib/lpp/./lpp_cna/APB_CNA.vhd,hdl"
1185 1290 STATE="utd"
1186 1291 LIBRARY="lpp"
@@ -1209,6 +1314,54 VALUE "<project>/../../lib/lpp/./lpp_cna
1209 1314 STATE="utd"
1210 1315 LIBRARY="lpp"
1211 1316 ENDFILE
1317 VALUE "<project>/../../lib/lpp/./lpp_matrix/ALU_Driver.vhd,hdl"
1318 STATE="utd"
1319 LIBRARY="lpp"
1320 ENDFILE
1321 VALUE "<project>/../../lib/lpp/./lpp_matrix/ALU_v2.vhd,hdl"
1322 STATE="utd"
1323 LIBRARY="lpp"
1324 ENDFILE
1325 VALUE "<project>/../../lib/lpp/./lpp_matrix/APB_Matrix.vhd,hdl"
1326 STATE="utd"
1327 LIBRARY="lpp"
1328 ENDFILE
1329 VALUE "<project>/../../lib/lpp/./lpp_matrix/DriveInputs.vhd,hdl"
1330 STATE="utd"
1331 LIBRARY="lpp"
1332 ENDFILE
1333 VALUE "<project>/../../lib/lpp/./lpp_matrix/GetResult.vhd,hdl"
1334 STATE="utd"
1335 LIBRARY="lpp"
1336 ENDFILE
1337 VALUE "<project>/../../lib/lpp/./lpp_matrix/MAC_v2.vhd,hdl"
1338 STATE="utd"
1339 LIBRARY="lpp"
1340 ENDFILE
1341 VALUE "<project>/../../lib/lpp/./lpp_matrix/Matrix.vhd,hdl"
1342 STATE="utd"
1343 LIBRARY="lpp"
1344 ENDFILE
1345 VALUE "<project>/../../lib/lpp/./lpp_matrix/SelectInputs.vhd,hdl"
1346 STATE="utd"
1347 LIBRARY="lpp"
1348 ENDFILE
1349 VALUE "<project>/../../lib/lpp/./lpp_matrix/SpectralMatrix.vhd,hdl"
1350 STATE="utd"
1351 LIBRARY="lpp"
1352 ENDFILE
1353 VALUE "<project>/../../lib/lpp/./lpp_matrix/Starter.vhd,hdl"
1354 STATE="utd"
1355 LIBRARY="lpp"
1356 ENDFILE
1357 VALUE "<project>/../../lib/lpp/./lpp_matrix/TwoComplementer.vhd,hdl"
1358 STATE="utd"
1359 LIBRARY="lpp"
1360 ENDFILE
1361 VALUE "<project>/../../lib/lpp/./lpp_matrix/lpp_matrix.vhd,hdl"
1362 STATE="utd"
1363 LIBRARY="lpp"
1364 ENDFILE
1212 1365 VALUE "<project>/../../lib/lpp/./lpp_memory/APB_FIFO.vhd,hdl"
1213 1366 STATE="utd"
1214 1367 LIBRARY="lpp"
@@ -1237,15 +1390,11 VALUE "<project>/../../lib/lpp/./lpp_mem
1237 1390 STATE="utd"
1238 1391 LIBRARY="lpp"
1239 1392 ENDFILE
1240 VALUE "<project>/../../lib/lpp/./lpp_memory/Top_FIFO.vhd,hdl"
1393 VALUE "<project>/../../lib/lpp/./lpp_memory/SSRAM_plugin.vhd,hdl"
1241 1394 STATE="utd"
1242 1395 LIBRARY="lpp"
1243 1396 ENDFILE
1244 VALUE "<project>/../../lib/lpp/./lpp_memory/Top_FifoRead.vhd,hdl"
1245 STATE="utd"
1246 LIBRARY="lpp"
1247 ENDFILE
1248 VALUE "<project>/../../lib/lpp/./lpp_memory/Top_FifoWrite.vhd,hdl"
1397 VALUE "<project>/../../lib/lpp/./lpp_memory/Top_FIFO.vhd,hdl"
1249 1398 STATE="utd"
1250 1399 LIBRARY="lpp"
1251 1400 ENDFILE
@@ -1273,6 +1422,14 VALUE "<project>/../../lib/lpp/./lpp_uar
1273 1422 STATE="utd"
1274 1423 LIBRARY="lpp"
1275 1424 ENDFILE
1425 VALUE "<project>/../../lib/lpp/./lpp_usb/RWbuf.vhd,hdl"
1426 STATE="utd"
1427 LIBRARY="lpp"
1428 ENDFILE
1429 VALUE "<project>/../../lib/lpp/./lpp_usb/lpp_usb.vhd,hdl"
1430 STATE="utd"
1431 LIBRARY="lpp"
1432 ENDFILE
1276 1433 VALUE "<project>/../../lib/cypress/ssram/components.vhd,hdl"
1277 1434 STATE="utd"
1278 1435 LIBRARY="cypress"
@@ -1332,6 +1489,7 VALUE "<project>/../../lib/grlib/sparc/s
1332 1489 VALUE "<project>/../../lib/grlib/sparc/cpu_disas.vhd,hdl"
1333 1490 VALUE "<project>/../../lib/grlib/amba/dma2ahb_tp.vhd,hdl"
1334 1491 VALUE "<project>/../../lib/grlib/amba/amba_tp.vhd,hdl"
1492 VALUE "<project>/../../lib/tech/dw02/comp/DW02_components.vhd,hdl"
1335 1493 VALUE "<project>/../../lib/synplify/sim/synplify.vhd,hdl"
1336 1494 VALUE "<project>/../../lib/synplify/sim/synattr.vhd,hdl"
1337 1495 VALUE "<project>/../../lib/gaisler/ambatest/ahbtbp.vhd,hdl"
@@ -1395,9 +1553,24 VALUE "<project>/../../lib/grlib/amba/dm
1395 1553 VALUE "<project>/../../lib/techmap/gencomp/gencomp.vhd,hdl"
1396 1554 VALUE "<project>/../../lib/techmap/gencomp/netcomp.vhd,hdl"
1397 1555 VALUE "<project>/../../lib/techmap/inferred/memory_inferred.vhd,hdl"
1556 VALUE "<project>/../../lib/techmap/inferred/tap_inferred.vhd,hdl"
1398 1557 VALUE "<project>/../../lib/techmap/inferred/ddr_inferred.vhd,hdl"
1399 1558 VALUE "<project>/../../lib/techmap/inferred/mul_inferred.vhd,hdl"
1400 1559 VALUE "<project>/../../lib/techmap/inferred/ddr_phy_inferred.vhd,hdl"
1560 VALUE "<project>/../../lib/techmap/dw02/mul_dw_gen.vhd,hdl"
1561 VALUE "<project>/../../lib/techmap/proasic3/a3pacomp.vhd,hdl"
1562 VALUE "<project>/../../lib/techmap/proasic3/memory_apa3.vhd,hdl"
1563 VALUE "<project>/../../lib/techmap/proasic3/buffer_apa3.vhd,hdl"
1564 VALUE "<project>/../../lib/techmap/proasic3/pads_apa3.vhd,hdl"
1565 VALUE "<project>/../../lib/techmap/proasic3/clkgen_proasic3.vhd,hdl"
1566 VALUE "<project>/../../lib/techmap/proasic3/ddr_proasic3.vhd,hdl"
1567 VALUE "<project>/../../lib/techmap/proasic3/tap_proasic3.vhd,hdl"
1568 VALUE "<project>/../../lib/techmap/proasic3/grspwc_proasic3.vhd,hdl"
1569 VALUE "<project>/../../lib/techmap/proasic3/leon3ft_proasic3.vhd,hdl"
1570 VALUE "<project>/../../lib/techmap/proasic3/leon3ft_proasic3_8_4_v8.vhd,hdl"
1571 VALUE "<project>/../../lib/techmap/proasic3/grspwc2_proasic3.vhd,hdl"
1572 VALUE "<project>/../../lib/techmap/proasic3/grspwc2_proasic3_16_16_rmap0.vhd,hdl"
1573 VALUE "<project>/../../lib/techmap/proasic3/grspwc2_proasic3_16_16_rmap1.vhd,hdl"
1401 1574 VALUE "<project>/../../lib/techmap/maps/allclkgen.vhd,hdl"
1402 1575 VALUE "<project>/../../lib/techmap/maps/allddr.vhd,hdl"
1403 1576 VALUE "<project>/../../lib/techmap/maps/allmem.vhd,hdl"
@@ -1595,6 +1768,7 VALUE "<project>/../../lib/lpp/./dsp/iir
1595 1768 VALUE "<project>/../../lib/lpp/./dsp/iir_filter/Top_Filtre_IIR.vhd,hdl"
1596 1769 VALUE "<project>/../../lib/lpp/./dsp/iir_filter/iir_filter.vhd,hdl"
1597 1770 VALUE "<project>/../../lib/lpp/./dsp/lpp_fft/APB_FFT.vhd,hdl"
1771 VALUE "<project>/../../lib/lpp/./dsp/lpp_fft/Flag_Extremum.vhd,hdl"
1598 1772 VALUE "<project>/../../lib/lpp/./dsp/lpp_fft/lpp_fft.vhd,hdl"
1599 1773 VALUE "<project>/../../lib/lpp/./general_purpose/ADDRcntr.vhd,hdl"
1600 1774 VALUE "<project>/../../lib/lpp/./general_purpose/ALU.vhd,hdl"
@@ -1619,6 +1793,14 VALUE "<project>/../../lib/lpp/./lpp_amb
1619 1793 VALUE "<project>/../../lib/lpp/./lpp_amba/APB_SIMPLE_DIODE.vhd,hdl"
1620 1794 VALUE "<project>/../../lib/lpp/./lpp_amba/apb_devices_list.vhd,hdl"
1621 1795 VALUE "<project>/../../lib/lpp/./lpp_amba/lpp_amba.vhd,hdl"
1796 VALUE "<project>/../../lib/lpp/./lpp_AMR/APB_AMR.vhd,hdl"
1797 VALUE "<project>/../../lib/lpp/./lpp_AMR/Clock_multi.vhd,hdl"
1798 VALUE "<project>/../../lib/lpp/./lpp_AMR/Dephaseur.vhd,hdl"
1799 VALUE "<project>/../../lib/lpp/./lpp_AMR/Gene_Rz.vhd,hdl"
1800 VALUE "<project>/../../lib/lpp/./lpp_AMR/bclk_reg.vhd,hdl"
1801 VALUE "<project>/../../lib/lpp/./lpp_AMR/lpp_AMR.vhd,hdl"
1802 VALUE "<project>/../../lib/lpp/./lpp_balise/APB_Balise.vhd,hdl"
1803 VALUE "<project>/../../lib/lpp/./lpp_balise/lpp_balise.vhd,hdl"
1622 1804 VALUE "<project>/../../lib/lpp/./lpp_cna/APB_CNA.vhd,hdl"
1623 1805 VALUE "<project>/../../lib/lpp/./lpp_cna/CNA_TabloC.vhd,hdl"
1624 1806 VALUE "<project>/../../lib/lpp/./lpp_cna/Convertisseur_config.vhd,hdl"
@@ -1626,6 +1808,18 VALUE "<project>/../../lib/lpp/./lpp_cna
1626 1808 VALUE "<project>/../../lib/lpp/./lpp_cna/Serialize.vhd,hdl"
1627 1809 VALUE "<project>/../../lib/lpp/./lpp_cna/Systeme_Clock.vhd,hdl"
1628 1810 VALUE "<project>/../../lib/lpp/./lpp_cna/lpp_cna.vhd,hdl"
1811 VALUE "<project>/../../lib/lpp/./lpp_matrix/ALU_Driver.vhd,hdl"
1812 VALUE "<project>/../../lib/lpp/./lpp_matrix/ALU_v2.vhd,hdl"
1813 VALUE "<project>/../../lib/lpp/./lpp_matrix/APB_Matrix.vhd,hdl"
1814 VALUE "<project>/../../lib/lpp/./lpp_matrix/DriveInputs.vhd,hdl"
1815 VALUE "<project>/../../lib/lpp/./lpp_matrix/GetResult.vhd,hdl"
1816 VALUE "<project>/../../lib/lpp/./lpp_matrix/MAC_v2.vhd,hdl"
1817 VALUE "<project>/../../lib/lpp/./lpp_matrix/Matrix.vhd,hdl"
1818 VALUE "<project>/../../lib/lpp/./lpp_matrix/SelectInputs.vhd,hdl"
1819 VALUE "<project>/../../lib/lpp/./lpp_matrix/SpectralMatrix.vhd,hdl"
1820 VALUE "<project>/../../lib/lpp/./lpp_matrix/Starter.vhd,hdl"
1821 VALUE "<project>/../../lib/lpp/./lpp_matrix/TwoComplementer.vhd,hdl"
1822 VALUE "<project>/../../lib/lpp/./lpp_matrix/lpp_matrix.vhd,hdl"
1629 1823 VALUE "<project>/../../lib/lpp/./lpp_memory/APB_FIFO.vhd,hdl"
1630 1824 VALUE "<project>/../../lib/lpp/./lpp_memory/APB_FifoRead.vhd,hdl"
1631 1825 VALUE "<project>/../../lib/lpp/./lpp_memory/APB_FifoWrite.vhd,hdl"
@@ -1633,15 +1827,16 VALUE "<project>/../../lib/lpp/./lpp_mem
1633 1827 VALUE "<project>/../../lib/lpp/./lpp_memory/Fifo_Read.vhd,hdl"
1634 1828 VALUE "<project>/../../lib/lpp/./lpp_memory/Fifo_Write.vhd,hdl"
1635 1829 VALUE "<project>/../../lib/lpp/./lpp_memory/Link_Reg.vhd,hdl"
1830 VALUE "<project>/../../lib/lpp/./lpp_memory/SSRAM_plugin.vhd,hdl"
1636 1831 VALUE "<project>/../../lib/lpp/./lpp_memory/Top_FIFO.vhd,hdl"
1637 VALUE "<project>/../../lib/lpp/./lpp_memory/Top_FifoRead.vhd,hdl"
1638 VALUE "<project>/../../lib/lpp/./lpp_memory/Top_FifoWrite.vhd,hdl"
1639 1832 VALUE "<project>/../../lib/lpp/./lpp_memory/lpp_memory.vhd,hdl"
1640 1833 VALUE "<project>/../../lib/lpp/./lpp_uart/APB_UART.vhd,hdl"
1641 1834 VALUE "<project>/../../lib/lpp/./lpp_uart/BaudGen.vhd,hdl"
1642 1835 VALUE "<project>/../../lib/lpp/./lpp_uart/Shift_REG.vhd,hdl"
1643 1836 VALUE "<project>/../../lib/lpp/./lpp_uart/UART.vhd,hdl"
1644 1837 VALUE "<project>/../../lib/lpp/./lpp_uart/lpp_uart.vhd,hdl"
1838 VALUE "<project>/../../lib/lpp/./lpp_usb/RWbuf.vhd,hdl"
1839 VALUE "<project>/../../lib/lpp/./lpp_usb/lpp_usb.vhd,hdl"
1645 1840 VALUE "<project>/config.vhd,hdl"
1646 1841 VALUE "<project>/ahbrom.vhd,hdl"
1647 1842 VALUE "<project>/leon3mp.vhd,hdl"
@@ -1670,14 +1865,30 VALUE "<project>/../../lib/grlib/amba/dm
1670 1865 VALUE "<project>/../../lib/grlib/amba/dma2ahb.vhd,hdl"
1671 1866 VALUE "<project>/../../lib/grlib/amba/dma2ahb_tp.vhd,hdl"
1672 1867 VALUE "<project>/../../lib/grlib/amba/amba_tp.vhd,hdl"
1868 VALUE "<project>/../../lib/tech/dw02/comp/DW02_components.vhd,hdl"
1673 1869 VALUE "<project>/../../lib/synplify/sim/synplify.vhd,hdl"
1674 1870 VALUE "<project>/../../lib/synplify/sim/synattr.vhd,hdl"
1675 1871 VALUE "<project>/../../lib/techmap/gencomp/gencomp.vhd,hdl"
1676 1872 VALUE "<project>/../../lib/techmap/gencomp/netcomp.vhd,hdl"
1677 1873 VALUE "<project>/../../lib/techmap/inferred/memory_inferred.vhd,hdl"
1874 VALUE "<project>/../../lib/techmap/inferred/tap_inferred.vhd,hdl"
1678 1875 VALUE "<project>/../../lib/techmap/inferred/ddr_inferred.vhd,hdl"
1679 1876 VALUE "<project>/../../lib/techmap/inferred/mul_inferred.vhd,hdl"
1680 1877 VALUE "<project>/../../lib/techmap/inferred/ddr_phy_inferred.vhd,hdl"
1878 VALUE "<project>/../../lib/techmap/dw02/mul_dw_gen.vhd,hdl"
1879 VALUE "<project>/../../lib/techmap/proasic3/a3pacomp.vhd,hdl"
1880 VALUE "<project>/../../lib/techmap/proasic3/memory_apa3.vhd,hdl"
1881 VALUE "<project>/../../lib/techmap/proasic3/buffer_apa3.vhd,hdl"
1882 VALUE "<project>/../../lib/techmap/proasic3/pads_apa3.vhd,hdl"
1883 VALUE "<project>/../../lib/techmap/proasic3/clkgen_proasic3.vhd,hdl"
1884 VALUE "<project>/../../lib/techmap/proasic3/ddr_proasic3.vhd,hdl"
1885 VALUE "<project>/../../lib/techmap/proasic3/tap_proasic3.vhd,hdl"
1886 VALUE "<project>/../../lib/techmap/proasic3/grspwc_proasic3.vhd,hdl"
1887 VALUE "<project>/../../lib/techmap/proasic3/leon3ft_proasic3.vhd,hdl"
1888 VALUE "<project>/../../lib/techmap/proasic3/leon3ft_proasic3_8_4_v8.vhd,hdl"
1889 VALUE "<project>/../../lib/techmap/proasic3/grspwc2_proasic3.vhd,hdl"
1890 VALUE "<project>/../../lib/techmap/proasic3/grspwc2_proasic3_16_16_rmap0.vhd,hdl"
1891 VALUE "<project>/../../lib/techmap/proasic3/grspwc2_proasic3_16_16_rmap1.vhd,hdl"
1681 1892 VALUE "<project>/../../lib/techmap/maps/allclkgen.vhd,hdl"
1682 1893 VALUE "<project>/../../lib/techmap/maps/allddr.vhd,hdl"
1683 1894 VALUE "<project>/../../lib/techmap/maps/allmem.vhd,hdl"
@@ -1900,6 +2111,7 VALUE "<project>/../../lib/lpp/./dsp/iir
1900 2111 VALUE "<project>/../../lib/lpp/./dsp/iir_filter/Top_Filtre_IIR.vhd,hdl"
1901 2112 VALUE "<project>/../../lib/lpp/./dsp/iir_filter/iir_filter.vhd,hdl"
1902 2113 VALUE "<project>/../../lib/lpp/./dsp/lpp_fft/APB_FFT.vhd,hdl"
2114 VALUE "<project>/../../lib/lpp/./dsp/lpp_fft/Flag_Extremum.vhd,hdl"
1903 2115 VALUE "<project>/../../lib/lpp/./dsp/lpp_fft/lpp_fft.vhd,hdl"
1904 2116 VALUE "<project>/../../lib/lpp/./general_purpose/ADDRcntr.vhd,hdl"
1905 2117 VALUE "<project>/../../lib/lpp/./general_purpose/ALU.vhd,hdl"
@@ -1924,6 +2136,14 VALUE "<project>/../../lib/lpp/./lpp_amb
1924 2136 VALUE "<project>/../../lib/lpp/./lpp_amba/APB_SIMPLE_DIODE.vhd,hdl"
1925 2137 VALUE "<project>/../../lib/lpp/./lpp_amba/apb_devices_list.vhd,hdl"
1926 2138 VALUE "<project>/../../lib/lpp/./lpp_amba/lpp_amba.vhd,hdl"
2139 VALUE "<project>/../../lib/lpp/./lpp_AMR/APB_AMR.vhd,hdl"
2140 VALUE "<project>/../../lib/lpp/./lpp_AMR/Clock_multi.vhd,hdl"
2141 VALUE "<project>/../../lib/lpp/./lpp_AMR/Dephaseur.vhd,hdl"
2142 VALUE "<project>/../../lib/lpp/./lpp_AMR/Gene_Rz.vhd,hdl"
2143 VALUE "<project>/../../lib/lpp/./lpp_AMR/bclk_reg.vhd,hdl"
2144 VALUE "<project>/../../lib/lpp/./lpp_AMR/lpp_AMR.vhd,hdl"
2145 VALUE "<project>/../../lib/lpp/./lpp_balise/APB_Balise.vhd,hdl"
2146 VALUE "<project>/../../lib/lpp/./lpp_balise/lpp_balise.vhd,hdl"
1927 2147 VALUE "<project>/../../lib/lpp/./lpp_cna/APB_CNA.vhd,hdl"
1928 2148 VALUE "<project>/../../lib/lpp/./lpp_cna/CNA_TabloC.vhd,hdl"
1929 2149 VALUE "<project>/../../lib/lpp/./lpp_cna/Convertisseur_config.vhd,hdl"
@@ -1931,6 +2151,18 VALUE "<project>/../../lib/lpp/./lpp_cna
1931 2151 VALUE "<project>/../../lib/lpp/./lpp_cna/Serialize.vhd,hdl"
1932 2152 VALUE "<project>/../../lib/lpp/./lpp_cna/Systeme_Clock.vhd,hdl"
1933 2153 VALUE "<project>/../../lib/lpp/./lpp_cna/lpp_cna.vhd,hdl"
2154 VALUE "<project>/../../lib/lpp/./lpp_matrix/ALU_Driver.vhd,hdl"
2155 VALUE "<project>/../../lib/lpp/./lpp_matrix/ALU_v2.vhd,hdl"
2156 VALUE "<project>/../../lib/lpp/./lpp_matrix/APB_Matrix.vhd,hdl"
2157 VALUE "<project>/../../lib/lpp/./lpp_matrix/DriveInputs.vhd,hdl"
2158 VALUE "<project>/../../lib/lpp/./lpp_matrix/GetResult.vhd,hdl"
2159 VALUE "<project>/../../lib/lpp/./lpp_matrix/MAC_v2.vhd,hdl"
2160 VALUE "<project>/../../lib/lpp/./lpp_matrix/Matrix.vhd,hdl"
2161 VALUE "<project>/../../lib/lpp/./lpp_matrix/SelectInputs.vhd,hdl"
2162 VALUE "<project>/../../lib/lpp/./lpp_matrix/SpectralMatrix.vhd,hdl"
2163 VALUE "<project>/../../lib/lpp/./lpp_matrix/Starter.vhd,hdl"
2164 VALUE "<project>/../../lib/lpp/./lpp_matrix/TwoComplementer.vhd,hdl"
2165 VALUE "<project>/../../lib/lpp/./lpp_matrix/lpp_matrix.vhd,hdl"
1934 2166 VALUE "<project>/../../lib/lpp/./lpp_memory/APB_FIFO.vhd,hdl"
1935 2167 VALUE "<project>/../../lib/lpp/./lpp_memory/APB_FifoRead.vhd,hdl"
1936 2168 VALUE "<project>/../../lib/lpp/./lpp_memory/APB_FifoWrite.vhd,hdl"
@@ -1938,15 +2170,16 VALUE "<project>/../../lib/lpp/./lpp_mem
1938 2170 VALUE "<project>/../../lib/lpp/./lpp_memory/Fifo_Read.vhd,hdl"
1939 2171 VALUE "<project>/../../lib/lpp/./lpp_memory/Fifo_Write.vhd,hdl"
1940 2172 VALUE "<project>/../../lib/lpp/./lpp_memory/Link_Reg.vhd,hdl"
2173 VALUE "<project>/../../lib/lpp/./lpp_memory/SSRAM_plugin.vhd,hdl"
1941 2174 VALUE "<project>/../../lib/lpp/./lpp_memory/Top_FIFO.vhd,hdl"
1942 VALUE "<project>/../../lib/lpp/./lpp_memory/Top_FifoRead.vhd,hdl"
1943 VALUE "<project>/../../lib/lpp/./lpp_memory/Top_FifoWrite.vhd,hdl"
1944 2175 VALUE "<project>/../../lib/lpp/./lpp_memory/lpp_memory.vhd,hdl"
1945 2176 VALUE "<project>/../../lib/lpp/./lpp_uart/APB_UART.vhd,hdl"
1946 2177 VALUE "<project>/../../lib/lpp/./lpp_uart/BaudGen.vhd,hdl"
1947 2178 VALUE "<project>/../../lib/lpp/./lpp_uart/Shift_REG.vhd,hdl"
1948 2179 VALUE "<project>/../../lib/lpp/./lpp_uart/UART.vhd,hdl"
1949 2180 VALUE "<project>/../../lib/lpp/./lpp_uart/lpp_uart.vhd,hdl"
2181 VALUE "<project>/../../lib/lpp/./lpp_usb/RWbuf.vhd,hdl"
2182 VALUE "<project>/../../lib/lpp/./lpp_usb/lpp_usb.vhd,hdl"
1950 2183 VALUE "<project>/../../lib/cypress/ssram/components.vhd,hdl"
1951 2184 VALUE "<project>/../../lib/cypress/ssram/package_utility.vhd,hdl"
1952 2185 VALUE "<project>/../../lib/cypress/ssram/cy7c1354b.vhd,hdl"
Show file before | Show file after | Hide comments
@@ -1,4 +1,4
1 # Doxyfile 1.7.1
1 # Doxyfile 1.7.5.1
2 2
3 3 # This file describes the settings to be used by the documentation system
4 4 # doxygen (www.doxygen.org) for a project
@@ -22,8 +22,9
22 22
23 23 DOXYFILE_ENCODING = UTF-8
24 24
25 # The PROJECT_NAME tag is a single word (or a sequence of words surrounded
26 # by quotes) that should identify the project.
25 # The PROJECT_NAME tag is a single word (or sequence of words) that should
26 # identify the project. Note that if you do not use Doxywizard you need
27 # to put quotes around the project name if it contains spaces.
27 28
28 29 PROJECT_NAME = lib-lpp
29 30
@@ -31,7 +32,20 PROJECT_NAME = lib-lpp
31 32 # This could be handy for archiving the generated documentation or
32 33 # if some version control system is used.
33 34
34 PROJECT_NUMBER = 0.4
35 PROJECT_NUMBER = 1.0
36
37 # Using the PROJECT_BRIEF tag one can provide an optional one line description
38 # for a project that appears at the top of each page and should give viewer
39 # a quick idea about the purpose of the project. Keep the description short.
40
41 PROJECT_BRIEF =
42
43 # With the PROJECT_LOGO tag one can specify an logo or icon that is
44 # included in the documentation. The maximum height of the logo should not
45 # exceed 55 pixels and the maximum width should not exceed 200 pixels.
46 # Doxygen will copy the logo to the output directory.
47
48 PROJECT_LOGO =
35 49
36 50 # The OUTPUT_DIRECTORY tag is used to specify the (relative or absolute)
37 51 # base path where the generated documentation will be put.
@@ -57,7 +71,7 CREATE_SUBDIRS = NO
57 71 # Croatian, Czech, Danish, Dutch, Esperanto, Farsi, Finnish, French, German,
58 72 # Greek, Hungarian, Italian, Japanese, Japanese-en (Japanese with English
59 73 # messages), Korean, Korean-en, Lithuanian, Norwegian, Macedonian, Persian,
60 # Polish, Portuguese, Romanian, Russian, Serbian, Serbian-Cyrilic, Slovak,
74 # Polish, Portuguese, Romanian, Russian, Serbian, Serbian-Cyrillic, Slovak,
61 75 # Slovene, Spanish, Swedish, Ukrainian, and Vietnamese.
62 76
63 77 OUTPUT_LANGUAGE = English
@@ -136,7 +150,7 STRIP_FROM_PATH =
136 150 STRIP_FROM_INC_PATH =
137 151
138 152 # If the SHORT_NAMES tag is set to YES, doxygen will generate much shorter
139 # (but less readable) file names. This can be useful is your file systems
153 # (but less readable) file names. This can be useful if your file system
140 154 # doesn't support long names like on DOS, Mac, or CD-ROM.
141 155
142 156 SHORT_NAMES = NO
@@ -233,7 +247,7 EXTENSION_MAPPING =
233 247 # to include (a tag file for) the STL sources as input, then you should
234 248 # set this tag to YES in order to let doxygen match functions declarations and
235 249 # definitions whose arguments contain STL classes (e.g. func(std::string); v.s.
236 # func(std::string) {}). This also make the inheritance and collaboration
250 # func(std::string) {}). This also makes the inheritance and collaboration
237 251 # diagrams that involve STL classes more complete and accurate.
238 252
239 253 BUILTIN_STL_SUPPORT = NO
@@ -251,7 +265,7 SIP_SUPPORT = NO
251 265
252 266 # For Microsoft's IDL there are propget and propput attributes to indicate getter
253 267 # and setter methods for a property. Setting this option to YES (the default)
254 # will make doxygen to replace the get and set methods by a property in the
268 # will make doxygen replace the get and set methods by a property in the
255 269 # documentation. This will only work if the methods are indeed getting or
256 270 # setting a simple type. If this is not the case, or you want to show the
257 271 # methods anyway, you should set this option to NO.
@@ -273,6 +287,22 DISTRIBUTE_GROUP_DOC = NO
273 287
274 288 SUBGROUPING = YES
275 289
290 # When the INLINE_GROUPED_CLASSES tag is set to YES, classes, structs and
291 # unions are shown inside the group in which they are included (e.g. using
292 # @ingroup) instead of on a separate page (for HTML and Man pages) or
293 # section (for LaTeX and RTF).
294
295 INLINE_GROUPED_CLASSES = NO
296
297 # When the INLINE_SIMPLE_STRUCTS tag is set to YES, structs, classes, and
298 # unions with only public data fields will be shown inline in the documentation
299 # of the scope in which they are defined (i.e. file, namespace, or group
300 # documentation), provided this scope is documented. If set to NO (the default),
301 # structs, classes, and unions are shown on a separate page (for HTML and Man
302 # pages) or section (for LaTeX and RTF).
303
304 INLINE_SIMPLE_STRUCTS = NO
305
276 306 # When TYPEDEF_HIDES_STRUCT is enabled, a typedef of a struct, union, or enum
277 307 # is documented as struct, union, or enum with the name of the typedef. So
278 308 # typedef struct TypeS {} TypeT, will appear in the documentation as a struct
@@ -289,10 +319,10 TYPEDEF_HIDES_STRUCT = NO
289 319 # For small to medium size projects (<1000 input files) the default value is
290 320 # probably good enough. For larger projects a too small cache size can cause
291 321 # doxygen to be busy swapping symbols to and from disk most of the time
292 # causing a significant performance penality.
322 # causing a significant performance penalty.
293 323 # If the system has enough physical memory increasing the cache will improve the
294 324 # performance by keeping more symbols in memory. Note that the value works on
295 # a logarithmic scale so increasing the size by one will rougly double the
325 # a logarithmic scale so increasing the size by one will roughly double the
296 326 # memory usage. The cache size is given by this formula:
297 327 # 2^(16+SYMBOL_CACHE_SIZE). The valid range is 0..9, the default is 0,
298 328 # corresponding to a cache size of 2^16 = 65536 symbols
@@ -337,7 +367,7 EXTRACT_LOCAL_METHODS = NO
337 367 # extracted and appear in the documentation as a namespace called
338 368 # 'anonymous_namespace{file}', where file will be replaced with the base
339 369 # name of the file that contains the anonymous namespace. By default
340 # anonymous namespace are hidden.
370 # anonymous namespaces are hidden.
341 371
342 372 EXTRACT_ANON_NSPACES = NO
343 373
@@ -448,6 +478,15 SORT_GROUP_NAMES = NO
448 478
449 479 SORT_BY_SCOPE_NAME = NO
450 480
481 # If the STRICT_PROTO_MATCHING option is enabled and doxygen fails to
482 # do proper type resolution of all parameters of a function it will reject a
483 # match between the prototype and the implementation of a member function even
484 # if there is only one candidate or it is obvious which candidate to choose
485 # by doing a simple string match. By disabling STRICT_PROTO_MATCHING doxygen
486 # will still accept a match between prototype and implementation in such cases.
487
488 STRICT_PROTO_MATCHING = NO
489
451 490 # The GENERATE_TODOLIST tag can be used to enable (YES) or
452 491 # disable (NO) the todo list. This list is created by putting \todo
453 492 # commands in the documentation.
@@ -478,10 +517,10 GENERATE_DEPRECATEDLIST= YES
478 517 ENABLED_SECTIONS =
479 518
480 519 # The MAX_INITIALIZER_LINES tag determines the maximum number of lines
481 # the initial value of a variable or define consists of for it to appear in
520 # the initial value of a variable or macro consists of for it to appear in
482 521 # the documentation. If the initializer consists of more lines than specified
483 522 # here it will be hidden. Use a value of 0 to hide initializers completely.
484 # The appearance of the initializer of individual variables and defines in the
523 # The appearance of the initializer of individual variables and macros in the
485 524 # documentation can be controlled using \showinitializer or \hideinitializer
486 525 # command in the documentation regardless of this setting.
487 526
@@ -530,6 +569,15 FILE_VERSION_FILTER =
530 569
531 570 LAYOUT_FILE =
532 571
572 # The CITE_BIB_FILES tag can be used to specify one or more bib files
573 # containing the references data. This must be a list of .bib files. The
574 # .bib extension is automatically appended if omitted. Using this command
575 # requires the bibtex tool to be installed. See also
576 # http://en.wikipedia.org/wiki/BibTeX for more info. For LaTeX the style
577 # of the bibliography can be controlled using LATEX_BIB_STYLE.
578
579 CITE_BIB_FILES =
580
533 581 #---------------------------------------------------------------------------
534 582 # configuration options related to warning and progress messages
535 583 #---------------------------------------------------------------------------
@@ -558,7 +606,7 WARN_IF_UNDOCUMENTED = YES
558 606
559 607 WARN_IF_DOC_ERROR = YES
560 608
561 # This WARN_NO_PARAMDOC option can be abled to get warnings for
609 # The WARN_NO_PARAMDOC option can be enabled to get warnings for
562 610 # functions that are documented, but have no documentation for their parameters
563 611 # or return value. If set to NO (the default) doxygen will only warn about
564 612 # wrong or incomplete parameter documentation, but not about the absence of
@@ -604,8 +652,9 INPUT_ENCODING = UTF-8
604 652 # FILE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp
605 653 # and *.h) to filter out the source-files in the directories. If left
606 654 # blank the following patterns are tested:
607 # *.c *.cc *.cxx *.cpp *.c++ *.java *.ii *.ixx *.ipp *.i++ *.inl *.h *.hh *.hxx
608 # *.hpp *.h++ *.idl *.odl *.cs *.php *.php3 *.inc *.m *.mm *.py *.f90
655 # *.c *.cc *.cxx *.cpp *.c++ *.d *.java *.ii *.ixx *.ipp *.i++ *.inl *.h *.hh
656 # *.hxx *.hpp *.h++ *.idl *.odl *.cs *.php *.php3 *.inc *.m *.mm *.dox *.py
657 # *.f90 *.f *.for *.vhd *.vhdl
609 658
610 659 FILE_PATTERNS = *.c \
611 660 *.cc \
@@ -648,6 +697,7 RECURSIVE = YES
648 697 # The EXCLUDE tag can be used to specify files and/or directories that should
649 698 # excluded from the INPUT source files. This way you can easily exclude a
650 699 # subdirectory from a directory tree whose root is specified with the INPUT tag.
700 # Note that relative paths are relative to directory from which doxygen is run.
651 701
652 702 EXCLUDE =
653 703
@@ -713,8 +763,8 INPUT_FILTER =
713 763 # basis. Doxygen will compare the file name with each pattern and apply the
714 764 # filter if there is a match. The filters are a list of the form:
715 765 # pattern=filter (like *.cpp=my_cpp_filter). See INPUT_FILTER for further
716 # info on how filters are used. If FILTER_PATTERNS is empty, INPUT_FILTER
717 # is applied to all files.
766 # info on how filters are used. If FILTER_PATTERNS is empty or if
767 # non of the patterns match the file name, INPUT_FILTER is applied.
718 768
719 769 FILTER_PATTERNS =
720 770
@@ -724,6 +774,14 FILTER_PATTERNS =
724 774
725 775 FILTER_SOURCE_FILES = NO
726 776
777 # The FILTER_SOURCE_PATTERNS tag can be used to specify source filters per file
778 # pattern. A pattern will override the setting for FILTER_PATTERN (if any)
779 # and it is also possible to disable source filtering for a specific pattern
780 # using *.ext= (so without naming a filter). This option only has effect when
781 # FILTER_SOURCE_FILES is enabled.
782
783 FILTER_SOURCE_PATTERNS =
784
727 785 #---------------------------------------------------------------------------
728 786 # configuration options related to source browsing
729 787 #---------------------------------------------------------------------------
@@ -733,7 +791,7 FILTER_SOURCE_FILES = NO
733 791 # Note: To get rid of all source code in the generated output, make sure also
734 792 # VERBATIM_HEADERS is set to NO.
735 793
736 SOURCE_BROWSER = YES
794 SOURCE_BROWSER = NO
737 795
738 796 # Setting the INLINE_SOURCES tag to YES will include the body
739 797 # of functions and classes directly in the documentation.
@@ -825,15 +883,22 HTML_FILE_EXTENSION = .html
825 883
826 884 # The HTML_HEADER tag can be used to specify a personal HTML header for
827 885 # each generated HTML page. If it is left blank doxygen will generate a
828 # standard header.
886 # standard header. Note that when using a custom header you are responsible
887 # for the proper inclusion of any scripts and style sheets that doxygen
888 # needs, which is dependent on the configuration options used.
889 # It is adviced to generate a default header using "doxygen -w html
890 # header.html footer.html stylesheet.css YourConfigFile" and then modify
891 # that header. Note that the header is subject to change so you typically
892 # have to redo this when upgrading to a newer version of doxygen or when
893 # changing the value of configuration settings such as GENERATE_TREEVIEW!
829 894
830 HTML_HEADER = ../../doc/ressources/Header
895 HTML_HEADER =
831 896
832 897 # The HTML_FOOTER tag can be used to specify a personal HTML footer for
833 898 # each generated HTML page. If it is left blank doxygen will generate a
834 899 # standard footer.
835 900
836 HTML_FOOTER = ../../doc/ressources/Footer
901 HTML_FOOTER =
837 902
838 903 # The HTML_STYLESHEET tag can be used to specify a user-defined cascading
839 904 # style sheet that is used by each HTML page. It can be used to
@@ -842,7 +907,16 HTML_FOOTER = ../../doc/resso
842 907 # the style sheet file to the HTML output directory, so don't put your own
843 908 # stylesheet in the HTML output directory as well, or it will be erased!
844 909
845 HTML_STYLESHEET = ../../doc/ressources/doxygen.css
910 HTML_STYLESHEET =
911
912 # The HTML_EXTRA_FILES tag can be used to specify one or more extra images or
913 # other source files which should be copied to the HTML output directory. Note
914 # that these files will be copied to the base HTML output directory. Use the
915 # $relpath$ marker in the HTML_HEADER and/or HTML_FOOTER files to load these
916 # files. In the HTML_STYLESHEET file, use the file name only. Also note that
917 # the files will be copied as-is; there are no commands or markers available.
918
919 HTML_EXTRA_FILES =
846 920
847 921 # The HTML_COLORSTYLE_HUE tag controls the color of the HTML output.
848 922 # Doxygen will adjust the colors in the stylesheet and background images
@@ -1046,8 +1120,10 ECLIPSE_DOC_ID = org.doxygen.Pro
1046 1120
1047 1121 DISABLE_INDEX = NO
1048 1122
1049 # This tag can be used to set the number of enum values (range [1..20])
1050 # that doxygen will group on one line in the generated HTML documentation.
1123 # The ENUM_VALUES_PER_LINE tag can be used to set the number of enum values
1124 # (range [0,1..20]) that doxygen will group on one line in the generated HTML
1125 # documentation. Note that a value of 0 will completely suppress the enum
1126 # values from appearing in the overview section.
1051 1127
1052 1128 ENUM_VALUES_PER_LINE = 4
1053 1129
@@ -1093,6 +1169,31 FORMULA_FONTSIZE = 10
1093 1169
1094 1170 FORMULA_TRANSPARENT = YES
1095 1171
1172 # Enable the USE_MATHJAX option to render LaTeX formulas using MathJax
1173 # (see http://www.mathjax.org) which uses client side Javascript for the
1174 # rendering instead of using prerendered bitmaps. Use this if you do not
1175 # have LaTeX installed or if you want to formulas look prettier in the HTML
1176 # output. When enabled you also need to install MathJax separately and
1177 # configure the path to it using the MATHJAX_RELPATH option.
1178
1179 USE_MATHJAX = NO
1180
1181 # When MathJax is enabled you need to specify the location relative to the
1182 # HTML output directory using the MATHJAX_RELPATH option. The destination
1183 # directory should contain the MathJax.js script. For instance, if the mathjax
1184 # directory is located at the same level as the HTML output directory, then
1185 # MATHJAX_RELPATH should be ../mathjax. The default value points to the
1186 # mathjax.org site, so you can quickly see the result without installing
1187 # MathJax, but it is strongly recommended to install a local copy of MathJax
1188 # before deployment.
1189
1190 MATHJAX_RELPATH = http://www.mathjax.org/mathjax
1191
1192 # The MATHJAX_EXTENSIONS tag can be used to specify one or MathJax extension
1193 # names that should be enabled during MathJax rendering.
1194
1195 MATHJAX_EXTENSIONS =
1196
1096 1197 # When the SEARCHENGINE tag is enabled doxygen will generate a search box
1097 1198 # for the HTML output. The underlying search engine uses javascript
1098 1199 # and DHTML and should work on any modern browser. Note that when using
@@ -1108,7 +1209,7 SEARCHENGINE = YES
1108 1209 # using Javascript. Doxygen will generate the search PHP script and index
1109 1210 # file to put on the web server. The advantage of the server
1110 1211 # based approach is that it scales better to large projects and allows
1111 # full text search. The disadvances is that it is more difficult to setup
1212 # full text search. The disadvantages are that it is more difficult to setup
1112 1213 # and does not have live searching capabilities.
1113 1214
1114 1215 SERVER_BASED_SEARCH = NO
@@ -1146,13 +1247,13 MAKEINDEX_CMD_NAME = makeindex
1146 1247 # LaTeX documents. This may be useful for small projects and may help to
1147 1248 # save some trees in general.
1148 1249
1149 COMPACT_LATEX = YES
1250 COMPACT_LATEX = NO
1150 1251
1151 1252 # The PAPER_TYPE tag can be used to set the paper type that is used
1152 # by the printer. Possible values are: a4, a4wide, letter, legal and
1253 # by the printer. Possible values are: a4, letter, legal and
1153 1254 # executive. If left blank a4wide will be used.
1154 1255
1155 PAPER_TYPE = letter
1256 PAPER_TYPE = a4wide
1156 1257
1157 1258 # The EXTRA_PACKAGES tag can be to specify one or more names of LaTeX
1158 1259 # packages that should be included in the LaTeX output.
@@ -1166,6 +1267,13 EXTRA_PACKAGES =
1166 1267
1167 1268 LATEX_HEADER =
1168 1269
1270 # The LATEX_FOOTER tag can be used to specify a personal LaTeX footer for
1271 # the generated latex document. The footer should contain everything after
1272 # the last chapter. If it is left blank doxygen will generate a
1273 # standard footer. Notice: only use this tag if you know what you are doing!
1274
1275 LATEX_FOOTER =
1276
1169 1277 # If the PDF_HYPERLINKS tag is set to YES, the LaTeX that is generated
1170 1278 # is prepared for conversion to pdf (using ps2pdf). The pdf file will
1171 1279 # contain links (just like the HTML output) instead of page references
@@ -1199,6 +1307,12 LATEX_HIDE_INDICES = NO
1199 1307
1200 1308 LATEX_SOURCE_CODE = NO
1201 1309
1310 # The LATEX_BIB_STYLE tag can be used to specify the style to use for the
1311 # bibliography, e.g. plainnat, or ieeetr. The default style is "plain". See
1312 # http://en.wikipedia.org/wiki/BibTeX for more info.
1313
1314 LATEX_BIB_STYLE = plain
1315
1202 1316 #---------------------------------------------------------------------------
1203 1317 # configuration options related to the RTF output
1204 1318 #---------------------------------------------------------------------------
@@ -1373,7 +1487,7 MACRO_EXPANSION = NO
1373 1487 EXPAND_ONLY_PREDEF = NO
1374 1488
1375 1489 # If the SEARCH_INCLUDES tag is set to YES (the default) the includes files
1376 # in the INCLUDE_PATH (see below) will be search if a #include is found.
1490 # pointed to by INCLUDE_PATH will be searched when a #include is found.
1377 1491
1378 1492 SEARCH_INCLUDES = YES
1379 1493
@@ -1403,15 +1517,15 PREDEFINED =
1403 1517 # If the MACRO_EXPANSION and EXPAND_ONLY_PREDEF tags are set to YES then
1404 1518 # this tag can be used to specify a list of macro names that should be expanded.
1405 1519 # The macro definition that is found in the sources will be used.
1406 # Use the PREDEFINED tag if you want to use a different macro definition.
1520 # Use the PREDEFINED tag if you want to use a different macro definition that
1521 # overrules the definition found in the source code.
1407 1522
1408 1523 EXPAND_AS_DEFINED =
1409 1524
1410 1525 # If the SKIP_FUNCTION_MACROS tag is set to YES (the default) then
1411 # doxygen's preprocessor will remove all function-like macros that are alone
1412 # on a line, have an all uppercase name, and do not end with a semicolon. Such
1413 # function macros are typically used for boiler-plate code, and will confuse
1414 # the parser if not removed.
1526 # doxygen's preprocessor will remove all references to function-like macros
1527 # that are alone on a line, have an all uppercase name, and do not end with a
1528 # semicolon, because these will confuse the parser if not removed.
1415 1529
1416 1530 SKIP_FUNCTION_MACROS = YES
1417 1531
@@ -1465,11 +1579,10 PERL_PATH = /usr/bin/perl
1465 1579 # If the CLASS_DIAGRAMS tag is set to YES (the default) Doxygen will
1466 1580 # generate a inheritance diagram (in HTML, RTF and LaTeX) for classes with base
1467 1581 # or super classes. Setting the tag to NO turns the diagrams off. Note that
1468 # this option is superseded by the HAVE_DOT option below. This is only a
1469 # fallback. It is recommended to install and use dot, since it yields more
1470 # powerful graphs.
1582 # this option also works with HAVE_DOT disabled, but it is recommended to
1583 # install and use dot, since it yields more powerful graphs.
1471 1584
1472 CLASS_DIAGRAMS = NO
1585 CLASS_DIAGRAMS = YES
1473 1586
1474 1587 # You can define message sequence charts within doxygen comments using the \msc
1475 1588 # command. Doxygen will then run the mscgen tool (see
@@ -1501,14 +1614,12 HAVE_DOT = YES
1501 1614
1502 1615 DOT_NUM_THREADS = 0
1503 1616
1504 # By default doxygen will write a font called FreeSans.ttf to the output
1505 # directory and reference it in all dot files that doxygen generates. This
1506 # font does not include all possible unicode characters however, so when you need
1507 # these (or just want a differently looking font) you can specify the font name
1508 # using DOT_FONTNAME. You need need to make sure dot is able to find the font,
1509 # which can be done by putting it in a standard location or by setting the
1510 # DOTFONTPATH environment variable or by setting DOT_FONTPATH to the directory
1511 # containing the font.
1617 # By default doxygen will use the Helvetica font for all dot files that
1618 # doxygen generates. When you want a differently looking font you can specify
1619 # the font name using DOT_FONTNAME. You need to make sure dot is able to find
1620 # the font, which can be done by putting it in a standard location or by setting
1621 # the DOTFONTPATH environment variable or by setting DOT_FONTPATH to the
1622 # directory containing the font.
1512 1623
1513 1624 DOT_FONTNAME = FreeSans.ttf
1514 1625
@@ -1517,10 +1628,9 DOT_FONTNAME = FreeSans.ttf
1517 1628
1518 1629 DOT_FONTSIZE = 10
1519 1630
1520 # By default doxygen will tell dot to use the output directory to look for the
1521 # FreeSans.ttf font (which doxygen will put there itself). If you specify a
1522 # different font using DOT_FONTNAME you can set the path where dot
1523 # can find it using this tag.
1631 # By default doxygen will tell dot to use the Helvetica font.
1632 # If you specify a different font using DOT_FONTNAME you can use DOT_FONTPATH to
1633 # set the path where dot can find it.
1524 1634
1525 1635 DOT_FONTPATH =
1526 1636
@@ -1547,7 +1657,7 GROUP_GRAPHS = YES
1547 1657 # collaboration diagrams in a style similar to the OMG's Unified Modeling
1548 1658 # Language.
1549 1659
1550 UML_LOOK = YES
1660 UML_LOOK = NO
1551 1661
1552 1662 # If set to YES, the inheritance and collaboration graphs will show the
1553 1663 # relations between templates and their instances.
@@ -1585,7 +1695,7 CALL_GRAPH = NO
1585 1695 CALLER_GRAPH = NO
1586 1696
1587 1697 # If the GRAPHICAL_HIERARCHY and HAVE_DOT tags are set to YES then doxygen
1588 # will graphical hierarchy of all classes instead of a textual one.
1698 # will generate a graphical hierarchy of all classes instead of a textual one.
1589 1699
1590 1700 GRAPHICAL_HIERARCHY = YES
1591 1701
@@ -1597,11 +1707,22 GRAPHICAL_HIERARCHY = YES
1597 1707 DIRECTORY_GRAPH = YES
1598 1708
1599 1709 # The DOT_IMAGE_FORMAT tag can be used to set the image format of the images
1600 # generated by dot. Possible values are png, jpg, or gif
1601 # If left blank png will be used.
1710 # generated by dot. Possible values are svg, png, jpg, or gif.
1711 # If left blank png will be used. If you choose svg you need to set
1712 # HTML_FILE_EXTENSION to xhtml in order to make the SVG files
1713 # visible in IE 9+ (other browsers do not have this requirement).
1602 1714
1603 1715 DOT_IMAGE_FORMAT = png
1604 1716
1717 # If DOT_IMAGE_FORMAT is set to svg, then this option can be set to YES to
1718 # enable generation of interactive SVG images that allow zooming and panning.
1719 # Note that this requires a modern browser other than Internet Explorer.
1720 # Tested and working are Firefox, Chrome, Safari, and Opera. For IE 9+ you
1721 # need to set HTML_FILE_EXTENSION to xhtml in order to make the SVG files
1722 # visible. Older versions of IE do not have SVG support.
1723
1724 INTERACTIVE_SVG = NO
1725
1605 1726 # The tag DOT_PATH can be used to specify the path where the dot tool can be
1606 1727 # found. If left blank, it is assumed the dot tool can be found in the path.
1607 1728
@@ -1613,6 +1734,12 DOT_PATH =
1613 1734
1614 1735 DOTFILE_DIRS =
1615 1736
1737 # The MSCFILE_DIRS tag can be used to specify one or more directories that
1738 # contain msc files that are included in the documentation (see the
1739 # \mscfile command).
1740
1741 MSCFILE_DIRS =
1742
1616 1743 # The DOT_GRAPH_MAX_NODES tag can be used to set the maximum number of
1617 1744 # nodes that will be shown in the graph. If the number of nodes in a graph
1618 1745 # becomes larger than this value, doxygen will truncate the graph, which is
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@@ -26,6 +26,9 use grlib.amba.all;
26 26 use std.textio.all;
27 27 library lpp;
28 28 use lpp.lpp_amba.all;
29 library gaisler;
30 use gaisler.misc.all;
31 use gaisler.memctrl.all;
29 32
30 33 --! Package contenant tous les programmes qui forment le composant int�gr� dans le l�on
31 34
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