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custom dma ready to test on board
pellion -
r576:4347a39d5ac8 simu_double_DMA
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1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Jean-christophe Pellion
20 20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 21 -------------------------------------------------------------------------------
22 22 LIBRARY IEEE;
23 23 USE IEEE.numeric_std.ALL;
24 24 USE IEEE.std_logic_1164.ALL;
25 25 LIBRARY grlib;
26 26 USE grlib.amba.ALL;
27 27 USE grlib.stdlib.ALL;
28 28 LIBRARY techmap;
29 29 USE techmap.gencomp.ALL;
30 30 LIBRARY gaisler;
31 31 USE gaisler.memctrl.ALL;
32 32 USE gaisler.leon3.ALL;
33 33 USE gaisler.uart.ALL;
34 34 USE gaisler.misc.ALL;
35 35 USE gaisler.spacewire.ALL;
36 36 LIBRARY esa;
37 37 USE esa.memoryctrl.ALL;
38 38 LIBRARY lpp;
39 39 USE lpp.lpp_memory.ALL;
40 40 USE lpp.lpp_ad_conv.ALL;
41 41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
42 42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
43 43 USE lpp.iir_filter.ALL;
44 44 USE lpp.general_purpose.ALL;
45 45 USE lpp.lpp_lfr_management.ALL;
46 46 USE lpp.lpp_leon3_soc_pkg.ALL;
47 47
48 --library proasic3l;
49 --use proasic3l.all;
48 library proasic3l;
49 use proasic3l.all;
50 50
51 51 ENTITY LFR_EQM IS
52 52 --GENERIC (
53 53 -- Mem_use : INTEGER := use_RAM);
54 54
55 55 PORT (
56 56 clk50MHz : IN STD_ULOGIC;
57 57 clk49_152MHz : IN STD_ULOGIC;
58 58 reset : IN STD_ULOGIC;
59 59
60 60 -- TAG --------------------------------------------------------------------
61 61 TAG1 : IN STD_ULOGIC; -- DSU rx data
62 62 TAG3 : OUT STD_ULOGIC; -- DSU tx data
63 63 -- UART APB ---------------------------------------------------------------
64 64 TAG2 : IN STD_ULOGIC; -- UART1 rx data
65 65 TAG4 : OUT STD_ULOGIC; -- UART1 tx data
66 66 -- RAM --------------------------------------------------------------------
67 address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
67 address : OUT STD_LOGIC_VECTOR(18 DOWNTO 0);
68 68 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
69 69
70 70 nSRAM_MBE : INOUT STD_LOGIC; -- new
71 71 nSRAM_E1 : OUT STD_LOGIC; -- new
72 72 nSRAM_E2 : OUT STD_LOGIC; -- new
73 73 -- nSRAM_SCRUB : OUT STD_LOGIC; -- new
74 74 nSRAM_W : OUT STD_LOGIC; -- new
75 75 nSRAM_G : OUT STD_LOGIC; -- new
76 76 nSRAM_BUSY : IN STD_LOGIC; -- new
77 77 -- SPW --------------------------------------------------------------------
78 78 spw1_en : OUT STD_LOGIC; -- new
79 79 spw1_din : IN STD_LOGIC;
80 80 spw1_sin : IN STD_LOGIC;
81 81 spw1_dout : OUT STD_LOGIC;
82 82 spw1_sout : OUT STD_LOGIC;
83 83 spw2_en : OUT STD_LOGIC; -- new
84 84 spw2_din : IN STD_LOGIC;
85 85 spw2_sin : IN STD_LOGIC;
86 86 spw2_dout : OUT STD_LOGIC;
87 87 spw2_sout : OUT STD_LOGIC;
88 88 -- ADC --------------------------------------------------------------------
89 89 bias_fail_sw : OUT STD_LOGIC;
90 90 ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
91 91 ADC_smpclk : OUT STD_LOGIC;
92 92 ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
93 93 -- DAC --------------------------------------------------------------------
94 94 DAC_SDO : OUT STD_LOGIC;
95 95 DAC_SCK : OUT STD_LOGIC;
96 96 DAC_SYNC : OUT STD_LOGIC;
97 97 DAC_CAL_EN : OUT STD_LOGIC;
98 98 -- HK ---------------------------------------------------------------------
99 99 HK_smpclk : OUT STD_LOGIC;
100 100 ADC_OEB_bar_HK : OUT STD_LOGIC;
101 101 HK_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
102 102 ---------------------------------------------------------------------------
103 103 TAG8 : OUT STD_LOGIC
104 104 );
105 105
106 106 END LFR_EQM;
107 107
108 108
109 109 ARCHITECTURE beh OF LFR_EQM IS
110 110
111 111 SIGNAL clk_25 : STD_LOGIC := '0';
112 112 SIGNAL clk_24 : STD_LOGIC := '0';
113 113 -----------------------------------------------------------------------------
114 114 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
115 115 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
116 116
117 117 -- CONSTANTS
118 118 CONSTANT CFG_PADTECH : INTEGER := inferred;
119 119 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
120 120 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
121 121 CONSTANT NB_AHB_MASTER : INTEGER := 3; -- 2 = grspw + waveform picker
122 122
123 123 SIGNAL apbi_ext : apb_slv_in_type;
124 124 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
125 125 SIGNAL ahbi_s_ext : ahb_slv_in_type;
126 126 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none);
127 127 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
128 128 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
129 129
130 130 -- Spacewire signals
131 131 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
132 132 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
133 133 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
134 134 SIGNAL spw_rxtxclk : STD_ULOGIC;
135 135 SIGNAL spw_rxclkn : STD_ULOGIC;
136 136 SIGNAL spw_clk : STD_LOGIC;
137 137 SIGNAL swni : grspw_in_type;
138 138 SIGNAL swno : grspw_out_type;
139 139
140 140 --GPIO
141 141 SIGNAL gpioi : gpio_in_type;
142 142 SIGNAL gpioo : gpio_out_type;
143 143
144 144 -- AD Converter ADS7886
145 145 SIGNAL sample : Samples14v(8 DOWNTO 0);
146 146 SIGNAL sample_s : Samples(8 DOWNTO 0);
147 147 SIGNAL sample_val : STD_LOGIC;
148 148 SIGNAL ADC_OEB_bar_CH_s : STD_LOGIC_VECTOR(8 DOWNTO 0);
149 149
150 150 -----------------------------------------------------------------------------
151 151 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
152 152
153 153 -----------------------------------------------------------------------------
154 154 SIGNAL rstn_25 : STD_LOGIC;
155 155 SIGNAL rstn_24 : STD_LOGIC;
156 156
157 157 SIGNAL LFR_soft_rstn : STD_LOGIC;
158 158 SIGNAL LFR_rstn : STD_LOGIC;
159 159
160 160 SIGNAL ADC_smpclk_s : STD_LOGIC;
161 161
162 162 SIGNAL nSRAM_CE : STD_LOGIC_VECTOR(1 DOWNTO 0);
163 163
164 164 SIGNAL clk50MHz_int : STD_LOGIC := '0';
165 165 SIGNAL clk_25_int : STD_LOGIC := '0';
166 166
167 167 component clkint port(A : in std_ulogic; Y :out std_ulogic); end component;
168 168
169 169 BEGIN -- beh
170 170
171 171 -----------------------------------------------------------------------------
172 172 -- CLK
173 173 -----------------------------------------------------------------------------
174 174 rst_domain25 : rstgen PORT MAP (reset, clk_25, '1', rstn_25, OPEN);
175 175 rst_domain24 : rstgen PORT MAP (reset, clk_24, '1', rstn_24, OPEN);
176 176
177 177 --clk_pad : clkint port map (A => clk50MHz, Y => clk50MHz_int );
178 178 clk50MHz_int <= clk50MHz;
179 179
180 180 PROCESS(clk50MHz_int)
181 181 BEGIN
182 182 IF clk50MHz_int'EVENT AND clk50MHz_int = '1' THEN
183 183 --clk_25_int <= NOT clk_25_int;
184 184 clk_25 <= NOT clk_25;
185 185 END IF;
186 186 END PROCESS;
187 187 --clk_pad_25 : clkint port map (A => clk_25_int, Y => clk_25 );
188 188
189 189 PROCESS(clk49_152MHz)
190 190 BEGIN
191 191 IF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN
192 192 clk_24 <= NOT clk_24;
193 193 END IF;
194 194 END PROCESS;
195 195
196 196 -----------------------------------------------------------------------------
197 197 --
198 198 leon3_soc_1 : leon3_soc
199 199 GENERIC MAP (
200 200 fabtech => apa3l,
201 201 memtech => apa3l,
202 202 padtech => inferred,
203 203 clktech => inferred,
204 204 disas => 0,
205 205 dbguart => 0,
206 206 pclow => 2,
207 207 clk_freq => 25000,
208 208 IS_RADHARD => 0,
209 209 NB_CPU => 1,
210 210 ENABLE_FPU => 1,
211 211 FPU_NETLIST => 0,
212 212 ENABLE_DSU => 1,
213 213 ENABLE_AHB_UART => 1,
214 214 ENABLE_APB_UART => 1,
215 215 ENABLE_IRQMP => 1,
216 216 ENABLE_GPT => 1,
217 217 NB_AHB_MASTER => NB_AHB_MASTER,
218 218 NB_AHB_SLAVE => NB_AHB_SLAVE,
219 219 NB_APB_SLAVE => NB_APB_SLAVE,
220 ADDRESS_SIZE => 20,
221 USES_IAP_MEMCTRLR => 0,
220 ADDRESS_SIZE => 19,
221 USES_IAP_MEMCTRLR => 1,
222 222 BYPASS_EDAC_MEMCTRLR => '0',
223 223 SRBANKSZ => 8)
224 224 PORT MAP (
225 225 clk => clk_25,
226 226 reset => rstn_25,
227 227 errorn => OPEN,
228 228
229 229 ahbrxd => TAG1,
230 230 ahbtxd => TAG3,
231 231 urxd1 => TAG2,
232 232 utxd1 => TAG4,
233 233
234 234 address => address,
235 235 data => data,
236 236 nSRAM_BE0 => OPEN,
237 237 nSRAM_BE1 => OPEN,
238 238 nSRAM_BE2 => OPEN,
239 239 nSRAM_BE3 => OPEN,
240 240 nSRAM_WE => nSRAM_W,
241 241 nSRAM_CE => nSRAM_CE,
242 242 nSRAM_OE => nSRAM_G,
243 243 nSRAM_READY => nSRAM_BUSY,
244 244 SRAM_MBE => nSRAM_MBE,
245 245
246 246 apbi_ext => apbi_ext,
247 247 apbo_ext => apbo_ext,
248 248 ahbi_s_ext => ahbi_s_ext,
249 249 ahbo_s_ext => ahbo_s_ext,
250 250 ahbi_m_ext => ahbi_m_ext,
251 251 ahbo_m_ext => ahbo_m_ext);
252 252
253 253
254 254 nSRAM_E1 <= nSRAM_CE(0);
255 255 nSRAM_E2 <= nSRAM_CE(1);
256 256
257 257 -------------------------------------------------------------------------------
258 258 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
259 259 -------------------------------------------------------------------------------
260 260 apb_lfr_management_1 : apb_lfr_management
261 261 GENERIC MAP (
262 262 tech => apa3l,
263 263 pindex => 6,
264 264 paddr => 6,
265 265 pmask => 16#fff#,
266 266 --FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
267 267 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
268 268 PORT MAP (
269 269 clk25MHz => clk_25,
270 270 resetn_25MHz => rstn_25, -- TODO
271 271 --clk24_576MHz => clk_24, -- 49.152MHz/2
272 272 --resetn_24_576MHz => rstn_24, -- TODO
273 273
274 274 grspw_tick => swno.tickout,
275 275 apbi => apbi_ext,
276 276 apbo => apbo_ext(6),
277 277
278 278 HK_sample => sample_s(8),
279 279 HK_val => sample_val,
280 280 HK_sel => HK_SEL,
281 281
282 282 DAC_SDO => DAC_SDO,
283 283 DAC_SCK => DAC_SCK,
284 284 DAC_SYNC => DAC_SYNC,
285 285 DAC_CAL_EN => DAC_CAL_EN,
286 286
287 287 coarse_time => coarse_time,
288 288 fine_time => fine_time,
289 289 LFR_soft_rstn => LFR_soft_rstn
290 290 );
291 291
292 292 -----------------------------------------------------------------------
293 293 --- SpaceWire --------------------------------------------------------
294 294 -----------------------------------------------------------------------
295 295
296 296 ------------------------------------------------------------------------------
297 297 -- \/\/\/\/ TODO : spacewire enable should be controled by the SPW IP \/\/\/\/
298 298 ------------------------------------------------------------------------------
299 299 spw1_en <= '1';
300 300 spw2_en <= '1';
301 301 ------------------------------------------------------------------------------
302 302 -- /\/\/\/\ --------------------------------------------------------- /\/\/\/\
303 303 ------------------------------------------------------------------------------
304 304
305 305 --spw_clk <= clk50MHz;
306 306 --spw_rxtxclk <= spw_clk;
307 307 --spw_rxclkn <= NOT spw_rxtxclk;
308 308
309 309 -- PADS for SPW1
310 310 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
311 311 PORT MAP (spw1_din, dtmp(0));
312 312 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
313 313 PORT MAP (spw1_sin, stmp(0));
314 314 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
315 315 PORT MAP (spw1_dout, swno.d(0));
316 316 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
317 317 PORT MAP (spw1_sout, swno.s(0));
318 318 -- PADS FOR SPW2
319 319 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
320 320 PORT MAP (spw2_din, dtmp(1));
321 321 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
322 322 PORT MAP (spw2_sin, stmp(1));
323 323 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
324 324 PORT MAP (spw2_dout, swno.d(1));
325 325 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
326 326 PORT MAP (spw2_sout, swno.s(1));
327 327
328 328 -- GRSPW PHY
329 329 --spw1_input: if CFG_SPW_GRSPW = 1 generate
330 330 spw_inputloop : FOR j IN 0 TO 1 GENERATE
331 331 spw_phy0 : grspw_phy
332 332 GENERIC MAP(
333 333 tech => apa3l,
334 334 rxclkbuftype => 1,
335 335 scantest => 0)
336 336 PORT MAP(
337 337 rxrst => swno.rxrst,
338 338 di => dtmp(j),
339 339 si => stmp(j),
340 340 rxclko => spw_rxclk(j),
341 341 do => swni.d(j),
342 342 ndo => swni.nd(j*5+4 DOWNTO j*5),
343 343 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
344 344 END GENERATE spw_inputloop;
345 345
346 346 -- SPW core
347 347 sw0 : grspwm GENERIC MAP(
348 348 tech => apa3l,
349 349 hindex => 1,
350 350 pindex => 5,
351 351 paddr => 5,
352 352 pirq => 11,
353 353 sysfreq => 25000, -- CPU_FREQ
354 354 rmap => 1,
355 355 rmapcrc => 1,
356 356 fifosize1 => 16,
357 357 fifosize2 => 16,
358 358 rxclkbuftype => 1,
359 359 rxunaligned => 0,
360 360 rmapbufs => 4,
361 361 ft => 0,
362 362 netlist => 0,
363 363 ports => 2,
364 364 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
365 365 memtech => apa3l,
366 366 destkey => 2,
367 367 spwcore => 1
368 368 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
369 369 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
370 370 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
371 371 )
372 372 PORT MAP(rstn_25, clk_25, spw_rxclk(0),
373 373 spw_rxclk(1),
374 374 clk50MHz_int,
375 375 clk50MHz_int,
376 376 -- spw_rxtxclk, spw_rxtxclk, spw_rxtxclk, spw_rxtxclk,
377 377 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
378 378 swni, swno);
379 379
380 380 swni.tickin <= '0';
381 381 swni.rmapen <= '1';
382 382 swni.clkdiv10 <= "00000100"; -- 50 MHz / (4 + 1) = 10 MHz
383 383 swni.tickinraw <= '0';
384 384 swni.timein <= (OTHERS => '0');
385 385 swni.dcrstval <= (OTHERS => '0');
386 386 swni.timerrstval <= (OTHERS => '0');
387 387
388 388 -------------------------------------------------------------------------------
389 389 -- LFR ------------------------------------------------------------------------
390 390 -------------------------------------------------------------------------------
391 391 LFR_rstn <= LFR_soft_rstn AND rstn_25;
392 392
393 393 lpp_lfr_1 : lpp_lfr
394 394 GENERIC MAP (
395 395 Mem_use => use_RAM,
396 396 nb_data_by_buffer_size => 32,
397 397 --nb_word_by_buffer_size => 30,
398 398 nb_snapshot_param_size => 32,
399 399 delta_vector_size => 32,
400 400 delta_vector_size_f0_2 => 7, -- log2(96)
401 401 pindex => 15,
402 402 paddr => 15,
403 403 pmask => 16#fff#,
404 404 pirq_ms => 6,
405 405 pirq_wfp => 14,
406 406 hindex => 2,
407 407 top_lfr_version => X"020145") -- aa.bb.cc version
408 408 -- AA : BOARD NUMBER
409 409 -- 0 => MINI_LFR
410 410 -- 1 => EM
411 411 -- 2 => EQM (with A3PE3000)
412 412 PORT MAP (
413 413 clk => clk_25,
414 414 rstn => LFR_rstn,
415 415 sample_B => sample_s(2 DOWNTO 0),
416 416 sample_E => sample_s(7 DOWNTO 3),
417 417 sample_val => sample_val,
418 418 apbi => apbi_ext,
419 419 apbo => apbo_ext(15),
420 420 ahbi => ahbi_m_ext,
421 421 ahbo => ahbo_m_ext(2),
422 422 coarse_time => coarse_time,
423 423 fine_time => fine_time,
424 424 data_shaping_BW => bias_fail_sw,
425 425 debug_vector => OPEN,
426 426 debug_vector_ms => OPEN); --,
427 427
428 428 lpp_lfr_2 : lpp_lfr
429 429 GENERIC MAP (
430 430 Mem_use => use_RAM,
431 431 nb_data_by_buffer_size => 32,
432 432 --nb_word_by_buffer_size => 30,
433 433 nb_snapshot_param_size => 32,
434 434 delta_vector_size => 32,
435 435 delta_vector_size_f0_2 => 7, -- log2(96)
436 436 pindex => 14,
437 437 paddr => 14,
438 438 pmask => 16#fff#,
439 439 pirq_ms => 6,
440 440 pirq_wfp => 14,
441 441 hindex => 3,
442 442 top_lfr_version => X"020145") -- aa.bb.cc version
443 443 -- AA : BOARD NUMBER
444 444 -- 0 => MINI_LFR
445 445 -- 1 => EM
446 446 -- 2 => EQM (with A3PE3000)
447 447 PORT MAP (
448 448 clk => clk_25,
449 449 rstn => LFR_rstn,
450 450 sample_B => sample_s(2 DOWNTO 0),
451 451 sample_E => sample_s(7 DOWNTO 3),
452 452 sample_val => sample_val,
453 453
454 454 apbi => apbi_ext,
455 455 apbo => apbo_ext(14),
456 456
457 457 ahbi => ahbi_m_ext,
458 458 ahbo => ahbo_m_ext(3),
459 459 coarse_time => coarse_time,
460 460 fine_time => fine_time,
461 461 data_shaping_BW => OPEN,--bias_fail_sw,
462 462 debug_vector => OPEN,
463 463 debug_vector_ms => OPEN); --,
464 464 --observation_vector_0 => OPEN,
465 465 --observation_vector_1 => OPEN,
466 466 --observation_reg => observation_reg);
467 467
468 468
469 469 all_sample : FOR I IN 7 DOWNTO 0 GENERATE
470 470 sample_s(I) <= sample(I) & '0' & '0';
471 471 END GENERATE all_sample;
472 472 sample_s(8) <= sample(8)(13) & sample(8)(13) & sample(8);
473 473
474 474 -----------------------------------------------------------------------------
475 475 --
476 476 -----------------------------------------------------------------------------
477 477 top_ad_conv_RHF1401_withFilter_1 : top_ad_conv_RHF1401_withFilter
478 478 GENERIC MAP (
479 479 ChanelCount => 9,
480 480 ncycle_cnv_high => 13,
481 481 ncycle_cnv => 25,
482 482 FILTER_ENABLED => 16#FF#)
483 483 PORT MAP (
484 484 cnv_clk => clk_24,
485 485 cnv_rstn => rstn_24,
486 486 cnv => ADC_smpclk_s,
487 487 clk => clk_25,
488 488 rstn => rstn_25,
489 489 ADC_data => ADC_data,
490 490 ADC_nOE => ADC_OEB_bar_CH_s,
491 491 sample => sample,
492 492 sample_val => sample_val);
493 493
494 494 ADC_OEB_bar_CH <= ADC_OEB_bar_CH_s(7 DOWNTO 0);
495 495
496 496 ADC_smpclk <= ADC_smpclk_s;
497 497 HK_smpclk <= ADC_smpclk_s;
498 498
499 499 TAG8 <= nSRAM_BUSY;
500 500
501 501 -----------------------------------------------------------------------------
502 502 -- HK
503 503 -----------------------------------------------------------------------------
504 504 ADC_OEB_bar_HK <= ADC_OEB_bar_CH_s(8);
505 505
506 506 END beh;
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@@ -1,178 +1,213
1
2 1 ------------------------------------------------------------------------------
3 2 -- This file is a part of the LPP VHDL IP LIBRARY
4 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
5 4 --
6 5 -- This program is free software; you can redistribute it and/or modify
7 6 -- it under the terms of the GNU General Public License as published by
8 7 -- the Free Software Foundation; either version 3 of the License, or
9 8 -- (at your option) any later version.
10 9 --
11 10 -- This program is distributed in the hope that it will be useful,
12 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
13 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 13 -- GNU General Public License for more details.
15 14 --
16 15 -- You should have received a copy of the GNU General Public License
17 16 -- along with this program; if not, write to the Free Software
18 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 18 -------------------------------------------------------------------------------
20 19 -- Author : Jean-christophe Pellion
21 20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
22 21 -- jean-christophe.pellion@easii-ic.com
23 22 -------------------------------------------------------------------------------
24 23 -- 1.0 - initial version
25 24 -------------------------------------------------------------------------------
26 25 LIBRARY ieee;
27 26 USE ieee.std_logic_1164.ALL;
28 27 USE ieee.numeric_std.ALL;
29 28 LIBRARY grlib;
30 29 USE grlib.amba.ALL;
31 30 USE grlib.stdlib.ALL;
32 31 USE grlib.devices.ALL;
33 32
34 33 LIBRARY lpp;
35 34 USE lpp.lpp_amba.ALL;
36 35 USE lpp.apb_devices_list.ALL;
37 36 USE lpp.lpp_memory.ALL;
38 37 USE lpp.lpp_dma_pkg.ALL;
39 38 USE lpp.general_purpose.ALL;
40 39 --USE lpp.lpp_waveform_pkg.ALL;
41 40 LIBRARY techmap;
42 41 USE techmap.gencomp.ALL;
43 42
44 43
45 44 ENTITY lpp_dma_SEND16B_FIFO2DMA IS
46 45 GENERIC (
47 46 hindex : INTEGER := 2;
48 47 vendorid : IN INTEGER := 0;
49 48 deviceid : IN INTEGER := 0;
50 49 version : IN INTEGER := 0
51 50 );
52 51 PORT (
53 52 clk : IN STD_LOGIC;
54 53 rstn : IN STD_LOGIC;
55 54
56 55 -- AMBA AHB Master Interface
57 56 AHB_Master_In : IN AHB_Mst_In_Type;
58 57 AHB_Master_Out : OUT AHB_Mst_Out_Type;
59 58
60 59 -- FIFO Interface
61 60 ren : OUT STD_LOGIC;
62 61 data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
63 62
64 63 -- Controls
65 64 send : IN STD_LOGIC;
66 65 valid_burst : IN STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
67 66 done : OUT STD_LOGIC;
68 67 address : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
69 68 );
70 69 END;
71 70
72 71 ARCHITECTURE Behavioral OF lpp_dma_SEND16B_FIFO2DMA IS
73 72
74 73 CONSTANT HConfig : AHB_Config_Type := (
75 74 0 => ahb_device_reg(vendorid, deviceid, 0, version, 0),
76 75 OTHERS => (OTHERS => '0'));
77 76
77 TYPE AHB_DMA_FSM_STATE IS (IDLE, s_ARBITER ,s_CTRL, s_CTRL_DATA, s_DATA);
78 SIGNAL state : AHB_DMA_FSM_STATE;
79
78 80 SIGNAL address_counter_reg : STD_LOGIC_VECTOR(3 DOWNTO 0);
79 81 SIGNAL address_counter : STD_LOGIC_VECTOR(3 DOWNTO 0);
80 82
81 SIGNAL address_counter_reset : STD_LOGIC;
82 SIGNAL address_counter_add1 : STD_LOGIC;
83 SIGNAL data_window : STD_LOGIC;
84 SIGNAL ctrl_window : STD_LOGIC;
83 85
84 SIGNAL REQ_ON_GOING : STD_LOGIC;
85 SIGNAL DATA_ON_GOING : STD_LOGIC;
86 SIGNAL DATA_ON_GOING_s : STD_LOGIC;
87 SIGNAL TRANSACTION_ON_GOING : STD_LOGIC;
88 SIGNAL internal_send : STD_LOGIC;
86 SIGNAL bus_request : STD_LOGIC;
87 SIGNAL bus_lock : STD_LOGIC;
89 88
90 89 BEGIN
91 90
92 91 -----------------------------------------------------------------------------
93 92 AHB_Master_Out.HCONFIG <= HConfig;
94 93 AHB_Master_Out.HSIZE <= "010"; --WORDS 32b
95 94 AHB_Master_Out.HINDEX <= hindex;
96 95 AHB_Master_Out.HPROT <= "0011"; --DATA ACCESS and PRIVILEDGED ACCESS
97 96 AHB_Master_Out.HIRQ <= (OTHERS => '0');
98 AHB_Master_Out.HBURST <= "001"; -- INCR --"111"; --INCR16
97 AHB_Master_Out.HBURST <= "111"; -- INCR --"111"; --INCR16
99 98 AHB_Master_Out.HWRITE <= '1';
100 AHB_Master_Out.HTRANS <= HTRANS_NONSEQ;
99
100 --AHB_Master_Out.HTRANS <= HTRANS_NONSEQ WHEN ctrl_window = '1' OR data_window = '1' ELSE HTRANS_IDLE;
101
102 --AHB_Master_Out.HBUSREQ <= bus_request;
103 --AHB_Master_Out.HLOCK <= data_window;
101 104
102 AHB_Master_Out.HBUSREQ <= REQ_ON_GOING WHEN NOT(address_counter = "1111" AND AHB_Master_In.HREADY = '1') ELSE '0';
103 AHB_Master_Out.HLOCK <= REQ_ON_GOING WHEN NOT(address_counter = "1111" AND AHB_Master_In.HREADY = '1') ELSE '0';
105 --bus_request <= '0' WHEN address_counter_reg = "1111" AND AHB_Master_In.HREADY = '1' ELSE
106 -- '1' WHEN ctrl_window = '1' ELSE
107 -- '0';
108
109 --bus_lock <= '0' WHEN address_counter_reg = "1111" ELSE
110 -- '1' WHEN ctrl_window = '1' ELSE '0';
111
104 112 -----------------------------------------------------------------------------
105
106 113 AHB_Master_Out.HADDR <= address(31 DOWNTO 6) & address_counter_reg & "00";
107 114 AHB_Master_Out.HWDATA <= ahbdrivedata(data);
108 115
109
110 116 -----------------------------------------------------------------------------
111 -- REN GEN
112 -----------------------------------------------------------------------------
113 ren <= NOT (AHB_Master_In.HREADY AND DATA_ON_GOING);
114
115 -----------------------------------------------------------------------------
116 -- ADDR GEN
117 --ren <= NOT ((AHB_Master_In.HGRANT(hindex) OR LAST_READ ) AND AHB_Master_In.HREADY );
118 --ren <= NOT beat;
117 119 -----------------------------------------------------------------------------
118 120 PROCESS (clk, rstn)
119 121 BEGIN -- PROCESS
120 122 IF rstn = '0' THEN -- asynchronous reset (active low)
123 state <= IDLE;
124 done <= '0';
121 125 address_counter_reg <= (OTHERS => '0');
122 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
123 IF DATA_ON_GOING = '0' THEN
124 address_counter_reg <= (OTHERS => '0');
125 ELSE
126 address_counter_reg <= address_counter;
127 END IF;
128 END IF;
129 END PROCESS;
130
131 --address_counter <= STD_LOGIC_VECTOR(UNSIGNED(address_counter_reg) + 1) WHEN AHB_Master_In.HGRANT(hindex) = '1' AND REQ_ON_GOING = '1' AND AHB_Master_In.HREADY = '1' ELSE
132 -- address_counter_reg;
133 address_counter <= STD_LOGIC_VECTOR(UNSIGNED(address_counter_reg) + 1) WHEN DATA_ON_GOING = '1' AND AHB_Master_In.HREADY = '1' ELSE
134 address_counter_reg;
135
136 -----------------------------------------------------------------------------
137 --
138 -----------------------------------------------------------------------------
139 PROCESS (clk, rstn)
140 BEGIN -- PROCESS
141 IF rstn = '0' THEN -- asynchronous reset (active low)
142 REQ_ON_GOING <= '0';
143 done <= '0';
144 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
126 AHB_Master_Out.HTRANS <= HTRANS_IDLE;
127 AHB_Master_Out.HBUSREQ <= '0';
128 AHB_Master_Out.HLOCK <= '0';
129 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
145 130 done <= '0';
146 IF send = '1' THEN --send = '1' THEN
147 REQ_ON_GOING <= '1';
148 ELSE
149 IF address_counter = "1111" AND AHB_Master_In.HREADY = '1' THEN
150 REQ_ON_GOING <= '0';
151 done <= '1';
152 END IF;
153 END IF;
131 CASE state IS
132 WHEN IDLE =>
133 AHB_Master_Out.HBUSREQ <= '0';
134 AHB_Master_Out.HLOCK <= '0';
135 AHB_Master_Out.HTRANS <= HTRANS_IDLE;
136 address_counter_reg <= (OTHERS => '0');
137 IF send = '1' THEN
138 AHB_Master_Out.HBUSREQ <= '1';
139 AHB_Master_Out.HLOCK <= '1';
140 AHB_Master_Out.HTRANS <= HTRANS_IDLE;
141 state <= s_ARBITER;
142 END IF;
143
144 WHEN s_ARBITER =>
145 AHB_Master_Out.HBUSREQ <= '1';
146 AHB_Master_Out.HLOCK <= '1';
147 AHB_Master_Out.HTRANS <= HTRANS_IDLE;
148 address_counter_reg <= (OTHERS => '0');
149
150 IF AHB_Master_In.HGRANT(hindex) = '1' THEN
151 AHB_Master_Out.HTRANS <= HTRANS_IDLE;
152 state <= s_CTRL;
153 END IF;
154
155 WHEN s_CTRL =>
156 AHB_Master_Out.HBUSREQ <= '1';
157 AHB_Master_Out.HLOCK <= '1';
158 AHB_Master_Out.HTRANS <= HTRANS_NONSEQ;
159 IF AHB_Master_In.HREADY = '1' AND AHB_Master_In.HGRANT(hindex) = '1' THEN
160 AHB_Master_Out.HTRANS <= HTRANS_SEQ;
161 state <= s_CTRL_DATA;
162 END IF;
163
164 WHEN s_CTRL_DATA =>
165 AHB_Master_Out.HBUSREQ <= '1';
166 AHB_Master_Out.HLOCK <= '1';
167 AHB_Master_Out.HTRANS <= HTRANS_SEQ;
168 IF AHB_Master_In.HREADY = '1' AND AHB_Master_In.HGRANT(hindex) = '1' THEN
169 address_counter_reg <= STD_LOGIC_VECTOR(UNSIGNED(address_counter_reg) + 1);
170 END IF;
171
172 IF address_counter_reg = "1111" AND AHB_Master_In.HREADY = '1' THEN
173 AHB_Master_Out.HBUSREQ <= '0';
174 AHB_Master_Out.HLOCK <= '1';--'0';
175 AHB_Master_Out.HTRANS <= HTRANS_IDLE;
176 state <= s_DATA;
177 END IF;
178
179 WHEN s_DATA =>
180 AHB_Master_Out.HBUSREQ <= '0';
181 AHB_Master_Out.HLOCK <= '0';
182 AHB_Master_Out.HTRANS <= HTRANS_IDLE;
183 IF AHB_Master_In.HREADY = '1' THEN
184 state <= IDLE;
185 done <= '1';
186 END IF;
187
188 WHEN OTHERS => NULL;
189 END CASE;
154 190 END IF;
155 191 END PROCESS;
156 192
193 ctrl_window <= '1' WHEN state = s_CTRL OR state = s_CTRL_DATA ELSE '0';
194 data_window <= '1' WHEN state = s_CTRL_DATA OR state = s_DATA ELSE '0';
157 195 -----------------------------------------------------------------------------
158 --
196 ren <= NOT( data_window AND AHB_Master_In.HREADY);
197
159 198 -----------------------------------------------------------------------------
160 PROCESS (clk, rstn)
161 BEGIN -- PROCESS
162 IF rstn = '0' THEN -- asynchronous reset (active low)
163 DATA_ON_GOING <= '0';
164 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
165 IF REQ_ON_GOING = '1' AND AHB_Master_In.HGRANT(hindex) = '1' THEN
166 DATA_ON_GOING <= '1';
167 ELSE
168 IF address_counter_reg = "1111" AND AHB_Master_In.HREADY = '1' THEN
169 DATA_ON_GOING <= '0';
170 END IF;
171 -- DATA_ON_GOING_s <= REQ_ON_GOING ;
172 END IF;
173 END IF;
174 END PROCESS;
175 --DATA_ON_GOING <= DATA_ON_GOING_s AND REQ_ON_GOING;
176
199 --PROCESS (clk, rstn)
200 --BEGIN -- PROCESS
201 -- IF rstn = '0' THEN -- asynchronous reset (active low)
202 -- address_counter_reg <= (OTHERS => '0');
203 -- ELSIF clk'event AND clk = '1' THEN -- rising clock edge
204 -- address_counter_reg <= address_counter;
205 -- END IF;
206 --END PROCESS;
207
208 --address_counter <= STD_LOGIC_VECTOR(UNSIGNED(address_counter_reg) + 1) WHEN data_window = '1' AND AHB_Master_In.HREADY = '1' AND AHB_Master_In.HGRANT(hindex) = '1' ELSE
209 -- address_counter_reg;
210 -----------------------------------------------------------------------------
211
177 212
178 213 END Behavioral;
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@@ -1,574 +1,574
1 1 -----------------------------------------------------------------------------
2 2 -- LEON3 Demonstration design
3 3 -- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 2 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 ------------------------------------------------------------------------------
19 19
20 20
21 21 LIBRARY ieee;
22 22 USE ieee.std_logic_1164.ALL;
23 23 LIBRARY grlib;
24 24 USE grlib.amba.ALL;
25 25 USE grlib.stdlib.ALL;
26 26 LIBRARY techmap;
27 27 USE techmap.gencomp.ALL;
28 28 LIBRARY gaisler;
29 29 USE gaisler.memctrl.ALL;
30 30 USE gaisler.leon3.ALL;
31 31 USE gaisler.uart.ALL;
32 32 USE gaisler.misc.ALL;
33 33 USE gaisler.spacewire.ALL; -- PLE
34 34 LIBRARY esa;
35 35 USE esa.memoryctrl.ALL;
36 36 LIBRARY lpp;
37 37 USE lpp.lpp_memory.ALL;
38 38 USE lpp.lpp_ad_conv.ALL;
39 39 USE lpp.lpp_lfr_pkg.ALL;
40 40 USE lpp.iir_filter.ALL;
41 41 USE lpp.general_purpose.ALL;
42 42 USE lpp.lpp_leon3_soc_pkg.ALL;
43 43 LIBRARY iap;
44 44 USE iap.memctrl.ALL;
45 45
46 46
47 47 ENTITY leon3_soc IS
48 48 GENERIC (
49 49 fabtech : INTEGER := apa3e;
50 50 memtech : INTEGER := apa3e;
51 51 padtech : INTEGER := inferred;
52 52 clktech : INTEGER := inferred;
53 53 disas : INTEGER := 0; -- Enable disassembly to console
54 54 dbguart : INTEGER := 0; -- Print UART on console
55 55 pclow : INTEGER := 2;
56 56 --
57 57 clk_freq : INTEGER := 25000; --kHz
58 58 --
59 59 IS_RADHARD : INTEGER := 0;
60 60 --
61 61 NB_CPU : INTEGER := 1;
62 62 ENABLE_FPU : INTEGER := 1;
63 63 FPU_NETLIST : INTEGER := 1;
64 64 ENABLE_DSU : INTEGER := 1;
65 65 ENABLE_AHB_UART : INTEGER := 1;
66 66 ENABLE_APB_UART : INTEGER := 1;
67 67 ENABLE_IRQMP : INTEGER := 1;
68 68 ENABLE_GPT : INTEGER := 1;
69 69 --
70 70 NB_AHB_MASTER : INTEGER := 1;
71 71 NB_AHB_SLAVE : INTEGER := 1;
72 72 NB_APB_SLAVE : INTEGER := 1;
73 73 --
74 74 ADDRESS_SIZE : INTEGER := 20;
75 75 USES_IAP_MEMCTRLR : INTEGER := 0;
76 76 BYPASS_EDAC_MEMCTRLR : STD_LOGIC := '0';
77 77 SRBANKSZ : INTEGER := 8
78 78
79 79 );
80 80 PORT (
81 81 clk : IN STD_ULOGIC;
82 82 reset : IN STD_ULOGIC;
83 83
84 84 errorn : OUT STD_ULOGIC;
85 85
86 86 -- UART AHB ---------------------------------------------------------------
87 87 ahbrxd : IN STD_ULOGIC; -- DSU rx data
88 88 ahbtxd : OUT STD_ULOGIC; -- DSU tx data
89 89
90 90 -- UART APB ---------------------------------------------------------------
91 91 urxd1 : IN STD_ULOGIC; -- UART1 rx data
92 92 utxd1 : OUT STD_ULOGIC; -- UART1 tx data
93 93
94 94 -- RAM --------------------------------------------------------------------
95 95 address : OUT STD_LOGIC_VECTOR(ADDRESS_SIZE-1 DOWNTO 0);
96 96 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
97 97 nSRAM_BE0 : OUT STD_LOGIC;
98 98 nSRAM_BE1 : OUT STD_LOGIC;
99 99 nSRAM_BE2 : OUT STD_LOGIC;
100 100 nSRAM_BE3 : OUT STD_LOGIC;
101 101 nSRAM_WE : OUT STD_LOGIC;
102 102 nSRAM_CE : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
103 103 nSRAM_OE : OUT STD_LOGIC;
104 104 nSRAM_READY : IN STD_LOGIC;
105 105 SRAM_MBE : INOUT STD_LOGIC;
106 106 -- APB --------------------------------------------------------------------
107 107 apbi_ext : OUT apb_slv_in_type;
108 108 apbo_ext : IN soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5);
109 109 -- AHB_Slave --------------------------------------------------------------
110 110 ahbi_s_ext : OUT ahb_slv_in_type;
111 111 ahbo_s_ext : IN soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3);
112 112 -- AHB_Master -------------------------------------------------------------
113 113 ahbi_m_ext : OUT AHB_Mst_In_Type;
114 114 ahbo_m_ext : IN soc_ahb_mst_out_vector(NB_AHB_MASTER-1+NB_CPU DOWNTO NB_CPU)
115 115
116 116 );
117 117 END;
118 118
119 119 ARCHITECTURE Behavioral OF leon3_soc IS
120 120
121 121 -----------------------------------------------------------------------------
122 122 -- CONFIG -------------------------------------------------------------------
123 123 -----------------------------------------------------------------------------
124 124
125 125 -- Clock generator
126 126 CONSTANT CFG_CLKMUL : INTEGER := (1);
127 127 CONSTANT CFG_CLKDIV : INTEGER := (1); -- divide 50MHz by 2 to get 25MHz
128 128 CONSTANT CFG_OCLKDIV : INTEGER := (1);
129 129 CONSTANT CFG_CLK_NOFB : INTEGER := 0;
130 130 -- LEON3 processor core
131 131 CONSTANT CFG_LEON3 : INTEGER := 1;
132 132 CONSTANT CFG_NCPU : INTEGER := NB_CPU;
133 133 CONSTANT CFG_NWIN : INTEGER := (8); -- to be compatible with BCC and RCC
134 134 CONSTANT CFG_V8 : INTEGER := 0;
135 135 CONSTANT CFG_MAC : INTEGER := 0;
136 136 CONSTANT CFG_SVT : INTEGER := 0;
137 137 CONSTANT CFG_RSTADDR : INTEGER := 16#00000#;
138 138 CONSTANT CFG_LDDEL : INTEGER := (1);
139 139 CONSTANT CFG_NWP : INTEGER := (0);
140 140 CONSTANT CFG_PWD : INTEGER := 1*2;
141 141 CONSTANT CFG_FPU : INTEGER := ENABLE_FPU *(8 + 16 * FPU_NETLIST);
142 142 -- 1*(8 + 16 * 0) => grfpu-light
143 143 -- 1*(8 + 16 * 1) => netlist
144 144 -- 0*(8 + 16 * 0) => No FPU
145 145 -- 0*(8 + 16 * 1) => No FPU;
146 146 CONSTANT CFG_ICEN : INTEGER := 1;
147 147 CONSTANT CFG_ISETS : INTEGER := 1;
148 148 CONSTANT CFG_ISETSZ : INTEGER := 4;
149 149 CONSTANT CFG_ILINE : INTEGER := 4;
150 150 CONSTANT CFG_IREPL : INTEGER := 0;
151 151 CONSTANT CFG_ILOCK : INTEGER := 0;
152 152 CONSTANT CFG_ILRAMEN : INTEGER := 0;
153 153 CONSTANT CFG_ILRAMADDR : INTEGER := 16#8E#;
154 154 CONSTANT CFG_ILRAMSZ : INTEGER := 1;
155 155 CONSTANT CFG_DCEN : INTEGER := 1;
156 156 CONSTANT CFG_DSETS : INTEGER := 1;
157 157 CONSTANT CFG_DSETSZ : INTEGER := 4;
158 158 CONSTANT CFG_DLINE : INTEGER := 4;
159 159 CONSTANT CFG_DREPL : INTEGER := 0;
160 160 CONSTANT CFG_DLOCK : INTEGER := 0;
161 161 CONSTANT CFG_DSNOOP : INTEGER := 0 + 0 + 4*0;
162 162 CONSTANT CFG_DLRAMEN : INTEGER := 0;
163 163 CONSTANT CFG_DLRAMADDR : INTEGER := 16#8F#;
164 164 CONSTANT CFG_DLRAMSZ : INTEGER := 1;
165 165 CONSTANT CFG_MMUEN : INTEGER := 0;
166 166 CONSTANT CFG_ITLBNUM : INTEGER := 2;
167 167 CONSTANT CFG_DTLBNUM : INTEGER := 2;
168 168 CONSTANT CFG_TLB_TYPE : INTEGER := 1 + 0*2;
169 169 CONSTANT CFG_TLB_REP : INTEGER := 1;
170 170
171 171 CONSTANT CFG_DSU : INTEGER := ENABLE_DSU;
172 172 CONSTANT CFG_ITBSZ : INTEGER := 0;
173 173 CONSTANT CFG_ATBSZ : INTEGER := 0;
174 174
175 175 -- AMBA settings
176 176 CONSTANT CFG_DEFMST : INTEGER := (0);
177 177 CONSTANT CFG_RROBIN : INTEGER := 1;
178 178 CONSTANT CFG_SPLIT : INTEGER := 0;
179 179 CONSTANT CFG_AHBIO : INTEGER := 16#FFF#;
180 180 CONSTANT CFG_APBADDR : INTEGER := 16#800#;
181 181
182 182 -- DSU UART
183 183 CONSTANT CFG_AHB_UART : INTEGER := ENABLE_AHB_UART;
184 184
185 185 -- LEON2 memory controller
186 186 CONSTANT CFG_MCTRL_SDEN : INTEGER := 0;
187 187
188 188 -- UART 1
189 189 CONSTANT CFG_UART1_ENABLE : INTEGER := ENABLE_APB_UART;
190 190 CONSTANT CFG_UART1_FIFO : INTEGER := 1;
191 191
192 192 -- LEON3 interrupt controller
193 193 CONSTANT CFG_IRQ3_ENABLE : INTEGER := ENABLE_IRQMP;
194 194
195 195 -- Modular timer
196 196 CONSTANT CFG_GPT_ENABLE : INTEGER := ENABLE_GPT;
197 197 CONSTANT CFG_GPT_NTIM : INTEGER := (2);
198 198 CONSTANT CFG_GPT_SW : INTEGER := (8);
199 199 CONSTANT CFG_GPT_TW : INTEGER := (32);
200 200 CONSTANT CFG_GPT_IRQ : INTEGER := (8);
201 201 CONSTANT CFG_GPT_SEPIRQ : INTEGER := 1;
202 202 CONSTANT CFG_GPT_WDOGEN : INTEGER := 0;
203 203 CONSTANT CFG_GPT_WDOG : INTEGER := 16#0#;
204 204 -----------------------------------------------------------------------------
205 205
206 206 -----------------------------------------------------------------------------
207 207 -- SIGNALs
208 208 -----------------------------------------------------------------------------
209 209 CONSTANT maxahbmsp : INTEGER := CFG_NCPU + CFG_AHB_UART + NB_AHB_MASTER;
210 210 -- CLK & RST --
211 211 SIGNAL clk2x : STD_ULOGIC;
212 212 SIGNAL clkmn : STD_ULOGIC;
213 213 SIGNAL clkm : STD_ULOGIC;
214 214 SIGNAL rstn : STD_ULOGIC;
215 215 SIGNAL rstraw : STD_ULOGIC;
216 216 SIGNAL pciclk : STD_ULOGIC;
217 217 SIGNAL sdclkl : STD_ULOGIC;
218 218 SIGNAL cgi : clkgen_in_type;
219 219 SIGNAL cgo : clkgen_out_type;
220 220 --- AHB / APB
221 221 SIGNAL apbi : apb_slv_in_type;
222 222 SIGNAL apbo : apb_slv_out_vector := (OTHERS => apb_none);
223 223 SIGNAL ahbsi : ahb_slv_in_type;
224 224 SIGNAL ahbso : ahb_slv_out_vector := (OTHERS => ahbs_none);
225 225 SIGNAL ahbmi : ahb_mst_in_type;
226 226 SIGNAL ahbmo : ahb_mst_out_vector := (OTHERS => ahbm_none);
227 227 --UART
228 228 SIGNAL ahbuarti : uart_in_type;
229 229 SIGNAL ahbuarto : uart_out_type;
230 230 SIGNAL apbuarti : uart_in_type;
231 231 SIGNAL apbuarto : uart_out_type;
232 232 --MEM CTRLR
233 233 SIGNAL memi : memory_in_type;
234 234 SIGNAL memo : memory_out_type;
235 235 SIGNAL wpo : wprot_out_type;
236 236 SIGNAL sdo : sdram_out_type;
237 237 SIGNAL mbe : STD_LOGIC; -- enable memory programming
238 238 SIGNAL mbe_drive : STD_LOGIC; -- drive the MBE memory signal
239 239 SIGNAL nSRAM_CE_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
240 240 SIGNAL nSRAM_OE_s : STD_LOGIC;
241 241 --IRQ
242 242 SIGNAL irqi : irq_in_vector(0 TO CFG_NCPU-1);
243 243 SIGNAL irqo : irq_out_vector(0 TO CFG_NCPU-1);
244 244 --Timer
245 245 SIGNAL gpti : gptimer_in_type;
246 246 SIGNAL gpto : gptimer_out_type;
247 247 --DSU
248 248 SIGNAL dbgi : l3_debug_in_vector(0 TO CFG_NCPU-1);
249 249 SIGNAL dbgo : l3_debug_out_vector(0 TO CFG_NCPU-1);
250 250 SIGNAL dsui : dsu_in_type;
251 251 SIGNAL dsuo : dsu_out_type;
252 252 -----------------------------------------------------------------------------
253 253
254 254
255 255 BEGIN
256 256
257 257
258 258 ----------------------------------------------------------------------
259 259 --- Reset and Clock generation -------------------------------------
260 260 ----------------------------------------------------------------------
261 261
262 262 cgi.pllctrl <= "00";
263 263 cgi.pllrst <= rstraw;
264 264
265 265 rst0 : rstgen PORT MAP (reset, clkm, cgo.clklock, rstn, rstraw);
266 266
267 267 clkgen0 : clkgen -- clock generator
268 268 GENERIC MAP (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN,
269 269 CFG_CLK_NOFB, 0, 0, 0, clk_freq, 0, 0, CFG_OCLKDIV)
270 270 PORT MAP (clk, clk, clkm, clkmn, clk2x, sdclkl, pciclk, cgi, cgo);
271 271
272 272 ----------------------------------------------------------------------
273 273 --- LEON3 processor / DSU / IRQ ------------------------------------
274 274 ----------------------------------------------------------------------
275 275
276 276 l3 : IF CFG_LEON3 = 1 GENERATE
277 277 cpu : FOR i IN 0 TO CFG_NCPU-1 GENERATE
278 278 leon3_non_radhard : IF IS_RADHARD = 0 GENERATE
279 279 u0 : ENTITY gaisler.leon3s -- LEON3 processor
280 280 GENERIC MAP (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
281 281 0, CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
282 282 CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
283 283 CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
284 284 CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
285 285 CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1)
286 286 PORT MAP (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
287 287 irqi(i), irqo(i), dbgi(i), dbgo(i));
288 288 END GENERATE leon3_non_radhard;
289 289
290 290 leon3_radhard_i : IF IS_RADHARD = 1 GENERATE
291 291 cpu : ENTITY gaisler.leon3ft
292 292 GENERIC MAP (
293 293 HINDEX => i, --: integer; --CPU_HINDEX,
294 294 FABTECH => fabtech, --CFG_TECH,
295 295 MEMTECH => memtech, --CFG_TECH,
296 296 NWINDOWS => CFG_NWIN, --CFG_NWIN,
297 297 DSU => CFG_DSU, --condSel (HAS_DEBUG, 1, 0),
298 298 FPU => CFG_FPU, --CFG_FPU,
299 299 V8 => CFG_V8, --CFG_V8,
300 300 CP => 0, --CFG_CP,
301 301 MAC => CFG_MAC, --CFG_MAC,
302 302 PCLOW => pclow, --CFG_PCLOW,
303 303 NOTAG => 0, --CFG_NOTAG,
304 304 NWP => CFG_NWP, --CFG_NWP,
305 305 ICEN => CFG_ICEN, --CFG_ICEN,
306 306 IREPL => CFG_IREPL, --CFG_IREPL,
307 307 ISETS => CFG_ISETS, --CFG_ISETS,
308 308 ILINESIZE => CFG_ILINE, --CFG_ILINE,
309 309 ISETSIZE => CFG_ISETSZ, --CFG_ISETSZ,
310 310 ISETLOCK => CFG_ILOCK, --CFG_ILOCK,
311 311 DCEN => CFG_DCEN, --CFG_DCEN,
312 312 DREPL => CFG_DREPL, --CFG_DREPL,
313 313 DSETS => CFG_DSETS, --CFG_DSETS,
314 314 DLINESIZE => CFG_DLINE, --CFG_DLINE,
315 315 DSETSIZE => CFG_DSETSZ, --CFG_DSETSZ,
316 316 DSETLOCK => CFG_DLOCK, --CFG_DLOCK,
317 317 DSNOOP => CFG_DSNOOP, --CFG_DSNOOP,
318 318 ILRAM => CFG_ILRAMEN, --CFG_ILRAMEN,
319 319 ILRAMSIZE => CFG_ILRAMSZ, --CFG_ILRAMSZ,
320 320 ILRAMSTART => CFG_ILRAMADDR, --CFG_ILRAMADDR,
321 321 DLRAM => CFG_DLRAMEN, --CFG_DLRAMEN,
322 322 DLRAMSIZE => CFG_DLRAMSZ, --CFG_DLRAMSZ,
323 323 DLRAMSTART => CFG_DLRAMADDR, --CFG_DLRAMADDR,
324 324 MMUEN => CFG_MMUEN, --CFG_MMUEN,
325 325 ITLBNUM => CFG_ITLBNUM, --CFG_ITLBNUM,
326 326 DTLBNUM => CFG_DTLBNUM, --CFG_DTLBNUM,
327 327 TLB_TYPE => CFG_TLB_TYPE, --CFG_TLB_TYPE,
328 328 TLB_REP => CFG_TLB_REP, --CFG_TLB_REP,
329 329 LDDEL => CFG_LDDEL, --CFG_LDDEL,
330 330 DISAS => disas, --condSel (SIM_ENABLED, 1, 0),
331 331 TBUF => CFG_ITBSZ, --CFG_ITBSZ,
332 332 PWD => CFG_PWD, --CFG_PWD,
333 333 SVT => CFG_SVT, --CFG_SVT,
334 334 RSTADDR => CFG_RSTADDR, --CFG_RSTADDR,
335 335 SMP => CFG_NCPU-1, --CFG_NCPU-1,
336 336 IUFT => 2, --: integer range 0 to 4;--CFG_IUFT_EN,
337 337 FPFT => 1, --: integer range 0 to 4;--CFG_FPUFT_EN,
338 338 CMFT => 1, --: integer range 0 to 1;--CFG_CACHE_FT_EN,
339 339 IUINJ => 0, --: integer; --CFG_RF_ERRINJ,
340 340 CEINJ => 0, --: integer range 0 to 3;--CFG_CACHE_ERRINJ,
341 341 CACHED => 0, --: integer; --CFG_DFIXED,
342 342 NETLIST => 0, --: integer; --CFG_LEON3_NETLIST,
343 343 SCANTEST => 0, --: integer; --CFG_SCANTEST,
344 344 MMUPGSZ => 0, --: integer range 0 to 5;--CFG_MMU_PAGE,
345 345 BP => 1) --CFG_BP
346 346 PORT MAP ( --
347 347 rstn => rstn, --rst_n,
348 348 clk => clkm, --clk,
349 349 ahbi => ahbmi, --ahbmi,
350 350 ahbo => ahbmo(i), --ahbmo(CPU_HINDEX),
351 351 ahbsi => ahbsi, --ahbsi,
352 352 ahbso => ahbso, --ahbso,
353 353 irqi => irqi(i), --irqi(CPU_HINDEX),
354 354 irqo => irqo(i), --irqo(CPU_HINDEX),
355 355 dbgi => dbgi(i), --dbgi(CPU_HINDEX),
356 356 dbgo => dbgo(i), --dbgo(CPU_HINDEX),
357 357 gclk => clkm --clk
358 358 );
359 359 END GENERATE leon3_radhard_i;
360 360
361 361 END GENERATE;
362 362 errorn_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (errorn, dbgo(0).error);
363 363
364 364 dsugen : IF CFG_DSU = 1 GENERATE
365 365
366 366 dsu0 : dsu3 -- LEON3 Debug Support Unit
367 GENERIC MAP (hindex => 2, -- TODO : hindex => 2
367 GENERIC MAP (hindex => 0, -- TODO : hindex => 2
368 368 haddr => 16#900#, hmask => 16#F00#,
369 369 ncpu => CFG_NCPU, tbits => 30, tech => memtech,
370 370 irq => 0, kbytes => CFG_ATBSZ)
371 PORT MAP (rstn, clkm, ahbmi, ahbsi, ahbso(2),-- TODO :ahbso(2)
371 PORT MAP (rstn, clkm, ahbmi, ahbsi, ahbso(0),-- TODO :ahbso(2)
372 372 dbgo, dbgi, dsui, dsuo);
373 373 dsui.enable <= '1';
374 374 dsui.break <= '0';
375 375
376 376 END GENERATE;
377 377 END GENERATE;
378 378
379 379 nodsu : IF CFG_DSU = 0 GENERATE
380 380 ahbso(2) <= ahbs_none;
381 381 dsuo.tstop <= '0';
382 382 dsuo.active <= '0';
383 383 END GENERATE;
384 384
385 385 irqctrl : IF CFG_IRQ3_ENABLE /= 0 GENERATE
386 386 irqctrl0 : irqmp -- interrupt controller
387 387 GENERIC MAP (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
388 388 PORT MAP (rstn, clkm, apbi, apbo(2), irqo, irqi);
389 389 END GENERATE;
390 390 irq3 : IF CFG_IRQ3_ENABLE = 0 GENERATE
391 391 x : FOR i IN 0 TO CFG_NCPU-1 GENERATE
392 392 irqi(i).irl <= "0000";
393 393 END GENERATE;
394 394 apbo(2) <= apb_none;
395 395 END GENERATE;
396 396
397 397 ----------------------------------------------------------------------
398 398 --- Memory controllers ---------------------------------------------
399 399 ----------------------------------------------------------------------
400 400 ESAMEMCT : IF USES_IAP_MEMCTRLR = 0 GENERATE
401 401 memctrlr : mctrl GENERIC MAP (
402 402 hindex => 0,
403 403 pindex => 0,
404 404 paddr => 0,
405 405 srbanks => 1
406 406 )
407 407 PORT MAP (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
408 408 memi.bexcn <= '1';
409 409 memi.brdyn <= '1';
410 410
411 411 nSRAM_CE_s <= NOT (memo.ramsn(1 DOWNTO 0));
412 412 nSRAM_OE_s <= memo.ramoen(0);
413 413 END GENERATE;
414 414
415 415 IAPMEMCT : IF USES_IAP_MEMCTRLR = 1 GENERATE
416 416 memctrlr : srctrle_0ws
417 417 GENERIC MAP(
418 418 hindex => 2, -- TODO : hindex => 0
419 419 pindex => 0,
420 420 paddr => 0,
421 421 srbanks => 2,
422 422 banksz => SRBANKSZ, --512k * 32
423 423 rmw => 1,
424 424 --Aeroflex memory generics:
425 425 mbpedac => BYPASS_EDAC_MEMCTRLR,
426 426 mprog => 1, -- program memory by default values after reset
427 427 mpsrate => 15, -- default scrub rate period
428 428 mpb2s => 14, -- default busy to scrub delay
429 429 mpapb => 1, -- instantiate apb register
430 430 mchipcnt => 2,
431 431 mpenall => 1 -- when 0 program only E1 chip, else program all dies
432 432 )
433 433 PORT MAP (
434 434 rst => rstn,
435 435 clk => clkm,
436 436 ahbsi => ahbsi,
437 437 ahbso => ahbso(2), -- TODO :ahbso(0),
438 438 apbi => apbi,
439 439 apbo => apbo(0),
440 440 sri => memi,
441 441 sro => memo,
442 442 --Aeroflex memory signals:
443 443 ucerr => OPEN, -- uncorrectable error signal
444 444 mbe => mbe, -- enable memory programming
445 445 mbe_drive => mbe_drive -- drive the MBE memory signal
446 446 );
447 447
448 448 memi.brdyn <= nSRAM_READY;
449 449
450 450 mbe_pad : iopad
451 451 GENERIC MAP(tech => padtech, oepol => USES_IAP_MEMCTRLR)
452 452 PORT MAP(pad => SRAM_MBE,
453 453 i => mbe,
454 454 en => mbe_drive,
455 455 o => memi.bexcn);
456 456
457 457 nSRAM_CE_s <= (memo.ramsn(1 DOWNTO 0));
458 458 nSRAM_OE_s <= memo.oen;
459 459
460 460 END GENERATE;
461 461
462 462
463 463 memi.writen <= '1';
464 464 memi.wrn <= "1111";
465 465 memi.bwidth <= "10";
466 466
467 467 bdr : FOR i IN 0 TO 3 GENERATE
468 468 data_pad : iopadv GENERIC MAP (tech => padtech, width => 8, oepol => USES_IAP_MEMCTRLR)
469 469 PORT MAP (
470 470 data(31-i*8 DOWNTO 24-i*8),
471 471 memo.data(31-i*8 DOWNTO 24-i*8),
472 472 memo.bdrive(i),
473 473 memi.data(31-i*8 DOWNTO 24-i*8));
474 474 END GENERATE;
475 475
476 476 addr_pad : outpadv GENERIC MAP (width => ADDRESS_SIZE, tech => padtech)
477 477 PORT MAP (address, memo.address(ADDRESS_SIZE+1 DOWNTO 2));
478 478 rams_pad : outpadv GENERIC MAP (tech => padtech, width => 2) PORT MAP (nSRAM_CE, nSRAM_CE_s);
479 479 oen_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_OE, nSRAM_OE_s);
480 480 nBWE_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_WE, memo.writen);
481 481 nBWa_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE0, memo.mben(3));
482 482 nBWb_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE1, memo.mben(2));
483 483 nBWc_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE2, memo.mben(1));
484 484 nBWd_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE3, memo.mben(0));
485 485
486 486
487 487
488 488 ----------------------------------------------------------------------
489 489 --- AHB CONTROLLER -------------------------------------------------
490 490 ----------------------------------------------------------------------
491 491 ahb0 : ahbctrl -- AHB arbiter/multiplexer
492 492 GENERIC MAP (defmast => CFG_DEFMST, split => CFG_SPLIT,
493 493 rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
494 494 ioen => 0, nahbm => maxahbmsp, nahbs => 8, fixbrst => 0)
495 495 PORT MAP (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
496 496
497 497 ----------------------------------------------------------------------
498 498 --- AHB UART -------------------------------------------------------
499 499 ----------------------------------------------------------------------
500 500 dcomgen : IF CFG_AHB_UART = 1 GENERATE
501 501 dcom0 : ahbuart
502 502 GENERIC MAP (hindex => maxahbmsp-1, pindex => 4, paddr => 4)
503 503 PORT MAP (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(4), ahbmi, ahbmo(maxahbmsp-1));
504 504 dsurx_pad : inpad GENERIC MAP (tech => padtech) PORT MAP (ahbrxd, ahbuarti.rxd);
505 505 dsutx_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (ahbtxd, ahbuarto.txd);
506 506 END GENERATE;
507 507 nouah : IF CFG_AHB_UART = 0 GENERATE apbo(4) <= apb_none; END GENERATE;
508 508
509 509 ----------------------------------------------------------------------
510 510 --- APB Bridge -----------------------------------------------------
511 511 ----------------------------------------------------------------------
512 512 apb0 : apbctrl -- AHB/APB bridge
513 513 GENERIC MAP (hindex => 1, haddr => CFG_APBADDR)
514 514 PORT MAP (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
515 515
516 516 ----------------------------------------------------------------------
517 517 --- GPT Timer ------------------------------------------------------
518 518 ----------------------------------------------------------------------
519 519 gpt : IF CFG_GPT_ENABLE /= 0 GENERATE
520 520 timer0 : gptimer -- timer unit
521 521 GENERIC MAP (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
522 522 sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
523 523 nbits => CFG_GPT_TW)
524 524 PORT MAP (rstn, clkm, apbi, apbo(3), gpti, gpto);
525 525 gpti.dhalt <= dsuo.tstop;
526 526 gpti.extclk <= '0';
527 527 END GENERATE;
528 528 notim : IF CFG_GPT_ENABLE = 0 GENERATE apbo(3) <= apb_none; END GENERATE;
529 529
530 530
531 531 ----------------------------------------------------------------------
532 532 --- APB UART -------------------------------------------------------
533 533 ----------------------------------------------------------------------
534 534 ua1 : IF CFG_UART1_ENABLE /= 0 GENERATE
535 535 uart1 : apbuart -- UART 1
536 536 GENERIC MAP (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
537 537 fifosize => CFG_UART1_FIFO)
538 538 PORT MAP (rstn, clkm, apbi, apbo(1), apbuarti, apbuarto);
539 539 apbuarti.rxd <= urxd1;
540 540 apbuarti.extclk <= '0';
541 541 utxd1 <= apbuarto.txd;
542 542 apbuarti.ctsn <= '0';
543 543 END GENERATE;
544 544 noua0 : IF CFG_UART1_ENABLE = 0 GENERATE apbo(1) <= apb_none; END GENERATE;
545 545
546 546 -------------------------------------------------------------------------------
547 547 -- AMBA BUS -------------------------------------------------------------------
548 548 -------------------------------------------------------------------------------
549 549
550 550 -- APB --------------------------------------------------------------------
551 551 apbi_ext <= apbi;
552 552 all_apb : FOR I IN 0 TO NB_APB_SLAVE-1 GENERATE
553 553 max_16_apb : IF I + 5 < 16 GENERATE
554 554 apbo(I+5) <= apbo_ext(I+5);
555 555 END GENERATE max_16_apb;
556 556 END GENERATE all_apb;
557 557 -- AHB_Slave --------------------------------------------------------------
558 558 ahbi_s_ext <= ahbsi;
559 559 all_ahbs : FOR I IN 0 TO NB_AHB_SLAVE-1 GENERATE
560 560 max_16_ahbs : IF I + 3 < 16 GENERATE
561 561 ahbso(I+3) <= ahbo_s_ext(I+3);
562 562 END GENERATE max_16_ahbs;
563 563 END GENERATE all_ahbs;
564 564 -- AHB_Master -------------------------------------------------------------
565 565 ahbi_m_ext <= ahbmi;
566 566 all_ahbm : FOR I IN 0 TO NB_AHB_MASTER-1 GENERATE
567 567 max_16_ahbm : IF I + CFG_NCPU + CFG_AHB_UART < 16 GENERATE
568 568 ahbmo(I + CFG_NCPU) <= ahbo_m_ext(I+CFG_NCPU);
569 569 END GENERATE max_16_ahbm;
570 570 END GENERATE all_ahbm;
571 571
572 572
573 573
574 574 END Behavioral;
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