@@ -310,11 +310,11 BEGIN -- beh | |||||
310 | pindex => 6, |
|
310 | pindex => 6, | |
311 | paddr => 6, |
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311 | paddr => 6, | |
312 | pmask => 16#fff#, |
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312 | pmask => 16#fff#, | |
313 | pirq => 12, |
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313 | FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374 | |
314 | nb_wait_pediod => 375) -- (49.152/2) /2^16 = 375 |
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314 | NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set | |
315 | PORT MAP ( |
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315 | PORT MAP ( | |
316 | clk25MHz => clk_25, |
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316 | clk25MHz => clk_25, | |
317 |
clk |
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317 | clk24_576MHz => clk_24, -- 49.152MHz/2 | |
318 | resetn => reset, |
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318 | resetn => reset, | |
319 | grspw_tick => swno.tickout, |
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319 | grspw_tick => swno.tickout, | |
320 | apbi => apbi_ext, |
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320 | apbi => apbi_ext, | |
@@ -425,7 +425,7 BEGIN -- beh | |||||
425 | pirq_ms => 6, |
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425 | pirq_ms => 6, | |
426 | pirq_wfp => 14, |
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426 | pirq_wfp => 14, | |
427 | hindex => 2, |
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427 | hindex => 2, | |
428 |
top_lfr_version => X"00010 |
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428 | top_lfr_version => X"000106") -- aa.bb.cc version | |
429 | PORT MAP ( |
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429 | PORT MAP ( | |
430 | clk => clk_25, |
|
430 | clk => clk_25, | |
431 | rstn => reset, |
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431 | rstn => reset, | |
@@ -577,4 +577,4 BEGIN -- beh | |||||
577 | END IF; |
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577 | END IF; | |
578 | END PROCESS; |
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578 | END PROCESS; | |
579 |
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579 | |||
580 |
END beh; |
|
580 | END beh; No newline at end of file |
@@ -142,7 +142,7 vcom_lpp: | |||||
142 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_positive_detection.vhd |
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142 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_positive_detection.vhd | |
143 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/SYNC_VALID_BIT.vhd |
|
143 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/SYNC_VALID_BIT.vhd | |
144 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/RR_Arbiter_4.vhd |
|
144 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/RR_Arbiter_4.vhd | |
145 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/counter.vhd |
|
145 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/general_counter.vhd | |
146 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lfr_time_management/lpp_lfr_time_management.vhd |
|
146 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lfr_time_management/lpp_lfr_time_management.vhd | |
147 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lfr_time_management/apb_lfr_time_management.vhd |
|
147 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lfr_time_management/apb_lfr_time_management.vhd | |
148 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lfr_time_management/lfr_time_management.vhd |
|
148 | $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lfr_time_management/lfr_time_management.vhd |
@@ -3,7 +3,7 USE IEEE.STD_LOGIC_1164.ALL; | |||||
3 | USE IEEE.std_logic_arith.ALL; |
|
3 | USE IEEE.std_logic_arith.ALL; | |
4 | USE IEEE.std_logic_unsigned.ALL; |
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4 | USE IEEE.std_logic_unsigned.ALL; | |
5 |
|
5 | |||
6 | ENTITY counter IS |
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6 | ENTITY general_counter IS | |
7 |
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7 | |||
8 | GENERIC ( |
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8 | GENERIC ( | |
9 | CYCLIC : STD_LOGIC := '1'; |
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9 | CYCLIC : STD_LOGIC := '1'; | |
@@ -23,9 +23,9 ENTITY counter IS | |||||
23 | counter : OUT STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0) |
|
23 | counter : OUT STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0) | |
24 | ); |
|
24 | ); | |
25 |
|
25 | |||
26 | END counter; |
|
26 | END general_counter; | |
27 |
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27 | |||
28 | ARCHITECTURE beh OF counter IS |
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28 | ARCHITECTURE beh OF general_counter IS | |
29 | SIGNAL counter_s : STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0); |
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29 | SIGNAL counter_s : STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0); | |
30 |
|
30 | |||
31 | BEGIN -- beh |
|
31 | BEGIN -- beh |
@@ -33,7 +33,7 USE IEEE.NUMERIC_STD.ALL; | |||||
33 |
|
33 | |||
34 | PACKAGE general_purpose IS |
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34 | PACKAGE general_purpose IS | |
35 |
|
35 | |||
36 | COMPONENT counter |
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36 | COMPONENT general_counter | |
37 | GENERIC ( |
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37 | GENERIC ( | |
38 | CYCLIC : STD_LOGIC; |
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38 | CYCLIC : STD_LOGIC; | |
39 | NB_BITS_COUNTER : INTEGER); |
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39 | NB_BITS_COUNTER : INTEGER); |
@@ -22,4 +22,4 lpp_front_detection.vhd | |||||
22 | lpp_front_positive_detection.vhd |
|
22 | lpp_front_positive_detection.vhd | |
23 | SYNC_VALID_BIT.vhd |
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23 | SYNC_VALID_BIT.vhd | |
24 | RR_Arbiter_4.vhd |
|
24 | RR_Arbiter_4.vhd | |
25 | counter.vhd |
|
25 | general_counter.vhd |
@@ -38,7 +38,7 ARCHITECTURE beh OF coarse_time_counter | |||||
38 | --CONSTANT NB_SECOND_DESYNC : INTEGER := 4; -- TODO : 60 |
|
38 | --CONSTANT NB_SECOND_DESYNC : INTEGER := 4; -- TODO : 60 | |
39 | BEGIN -- beh |
|
39 | BEGIN -- beh | |
40 |
|
40 | |||
41 | counter_1 : counter |
|
41 | counter_1 : general_counter | |
42 | GENERIC MAP ( |
|
42 | GENERIC MAP ( | |
43 | CYCLIC => '1', |
|
43 | CYCLIC => '1', | |
44 | NB_BITS_COUNTER => 31) |
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44 | NB_BITS_COUNTER => 31) | |
@@ -55,7 +55,7 BEGIN -- beh | |||||
55 |
|
55 | |||
56 | add1_bit31 <= '1' WHEN fsm_desync = '1' AND FT_max = '1' ELSE '0'; |
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56 | add1_bit31 <= '1' WHEN fsm_desync = '1' AND FT_max = '1' ELSE '0'; | |
57 |
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57 | |||
58 | counter_2 : counter |
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58 | counter_2 : general_counter | |
59 | GENERIC MAP ( |
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59 | GENERIC MAP ( | |
60 | CYCLIC => '0', |
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60 | CYCLIC => '0', | |
61 | NB_BITS_COUNTER => 6) |
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61 | NB_BITS_COUNTER => 6) |
@@ -40,7 +40,7 BEGIN -- beh | |||||
40 |
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40 | |||
41 |
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41 | |||
42 |
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42 | |||
43 | counter_1 : counter |
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43 | counter_1 : general_counter | |
44 | GENERIC MAP ( |
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44 | GENERIC MAP ( | |
45 | CYCLIC => '1', |
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45 | CYCLIC => '1', | |
46 | NB_BITS_COUNTER => 9) |
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46 | NB_BITS_COUNTER => 9) | |
@@ -56,7 +56,7 BEGIN -- beh | |||||
56 |
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56 | |||
57 | new_ft <= '1' WHEN new_ft_counter = STD_LOGIC_VECTOR(to_unsigned(FIRST_DIVISION, 9)) ELSE '0'; |
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57 | new_ft <= '1' WHEN new_ft_counter = STD_LOGIC_VECTOR(to_unsigned(FIRST_DIVISION, 9)) ELSE '0'; | |
58 |
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58 | |||
59 | counter_2 : counter |
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59 | counter_2 : general_counter | |
60 | GENERIC MAP ( |
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60 | GENERIC MAP ( | |
61 | CYCLIC => '1', |
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61 | CYCLIC => '1', | |
62 | NB_BITS_COUNTER => 16) |
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62 | NB_BITS_COUNTER => 16) |
@@ -115,8 +115,7 ARCHITECTURE Behavioral OF lpp_lfr_ms_fs | |||||
115 | WRITE_FINE_TIME, |
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115 | WRITE_FINE_TIME, | |
116 | TRASH_FIFO, |
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116 | TRASH_FIFO, | |
117 | SEND_DATA, |
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117 | SEND_DATA, | |
118 |
WAIT_DATA_ACK |
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118 | WAIT_DATA_ACK | |
119 | CHECK_LENGTH |
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|||
120 | ); |
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119 | ); | |
121 | SIGNAL state : state_DMAWriteBurst; -- := IDLE; |
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120 | SIGNAL state : state_DMAWriteBurst; -- := IDLE; | |
122 |
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121 | |||
@@ -150,6 +149,9 ARCHITECTURE Behavioral OF lpp_lfr_ms_fs | |||||
150 | SIGNAL debug_reg_s : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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149 | SIGNAL debug_reg_s : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
151 | SIGNAL fine_time_reg : STD_LOGIC_VECTOR(15 DOWNTO 0); |
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150 | SIGNAL fine_time_reg : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
152 |
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151 | |||
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152 | ----------------------------------------------------------------------------- | |||
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153 | SIGNAL log_empty_fifo : STD_LOGIC; | |||
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154 | ||||
153 | BEGIN |
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155 | BEGIN | |
154 |
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156 | |||
155 | debug_reg <= debug_reg_s; |
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157 | debug_reg <= debug_reg_s; | |
@@ -199,6 +201,8 BEGIN | |||||
199 |
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201 | |||
200 | debug_reg_s(31 DOWNTO 0) <= (OTHERS => '0'); |
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202 | debug_reg_s(31 DOWNTO 0) <= (OTHERS => '0'); | |
201 |
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203 | |||
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204 | log_empty_fifo <= '0'; | |||
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205 | ||||
202 | ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge |
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206 | ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge | |
203 | debug_reg_s(31 DOWNTO 10) <= (OTHERS => '0'); |
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207 | debug_reg_s(31 DOWNTO 10) <= (OTHERS => '0'); | |
204 |
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208 | |||
@@ -227,6 +231,7 BEGIN | |||||
227 | component_type_pre <= component_type; |
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231 | component_type_pre <= component_type; | |
228 | state <= CHECK_COMPONENT_TYPE; |
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232 | state <= CHECK_COMPONENT_TYPE; | |
229 | END IF; |
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233 | END IF; | |
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234 | log_empty_fifo <= '0'; | |||
230 |
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235 | |||
231 | WHEN CHECK_COMPONENT_TYPE => |
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236 | WHEN CHECK_COMPONENT_TYPE => | |
232 | debug_reg_s(2 DOWNTO 0) <= "001"; |
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237 | debug_reg_s(2 DOWNTO 0) <= "001"; | |
@@ -330,7 +335,7 BEGIN | |||||
330 | header_ack <= '0'; |
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335 | header_ack <= '0'; | |
331 | debug_reg_s(2 DOWNTO 0) <= "101"; |
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336 | debug_reg_s(2 DOWNTO 0) <= "101"; | |
332 |
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337 | |||
333 | IF fifo_empty = '1' THEN |
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338 | IF fifo_empty = '1' OR log_empty_fifo = '1' THEN | |
334 | state <= IDLE; |
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339 | state <= IDLE; | |
335 | IF component_type = "1110" THEN --"1110" -- JC |
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340 | IF component_type = "1110" THEN --"1110" -- JC | |
336 | CASE matrix_type IS |
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341 | CASE matrix_type IS | |
@@ -349,6 +354,8 BEGIN | |||||
349 | END IF; |
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354 | END IF; | |
350 |
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355 | |||
351 | WHEN WAIT_DATA_ACK => |
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356 | WHEN WAIT_DATA_ACK => | |
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357 | log_empty_fifo <= fifo_empty OR log_empty_fifo; | |||
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358 | ||||
352 |
|
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359 | debug_reg_s(2 DOWNTO 0) <= "110"; | |
353 |
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360 | |||
354 | component_send <= '0'; |
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361 | component_send <= '0'; | |
@@ -360,10 +367,11 BEGIN | |||||
360 |
state |
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367 | state <= TRASH_FIFO; | |
361 | END IF; |
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368 | END IF; | |
362 |
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369 | |||
363 | WHEN CHECK_LENGTH => |
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370 | ||
364 | component_send <= '0'; |
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371 | --WHEN CHECK_LENGTH => | |
365 | debug_reg_s(2 DOWNTO 0) <= "111"; |
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372 | -- component_send <= '0'; | |
366 | state <= IDLE; |
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373 | -- debug_reg_s(2 DOWNTO 0) <= "111"; | |
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374 | -- state <= IDLE; | |||
367 |
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375 | |||
368 | WHEN OTHERS => NULL; |
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376 | WHEN OTHERS => NULL; | |
369 | END CASE; |
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377 | END CASE; |
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