diff --git a/designs/MINI-LFR_WFP_MS/MINI_LFR_top.vhd b/designs/MINI-LFR_WFP_MS/MINI_LFR_top.vhd --- a/designs/MINI-LFR_WFP_MS/MINI_LFR_top.vhd +++ b/designs/MINI-LFR_WFP_MS/MINI_LFR_top.vhd @@ -310,11 +310,11 @@ BEGIN -- beh pindex => 6, paddr => 6, pmask => 16#fff#, - pirq => 12, - nb_wait_pediod => 375) -- (49.152/2) /2^16 = 375 + FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374 + NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set PORT MAP ( clk25MHz => clk_25, - clk49_152MHz => clk_24, -- 49.152MHz/2 + clk24_576MHz => clk_24, -- 49.152MHz/2 resetn => reset, grspw_tick => swno.tickout, apbi => apbi_ext, @@ -425,7 +425,7 @@ BEGIN -- beh pirq_ms => 6, pirq_wfp => 14, hindex => 2, - top_lfr_version => X"000105") -- aa.bb.cc version + top_lfr_version => X"000106") -- aa.bb.cc version PORT MAP ( clk => clk_25, rstn => reset, @@ -577,4 +577,4 @@ BEGIN -- beh END IF; END PROCESS; -END beh; +END beh; \ No newline at end of file diff --git a/designs/Validation_LFR_TIME_MANAGEMENT/Makefile b/designs/Validation_LFR_TIME_MANAGEMENT/Makefile --- a/designs/Validation_LFR_TIME_MANAGEMENT/Makefile +++ b/designs/Validation_LFR_TIME_MANAGEMENT/Makefile @@ -142,7 +142,7 @@ vcom_lpp: $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_positive_detection.vhd $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/SYNC_VALID_BIT.vhd $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/RR_Arbiter_4.vhd - $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/counter.vhd + $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/general_counter.vhd $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lfr_time_management/lpp_lfr_time_management.vhd $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lfr_time_management/apb_lfr_time_management.vhd $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lfr_time_management/lfr_time_management.vhd diff --git a/lib/lpp/general_purpose/counter.vhd b/lib/lpp/general_purpose/general_counter.vhd rename from lib/lpp/general_purpose/counter.vhd rename to lib/lpp/general_purpose/general_counter.vhd --- a/lib/lpp/general_purpose/counter.vhd +++ b/lib/lpp/general_purpose/general_counter.vhd @@ -3,7 +3,7 @@ USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.std_logic_arith.ALL; USE IEEE.std_logic_unsigned.ALL; -ENTITY counter IS +ENTITY general_counter IS GENERIC ( CYCLIC : STD_LOGIC := '1'; @@ -23,9 +23,9 @@ ENTITY counter IS counter : OUT STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0) ); -END counter; +END general_counter; -ARCHITECTURE beh OF counter IS +ARCHITECTURE beh OF general_counter IS SIGNAL counter_s : STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0); BEGIN -- beh diff --git a/lib/lpp/general_purpose/general_purpose.vhd b/lib/lpp/general_purpose/general_purpose.vhd --- a/lib/lpp/general_purpose/general_purpose.vhd +++ b/lib/lpp/general_purpose/general_purpose.vhd @@ -33,7 +33,7 @@ USE IEEE.NUMERIC_STD.ALL; PACKAGE general_purpose IS - COMPONENT counter + COMPONENT general_counter GENERIC ( CYCLIC : STD_LOGIC; NB_BITS_COUNTER : INTEGER); diff --git a/lib/lpp/general_purpose/vhdlsyn.txt b/lib/lpp/general_purpose/vhdlsyn.txt --- a/lib/lpp/general_purpose/vhdlsyn.txt +++ b/lib/lpp/general_purpose/vhdlsyn.txt @@ -22,4 +22,4 @@ lpp_front_detection.vhd lpp_front_positive_detection.vhd SYNC_VALID_BIT.vhd RR_Arbiter_4.vhd -counter.vhd +general_counter.vhd diff --git a/lib/lpp/lfr_time_management/coarse_time_counter.vhd b/lib/lpp/lfr_time_management/coarse_time_counter.vhd --- a/lib/lpp/lfr_time_management/coarse_time_counter.vhd +++ b/lib/lpp/lfr_time_management/coarse_time_counter.vhd @@ -38,7 +38,7 @@ ARCHITECTURE beh OF coarse_time_counter --CONSTANT NB_SECOND_DESYNC : INTEGER := 4; -- TODO : 60 BEGIN -- beh - counter_1 : counter + counter_1 : general_counter GENERIC MAP ( CYCLIC => '1', NB_BITS_COUNTER => 31) @@ -55,7 +55,7 @@ BEGIN -- beh add1_bit31 <= '1' WHEN fsm_desync = '1' AND FT_max = '1' ELSE '0'; - counter_2 : counter + counter_2 : general_counter GENERIC MAP ( CYCLIC => '0', NB_BITS_COUNTER => 6) diff --git a/lib/lpp/lfr_time_management/fine_time_counter.vhd b/lib/lpp/lfr_time_management/fine_time_counter.vhd --- a/lib/lpp/lfr_time_management/fine_time_counter.vhd +++ b/lib/lpp/lfr_time_management/fine_time_counter.vhd @@ -40,7 +40,7 @@ BEGIN -- beh - counter_1 : counter + counter_1 : general_counter GENERIC MAP ( CYCLIC => '1', NB_BITS_COUNTER => 9) @@ -56,7 +56,7 @@ BEGIN -- beh new_ft <= '1' WHEN new_ft_counter = STD_LOGIC_VECTOR(to_unsigned(FIRST_DIVISION, 9)) ELSE '0'; - counter_2 : counter + counter_2 : general_counter GENERIC MAP ( CYCLIC => '1', NB_BITS_COUNTER => 16) diff --git a/lib/lpp/lpp_top_lfr/lpp_lfr_ms_fsmdma.vhd b/lib/lpp/lpp_top_lfr/lpp_lfr_ms_fsmdma.vhd --- a/lib/lpp/lpp_top_lfr/lpp_lfr_ms_fsmdma.vhd +++ b/lib/lpp/lpp_top_lfr/lpp_lfr_ms_fsmdma.vhd @@ -115,8 +115,7 @@ ARCHITECTURE Behavioral OF lpp_lfr_ms_fs WRITE_FINE_TIME, TRASH_FIFO, SEND_DATA, - WAIT_DATA_ACK, - CHECK_LENGTH + WAIT_DATA_ACK ); SIGNAL state : state_DMAWriteBurst; -- := IDLE; @@ -149,6 +148,9 @@ ARCHITECTURE Behavioral OF lpp_lfr_ms_fs ----------------------------------------------------------------------------- SIGNAL debug_reg_s : STD_LOGIC_VECTOR(31 DOWNTO 0); SIGNAL fine_time_reg : STD_LOGIC_VECTOR(15 DOWNTO 0); + + ----------------------------------------------------------------------------- + SIGNAL log_empty_fifo : STD_LOGIC; BEGIN @@ -199,6 +201,8 @@ BEGIN debug_reg_s(31 DOWNTO 0) <= (OTHERS => '0'); + log_empty_fifo <= '0'; + ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge debug_reg_s(31 DOWNTO 10) <= (OTHERS => '0'); @@ -227,6 +231,7 @@ BEGIN component_type_pre <= component_type; state <= CHECK_COMPONENT_TYPE; END IF; + log_empty_fifo <= '0'; WHEN CHECK_COMPONENT_TYPE => debug_reg_s(2 DOWNTO 0) <= "001"; @@ -330,7 +335,7 @@ BEGIN header_ack <= '0'; debug_reg_s(2 DOWNTO 0) <= "101"; - IF fifo_empty = '1' THEN + IF fifo_empty = '1' OR log_empty_fifo = '1' THEN state <= IDLE; IF component_type = "1110" THEN --"1110" -- JC CASE matrix_type IS @@ -349,6 +354,8 @@ BEGIN END IF; WHEN WAIT_DATA_ACK => + log_empty_fifo <= fifo_empty OR log_empty_fifo; + debug_reg_s(2 DOWNTO 0) <= "110"; component_send <= '0'; @@ -357,13 +364,14 @@ BEGIN state <= SEND_DATA; ELSIF component_send_ko = '1' THEN error_anticipating_empty_fifo <= '0'; - state <= TRASH_FIFO; + state <= TRASH_FIFO; END IF; - WHEN CHECK_LENGTH => - component_send <= '0'; - debug_reg_s(2 DOWNTO 0) <= "111"; - state <= IDLE; + + --WHEN CHECK_LENGTH => + -- component_send <= '0'; + -- debug_reg_s(2 DOWNTO 0) <= "111"; + -- state <= IDLE; WHEN OTHERS => NULL; END CASE;