HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib Commit - r330:420e00cb22ab

MINI LFR - WFP&MS - 0.1.6...

pellion -

r330:420e00cb22ab (MINI-LFR) WFP_MS-0-1-6 JC

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r330:420e00cb22ab

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designs/MINI-LFR_WFP_MS/MINI_LFR_top.vhd +5 -5

                   pindex => 6,
                   paddr  => 6,
                   pmask  => 16#fff#,
-                  pirq   => 12,
+                  FIRST_DIVISION   => 374, -- ((49.152/2) /2^16) - 1  = 375 - 1 = 374
-                  nb_wait_pediod => 375)            -- (49.152/2) /2^16 = 375
+                  NB_SECOND_DESYNC => 60)  -- 60 secondes of desynchronization before CoarseTime's MSB is Set
                 PORT MAP (
                   clk25MHz     => clk_25,
-                  clk49_152MHz => clk_24,           -- 49.152MHz/2
+                  clk24_576MHz => clk_24,           -- 49.152MHz/2
                   resetn       => reset,
                   grspw_tick   => swno.tickout,
                   apbi         => apbi_ext,
                   pirq_ms                => 6,
                   pirq_wfp               => 14,
                   hindex                 => 2,
-                  top_lfr_version        => X"000105")  -- aa.bb.cc version
+                  top_lfr_version        => X"000106")  -- aa.bb.cc version
                 PORT MAP (
                   clk             => clk_25,
                   rstn            => reset,
                 END IF;
               END PROCESS;
-            END beh;
+            END beh;
  No newline at end of file

designs/Validation_LFR_TIME_MANAGEMENT/Makefile +1 -1

             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_positive_detection.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/SYNC_VALID_BIT.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/RR_Arbiter_4.vhd
-            	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/counter.vhd
+            	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/general_counter.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lfr_time_management/lpp_lfr_time_management.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lfr_time_management/apb_lfr_time_management.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lfr_time_management/lfr_time_management.vhd

lib/lpp/general_purpose/general_counter.vhd ~~lib/lpp/general_purpose/counter.vhd~~ renamed +3 -3

             USE IEEE.std_logic_arith.ALL;
             USE IEEE.std_logic_unsigned.ALL;
-            ENTITY counter IS
+            ENTITY general_counter IS
               GENERIC (
                 CYCLIC          : STD_LOGIC := '1';
                 counter   : OUT STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0)
                 );
-            END counter;
+            END general_counter;
-            ARCHITECTURE beh OF counter IS
+            ARCHITECTURE beh OF general_counter IS
               SIGNAL counter_s : STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0);
             BEGIN  -- beh

lib/lpp/general_purpose/general_purpose.vhd +1 -1

             PACKAGE general_purpose IS
-              COMPONENT counter
+              COMPONENT general_counter
                 GENERIC (
                   CYCLIC          : STD_LOGIC;
                   NB_BITS_COUNTER : INTEGER);

lib/lpp/general_purpose/vhdlsyn.txt +1 -1

             lpp_front_positive_detection.vhd
             SYNC_VALID_BIT.vhd
             RR_Arbiter_4.vhd
-            counter.vhd
+            general_counter.vhd

lib/lpp/lfr_time_management/coarse_time_counter.vhd +2 -2

               --CONSTANT NB_SECOND_DESYNC : INTEGER := 4; -- TODO : 60
             BEGIN  -- beh
-              counter_1 : counter
+              counter_1 : general_counter
                 GENERIC MAP (
                   CYCLIC => '1',
                   NB_BITS_COUNTER => 31)
               add1_bit31 <= '1' WHEN fsm_desync = '1' AND FT_max = '1' ELSE '0';
-              counter_2 : counter
+              counter_2 : general_counter
                 GENERIC MAP (
                   CYCLIC          => '0',
                   NB_BITS_COUNTER => 6)

lib/lpp/lfr_time_management/fine_time_counter.vhd +2 -2

-              counter_1 : counter
+              counter_1 : general_counter
                 GENERIC MAP (
                   CYCLIC          => '1',
                   NB_BITS_COUNTER => 9)
               new_ft <= '1' WHEN new_ft_counter = STD_LOGIC_VECTOR(to_unsigned(FIRST_DIVISION, 9)) ELSE '0';
-              counter_2 : counter
+              counter_2 : general_counter
                 GENERIC MAP (
                   CYCLIC          => '1',
                   NB_BITS_COUNTER => 16)

lib/lpp/lpp_top_lfr/lpp_lfr_ms_fsmdma.vhd +16 -8

                                            WRITE_FINE_TIME,
                                            TRASH_FIFO,
                                            SEND_DATA,
-                                           WAIT_DATA_ACK,
+                                           WAIT_DATA_ACK
-                                           CHECK_LENGTH
                                            );
               SIGNAL state : state_DMAWriteBurst;   -- := IDLE;
               -----------------------------------------------------------------------------
               SIGNAL debug_reg_s   : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL fine_time_reg : STD_LOGIC_VECTOR(15 DOWNTO 0);
+              -----------------------------------------------------------------------------
+              SIGNAL log_empty_fifo : STD_LOGIC;
             BEGIN
                   debug_reg_s(31 DOWNTO 0) <= (OTHERS => '0');
+                  log_empty_fifo <= '0';
                 ELSIF HCLK'EVENT AND HCLK = '1' THEN  -- rising clock edge
                   debug_reg_s(31 DOWNTO 10) <= (OTHERS => '0');
                         component_type_pre <= component_type;
                         state              <= CHECK_COMPONENT_TYPE;
                       END IF;
+                      log_empty_fifo <= '0';
                     WHEN CHECK_COMPONENT_TYPE =>
                       debug_reg_s(2 DOWNTO 0) <= "001";
                       header_ack <= '0';
                       debug_reg_s(2 DOWNTO 0) <= "101";
-                      IF fifo_empty = '1' THEN
+                      IF fifo_empty = '1' OR log_empty_fifo = '1' THEN
                         state <= IDLE;
                         IF component_type = "1110" THEN  --"1110" -- JC
                           CASE matrix_type IS
                       END IF;
                     WHEN WAIT_DATA_ACK =>
+                      log_empty_fifo <= fifo_empty OR log_empty_fifo;
                       debug_reg_s(2 DOWNTO 0) <= "110";
                       component_send <= '0';
                         state   <= SEND_DATA;
                       ELSIF component_send_ko = '1' THEN
                         error_anticipating_empty_fifo <= '0';
-                        state                         <= TRASH_FIFO;
+                        state   <= TRASH_FIFO;
                       END IF;
-                    WHEN CHECK_LENGTH =>
-                      component_send <= '0';
+                    --WHEN CHECK_LENGTH =>
-                      debug_reg_s(2 DOWNTO 0) <= "111";
+                    --  component_send <= '0';
-                      state <= IDLE;
+                    --  debug_reg_s(2 DOWNTO 0) <= "111";
+                    --  state <= IDLE;
                     WHEN OTHERS => NULL;
                   END CASE;

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