HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib Commit - r24:4029ae6c7747

optimisation code CNA

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r24:4029ae6c7747

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lib/lpp/lpp_cna/Gene_SYNC.vhd created 644 +53 0

			@@ -0,0 +1,53
		1	-- Gene_SYNC.vhd
		2	library IEEE;
		3	use IEEE.std_logic_1164.all;
		4	use IEEE.numeric_std.all;
		5
		6	entity Gene_SYNC is
		7
		8	port(
		9	SCLK,raz : in std_logic;
		10	enable : in std_logic;
		11	-- Sysclk : in std_logic;
		12	OKAI_send : out std_logic;
		13	SYNC : out std_logic
		14	);
		15
		16	end Gene_SYNC;
		17
		18
		19	architecture ar_Gene_SYNC of Gene_SYNC is
		20
		21	--signal Sysclk_reg : std_logic;
		22	signal count : integer;
		23
		24
		25	begin
		26	process (SCLK,raz)
		27	begin
		28	if(raz='0')then
		29	SYNC <= '0';
		30	-- Sysclk_reg <= '0';
		31	count <= 14;
		32	OKAI_send <= '0';
		33
		34	elsif(SCLK' event and SCLK='1')then
		35	if(enable='1')then
		36
		37	-- Sysclk_reg <= Sysclk;
		38	if(count=15)then
		39	SYNC <= '1';
		40	count <= count+1;
		41	elsif(count=16)then
		42	count <= 0;
		43	SYNC <= '0';
		44	OKAI_send <= '1';
		45	else
		46	count <= count+1;
		47	OKAI_send <= '0';
		48	end if;
		49	end if;
		50	end if;
		51	end process;
		52
		53	end ar_Gene_SYNC; No newline at end of file

lib/lpp/lpp_cna/APB_CNA.vhd +9 -14

 => ahb_device_reg (VENDOR_LPP, LPP_CNA, 0, REVISION, 0),
 => apb_iobar(paddr, pmask));
-             signal flag_nw   : std_logic;
-             signal bp        : std_logic;
-             signal Rz        : std_logic;
-             signal flag_sd   : std_logic;
+             signal enable   : std_logic;
+             signal flag_sd : std_logic;
              type CNA_ctrlr_Reg is record
-                  CNA_Cfg  : std_logic_vector(3 downto 0);
+                  CNA_Cfg  : std_logic_vector(1 downto 0);
                   CNA_Data : std_logic_vector(15 downto 0);
              end record;
              begin
-             bp <= Rec.CNA_Cfg(0);
-             flag_nw <= Rec.CNA_Cfg(1);
-             Rec.CNA_Cfg(2) <= flag_sd;
-             Rec.CNA_Cfg(3) <= Rz;
+             enable <= Rec.CNA_Cfg(0);
+             Rec.CNA_Cfg(1) <= flag_sd;
                  CONVERTER : entity Work.CNA_TabloC
-                     port map(clk,rst,flag_nw,bp,Rec.CNA_Data,SYNC,SCLK,Rz,flag_sd,Data);
+                     port map(clk,rst,enable,Rec.CNA_Data,SYNC,SCLK,flag_sd,Data);
                  process(rst,clk)
                          if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
                              case apbi.paddr(abits-1 downto 2) is
                                  when "000000" =>
-                                     Rec.CNA_Cfg(1 downto 0) <= apbi.pwdata(1 downto 0);
+                                     Rec.CNA_Cfg(0) <= apbi.pwdata(0);
                                  when "000001" =>
                                      Rec.CNA_Data <= apbi.pwdata(15 downto 0);
                                  when others =>
                          if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
                              case apbi.paddr(abits-1 downto 2) is
                                  when "000000" =>
-                                     Rdata(31 downto 4) <= X"ABCDEF5";
-                                     Rdata(3 downto 0) <= Rec.CNA_Cfg;
+                                     Rdata(31 downto 2) <= X"ABCDEF5" & "00";
+                                     Rdata(1 downto 0) <= Rec.CNA_Cfg;
                                  when "000001" =>
                                      Rdata(31 downto 16) <= X"FD18";
                                      Rdata(15 downto 0) <= Rec.CNA_Data;

lib/lpp/lpp_cna/CNA_TabloC.vhd +14 -18

                  port(
                      clock       : in std_logic;
                      rst         : in std_logic;
-                     flag_nw     : in std_logic;
-                     bp          : in std_logic;
+                     enable      : in std_logic;
+                     --bp          : in std_logic;
                      Data_C      : in std_logic_vector(15 downto 0);
                      SYNC        : out std_logic;
                      SCLK        : out std_logic;
-                     Rz          : out std_logic;
+                     --Rz          : out std_logic;
                      flag_sd     : out std_logic;
                      Data        : out std_logic
                      );
              end component;
              signal clk      : std_logic;
-             --signal reset    : std_logic;
              signal raz          : std_logic;
-             signal sys_clk      : std_logic;
-             signal Data_int     : std_logic_vector(15 downto 0);
+             signal s_SCLK      : std_logic;
              signal OKAI_send    : std_logic;
+             --signal Data_int     : std_logic_vector(15 downto 0);
              begin
              SystemCLK : entity work.Clock_Serie
                  generic map (nb_serial)
-                 port map (clk,raz,sys_clk);
+                 port map (clk,raz,s_SCLK);
-             Signal_sync : entity work.GeneSYNC_flag
-                 port map (clk,raz,flag_nw,sys_clk,OKAI_send,SYNC);
+             Signal_sync : entity work.Gene_SYNC
+                 port map (s_SCLK,raz,enable,OKAI_send,SYNC);
              Serial : entity work.serialize
-                 port map (clk,raz,sys_clk,Data_int,OKAI_send,flag_sd,Data);
+                 port map (clk,raz,s_SCLK,Data_C,OKAI_send,flag_sd,Data);
-             --raz         <= not reset;
-             Rz          <= raz;
-             SCLK        <= not sys_clk;
-             --Data_Cvec   <= std_logic_vector(to_unsigned(Data_C,12));
-             --Data_TOT    <= "0001" & Data_Cvec;
+             --Rz          <= raz;
+             SCLK        <= s_SCLK;
-             with bp select
-                 Data_int <= X"9555" when '1',
-                             Data_C when others;
+             --with bp select
+             --    Data_int <= X"9555" when '1',
+             --                Data_C when others;
              end ar_CNA_TabloC;
  No newline at end of file

lib/lpp/lpp_cna/Convertisseur_config.vhd +2 -2

              --===========================================================|
              --============= Fr�quence de s�rialisation ==================|
              --===========================================================|
-             constant Freq_serial : integer := 1_000_000;
-             constant nb_serial : integer := 40_000_000 / Freq_serial;
+             constant Freq_serial : integer := 5_000_000;
+             constant nb_serial : integer := 30_000_000 / Freq_serial;
              end;
  No newline at end of file

lib/lpp/lpp_cna/Serialize.vhd +1 -1

                      elsif(load='1')then
                          vector_int <= vectin & '0';
                          N <= 0;
-                     elsif(sclk'event and sclk='0')then
+                     elsif(sclk'event and sclk='1')then
                          if (CPT_ended='0') then
                              vector_int <= vector_int(15 downto 0) & '0';
                              N <= N+1;

lib/lpp/lpp_cna/lpp_cna.vhd +2 -2

              end component;
-             component GeneSYNC_flag is
+             component Gene_SYNC is
                  port(
                      clk,raz     : in std_logic;
-                     flag_nw     : in std_logic;
+                     send     : in std_logic;
                      Sysclk      : in std_logic;
                      OKAI_send   : out std_logic;
                      SYNC        : out std_logic);

lib/lpp/lpp_cna/GeneSYNC_flag.vhd removed 0 -94

NO CONTENT: file was removed

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