@@ -0,0 +1,53 | |||||
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1 | -- Gene_SYNC.vhd | |||
|
2 | library IEEE; | |||
|
3 | use IEEE.std_logic_1164.all; | |||
|
4 | use IEEE.numeric_std.all; | |||
|
5 | ||||
|
6 | entity Gene_SYNC is | |||
|
7 | ||||
|
8 | port( | |||
|
9 | SCLK,raz : in std_logic; | |||
|
10 | enable : in std_logic; | |||
|
11 | -- Sysclk : in std_logic; | |||
|
12 | OKAI_send : out std_logic; | |||
|
13 | SYNC : out std_logic | |||
|
14 | ); | |||
|
15 | ||||
|
16 | end Gene_SYNC; | |||
|
17 | ||||
|
18 | ||||
|
19 | architecture ar_Gene_SYNC of Gene_SYNC is | |||
|
20 | ||||
|
21 | --signal Sysclk_reg : std_logic; | |||
|
22 | signal count : integer; | |||
|
23 | ||||
|
24 | ||||
|
25 | begin | |||
|
26 | process (SCLK,raz) | |||
|
27 | begin | |||
|
28 | if(raz='0')then | |||
|
29 | SYNC <= '0'; | |||
|
30 | -- Sysclk_reg <= '0'; | |||
|
31 | count <= 14; | |||
|
32 | OKAI_send <= '0'; | |||
|
33 | ||||
|
34 | elsif(SCLK' event and SCLK='1')then | |||
|
35 | if(enable='1')then | |||
|
36 | ||||
|
37 | -- Sysclk_reg <= Sysclk; | |||
|
38 | if(count=15)then | |||
|
39 | SYNC <= '1'; | |||
|
40 | count <= count+1; | |||
|
41 | elsif(count=16)then | |||
|
42 | count <= 0; | |||
|
43 | SYNC <= '0'; | |||
|
44 | OKAI_send <= '1'; | |||
|
45 | else | |||
|
46 | count <= count+1; | |||
|
47 | OKAI_send <= '0'; | |||
|
48 | end if; | |||
|
49 | end if; | |||
|
50 | end if; | |||
|
51 | end process; | |||
|
52 | ||||
|
53 | end ar_Gene_SYNC; No newline at end of file |
@@ -1,105 +1,100 | |||||
1 | -- APB_CNA.vhd |
|
1 | -- APB_CNA.vhd | |
2 |
|
2 | |||
3 | library ieee; |
|
3 | library ieee; | |
4 | use ieee.std_logic_1164.all; |
|
4 | use ieee.std_logic_1164.all; | |
5 | library grlib; |
|
5 | library grlib; | |
6 | use grlib.amba.all; |
|
6 | use grlib.amba.all; | |
7 | use grlib.stdlib.all; |
|
7 | use grlib.stdlib.all; | |
8 | use grlib.devices.all; |
|
8 | use grlib.devices.all; | |
9 | library lpp; |
|
9 | library lpp; | |
10 | use lpp.lpp_amba.all; |
|
10 | use lpp.lpp_amba.all; | |
11 | use lpp.lpp_cna.all; |
|
11 | use lpp.lpp_cna.all; | |
12 |
|
12 | |||
13 |
|
13 | |||
14 | entity APB_CNA is |
|
14 | entity APB_CNA is | |
15 | generic ( |
|
15 | generic ( | |
16 | pindex : integer := 0; |
|
16 | pindex : integer := 0; | |
17 | paddr : integer := 0; |
|
17 | paddr : integer := 0; | |
18 | pmask : integer := 16#fff#; |
|
18 | pmask : integer := 16#fff#; | |
19 | pirq : integer := 0; |
|
19 | pirq : integer := 0; | |
20 | abits : integer := 8); |
|
20 | abits : integer := 8); | |
21 | port ( |
|
21 | port ( | |
22 | clk : in std_logic; |
|
22 | clk : in std_logic; | |
23 | rst : in std_logic; |
|
23 | rst : in std_logic; | |
24 | apbi : in apb_slv_in_type; |
|
24 | apbi : in apb_slv_in_type; | |
25 | apbo : out apb_slv_out_type; |
|
25 | apbo : out apb_slv_out_type; | |
26 | SYNC : out std_logic; |
|
26 | SYNC : out std_logic; | |
27 | SCLK : out std_logic; |
|
27 | SCLK : out std_logic; | |
28 | DATA : out std_logic |
|
28 | DATA : out std_logic | |
29 | ); |
|
29 | ); | |
30 | end APB_CNA; |
|
30 | end APB_CNA; | |
31 |
|
31 | |||
32 |
|
32 | |||
33 | architecture ar_APB_CNA of APB_CNA is |
|
33 | architecture ar_APB_CNA of APB_CNA is | |
34 |
|
34 | |||
35 | constant REVISION : integer := 1; |
|
35 | constant REVISION : integer := 1; | |
36 |
|
36 | |||
37 | constant pconfig : apb_config_type := ( |
|
37 | constant pconfig : apb_config_type := ( | |
38 | 0 => ahb_device_reg (VENDOR_LPP, LPP_CNA, 0, REVISION, 0), |
|
38 | 0 => ahb_device_reg (VENDOR_LPP, LPP_CNA, 0, REVISION, 0), | |
39 | 1 => apb_iobar(paddr, pmask)); |
|
39 | 1 => apb_iobar(paddr, pmask)); | |
40 |
|
40 | |||
41 |
signal |
|
41 | signal enable : std_logic; | |
42 | signal bp : std_logic; |
|
|||
43 | signal Rz : std_logic; |
|
|||
44 |
signal flag_sd |
|
42 | signal flag_sd : std_logic; | |
45 |
|
43 | |||
46 | type CNA_ctrlr_Reg is record |
|
44 | type CNA_ctrlr_Reg is record | |
47 |
CNA_Cfg : std_logic_vector( |
|
45 | CNA_Cfg : std_logic_vector(1 downto 0); | |
48 | CNA_Data : std_logic_vector(15 downto 0); |
|
46 | CNA_Data : std_logic_vector(15 downto 0); | |
49 | end record; |
|
47 | end record; | |
50 |
|
48 | |||
51 | signal Rec : CNA_ctrlr_Reg; |
|
49 | signal Rec : CNA_ctrlr_Reg; | |
52 | signal Rdata : std_logic_vector(31 downto 0); |
|
50 | signal Rdata : std_logic_vector(31 downto 0); | |
53 |
|
51 | |||
54 | begin |
|
52 | begin | |
55 |
|
53 | |||
56 |
|
|
54 | enable <= Rec.CNA_Cfg(0); | |
57 | flag_nw <= Rec.CNA_Cfg(1); |
|
55 | Rec.CNA_Cfg(1) <= flag_sd; | |
58 | Rec.CNA_Cfg(2) <= flag_sd; |
|
|||
59 | Rec.CNA_Cfg(3) <= Rz; |
|
|||
60 |
|
||||
61 |
|
56 | |||
62 | CONVERTER : entity Work.CNA_TabloC |
|
57 | CONVERTER : entity Work.CNA_TabloC | |
63 |
port map(clk,rst, |
|
58 | port map(clk,rst,enable,Rec.CNA_Data,SYNC,SCLK,flag_sd,Data); | |
64 |
|
59 | |||
65 |
|
60 | |||
66 | process(rst,clk) |
|
61 | process(rst,clk) | |
67 | begin |
|
62 | begin | |
68 | if(rst='0')then |
|
63 | if(rst='0')then | |
69 | Rec.CNA_Data <= (others => '0'); |
|
64 | Rec.CNA_Data <= (others => '0'); | |
70 |
|
65 | |||
71 | elsif(clk'event and clk='1')then |
|
66 | elsif(clk'event and clk='1')then | |
72 |
|
67 | |||
73 |
|
68 | |||
74 | --APB Write OP |
|
69 | --APB Write OP | |
75 | if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then |
|
70 | if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then | |
76 | case apbi.paddr(abits-1 downto 2) is |
|
71 | case apbi.paddr(abits-1 downto 2) is | |
77 | when "000000" => |
|
72 | when "000000" => | |
78 |
Rec.CNA_Cfg( |
|
73 | Rec.CNA_Cfg(0) <= apbi.pwdata(0); | |
79 | when "000001" => |
|
74 | when "000001" => | |
80 | Rec.CNA_Data <= apbi.pwdata(15 downto 0); |
|
75 | Rec.CNA_Data <= apbi.pwdata(15 downto 0); | |
81 | when others => |
|
76 | when others => | |
82 | null; |
|
77 | null; | |
83 | end case; |
|
78 | end case; | |
84 | end if; |
|
79 | end if; | |
85 |
|
80 | |||
86 | --APB READ OP |
|
81 | --APB READ OP | |
87 | if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then |
|
82 | if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then | |
88 | case apbi.paddr(abits-1 downto 2) is |
|
83 | case apbi.paddr(abits-1 downto 2) is | |
89 | when "000000" => |
|
84 | when "000000" => | |
90 |
Rdata(31 downto |
|
85 | Rdata(31 downto 2) <= X"ABCDEF5" & "00"; | |
91 |
Rdata( |
|
86 | Rdata(1 downto 0) <= Rec.CNA_Cfg; | |
92 | when "000001" => |
|
87 | when "000001" => | |
93 | Rdata(31 downto 16) <= X"FD18"; |
|
88 | Rdata(31 downto 16) <= X"FD18"; | |
94 | Rdata(15 downto 0) <= Rec.CNA_Data; |
|
89 | Rdata(15 downto 0) <= Rec.CNA_Data; | |
95 | when others => |
|
90 | when others => | |
96 | Rdata <= (others => '0'); |
|
91 | Rdata <= (others => '0'); | |
97 | end case; |
|
92 | end case; | |
98 | end if; |
|
93 | end if; | |
99 |
|
94 | |||
100 | end if; |
|
95 | end if; | |
101 | apbo.pconfig <= pconfig; |
|
96 | apbo.pconfig <= pconfig; | |
102 | end process; |
|
97 | end process; | |
103 |
|
98 | |||
104 | apbo.prdata <= Rdata when apbi.penable = '1'; |
|
99 | apbo.prdata <= Rdata when apbi.penable = '1'; | |
105 | end ar_APB_CNA; No newline at end of file |
|
100 | end ar_APB_CNA; |
@@ -1,71 +1,67 | |||||
1 | -- CNA_TabloC.vhd |
|
1 | -- CNA_TabloC.vhd | |
2 | library IEEE; |
|
2 | library IEEE; | |
3 | use IEEE.std_logic_1164.all; |
|
3 | use IEEE.std_logic_1164.all; | |
4 | use IEEE.numeric_std.all; |
|
4 | use IEEE.numeric_std.all; | |
5 | use work.Convertisseur_config.all; |
|
5 | use work.Convertisseur_config.all; | |
6 |
|
6 | |||
7 | entity CNA_TabloC is |
|
7 | entity CNA_TabloC is | |
8 | port( |
|
8 | port( | |
9 | clock : in std_logic; |
|
9 | clock : in std_logic; | |
10 | rst : in std_logic; |
|
10 | rst : in std_logic; | |
11 |
|
|
11 | enable : in std_logic; | |
12 | bp : in std_logic; |
|
12 | --bp : in std_logic; | |
13 | Data_C : in std_logic_vector(15 downto 0); |
|
13 | Data_C : in std_logic_vector(15 downto 0); | |
14 | SYNC : out std_logic; |
|
14 | SYNC : out std_logic; | |
15 | SCLK : out std_logic; |
|
15 | SCLK : out std_logic; | |
16 | Rz : out std_logic; |
|
16 | --Rz : out std_logic; | |
17 | flag_sd : out std_logic; |
|
17 | flag_sd : out std_logic; | |
18 | Data : out std_logic |
|
18 | Data : out std_logic | |
19 | ); |
|
19 | ); | |
20 | end CNA_TabloC; |
|
20 | end CNA_TabloC; | |
21 |
|
21 | |||
22 |
|
22 | |||
23 | architecture ar_CNA_TabloC of CNA_TabloC is |
|
23 | architecture ar_CNA_TabloC of CNA_TabloC is | |
24 |
|
24 | |||
25 | component CLKINT |
|
25 | component CLKINT | |
26 | port( A : in std_logic := 'U'; |
|
26 | port( A : in std_logic := 'U'; | |
27 | Y : out std_logic); |
|
27 | Y : out std_logic); | |
28 | end component; |
|
28 | end component; | |
29 |
|
29 | |||
30 | signal clk : std_logic; |
|
30 | signal clk : std_logic; | |
31 | --signal reset : std_logic; |
|
|||
32 |
|
31 | |||
33 | signal raz : std_logic; |
|
32 | signal raz : std_logic; | |
34 |
signal s |
|
33 | signal s_SCLK : std_logic; | |
35 | signal Data_int : std_logic_vector(15 downto 0); |
|
|||
36 | signal OKAI_send : std_logic; |
|
34 | signal OKAI_send : std_logic; | |
|
35 | --signal Data_int : std_logic_vector(15 downto 0); | |||
37 |
|
36 | |||
38 | begin |
|
37 | begin | |
39 |
|
38 | |||
40 |
|
39 | |||
41 | CLKINT_0 : CLKINT |
|
40 | CLKINT_0 : CLKINT | |
42 | port map(A => clock, Y => clk); |
|
41 | port map(A => clock, Y => clk); | |
43 |
|
42 | |||
44 | CLKINT_1 : CLKINT |
|
43 | CLKINT_1 : CLKINT | |
45 | port map(A => rst, Y => raz); |
|
44 | port map(A => rst, Y => raz); | |
46 |
|
45 | |||
47 |
|
46 | |||
48 | SystemCLK : entity work.Clock_Serie |
|
47 | SystemCLK : entity work.Clock_Serie | |
49 | generic map (nb_serial) |
|
48 | generic map (nb_serial) | |
50 |
port map (clk,raz,s |
|
49 | port map (clk,raz,s_SCLK); | |
51 |
|
50 | |||
52 |
|
51 | |||
53 |
Signal_sync : entity work.GeneSYNC |
|
52 | Signal_sync : entity work.Gene_SYNC | |
54 |
port map ( |
|
53 | port map (s_SCLK,raz,enable,OKAI_send,SYNC); | |
55 |
|
54 | |||
56 |
|
55 | |||
57 | Serial : entity work.serialize |
|
56 | Serial : entity work.serialize | |
58 |
port map (clk,raz,s |
|
57 | port map (clk,raz,s_SCLK,Data_C,OKAI_send,flag_sd,Data); | |
59 |
|
58 | |||
60 |
|
59 | |||
61 |
-- |
|
60 | --Rz <= raz; | |
62 | Rz <= raz; |
|
61 | SCLK <= s_SCLK; | |
63 | SCLK <= not sys_clk; |
|
|||
64 | --Data_Cvec <= std_logic_vector(to_unsigned(Data_C,12)); |
|
|||
65 | --Data_TOT <= "0001" & Data_Cvec; |
|
|||
66 |
|
62 | |||
67 | with bp select |
|
63 | --with bp select | |
68 | Data_int <= X"9555" when '1', |
|
64 | -- Data_int <= X"9555" when '1', | |
69 | Data_C when others; |
|
65 | -- Data_C when others; | |
70 |
|
66 | |||
71 | end ar_CNA_TabloC; No newline at end of file |
|
67 | end ar_CNA_TabloC; |
@@ -1,24 +1,24 | |||||
1 | -- Convertisseur_config.vhd |
|
1 | -- Convertisseur_config.vhd | |
2 | library IEEE; |
|
2 | library IEEE; | |
3 | use IEEE.std_logic_1164.all; |
|
3 | use IEEE.std_logic_1164.all; | |
4 | use IEEE.numeric_std.all; |
|
4 | use IEEE.numeric_std.all; | |
5 |
|
5 | |||
6 | Package Convertisseur_config is |
|
6 | Package Convertisseur_config is | |
7 |
|
7 | |||
8 |
|
8 | |||
9 | --===========================================================| |
|
9 | --===========================================================| | |
10 | --================= Valeurs Sinus 1Khz ======================| |
|
10 | --================= Valeurs Sinus 1Khz ======================| | |
11 | --===========================================================| |
|
11 | --===========================================================| | |
12 | type Tbl is array(natural range <>) of std_logic_vector(11 downto 0); |
|
12 | type Tbl is array(natural range <>) of std_logic_vector(11 downto 0); | |
13 | constant Tablo : Tbl (0 to 49):= (X"800",X"901",X"9FD",X"AF2",X"BDB",X"CB4",X"D7A",X"E2A",X"EC1",X"F3D",X"F9C",X"FDC",X"FFC",X"FFC",X"FDC",X"F9C",X"F3D",X"EC1",X"E2A",X"D7A",X"CB4",X"BDB",X"AF2",X"9FD",X"901",X"800",X"6FF",X"603",X"50E",X"425",X"34C",X"286",X"1D6",X"13F",X"0C3",X"064",X"024",X"004",X"004",X"024",X"064",X"0C3",X"13F",X"1D6",X"286",X"34C",X"425",X"50E",X"603",X"6FF"); |
|
13 | constant Tablo : Tbl (0 to 49):= (X"800",X"901",X"9FD",X"AF2",X"BDB",X"CB4",X"D7A",X"E2A",X"EC1",X"F3D",X"F9C",X"FDC",X"FFC",X"FFC",X"FDC",X"F9C",X"F3D",X"EC1",X"E2A",X"D7A",X"CB4",X"BDB",X"AF2",X"9FD",X"901",X"800",X"6FF",X"603",X"50E",X"425",X"34C",X"286",X"1D6",X"13F",X"0C3",X"064",X"024",X"004",X"004",X"024",X"064",X"0C3",X"13F",X"1D6",X"286",X"34C",X"425",X"50E",X"603",X"6FF"); | |
14 |
|
14 | |||
15 | --constant Tablo : Tbl (0 to 49):= (X"C00",X"C80",X"CFF",X"D79",X"DED",X"E5A",X"EBD",X"F15",X"F61",X"F9F",X"FCE",X"FEE",X"FFE",X"FFE",X"FEE",X"FCE",X"F9F",X"F61",X"F15",X"EBD",X"E5A",X"DED",X"D79",X"CFF",X"C80",X"C00",X"B80",X"B01",X"A87",X"A13",X"9A6",X"943",X"8EB",X"89F",X"861",X"832",X"812",X"802",X"802",X"812",X"832",X"861",X"89F",X"8EB",X"943",X"9A6",X"A13",X"A87",X"B01",X"B80"); |
|
15 | --constant Tablo : Tbl (0 to 49):= (X"C00",X"C80",X"CFF",X"D79",X"DED",X"E5A",X"EBD",X"F15",X"F61",X"F9F",X"FCE",X"FEE",X"FFE",X"FFE",X"FEE",X"FCE",X"F9F",X"F61",X"F15",X"EBD",X"E5A",X"DED",X"D79",X"CFF",X"C80",X"C00",X"B80",X"B01",X"A87",X"A13",X"9A6",X"943",X"8EB",X"89F",X"861",X"832",X"812",X"802",X"802",X"812",X"832",X"861",X"89F",X"8EB",X"943",X"9A6",X"A13",X"A87",X"B01",X"B80"); | |
16 |
|
16 | |||
17 |
|
17 | |||
18 | --===========================================================| |
|
18 | --===========================================================| | |
19 | --============= Fr�quence de s�rialisation ==================| |
|
19 | --============= Fr�quence de s�rialisation ==================| | |
20 | --===========================================================| |
|
20 | --===========================================================| | |
21 |
constant Freq_serial : integer := |
|
21 | constant Freq_serial : integer := 5_000_000; | |
22 |
constant nb_serial : integer := |
|
22 | constant nb_serial : integer := 30_000_000 / Freq_serial; | |
23 |
|
23 | |||
24 | end; No newline at end of file |
|
24 | end; |
@@ -1,86 +1,86 | |||||
1 | -- Serialize.vhd |
|
1 | -- Serialize.vhd | |
2 | library IEEE; |
|
2 | library IEEE; | |
3 | use IEEE.numeric_std.all; |
|
3 | use IEEE.numeric_std.all; | |
4 | use IEEE.std_logic_1164.all; |
|
4 | use IEEE.std_logic_1164.all; | |
5 |
|
5 | |||
6 | entity Serialize is |
|
6 | entity Serialize is | |
7 |
|
7 | |||
8 | port( |
|
8 | port( | |
9 | clk,raz : in std_logic; |
|
9 | clk,raz : in std_logic; | |
10 | sclk : in std_logic; |
|
10 | sclk : in std_logic; | |
11 | vectin : in std_logic_vector(15 downto 0); |
|
11 | vectin : in std_logic_vector(15 downto 0); | |
12 | send : in std_logic; |
|
12 | send : in std_logic; | |
13 | sended : out std_logic; |
|
13 | sended : out std_logic; | |
14 | Data : out std_logic); |
|
14 | Data : out std_logic); | |
15 |
|
15 | |||
16 | end Serialize; |
|
16 | end Serialize; | |
17 |
|
17 | |||
18 |
|
18 | |||
19 | architecture ar_Serialize of Serialize is |
|
19 | architecture ar_Serialize of Serialize is | |
20 |
|
20 | |||
21 | type etat is (attente,serialize); |
|
21 | type etat is (attente,serialize); | |
22 | signal ect : etat; |
|
22 | signal ect : etat; | |
23 |
|
23 | |||
24 | signal vector_int : std_logic_vector(16 downto 0); |
|
24 | signal vector_int : std_logic_vector(16 downto 0); | |
25 | signal vectin_reg : std_logic_vector(15 downto 0); |
|
25 | signal vectin_reg : std_logic_vector(15 downto 0); | |
26 | signal load : std_logic; |
|
26 | signal load : std_logic; | |
27 | signal N : integer range 0 to 16; |
|
27 | signal N : integer range 0 to 16; | |
28 | signal CPT_ended : std_logic:='0'; |
|
28 | signal CPT_ended : std_logic:='0'; | |
29 |
|
29 | |||
30 | begin |
|
30 | begin | |
31 | process(clk,raz) |
|
31 | process(clk,raz) | |
32 | begin |
|
32 | begin | |
33 | if(raz='0')then |
|
33 | if(raz='0')then | |
34 | ect <= attente; |
|
34 | ect <= attente; | |
35 | vectin_reg <= (others=> '0'); |
|
35 | vectin_reg <= (others=> '0'); | |
36 | load <= '0'; |
|
36 | load <= '0'; | |
37 | sended <= '1'; |
|
37 | sended <= '1'; | |
38 |
|
38 | |||
39 | elsif(clk'event and clk='1')then |
|
39 | elsif(clk'event and clk='1')then | |
40 | vectin_reg <= vectin; |
|
40 | vectin_reg <= vectin; | |
41 |
|
41 | |||
42 | case ect is |
|
42 | case ect is | |
43 | when attente => |
|
43 | when attente => | |
44 | if (send='1') then |
|
44 | if (send='1') then | |
45 | sended <= '0'; |
|
45 | sended <= '0'; | |
46 | load <= '1'; |
|
46 | load <= '1'; | |
47 | ect <= serialize; |
|
47 | ect <= serialize; | |
48 | else |
|
48 | else | |
49 | ect <= attente; |
|
49 | ect <= attente; | |
50 | end if; |
|
50 | end if; | |
51 |
|
51 | |||
52 | when serialize => |
|
52 | when serialize => | |
53 | load <= '0'; |
|
53 | load <= '0'; | |
54 | if(CPT_ended='1')then |
|
54 | if(CPT_ended='1')then | |
55 | ect <= attente; |
|
55 | ect <= attente; | |
56 | sended <= '1'; |
|
56 | sended <= '1'; | |
57 | end if; |
|
57 | end if; | |
58 |
|
58 | |||
59 | end case; |
|
59 | end case; | |
60 | end if; |
|
60 | end if; | |
61 | end process; |
|
61 | end process; | |
62 |
|
62 | |||
63 | process(sclk,load,raz) |
|
63 | process(sclk,load,raz) | |
64 | begin |
|
64 | begin | |
65 | if (raz='0')then |
|
65 | if (raz='0')then | |
66 | vector_int <= (others=> '0'); |
|
66 | vector_int <= (others=> '0'); | |
67 | N <= 16; |
|
67 | N <= 16; | |
68 | elsif(load='1')then |
|
68 | elsif(load='1')then | |
69 | vector_int <= vectin & '0'; |
|
69 | vector_int <= vectin & '0'; | |
70 | N <= 0; |
|
70 | N <= 0; | |
71 |
elsif(sclk'event and sclk=' |
|
71 | elsif(sclk'event and sclk='1')then | |
72 | if (CPT_ended='0') then |
|
72 | if (CPT_ended='0') then | |
73 | vector_int <= vector_int(15 downto 0) & '0'; |
|
73 | vector_int <= vector_int(15 downto 0) & '0'; | |
74 | N <= N+1; |
|
74 | N <= N+1; | |
75 | end if; |
|
75 | end if; | |
76 | end if; |
|
76 | end if; | |
77 | end process; |
|
77 | end process; | |
78 |
|
78 | |||
79 | CPT_ended <= '1' when N = 16 else '0'; |
|
79 | CPT_ended <= '1' when N = 16 else '0'; | |
80 |
|
80 | |||
81 | with ect select |
|
81 | with ect select | |
82 | Data <= vector_int(16) when serialize, |
|
82 | Data <= vector_int(16) when serialize, | |
83 | '0' when others; |
|
83 | '0' when others; | |
84 |
|
84 | |||
85 | end ar_Serialize; |
|
85 | end ar_Serialize; | |
86 |
|
86 |
@@ -1,77 +1,77 | |||||
1 | library ieee; |
|
1 | library ieee; | |
2 | use ieee.std_logic_1164.all; |
|
2 | use ieee.std_logic_1164.all; | |
3 | library grlib; |
|
3 | library grlib; | |
4 | use grlib.amba.all; |
|
4 | use grlib.amba.all; | |
5 | -- pragma translate_off |
|
5 | -- pragma translate_off | |
6 | use std.textio.all; |
|
6 | use std.textio.all; | |
7 | -- pragma translate_on |
|
7 | -- pragma translate_on | |
8 | library lpp; |
|
8 | library lpp; | |
9 | use lpp.lpp_amba.all; |
|
9 | use lpp.lpp_amba.all; | |
10 |
|
10 | |||
11 |
|
11 | |||
12 | package lpp_cna is |
|
12 | package lpp_cna is | |
13 |
|
13 | |||
14 | component APB_CNA is |
|
14 | component APB_CNA is | |
15 | generic ( |
|
15 | generic ( | |
16 | pindex : integer := 0; |
|
16 | pindex : integer := 0; | |
17 | paddr : integer := 0; |
|
17 | paddr : integer := 0; | |
18 | pmask : integer := 16#fff#; |
|
18 | pmask : integer := 16#fff#; | |
19 | pirq : integer := 0; |
|
19 | pirq : integer := 0; | |
20 | abits : integer := 8); |
|
20 | abits : integer := 8); | |
21 | port ( |
|
21 | port ( | |
22 | clk : in std_logic; |
|
22 | clk : in std_logic; | |
23 | rst : in std_logic; |
|
23 | rst : in std_logic; | |
24 | apbi : in apb_slv_in_type; |
|
24 | apbi : in apb_slv_in_type; | |
25 | apbo : out apb_slv_out_type; |
|
25 | apbo : out apb_slv_out_type; | |
26 | SYNC : out std_logic; |
|
26 | SYNC : out std_logic; | |
27 | SCLK : out std_logic; |
|
27 | SCLK : out std_logic; | |
28 | DATA : out std_logic |
|
28 | DATA : out std_logic | |
29 | ); |
|
29 | ); | |
30 | end component; |
|
30 | end component; | |
31 |
|
31 | |||
32 |
|
32 | |||
33 | component CNA_TabloC is |
|
33 | component CNA_TabloC is | |
34 | port( |
|
34 | port( | |
35 | clock : in std_logic; |
|
35 | clock : in std_logic; | |
36 | rst : in std_logic; |
|
36 | rst : in std_logic; | |
37 | flag_nw : in std_logic; |
|
37 | flag_nw : in std_logic; | |
38 | bp : in std_logic; |
|
38 | bp : in std_logic; | |
39 | Data_C : in std_logic_vector(15 downto 0); |
|
39 | Data_C : in std_logic_vector(15 downto 0); | |
40 | SYNC : out std_logic; |
|
40 | SYNC : out std_logic; | |
41 | SCLK : out std_logic; |
|
41 | SCLK : out std_logic; | |
42 | Rz : out std_logic; |
|
42 | Rz : out std_logic; | |
43 | flag_sd : out std_logic; |
|
43 | flag_sd : out std_logic; | |
44 | Data : out std_logic |
|
44 | Data : out std_logic | |
45 | ); |
|
45 | ); | |
46 | end component; |
|
46 | end component; | |
47 |
|
47 | |||
48 |
|
48 | |||
49 | component Clock_Serie is |
|
49 | component Clock_Serie is | |
50 | generic(N :integer := 695); |
|
50 | generic(N :integer := 695); | |
51 | port( |
|
51 | port( | |
52 | clk, raz : in std_logic ; |
|
52 | clk, raz : in std_logic ; | |
53 | clock : out std_logic); |
|
53 | clock : out std_logic); | |
54 | end component; |
|
54 | end component; | |
55 |
|
55 | |||
56 |
|
56 | |||
57 |
component GeneSYNC |
|
57 | component Gene_SYNC is | |
58 | port( |
|
58 | port( | |
59 | clk,raz : in std_logic; |
|
59 | clk,raz : in std_logic; | |
60 |
|
|
60 | send : in std_logic; | |
61 | Sysclk : in std_logic; |
|
61 | Sysclk : in std_logic; | |
62 | OKAI_send : out std_logic; |
|
62 | OKAI_send : out std_logic; | |
63 | SYNC : out std_logic); |
|
63 | SYNC : out std_logic); | |
64 | end component; |
|
64 | end component; | |
65 |
|
65 | |||
66 |
|
66 | |||
67 | component Serialize is |
|
67 | component Serialize is | |
68 | port( |
|
68 | port( | |
69 | clk,raz : in std_logic; |
|
69 | clk,raz : in std_logic; | |
70 | sclk : in std_logic; |
|
70 | sclk : in std_logic; | |
71 | vectin : in std_logic_vector(15 downto 0); |
|
71 | vectin : in std_logic_vector(15 downto 0); | |
72 | send : in std_logic; |
|
72 | send : in std_logic; | |
73 | sended : out std_logic; |
|
73 | sended : out std_logic; | |
74 | Data : out std_logic); |
|
74 | Data : out std_logic); | |
75 | end component; |
|
75 | end component; | |
76 |
|
76 | |||
77 | end; |
|
77 | end; |
1 | NO CONTENT: file was removed |
|
NO CONTENT: file was removed |
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