@@ -0,0 +1,53 | |||||
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1 | -- Gene_SYNC.vhd | |||
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2 | library IEEE; | |||
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3 | use IEEE.std_logic_1164.all; | |||
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4 | use IEEE.numeric_std.all; | |||
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5 | ||||
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6 | entity Gene_SYNC is | |||
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7 | ||||
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8 | port( | |||
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9 | SCLK,raz : in std_logic; | |||
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10 | enable : in std_logic; | |||
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11 | -- Sysclk : in std_logic; | |||
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12 | OKAI_send : out std_logic; | |||
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13 | SYNC : out std_logic | |||
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14 | ); | |||
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15 | ||||
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16 | end Gene_SYNC; | |||
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17 | ||||
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18 | ||||
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19 | architecture ar_Gene_SYNC of Gene_SYNC is | |||
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20 | ||||
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21 | --signal Sysclk_reg : std_logic; | |||
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22 | signal count : integer; | |||
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23 | ||||
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24 | ||||
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25 | begin | |||
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26 | process (SCLK,raz) | |||
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27 | begin | |||
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28 | if(raz='0')then | |||
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29 | SYNC <= '0'; | |||
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30 | -- Sysclk_reg <= '0'; | |||
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31 | count <= 14; | |||
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32 | OKAI_send <= '0'; | |||
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33 | ||||
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34 | elsif(SCLK' event and SCLK='1')then | |||
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35 | if(enable='1')then | |||
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36 | ||||
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37 | -- Sysclk_reg <= Sysclk; | |||
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38 | if(count=15)then | |||
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39 | SYNC <= '1'; | |||
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40 | count <= count+1; | |||
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41 | elsif(count=16)then | |||
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42 | count <= 0; | |||
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43 | SYNC <= '0'; | |||
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44 | OKAI_send <= '1'; | |||
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45 | else | |||
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46 | count <= count+1; | |||
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47 | OKAI_send <= '0'; | |||
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48 | end if; | |||
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49 | end if; | |||
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50 | end if; | |||
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51 | end process; | |||
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52 | ||||
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53 | end ar_Gene_SYNC; No newline at end of file |
@@ -38,13 +38,11 constant pconfig : apb_config_type := ( | |||||
38 | 0 => ahb_device_reg (VENDOR_LPP, LPP_CNA, 0, REVISION, 0), |
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38 | 0 => ahb_device_reg (VENDOR_LPP, LPP_CNA, 0, REVISION, 0), | |
39 | 1 => apb_iobar(paddr, pmask)); |
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39 | 1 => apb_iobar(paddr, pmask)); | |
40 |
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40 | |||
41 |
signal |
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41 | signal enable : std_logic; | |
42 |
signal |
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42 | signal flag_sd : std_logic; | |
43 | signal Rz : std_logic; |
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44 | signal flag_sd : std_logic; |
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45 |
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43 | |||
46 | type CNA_ctrlr_Reg is record |
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44 | type CNA_ctrlr_Reg is record | |
47 |
CNA_Cfg : std_logic_vector( |
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45 | CNA_Cfg : std_logic_vector(1 downto 0); | |
48 | CNA_Data : std_logic_vector(15 downto 0); |
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46 | CNA_Data : std_logic_vector(15 downto 0); | |
49 | end record; |
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47 | end record; | |
50 |
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48 | |||
@@ -53,14 +51,11 signal Rdata : std_logic_vector(31 d | |||||
53 |
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51 | |||
54 | begin |
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52 | begin | |
55 |
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53 | |||
56 |
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54 | enable <= Rec.CNA_Cfg(0); | |
57 | flag_nw <= Rec.CNA_Cfg(1); |
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55 | Rec.CNA_Cfg(1) <= flag_sd; | |
58 | Rec.CNA_Cfg(2) <= flag_sd; |
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59 | Rec.CNA_Cfg(3) <= Rz; |
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60 |
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56 | |||
61 |
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62 | CONVERTER : entity Work.CNA_TabloC |
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57 | CONVERTER : entity Work.CNA_TabloC | |
63 |
port map(clk,rst, |
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58 | port map(clk,rst,enable,Rec.CNA_Data,SYNC,SCLK,flag_sd,Data); | |
64 |
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59 | |||
65 |
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60 | |||
66 | process(rst,clk) |
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61 | process(rst,clk) | |
@@ -75,7 +70,7 Rec.CNA_Cfg(3) <= Rz; | |||||
75 | if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then |
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70 | if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then | |
76 | case apbi.paddr(abits-1 downto 2) is |
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71 | case apbi.paddr(abits-1 downto 2) is | |
77 | when "000000" => |
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72 | when "000000" => | |
78 |
Rec.CNA_Cfg( |
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73 | Rec.CNA_Cfg(0) <= apbi.pwdata(0); | |
79 | when "000001" => |
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74 | when "000001" => | |
80 | Rec.CNA_Data <= apbi.pwdata(15 downto 0); |
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75 | Rec.CNA_Data <= apbi.pwdata(15 downto 0); | |
81 | when others => |
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76 | when others => | |
@@ -87,8 +82,8 Rec.CNA_Cfg(3) <= Rz; | |||||
87 | if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then |
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82 | if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then | |
88 | case apbi.paddr(abits-1 downto 2) is |
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83 | case apbi.paddr(abits-1 downto 2) is | |
89 | when "000000" => |
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84 | when "000000" => | |
90 |
Rdata(31 downto |
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85 | Rdata(31 downto 2) <= X"ABCDEF5" & "00"; | |
91 |
Rdata( |
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86 | Rdata(1 downto 0) <= Rec.CNA_Cfg; | |
92 | when "000001" => |
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87 | when "000001" => | |
93 | Rdata(31 downto 16) <= X"FD18"; |
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88 | Rdata(31 downto 16) <= X"FD18"; | |
94 | Rdata(15 downto 0) <= Rec.CNA_Data; |
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89 | Rdata(15 downto 0) <= Rec.CNA_Data; |
@@ -8,12 +8,12 entity CNA_TabloC is | |||||
8 | port( |
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8 | port( | |
9 | clock : in std_logic; |
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9 | clock : in std_logic; | |
10 | rst : in std_logic; |
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10 | rst : in std_logic; | |
11 |
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11 | enable : in std_logic; | |
12 | bp : in std_logic; |
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12 | --bp : in std_logic; | |
13 | Data_C : in std_logic_vector(15 downto 0); |
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13 | Data_C : in std_logic_vector(15 downto 0); | |
14 | SYNC : out std_logic; |
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14 | SYNC : out std_logic; | |
15 | SCLK : out std_logic; |
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15 | SCLK : out std_logic; | |
16 | Rz : out std_logic; |
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16 | --Rz : out std_logic; | |
17 | flag_sd : out std_logic; |
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17 | flag_sd : out std_logic; | |
18 | Data : out std_logic |
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18 | Data : out std_logic | |
19 | ); |
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19 | ); | |
@@ -28,12 +28,11 port( A : in std_logic := 'U'; | |||||
28 | end component; |
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28 | end component; | |
29 |
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29 | |||
30 | signal clk : std_logic; |
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30 | signal clk : std_logic; | |
31 | --signal reset : std_logic; |
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32 |
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31 | |||
33 | signal raz : std_logic; |
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32 | signal raz : std_logic; | |
34 |
signal s |
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33 | signal s_SCLK : std_logic; | |
35 | signal Data_int : std_logic_vector(15 downto 0); |
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36 | signal OKAI_send : std_logic; |
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34 | signal OKAI_send : std_logic; | |
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35 | --signal Data_int : std_logic_vector(15 downto 0); | |||
37 |
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36 | |||
38 | begin |
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37 | begin | |
39 |
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38 | |||
@@ -47,25 +46,22 CLKINT_1 : CLKINT | |||||
47 |
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46 | |||
48 | SystemCLK : entity work.Clock_Serie |
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47 | SystemCLK : entity work.Clock_Serie | |
49 | generic map (nb_serial) |
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48 | generic map (nb_serial) | |
50 |
port map (clk,raz,s |
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49 | port map (clk,raz,s_SCLK); | |
51 |
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50 | |||
52 |
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51 | |||
53 |
Signal_sync : entity work.GeneSYNC |
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52 | Signal_sync : entity work.Gene_SYNC | |
54 |
port map ( |
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53 | port map (s_SCLK,raz,enable,OKAI_send,SYNC); | |
55 |
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54 | |||
56 |
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55 | |||
57 | Serial : entity work.serialize |
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56 | Serial : entity work.serialize | |
58 |
port map (clk,raz,s |
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57 | port map (clk,raz,s_SCLK,Data_C,OKAI_send,flag_sd,Data); | |
59 |
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58 | |||
60 |
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59 | |||
61 |
-- |
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60 | --Rz <= raz; | |
62 | Rz <= raz; |
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61 | SCLK <= s_SCLK; | |
63 | SCLK <= not sys_clk; |
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64 | --Data_Cvec <= std_logic_vector(to_unsigned(Data_C,12)); |
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65 | --Data_TOT <= "0001" & Data_Cvec; |
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66 |
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62 | |||
67 | with bp select |
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63 | --with bp select | |
68 | Data_int <= X"9555" when '1', |
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64 | -- Data_int <= X"9555" when '1', | |
69 | Data_C when others; |
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65 | -- Data_C when others; | |
70 |
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66 | |||
71 | end ar_CNA_TabloC; No newline at end of file |
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67 | end ar_CNA_TabloC; |
@@ -18,7 +18,7 constant Tablo : Tbl (0 to 49):= (X"800" | |||||
18 | --===========================================================| |
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18 | --===========================================================| | |
19 | --============= Fr�quence de s�rialisation ==================| |
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19 | --============= Fr�quence de s�rialisation ==================| | |
20 | --===========================================================| |
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20 | --===========================================================| | |
21 |
constant Freq_serial : integer := |
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21 | constant Freq_serial : integer := 5_000_000; | |
22 |
constant nb_serial : integer := |
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22 | constant nb_serial : integer := 30_000_000 / Freq_serial; | |
23 |
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23 | |||
24 | end; No newline at end of file |
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24 | end; |
@@ -68,7 +68,7 begin | |||||
68 | elsif(load='1')then |
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68 | elsif(load='1')then | |
69 | vector_int <= vectin & '0'; |
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69 | vector_int <= vectin & '0'; | |
70 | N <= 0; |
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70 | N <= 0; | |
71 |
elsif(sclk'event and sclk=' |
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71 | elsif(sclk'event and sclk='1')then | |
72 | if (CPT_ended='0') then |
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72 | if (CPT_ended='0') then | |
73 | vector_int <= vector_int(15 downto 0) & '0'; |
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73 | vector_int <= vector_int(15 downto 0) & '0'; | |
74 | N <= N+1; |
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74 | N <= N+1; |
@@ -54,10 +54,10 component Clock_Serie is | |||||
54 | end component; |
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54 | end component; | |
55 |
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55 | |||
56 |
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56 | |||
57 |
component GeneSYNC |
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57 | component Gene_SYNC is | |
58 | port( |
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58 | port( | |
59 | clk,raz : in std_logic; |
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59 | clk,raz : in std_logic; | |
60 |
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60 | send : in std_logic; | |
61 | Sysclk : in std_logic; |
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61 | Sysclk : in std_logic; | |
62 | OKAI_send : out std_logic; |
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62 | OKAI_send : out std_logic; | |
63 | SYNC : out std_logic); |
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63 | SYNC : out std_logic); |
1 | NO CONTENT: file was removed |
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NO CONTENT: file was removed |
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