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Simulation without RAM_CEL
pellion -
r582:3fed66e2161d simu_with_Leon3
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1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Jean-christophe Pellion
20 20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 21 -- jean-christophe.pellion@easii-ic.com
22 22 -------------------------------------------------------------------------------
23 23 -- 1.0 - initial version
24 24 -------------------------------------------------------------------------------
25 25 LIBRARY ieee;
26 26 USE ieee.std_logic_1164.ALL;
27 27 USE ieee.numeric_std.ALL;
28 28 LIBRARY grlib;
29 29 USE grlib.amba.ALL;
30 30 USE grlib.stdlib.ALL;
31 31 USE grlib.devices.ALL;
32 32
33 33 LIBRARY lpp;
34 34 USE lpp.lpp_amba.ALL;
35 35 USE lpp.apb_devices_list.ALL;
36 36 USE lpp.lpp_memory.ALL;
37 37 USE lpp.lpp_dma_pkg.ALL;
38 38 USE lpp.general_purpose.ALL;
39 39 --USE lpp.lpp_waveform_pkg.ALL;
40 40 LIBRARY techmap;
41 41 USE techmap.gencomp.ALL;
42 42
43 43
44 44 ENTITY lpp_dma_SEND16B_FIFO2DMA IS
45 45 GENERIC (
46 46 hindex : INTEGER := 2;
47 47 vendorid : IN INTEGER := 0;
48 48 deviceid : IN INTEGER := 0;
49 49 version : IN INTEGER := 0
50 50 );
51 51 PORT (
52 52 clk : IN STD_LOGIC;
53 53 rstn : IN STD_LOGIC;
54 54
55 55 -- AMBA AHB Master Interface
56 56 AHB_Master_In : IN AHB_Mst_In_Type;
57 57 AHB_Master_Out : OUT AHB_Mst_Out_Type;
58 58
59 59 -- FIFO Interface
60 60 ren : OUT STD_LOGIC;
61 61 data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
62 62
63 63 -- Controls
64 64 send : IN STD_LOGIC;
65 65 valid_burst : IN STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
66 66 done : OUT STD_LOGIC;
67 67 address : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
68 68 );
69 69 END;
70 70
71 71 ARCHITECTURE Behavioral OF lpp_dma_SEND16B_FIFO2DMA IS
72 72
73 73 CONSTANT HConfig : AHB_Config_Type := (
74 74 0 => ahb_device_reg(vendorid, deviceid, 0, version, 0),
75 75 OTHERS => (OTHERS => '0'));
76 76
77 77 TYPE AHB_DMA_FSM_STATE IS (IDLE, s_ARBITER ,s_CTRL, s_CTRL_DATA, s_DATA);
78 78 SIGNAL state : AHB_DMA_FSM_STATE;
79 79
80 80 SIGNAL address_counter_reg : STD_LOGIC_VECTOR(3 DOWNTO 0);
81 81 SIGNAL address_counter : STD_LOGIC_VECTOR(3 DOWNTO 0);
82 82
83 83 SIGNAL data_window : STD_LOGIC;
84 84 SIGNAL ctrl_window : STD_LOGIC;
85 85
86 86 SIGNAL bus_request : STD_LOGIC;
87 87 SIGNAL bus_lock : STD_LOGIC;
88
89 SIGNAL data_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
88 90
89 91 BEGIN
90 92
91 93 -----------------------------------------------------------------------------
92 94 AHB_Master_Out.HCONFIG <= HConfig;
93 95 AHB_Master_Out.HSIZE <= "010"; --WORDS 32b
94 96 AHB_Master_Out.HINDEX <= hindex;
95 97 AHB_Master_Out.HPROT <= "0011"; --DATA ACCESS and PRIVILEDGED ACCESS
96 98 AHB_Master_Out.HIRQ <= (OTHERS => '0');
97 99 AHB_Master_Out.HBURST <= "111"; -- INCR --"111"; --INCR16
98 100 AHB_Master_Out.HWRITE <= '1';
99 101
100 102 --AHB_Master_Out.HTRANS <= HTRANS_NONSEQ WHEN ctrl_window = '1' OR data_window = '1' ELSE HTRANS_IDLE;
101 103
102 104 --AHB_Master_Out.HBUSREQ <= bus_request;
103 105 --AHB_Master_Out.HLOCK <= data_window;
104 106
105 107 --bus_request <= '0' WHEN address_counter_reg = "1111" AND AHB_Master_In.HREADY = '1' ELSE
106 108 -- '1' WHEN ctrl_window = '1' ELSE
107 109 -- '0';
108 110
109 111 --bus_lock <= '0' WHEN address_counter_reg = "1111" ELSE
110 112 -- '1' WHEN ctrl_window = '1' ELSE '0';
111 113
112 114 -----------------------------------------------------------------------------
113 115 AHB_Master_Out.HADDR <= address(31 DOWNTO 6) & address_counter_reg & "00";
114 AHB_Master_Out.HWDATA <= ahbdrivedata(data);
115
116 AHB_Master_Out.HWDATA <= ahbdrivedata(data) WHEN AHB_Master_In.HREADY = '1' ELSE ahbdrivedata(data_reg);
117
116 118 -----------------------------------------------------------------------------
117 119 --ren <= NOT ((AHB_Master_In.HGRANT(hindex) OR LAST_READ ) AND AHB_Master_In.HREADY );
118 120 --ren <= NOT beat;
119 121 -----------------------------------------------------------------------------
120 122 PROCESS (clk, rstn)
121 123 BEGIN -- PROCESS
122 124 IF rstn = '0' THEN -- asynchronous reset (active low)
123 125 state <= IDLE;
124 126 done <= '0';
127 ren <= '1';
125 128 address_counter_reg <= (OTHERS => '0');
126 129 AHB_Master_Out.HTRANS <= HTRANS_IDLE;
127 130 AHB_Master_Out.HBUSREQ <= '0';
128 131 AHB_Master_Out.HLOCK <= '0';
132
133 data_reg <= (OTHERS => '0');
129 134 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
135
136 IF AHB_Master_In.HREADY = '1' AND AHB_Master_In.HGRANT(hindex) = '1' THEN
137 data_reg <= data;
138 END IF;
139
130 140 done <= '0';
141 ren <= '1';
131 142 CASE state IS
132 143 WHEN IDLE =>
133 144 AHB_Master_Out.HBUSREQ <= '0';
134 145 AHB_Master_Out.HLOCK <= '0';
135 146 AHB_Master_Out.HTRANS <= HTRANS_IDLE;
136 147 address_counter_reg <= (OTHERS => '0');
137 148 IF send = '1' THEN
138 149 AHB_Master_Out.HBUSREQ <= '1';
139 150 AHB_Master_Out.HLOCK <= '1';
140 151 AHB_Master_Out.HTRANS <= HTRANS_IDLE;
141 152 state <= s_ARBITER;
142 153 END IF;
143 154
144 155 WHEN s_ARBITER =>
145 156 AHB_Master_Out.HBUSREQ <= '1';
146 157 AHB_Master_Out.HLOCK <= '1';
147 158 AHB_Master_Out.HTRANS <= HTRANS_IDLE;
148 159 address_counter_reg <= (OTHERS => '0');
149 160
150 161 IF AHB_Master_In.HREADY = '1' AND AHB_Master_In.HGRANT(hindex) = '1' THEN
151 162 AHB_Master_Out.HTRANS <= HTRANS_IDLE;
152 163 state <= s_CTRL;
153 164 END IF;
154 165
155 166 WHEN s_CTRL =>
156 167 AHB_Master_Out.HBUSREQ <= '1';
157 168 AHB_Master_Out.HLOCK <= '1';
158 169 AHB_Master_Out.HTRANS <= HTRANS_NONSEQ;
159 170 IF AHB_Master_In.HREADY = '1' AND AHB_Master_In.HGRANT(hindex) = '1' THEN
160 171 AHB_Master_Out.HTRANS <= HTRANS_SEQ;
161 172 state <= s_CTRL_DATA;
173 ren <= '0';
162 174 END IF;
163 175
164 176 WHEN s_CTRL_DATA =>
165 177 AHB_Master_Out.HBUSREQ <= '1';
166 178 AHB_Master_Out.HLOCK <= '1';
167 179 AHB_Master_Out.HTRANS <= HTRANS_SEQ;
168 180 IF AHB_Master_In.HREADY = '1' AND AHB_Master_In.HGRANT(hindex) = '1' THEN
169 181 address_counter_reg <= STD_LOGIC_VECTOR(UNSIGNED(address_counter_reg) + 1);
170 182 END IF;
171 183
172 184 IF address_counter_reg = "1111" AND AHB_Master_In.HREADY = '1' THEN
173 185 AHB_Master_Out.HBUSREQ <= '0';
174 186 AHB_Master_Out.HLOCK <= '1';--'0';
175 187 AHB_Master_Out.HTRANS <= HTRANS_IDLE;
176 188 state <= s_DATA;
177 189 END IF;
178 190
191 IF AHB_Master_In.HREADY = '1' AND AHB_Master_In.HGRANT(hindex) = '1' AND address_counter_reg /= "1111" THEN
192 ren <= '0';
193 END IF;
194
195
179 196 WHEN s_DATA =>
180 197 AHB_Master_Out.HBUSREQ <= '0';
181 198 --AHB_Master_Out.HLOCK <= '0';
182 199 AHB_Master_Out.HTRANS <= HTRANS_IDLE;
183 200 IF AHB_Master_In.HREADY = '1' THEN
184 201 AHB_Master_Out.HLOCK <= '0';
185 202 state <= IDLE;
186 203 done <= '1';
187 204 END IF;
188 205
189 206 WHEN OTHERS => NULL;
190 207 END CASE;
191 208 END IF;
192 209 END PROCESS;
193 210
194 211 ctrl_window <= '1' WHEN state = s_CTRL OR state = s_CTRL_DATA ELSE '0';
195 212 data_window <= '1' WHEN state = s_CTRL_DATA OR state = s_DATA ELSE '0';
196 213 -----------------------------------------------------------------------------
197 ren <= NOT(AHB_Master_In.HREADY) WHEN state = s_CTRL_DATA ELSE '1';
214
215
216 --ren <= NOT(AHB_Master_In.HREADY) WHEN state = s_CTRL_DATA ELSE '1';
198 217
199 218 -----------------------------------------------------------------------------
200 219 --PROCESS (clk, rstn)
201 220 --BEGIN -- PROCESS
202 221 -- IF rstn = '0' THEN -- asynchronous reset (active low)
203 222 -- address_counter_reg <= (OTHERS => '0');
204 223 -- ELSIF clk'event AND clk = '1' THEN -- rising clock edge
205 224 -- address_counter_reg <= address_counter;
206 225 -- END IF;
207 226 --END PROCESS;
208 227
209 228 --address_counter <= STD_LOGIC_VECTOR(UNSIGNED(address_counter_reg) + 1) WHEN data_window = '1' AND AHB_Master_In.HREADY = '1' AND AHB_Master_In.HGRANT(hindex) = '1' ELSE
210 229 -- address_counter_reg;
211 230 -----------------------------------------------------------------------------
212 231
213 232
214 233 END Behavioral;
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@@ -1,572 +1,572
1 1 -----------------------------------------------------------------------------
2 2 -- LEON3 Demonstration design
3 3 -- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 2 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 ------------------------------------------------------------------------------
19 19
20 20
21 21 LIBRARY ieee;
22 22 USE ieee.std_logic_1164.ALL;
23 23 LIBRARY grlib;
24 24 USE grlib.amba.ALL;
25 25 USE grlib.stdlib.ALL;
26 26 LIBRARY techmap;
27 27 USE techmap.gencomp.ALL;
28 28 LIBRARY gaisler;
29 29 USE gaisler.memctrl.ALL;
30 30 USE gaisler.leon3.ALL;
31 31 USE gaisler.uart.ALL;
32 32 USE gaisler.misc.ALL;
33 33 USE gaisler.spacewire.ALL; -- PLE
34 34 LIBRARY esa;
35 35 USE esa.memoryctrl.ALL;
36 36 LIBRARY lpp;
37 37 USE lpp.lpp_memory.ALL;
38 38 USE lpp.lpp_ad_conv.ALL;
39 39 USE lpp.lpp_lfr_pkg.ALL;
40 40 USE lpp.iir_filter.ALL;
41 41 USE lpp.general_purpose.ALL;
42 42 USE lpp.lpp_leon3_soc_pkg.ALL;
43 43 LIBRARY iap;
44 44 USE iap.memctrl.ALL;
45 45
46 46
47 47 ENTITY leon3_soc IS
48 48 GENERIC (
49 49 fabtech : INTEGER := apa3e;
50 50 memtech : INTEGER := apa3e;
51 51 padtech : INTEGER := inferred;
52 52 clktech : INTEGER := inferred;
53 53 disas : INTEGER := 0; -- Enable disassembly to console
54 54 dbguart : INTEGER := 0; -- Print UART on console
55 55 pclow : INTEGER := 2;
56 56 --
57 57 clk_freq : INTEGER := 25000; --kHz
58 58 --
59 59 IS_RADHARD : INTEGER := 0;
60 60 --
61 61 NB_CPU : INTEGER := 1;
62 62 ENABLE_FPU : INTEGER := 1;
63 63 FPU_NETLIST : INTEGER := 1;
64 64 ENABLE_DSU : INTEGER := 1;
65 65 ENABLE_AHB_UART : INTEGER := 1;
66 66 ENABLE_APB_UART : INTEGER := 1;
67 67 ENABLE_IRQMP : INTEGER := 1;
68 68 ENABLE_GPT : INTEGER := 1;
69 69 --
70 70 NB_AHB_MASTER : INTEGER := 1;
71 71 NB_AHB_SLAVE : INTEGER := 1;
72 72 NB_APB_SLAVE : INTEGER := 1;
73 73 --
74 74 ADDRESS_SIZE : INTEGER := 20;
75 75 USES_IAP_MEMCTRLR : INTEGER := 0;
76 76 BYPASS_EDAC_MEMCTRLR : STD_LOGIC := '0';
77 77 SRBANKSZ : INTEGER := 8
78 78
79 79 );
80 80 PORT (
81 81 clk : IN STD_ULOGIC;
82 82 reset : IN STD_ULOGIC;
83 83
84 84 errorn : OUT STD_ULOGIC;
85 85
86 86 -- UART AHB ---------------------------------------------------------------
87 87 ahbrxd : IN STD_ULOGIC; -- DSU rx data
88 88 ahbtxd : OUT STD_ULOGIC; -- DSU tx data
89 89
90 90 -- UART APB ---------------------------------------------------------------
91 91 urxd1 : IN STD_ULOGIC; -- UART1 rx data
92 92 utxd1 : OUT STD_ULOGIC; -- UART1 tx data
93 93
94 94 -- RAM --------------------------------------------------------------------
95 95 address : OUT STD_LOGIC_VECTOR(ADDRESS_SIZE-1 DOWNTO 0);
96 96 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
97 97 nSRAM_BE0 : OUT STD_LOGIC;
98 98 nSRAM_BE1 : OUT STD_LOGIC;
99 99 nSRAM_BE2 : OUT STD_LOGIC;
100 100 nSRAM_BE3 : OUT STD_LOGIC;
101 101 nSRAM_WE : OUT STD_LOGIC;
102 102 nSRAM_CE : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
103 103 nSRAM_OE : OUT STD_LOGIC;
104 104 nSRAM_READY : IN STD_LOGIC;
105 105 SRAM_MBE : INOUT STD_LOGIC;
106 106 -- APB --------------------------------------------------------------------
107 107 apbi_ext : OUT apb_slv_in_type;
108 108 apbo_ext : IN soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5);
109 109 -- AHB_Slave --------------------------------------------------------------
110 110 ahbi_s_ext : OUT ahb_slv_in_type;
111 111 ahbo_s_ext : IN soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3);
112 112 -- AHB_Master -------------------------------------------------------------
113 113 ahbi_m_ext : OUT AHB_Mst_In_Type;
114 114 ahbo_m_ext : IN soc_ahb_mst_out_vector(NB_AHB_MASTER-1+NB_CPU DOWNTO NB_CPU)
115 115
116 116 );
117 117 END;
118 118
119 119 ARCHITECTURE Behavioral OF leon3_soc IS
120 120
121 121 -----------------------------------------------------------------------------
122 122 -- CONFIG -------------------------------------------------------------------
123 123 -----------------------------------------------------------------------------
124 124
125 125 -- Clock generator
126 126 CONSTANT CFG_CLKMUL : INTEGER := (1);
127 127 CONSTANT CFG_CLKDIV : INTEGER := (1); -- divide 50MHz by 2 to get 25MHz
128 128 CONSTANT CFG_OCLKDIV : INTEGER := (1);
129 129 CONSTANT CFG_CLK_NOFB : INTEGER := 0;
130 130 -- LEON3 processor core
131 131 CONSTANT CFG_LEON3 : INTEGER := 1;
132 132 CONSTANT CFG_NCPU : INTEGER := NB_CPU;
133 133 CONSTANT CFG_NWIN : INTEGER := (8); -- to be compatible with BCC and RCC
134 134 CONSTANT CFG_V8 : INTEGER := 0;
135 135 CONSTANT CFG_MAC : INTEGER := 0;
136 136 CONSTANT CFG_SVT : INTEGER := 0;
137 137 CONSTANT CFG_RSTADDR : INTEGER := 16#00000#;
138 138 CONSTANT CFG_LDDEL : INTEGER := (1);
139 139 CONSTANT CFG_NWP : INTEGER := (0);
140 140 CONSTANT CFG_PWD : INTEGER := 1*2;
141 141 CONSTANT CFG_FPU : INTEGER := ENABLE_FPU *(8 + 16 * FPU_NETLIST);
142 142 -- 1*(8 + 16 * 0) => grfpu-light
143 143 -- 1*(8 + 16 * 1) => netlist
144 144 -- 0*(8 + 16 * 0) => No FPU
145 145 -- 0*(8 + 16 * 1) => No FPU;
146 146 CONSTANT CFG_ICEN : INTEGER := 1;
147 147 CONSTANT CFG_ISETS : INTEGER := 1;
148 148 CONSTANT CFG_ISETSZ : INTEGER := 4;
149 149 CONSTANT CFG_ILINE : INTEGER := 4;
150 150 CONSTANT CFG_IREPL : INTEGER := 0;
151 151 CONSTANT CFG_ILOCK : INTEGER := 0;
152 152 CONSTANT CFG_ILRAMEN : INTEGER := 0;
153 153 CONSTANT CFG_ILRAMADDR : INTEGER := 16#8E#;
154 154 CONSTANT CFG_ILRAMSZ : INTEGER := 1;
155 155 CONSTANT CFG_DCEN : INTEGER := 1;
156 156 CONSTANT CFG_DSETS : INTEGER := 1;
157 157 CONSTANT CFG_DSETSZ : INTEGER := 4;
158 158 CONSTANT CFG_DLINE : INTEGER := 4;
159 159 CONSTANT CFG_DREPL : INTEGER := 0;
160 160 CONSTANT CFG_DLOCK : INTEGER := 0;
161 161 CONSTANT CFG_DSNOOP : INTEGER := 0 + 0 + 4*0;
162 162 CONSTANT CFG_DLRAMEN : INTEGER := 0;
163 163 CONSTANT CFG_DLRAMADDR : INTEGER := 16#8F#;
164 164 CONSTANT CFG_DLRAMSZ : INTEGER := 1;
165 165 CONSTANT CFG_MMUEN : INTEGER := 0;
166 166 CONSTANT CFG_ITLBNUM : INTEGER := 2;
167 167 CONSTANT CFG_DTLBNUM : INTEGER := 2;
168 168 CONSTANT CFG_TLB_TYPE : INTEGER := 1 + 0*2;
169 169 CONSTANT CFG_TLB_REP : INTEGER := 1;
170 170
171 171 CONSTANT CFG_DSU : INTEGER := ENABLE_DSU;
172 172 CONSTANT CFG_ITBSZ : INTEGER := 0;
173 173 CONSTANT CFG_ATBSZ : INTEGER := 0;
174 174
175 175 -- AMBA settings
176 176 CONSTANT CFG_DEFMST : INTEGER := (0);
177 177 CONSTANT CFG_RROBIN : INTEGER := 1;
178 178 CONSTANT CFG_SPLIT : INTEGER := 0;
179 179 CONSTANT CFG_AHBIO : INTEGER := 16#FFF#;
180 180 CONSTANT CFG_APBADDR : INTEGER := 16#800#;
181 181
182 182 -- DSU UART
183 183 CONSTANT CFG_AHB_UART : INTEGER := ENABLE_AHB_UART;
184 184
185 185 -- LEON2 memory controller
186 186 CONSTANT CFG_MCTRL_SDEN : INTEGER := 0;
187 187
188 188 -- UART 1
189 189 CONSTANT CFG_UART1_ENABLE : INTEGER := ENABLE_APB_UART;
190 190 CONSTANT CFG_UART1_FIFO : INTEGER := 1;
191 191
192 192 -- LEON3 interrupt controller
193 193 CONSTANT CFG_IRQ3_ENABLE : INTEGER := ENABLE_IRQMP;
194 194
195 195 -- Modular timer
196 196 CONSTANT CFG_GPT_ENABLE : INTEGER := ENABLE_GPT;
197 197 CONSTANT CFG_GPT_NTIM : INTEGER := (2);
198 198 CONSTANT CFG_GPT_SW : INTEGER := (8);
199 199 CONSTANT CFG_GPT_TW : INTEGER := (32);
200 200 CONSTANT CFG_GPT_IRQ : INTEGER := (8);
201 201 CONSTANT CFG_GPT_SEPIRQ : INTEGER := 1;
202 202 CONSTANT CFG_GPT_WDOGEN : INTEGER := 0;
203 203 CONSTANT CFG_GPT_WDOG : INTEGER := 16#0#;
204 204 -----------------------------------------------------------------------------
205 205
206 206 -----------------------------------------------------------------------------
207 207 -- SIGNALs
208 208 -----------------------------------------------------------------------------
209 209 CONSTANT maxahbmsp : INTEGER := CFG_NCPU + CFG_AHB_UART + NB_AHB_MASTER;
210 210 -- CLK & RST --
211 211 SIGNAL clk2x : STD_ULOGIC;
212 212 SIGNAL clkmn : STD_ULOGIC;
213 213 SIGNAL clkm : STD_ULOGIC;
214 214 SIGNAL rstn : STD_ULOGIC;
215 215 SIGNAL rstraw : STD_ULOGIC;
216 216 SIGNAL pciclk : STD_ULOGIC;
217 217 SIGNAL sdclkl : STD_ULOGIC;
218 218 SIGNAL cgi : clkgen_in_type;
219 219 SIGNAL cgo : clkgen_out_type;
220 220 --- AHB / APB
221 221 SIGNAL apbi : apb_slv_in_type;
222 222 SIGNAL apbo : apb_slv_out_vector := (OTHERS => apb_none);
223 223 SIGNAL ahbsi : ahb_slv_in_type;
224 224 SIGNAL ahbso : ahb_slv_out_vector := (OTHERS => ahbs_none);
225 225 SIGNAL ahbmi : ahb_mst_in_type;
226 226 SIGNAL ahbmo : ahb_mst_out_vector := (OTHERS => ahbm_none);
227 227 --UART
228 228 SIGNAL ahbuarti : uart_in_type;
229 229 SIGNAL ahbuarto : uart_out_type;
230 230 SIGNAL apbuarti : uart_in_type;
231 231 SIGNAL apbuarto : uart_out_type;
232 232 --MEM CTRLR
233 233 SIGNAL memi : memory_in_type;
234 234 SIGNAL memo : memory_out_type;
235 235 SIGNAL wpo : wprot_out_type;
236 236 SIGNAL sdo : sdram_out_type;
237 237 SIGNAL mbe : STD_LOGIC; -- enable memory programming
238 238 SIGNAL mbe_drive : STD_LOGIC; -- drive the MBE memory signal
239 239 SIGNAL nSRAM_CE_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
240 240 SIGNAL nSRAM_OE_s : STD_LOGIC;
241 241 --IRQ
242 242 SIGNAL irqi : irq_in_vector(0 TO CFG_NCPU-1);
243 243 SIGNAL irqo : irq_out_vector(0 TO CFG_NCPU-1);
244 244 --Timer
245 245 SIGNAL gpti : gptimer_in_type;
246 246 SIGNAL gpto : gptimer_out_type;
247 247 --DSU
248 248 SIGNAL dbgi : l3_debug_in_vector(0 TO CFG_NCPU-1);
249 249 SIGNAL dbgo : l3_debug_out_vector(0 TO CFG_NCPU-1);
250 250 SIGNAL dsui : dsu_in_type;
251 251 SIGNAL dsuo : dsu_out_type;
252 252 -----------------------------------------------------------------------------
253 253
254 254
255 255 BEGIN
256 256
257 257
258 258 ----------------------------------------------------------------------
259 259 --- Reset and Clock generation -------------------------------------
260 260 ----------------------------------------------------------------------
261 261
262 262 cgi.pllctrl <= "00";
263 263 cgi.pllrst <= rstraw;
264 264
265 265 rst0 : rstgen PORT MAP (reset, clkm, cgo.clklock, rstn, rstraw);
266 266
267 267 clkgen0 : clkgen -- clock generator
268 268 GENERIC MAP (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN,
269 269 CFG_CLK_NOFB, 0, 0, 0, clk_freq, 0, 0, CFG_OCLKDIV)
270 270 PORT MAP (clk, clk, clkm, clkmn, clk2x, sdclkl, pciclk, cgi, cgo);
271 271
272 272 ----------------------------------------------------------------------
273 273 --- LEON3 processor / DSU / IRQ ------------------------------------
274 274 ----------------------------------------------------------------------
275 275
276 276 l3 : IF CFG_LEON3 = 1 GENERATE
277 277 cpu : FOR i IN 0 TO CFG_NCPU-1 GENERATE
278 278 leon3_non_radhard : IF IS_RADHARD = 0 GENERATE
279 279 u0 : ENTITY gaisler.leon3s -- LEON3 processor
280 280 GENERIC MAP (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
281 281 0, CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
282 282 CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
283 283 CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
284 284 CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
285 285 CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1)
286 286 PORT MAP (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
287 287 irqi(i), irqo(i), dbgi(i), dbgo(i));
288 288 END GENERATE leon3_non_radhard;
289 289
290 290 leon3_radhard_i : IF IS_RADHARD = 1 GENERATE
291 291 cpu : ENTITY gaisler.leon3ft
292 292 GENERIC MAP (
293 293 HINDEX => i, --: integer; --CPU_HINDEX,
294 294 FABTECH => fabtech, --CFG_TECH,
295 295 MEMTECH => memtech, --CFG_TECH,
296 296 NWINDOWS => CFG_NWIN, --CFG_NWIN,
297 297 DSU => CFG_DSU, --condSel (HAS_DEBUG, 1, 0),
298 298 FPU => CFG_FPU, --CFG_FPU,
299 299 V8 => CFG_V8, --CFG_V8,
300 300 CP => 0, --CFG_CP,
301 301 MAC => CFG_MAC, --CFG_MAC,
302 302 PCLOW => pclow, --CFG_PCLOW,
303 303 NOTAG => 0, --CFG_NOTAG,
304 304 NWP => CFG_NWP, --CFG_NWP,
305 305 ICEN => CFG_ICEN, --CFG_ICEN,
306 306 IREPL => CFG_IREPL, --CFG_IREPL,
307 307 ISETS => CFG_ISETS, --CFG_ISETS,
308 308 ILINESIZE => CFG_ILINE, --CFG_ILINE,
309 309 ISETSIZE => CFG_ISETSZ, --CFG_ISETSZ,
310 310 ISETLOCK => CFG_ILOCK, --CFG_ILOCK,
311 311 DCEN => CFG_DCEN, --CFG_DCEN,
312 312 DREPL => CFG_DREPL, --CFG_DREPL,
313 313 DSETS => CFG_DSETS, --CFG_DSETS,
314 314 DLINESIZE => CFG_DLINE, --CFG_DLINE,
315 315 DSETSIZE => CFG_DSETSZ, --CFG_DSETSZ,
316 316 DSETLOCK => CFG_DLOCK, --CFG_DLOCK,
317 317 DSNOOP => CFG_DSNOOP, --CFG_DSNOOP,
318 318 ILRAM => CFG_ILRAMEN, --CFG_ILRAMEN,
319 319 ILRAMSIZE => CFG_ILRAMSZ, --CFG_ILRAMSZ,
320 320 ILRAMSTART => CFG_ILRAMADDR, --CFG_ILRAMADDR,
321 321 DLRAM => CFG_DLRAMEN, --CFG_DLRAMEN,
322 322 DLRAMSIZE => CFG_DLRAMSZ, --CFG_DLRAMSZ,
323 323 DLRAMSTART => CFG_DLRAMADDR, --CFG_DLRAMADDR,
324 324 MMUEN => CFG_MMUEN, --CFG_MMUEN,
325 325 ITLBNUM => CFG_ITLBNUM, --CFG_ITLBNUM,
326 326 DTLBNUM => CFG_DTLBNUM, --CFG_DTLBNUM,
327 327 TLB_TYPE => CFG_TLB_TYPE, --CFG_TLB_TYPE,
328 328 TLB_REP => CFG_TLB_REP, --CFG_TLB_REP,
329 329 LDDEL => CFG_LDDEL, --CFG_LDDEL,
330 330 DISAS => disas, --condSel (SIM_ENABLED, 1, 0),
331 331 TBUF => CFG_ITBSZ, --CFG_ITBSZ,
332 332 PWD => CFG_PWD, --CFG_PWD,
333 333 SVT => CFG_SVT, --CFG_SVT,
334 334 RSTADDR => CFG_RSTADDR, --CFG_RSTADDR,
335 335 SMP => CFG_NCPU-1, --CFG_NCPU-1,
336 336 IUFT => 2, --: integer range 0 to 4;--CFG_IUFT_EN,
337 337 FPFT => 1, --: integer range 0 to 4;--CFG_FPUFT_EN,
338 338 CMFT => 1, --: integer range 0 to 1;--CFG_CACHE_FT_EN,
339 339 IUINJ => 0, --: integer; --CFG_RF_ERRINJ,
340 340 CEINJ => 0, --: integer range 0 to 3;--CFG_CACHE_ERRINJ,
341 341 CACHED => 0, --: integer; --CFG_DFIXED,
342 342 NETLIST => 0, --: integer; --CFG_LEON3_NETLIST,
343 343 SCANTEST => 0, --: integer; --CFG_SCANTEST,
344 344 MMUPGSZ => 0, --: integer range 0 to 5;--CFG_MMU_PAGE,
345 345 BP => 1) --CFG_BP
346 346 PORT MAP ( --
347 347 rstn => rstn, --rst_n,
348 348 clk => clkm, --clk,
349 349 ahbi => ahbmi, --ahbmi,
350 350 ahbo => ahbmo(i), --ahbmo(CPU_HINDEX),
351 351 ahbsi => ahbsi, --ahbsi,
352 352 ahbso => ahbso, --ahbso,
353 353 irqi => irqi(i), --irqi(CPU_HINDEX),
354 354 irqo => irqo(i), --irqo(CPU_HINDEX),
355 355 dbgi => dbgi(i), --dbgi(CPU_HINDEX),
356 356 dbgo => dbgo(i), --dbgo(CPU_HINDEX),
357 357 gclk => clkm --clk
358 358 );
359 359 END GENERATE leon3_radhard_i;
360 360
361 361 END GENERATE;
362 362 errorn_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (errorn, dbgo(0).error);
363 363
364 364 dsugen : IF CFG_DSU = 1 GENERATE
365 365 dsu0 : dsu3 -- LEON3 Debug Support Unit
366 366 GENERIC MAP (hindex => 0, -- TODO : hindex => 2
367 367 haddr => 16#900#, hmask => 16#F00#,
368 368 ncpu => CFG_NCPU, tbits => 30, tech => memtech,
369 369 irq => 0, kbytes => CFG_ATBSZ)
370 370 PORT MAP (rstn, clkm, ahbmi, ahbsi, ahbso(0),-- TODO :ahbso(2)
371 371 dbgo, dbgi, dsui, dsuo);
372 372 dsui.enable <= '1';
373 373 dsui.break <= '0';
374 374 END GENERATE;
375 375 END GENERATE;
376 376
377 377 nodsu : IF CFG_DSU = 0 GENERATE
378 378 ahbso(0) <= ahbs_none;
379 379 dsuo.tstop <= '0';
380 380 dsuo.active <= '0';
381 381 END GENERATE;
382 382
383 383 irqctrl : IF CFG_IRQ3_ENABLE /= 0 GENERATE
384 384 irqctrl0 : irqmp -- interrupt controller
385 385 GENERIC MAP (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
386 386 PORT MAP (rstn, clkm, apbi, apbo(2), irqo, irqi);
387 387 END GENERATE;
388 388 irq3 : IF CFG_IRQ3_ENABLE = 0 GENERATE
389 389 x : FOR i IN 0 TO CFG_NCPU-1 GENERATE
390 390 irqi(i).irl <= "0000";
391 391 END GENERATE;
392 392 apbo(2) <= apb_none;
393 393 END GENERATE;
394 394
395 395 ----------------------------------------------------------------------
396 396 --- Memory controllers ---------------------------------------------
397 397 ----------------------------------------------------------------------
398 398 ESAMEMCT : IF USES_IAP_MEMCTRLR = 0 GENERATE
399 399 memctrlr : mctrl GENERIC MAP (
400 400 hindex => 2,
401 401 pindex => 0,
402 402 paddr => 0,
403 403 srbanks => 1
404 404 )
405 405 PORT MAP (rstn, clkm, memi, memo, ahbsi, ahbso(2), apbi, apbo(0), wpo, sdo);
406 406 memi.bexcn <= '1';
407 407 memi.brdyn <= '1';
408 408
409 409 nSRAM_CE_s <= NOT (memo.ramsn(1 DOWNTO 0));
410 410 nSRAM_OE_s <= memo.ramoen(0);
411 411 END GENERATE;
412 412
413 413 IAPMEMCT : IF USES_IAP_MEMCTRLR = 1 GENERATE
414 414 memctrlr : srctrle_0ws
415 415 GENERIC MAP(
416 416 hindex => 2, -- TODO : hindex => 0
417 417 pindex => 0,
418 418 paddr => 0,
419 419 srbanks => 2,
420 420 banksz => SRBANKSZ, --512k * 32
421 421 rmw => 1,
422 422 --Aeroflex memory generics:
423 423 mbpedac => BYPASS_EDAC_MEMCTRLR,
424 424 mprog => 1, -- program memory by default values after reset
425 mpsrate => 15, -- default scrub rate period
425 mpsrate => 5, -- default scrub rate period
426 426 mpb2s => 14, -- default busy to scrub delay
427 427 mpapb => 1, -- instantiate apb register
428 428 mchipcnt => 2,
429 429 mpenall => 1 -- when 0 program only E1 chip, else program all dies
430 430 )
431 431 PORT MAP (
432 432 rst => rstn,
433 433 clk => clkm,
434 434 ahbsi => ahbsi,
435 435 ahbso => ahbso(2), -- TODO :ahbso(0),
436 436 apbi => apbi,
437 437 apbo => apbo(0),
438 438 sri => memi,
439 439 sro => memo,
440 440 --Aeroflex memory signals:
441 441 ucerr => OPEN, -- uncorrectable error signal
442 442 mbe => mbe, -- enable memory programming
443 443 mbe_drive => mbe_drive -- drive the MBE memory signal
444 444 );
445 445
446 446 memi.brdyn <= nSRAM_READY;
447 447
448 448 mbe_pad : iopad
449 449 GENERIC MAP(tech => padtech, oepol => USES_IAP_MEMCTRLR)
450 450 PORT MAP(pad => SRAM_MBE,
451 451 i => mbe,
452 452 en => mbe_drive,
453 453 o => memi.bexcn);
454 454
455 455 nSRAM_CE_s <= (memo.ramsn(1 DOWNTO 0));
456 456 nSRAM_OE_s <= memo.oen;
457 457
458 458 END GENERATE;
459 459
460 460
461 461 memi.writen <= '1';
462 462 memi.wrn <= "1111";
463 463 memi.bwidth <= "10";
464 464
465 465 bdr : FOR i IN 0 TO 3 GENERATE
466 466 data_pad : iopadv GENERIC MAP (tech => padtech, width => 8, oepol => USES_IAP_MEMCTRLR)
467 467 PORT MAP (
468 468 data(31-i*8 DOWNTO 24-i*8),
469 469 memo.data(31-i*8 DOWNTO 24-i*8),
470 470 memo.bdrive(i),
471 471 memi.data(31-i*8 DOWNTO 24-i*8));
472 472 END GENERATE;
473 473
474 474 addr_pad : outpadv GENERIC MAP (width => ADDRESS_SIZE, tech => padtech)
475 475 PORT MAP (address, memo.address(ADDRESS_SIZE+1 DOWNTO 2));
476 476 rams_pad : outpadv GENERIC MAP (tech => padtech, width => 2) PORT MAP (nSRAM_CE, nSRAM_CE_s);
477 477 oen_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_OE, nSRAM_OE_s);
478 478 nBWE_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_WE, memo.writen);
479 479 nBWa_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE0, memo.mben(3));
480 480 nBWb_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE1, memo.mben(2));
481 481 nBWc_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE2, memo.mben(1));
482 482 nBWd_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE3, memo.mben(0));
483 483
484 484
485 485
486 486 ----------------------------------------------------------------------
487 487 --- AHB CONTROLLER -------------------------------------------------
488 488 ----------------------------------------------------------------------
489 489 ahb0 : ahbctrl -- AHB arbiter/multiplexer
490 490 GENERIC MAP (defmast => CFG_DEFMST, split => CFG_SPLIT,
491 491 rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
492 492 ioen => 0, nahbm => maxahbmsp, nahbs => 8, fixbrst => 0)
493 493 PORT MAP (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
494 494
495 495 ----------------------------------------------------------------------
496 496 --- AHB UART -------------------------------------------------------
497 497 ----------------------------------------------------------------------
498 498 dcomgen : IF CFG_AHB_UART = 1 GENERATE
499 499 dcom0 : ahbuart
500 500 GENERIC MAP (hindex => maxahbmsp-1, pindex => 4, paddr => 4)
501 501 PORT MAP (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(4), ahbmi, ahbmo(maxahbmsp-1));
502 502 dsurx_pad : inpad GENERIC MAP (tech => padtech) PORT MAP (ahbrxd, ahbuarti.rxd);
503 503 dsutx_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (ahbtxd, ahbuarto.txd);
504 504 END GENERATE;
505 505 nouah : IF CFG_AHB_UART = 0 GENERATE apbo(4) <= apb_none; END GENERATE;
506 506
507 507 ----------------------------------------------------------------------
508 508 --- APB Bridge -----------------------------------------------------
509 509 ----------------------------------------------------------------------
510 510 apb0 : apbctrl -- AHB/APB bridge
511 511 GENERIC MAP (hindex => 1, haddr => CFG_APBADDR)
512 512 PORT MAP (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
513 513
514 514 ----------------------------------------------------------------------
515 515 --- GPT Timer ------------------------------------------------------
516 516 ----------------------------------------------------------------------
517 517 gpt : IF CFG_GPT_ENABLE /= 0 GENERATE
518 518 timer0 : gptimer -- timer unit
519 519 GENERIC MAP (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
520 520 sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
521 521 nbits => CFG_GPT_TW)
522 522 PORT MAP (rstn, clkm, apbi, apbo(3), gpti, gpto);
523 523 gpti.dhalt <= dsuo.tstop;
524 524 gpti.extclk <= '0';
525 525 END GENERATE;
526 526 notim : IF CFG_GPT_ENABLE = 0 GENERATE apbo(3) <= apb_none; END GENERATE;
527 527
528 528
529 529 ----------------------------------------------------------------------
530 530 --- APB UART -------------------------------------------------------
531 531 ----------------------------------------------------------------------
532 532 ua1 : IF CFG_UART1_ENABLE /= 0 GENERATE
533 533 uart1 : apbuart -- UART 1
534 534 GENERIC MAP (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
535 535 fifosize => CFG_UART1_FIFO)
536 536 PORT MAP (rstn, clkm, apbi, apbo(1), apbuarti, apbuarto);
537 537 apbuarti.rxd <= urxd1;
538 538 apbuarti.extclk <= '0';
539 539 utxd1 <= apbuarto.txd;
540 540 apbuarti.ctsn <= '0';
541 541 END GENERATE;
542 542 noua0 : IF CFG_UART1_ENABLE = 0 GENERATE apbo(1) <= apb_none; END GENERATE;
543 543
544 544 -------------------------------------------------------------------------------
545 545 -- AMBA BUS -------------------------------------------------------------------
546 546 -------------------------------------------------------------------------------
547 547
548 548 -- APB --------------------------------------------------------------------
549 549 apbi_ext <= apbi;
550 550 all_apb : FOR I IN 0 TO NB_APB_SLAVE-1 GENERATE
551 551 max_16_apb : IF I + 5 < 16 GENERATE
552 552 apbo(I+5) <= apbo_ext(I+5);
553 553 END GENERATE max_16_apb;
554 554 END GENERATE all_apb;
555 555 -- AHB_Slave --------------------------------------------------------------
556 556 ahbi_s_ext <= ahbsi;
557 557 all_ahbs : FOR I IN 0 TO NB_AHB_SLAVE-1 GENERATE
558 558 max_16_ahbs : IF I + 3 < 16 GENERATE
559 559 ahbso(I+3) <= ahbo_s_ext(I+3);
560 560 END GENERATE max_16_ahbs;
561 561 END GENERATE all_ahbs;
562 562 -- AHB_Master -------------------------------------------------------------
563 563 ahbi_m_ext <= ahbmi;
564 564 all_ahbm : FOR I IN 0 TO NB_AHB_MASTER-1 GENERATE
565 565 max_16_ahbm : IF I + CFG_NCPU + CFG_AHB_UART < 16 GENERATE
566 566 ahbmo(I + CFG_NCPU) <= ahbo_m_ext(I+CFG_NCPU);
567 567 END GENERATE max_16_ahbm;
568 568 END GENERATE all_ahbm;
569 569
570 570
571 571
572 572 END Behavioral;
Show file before | Show file after | Hide comments
@@ -1,542 +1,591
1 1 LIBRARY ieee;
2 2 USE ieee.std_logic_1164.ALL;
3 3 USE ieee.numeric_std.ALL;
4 4
5 5 LIBRARY lpp;
6 6 USE lpp.lpp_ad_conv.ALL;
7 7 USE lpp.iir_filter.ALL;
8 8 USE lpp.FILTERcfg.ALL;
9 9 USE lpp.lpp_memory.ALL;
10 10 USE lpp.lpp_waveform_pkg.ALL;
11 11 USE lpp.lpp_dma_pkg.ALL;
12 12 USE lpp.lpp_top_lfr_pkg.ALL;
13 13 USE lpp.lpp_lfr_pkg.ALL;
14 14 USE lpp.general_purpose.ALL;
15 15
16 16 LIBRARY techmap;
17 17 USE techmap.gencomp.ALL;
18 18
19 19 LIBRARY grlib;
20 20 USE grlib.amba.ALL;
21 21 USE grlib.stdlib.ALL;
22 22 USE grlib.devices.ALL;
23 23 USE GRLIB.DMA2AHB_Package.ALL;
24 24
25 25 ENTITY lpp_lfr IS
26 26 GENERIC (
27 27 Mem_use : INTEGER := use_RAM;
28 28 nb_data_by_buffer_size : INTEGER := 11;
29 29 nb_snapshot_param_size : INTEGER := 11;
30 30 delta_vector_size : INTEGER := 20;
31 31 delta_vector_size_f0_2 : INTEGER := 7;
32 32
33 33 pindex : INTEGER := 4;
34 34 paddr : INTEGER := 4;
35 35 pmask : INTEGER := 16#fff#;
36 36 pirq_ms : INTEGER := 0;
37 37 pirq_wfp : INTEGER := 1;
38 38
39 39 hindex : INTEGER := 2;
40 40
41 41 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) := (OTHERS => '0')
42 42
43 43 );
44 44 PORT (
45 45 clk : IN STD_LOGIC;
46 46 rstn : IN STD_LOGIC;
47 47 -- SAMPLE
48 48 sample_B : IN Samples(2 DOWNTO 0);
49 49 sample_E : IN Samples(4 DOWNTO 0);
50 50 sample_val : IN STD_LOGIC;
51 51 -- APB
52 52 apbi : IN apb_slv_in_type;
53 53 apbo : OUT apb_slv_out_type;
54 54 -- AHB
55 55 ahbi : IN AHB_Mst_In_Type;
56 56 ahbo : OUT AHB_Mst_Out_Type;
57 57 -- TIME
58 58 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
59 59 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
60 60 --
61 61 data_shaping_BW : OUT STD_LOGIC;
62 62 --
63 63 debug_vector : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
64 64 debug_vector_ms : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
65 65 );
66 66 END lpp_lfr;
67 67
68 68 ARCHITECTURE beh OF lpp_lfr IS
69 69 SIGNAL sample_s : Samples(7 DOWNTO 0);
70 70 --
71 71 SIGNAL data_shaping_SP0 : STD_LOGIC;
72 72 SIGNAL data_shaping_SP1 : STD_LOGIC;
73 73 SIGNAL data_shaping_R0 : STD_LOGIC;
74 74 SIGNAL data_shaping_R1 : STD_LOGIC;
75 75 SIGNAL data_shaping_R2 : STD_LOGIC;
76 76 --
77 77 SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
78 78 SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
79 79 SIGNAL sample_f2_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
80 80 --
81 81 SIGNAL sample_f0_val : STD_LOGIC;
82 82 SIGNAL sample_f1_val : STD_LOGIC;
83 83 SIGNAL sample_f2_val : STD_LOGIC;
84 84 SIGNAL sample_f3_val : STD_LOGIC;
85 85 --
86 SIGNAL sample_f_val : STD_LOGIC_VECTOR(3 DOWNTO 0);
87 SIGNAL sample_f_data : STD_LOGIC_VECTOR((6*16)*4-1 DOWNTO 0);
88 --
86 89 SIGNAL sample_f0_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
87 90 SIGNAL sample_f1_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
88 91 SIGNAL sample_f2_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
89 92 SIGNAL sample_f3_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
90 93 --
91 94 SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
92 95 SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
93 96 SIGNAL sample_f2_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
94 97
95 98 -- SM
96 99 SIGNAL ready_matrix_f0 : STD_LOGIC;
97 100 -- SIGNAL ready_matrix_f0_1 : STD_LOGIC;
98 101 SIGNAL ready_matrix_f1 : STD_LOGIC;
99 102 SIGNAL ready_matrix_f2 : STD_LOGIC;
100 103 SIGNAL status_ready_matrix_f0 : STD_LOGIC;
101 104 -- SIGNAL status_ready_matrix_f0_1 : STD_LOGIC;
102 105 SIGNAL status_ready_matrix_f1 : STD_LOGIC;
103 106 SIGNAL status_ready_matrix_f2 : STD_LOGIC;
104 107 SIGNAL addr_matrix_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
105 108 SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
106 109 SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
107 110 SIGNAL length_matrix_f0 : STD_LOGIC_VECTOR(25 DOWNTO 0);
108 111 SIGNAL length_matrix_f1 : STD_LOGIC_VECTOR(25 DOWNTO 0);
109 112 SIGNAL length_matrix_f2 : STD_LOGIC_VECTOR(25 DOWNTO 0);
110 113
111 114 -- WFP
112 115 SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
113 116 SIGNAL delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
114 117 SIGNAL delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
115 118 SIGNAL delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
116 119 SIGNAL delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
117 120 SIGNAL delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
118 121
119 122 SIGNAL nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
120 123 SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
121 124 SIGNAL enable_f0 : STD_LOGIC;
122 125 SIGNAL enable_f1 : STD_LOGIC;
123 126 SIGNAL enable_f2 : STD_LOGIC;
124 127 SIGNAL enable_f3 : STD_LOGIC;
125 128 SIGNAL burst_f0 : STD_LOGIC;
126 129 SIGNAL burst_f1 : STD_LOGIC;
127 130 SIGNAL burst_f2 : STD_LOGIC;
128 131
129 132 --SIGNAL run : STD_LOGIC;
130 133 SIGNAL start_date : STD_LOGIC_VECTOR(30 DOWNTO 0);
131 134
132 135 -----------------------------------------------------------------------------
133 136 --
134 137 -----------------------------------------------------------------------------
135 138 -- SIGNAL data_f0_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
136 139 -- SIGNAL data_f0_data_out_valid_s : STD_LOGIC;
137 140 -- SIGNAL data_f0_data_out_valid_burst_s : STD_LOGIC;
138 141 --f1
139 142 -- SIGNAL data_f1_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
140 143 -- SIGNAL data_f1_data_out_valid_s : STD_LOGIC;
141 144 -- SIGNAL data_f1_data_out_valid_burst_s : STD_LOGIC;
142 145 --f2
143 146 -- SIGNAL data_f2_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
144 147 -- SIGNAL data_f2_data_out_valid_s : STD_LOGIC;
145 148 -- SIGNAL data_f2_data_out_valid_burst_s : STD_LOGIC;
146 149 --f3
147 150 -- SIGNAL data_f3_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
148 151 -- SIGNAL data_f3_data_out_valid_s : STD_LOGIC;
149 152 -- SIGNAL data_f3_data_out_valid_burst_s : STD_LOGIC;
150 153
151 154 SIGNAL wfp_status_buffer_ready : STD_LOGIC_VECTOR(3 DOWNTO 0);
152 155 SIGNAL wfp_addr_buffer : STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
153 156 SIGNAL wfp_length_buffer : STD_LOGIC_VECTOR(25 DOWNTO 0);
154 157 SIGNAL wfp_ready_buffer : STD_LOGIC_VECTOR(3 DOWNTO 0);
155 158 SIGNAL wfp_buffer_time : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
156 159 SIGNAL wfp_error_buffer_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
157 160 -----------------------------------------------------------------------------
158 161 -- DMA RR
159 162 -----------------------------------------------------------------------------
160 163 -- SIGNAL dma_sel_valid : STD_LOGIC;
161 164 -- SIGNAL dma_rr_valid : STD_LOGIC_VECTOR(3 DOWNTO 0);
162 165 -- SIGNAL dma_rr_grant_s : STD_LOGIC_VECTOR(3 DOWNTO 0);
163 166 -- SIGNAL dma_rr_grant_ms : STD_LOGIC_VECTOR(3 DOWNTO 0);
164 167 -- SIGNAL dma_rr_valid_ms : STD_LOGIC_VECTOR(3 DOWNTO 0);
165 168
166 169 -- SIGNAL dma_rr_grant : STD_LOGIC_VECTOR(4 DOWNTO 0);
167 170 -- SIGNAL dma_sel : STD_LOGIC_VECTOR(4 DOWNTO 0);
168 171
169 172 -----------------------------------------------------------------------------
170 173 -- DMA_REG
171 174 -----------------------------------------------------------------------------
172 175 -- SIGNAL ongoing_reg : STD_LOGIC;
173 176 -- SIGNAL dma_sel_reg : STD_LOGIC_VECTOR(3 DOWNTO 0);
174 177 -- SIGNAL dma_send_reg : STD_LOGIC;
175 178 -- SIGNAL dma_valid_burst_reg : STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
176 179 -- SIGNAL dma_address_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
177 180 -- SIGNAL dma_data_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
178 181
179 182
180 183 -----------------------------------------------------------------------------
181 184 -- DMA
182 185 -----------------------------------------------------------------------------
183 186 -- SIGNAL dma_send : STD_LOGIC;
184 187 -- SIGNAL dma_valid_burst : STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
185 188 -- SIGNAL dma_done : STD_LOGIC;
186 189 -- SIGNAL dma_ren : STD_LOGIC;
187 190 -- SIGNAL dma_address : STD_LOGIC_VECTOR(31 DOWNTO 0);
188 191 -- SIGNAL dma_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
189 192 -- SIGNAL dma_data_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
190 193
191 194 -----------------------------------------------------------------------------
192 195 -- MS
193 196 -----------------------------------------------------------------------------
194 197
195 198 -- SIGNAL data_ms_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
196 199 -- SIGNAL data_ms_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
197 200 -- SIGNAL data_ms_valid : STD_LOGIC;
198 201 -- SIGNAL data_ms_valid_burst : STD_LOGIC;
199 202 -- SIGNAL data_ms_ren : STD_LOGIC;
200 203 -- SIGNAL data_ms_done : STD_LOGIC;
201 204 -- SIGNAL dma_ms_ongoing : STD_LOGIC;
202 205
203 206 -- SIGNAL run_ms : STD_LOGIC;
204 207 -- SIGNAL ms_softandhard_rstn : STD_LOGIC;
205 208
206 209 SIGNAL matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
207 210 -- SIGNAL matrix_time_f0_1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
208 211 SIGNAL matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
209 212 SIGNAL matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
210 213
211 214
212 215 SIGNAL error_buffer_full : STD_LOGIC;
213 216 SIGNAL error_input_fifo_write : STD_LOGIC_VECTOR(2 DOWNTO 0);
214 217
215 218 -- SIGNAL debug_ms : STD_LOGIC_VECTOR(31 DOWNTO 0);
216 219 -- SIGNAL debug_signal : STD_LOGIC_VECTOR(31 DOWNTO 0);
217 220
218 221 -----------------------------------------------------------------------------
219 222 SIGNAL dma_fifo_burst_valid : STD_LOGIC_VECTOR(4 DOWNTO 0);
220 223 SIGNAL dma_fifo_data : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
221 224 SIGNAL dma_fifo_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
222 225 SIGNAL dma_buffer_new : STD_LOGIC_VECTOR(4 DOWNTO 0);
223 226 SIGNAL dma_buffer_addr : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
224 227 SIGNAL dma_buffer_length : STD_LOGIC_VECTOR(26*5-1 DOWNTO 0);
225 228 SIGNAL dma_buffer_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
226 229 SIGNAL dma_buffer_full_err : STD_LOGIC_VECTOR(4 DOWNTO 0);
227 230 SIGNAL dma_grant_error : STD_LOGIC;
228 231
229 232 SIGNAL apb_reg_debug_vector : STD_LOGIC_VECTOR(11 DOWNTO 0);
230 233 -----------------------------------------------------------------------------
231 234 SIGNAL sample_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
232 235 SIGNAL sample_f0_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
233 236 SIGNAL sample_f1_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
234 237 SIGNAL sample_f2_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
235 238 SIGNAL sample_f3_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
236 239
237 240 BEGIN
238 241
239 242 debug_vector <= apb_reg_debug_vector;
240 243 -----------------------------------------------------------------------------
241 244
242 245 sample_s(4 DOWNTO 0) <= sample_E(4 DOWNTO 0);
243 246 sample_s(7 DOWNTO 5) <= sample_B(2 DOWNTO 0);
244 247 sample_time <= coarse_time & fine_time;
245 248
246 249 --all_channel : FOR i IN 7 DOWNTO 0 GENERATE
247 250 -- sample_s(i) <= sample(i)(13) & sample(i)(13) & sample(i);
248 251 --END GENERATE all_channel;
249 252
250 253 -----------------------------------------------------------------------------
251 254 lpp_lfr_filter_1 : lpp_lfr_filter
252 255 GENERIC MAP (
253 256 Mem_use => Mem_use)
254 257 PORT MAP (
255 258 sample => sample_s,
256 259 sample_val => sample_val,
257 260 sample_time => sample_time,
258 261 clk => clk,
259 262 rstn => rstn,
260 263 data_shaping_SP0 => data_shaping_SP0,
261 264 data_shaping_SP1 => data_shaping_SP1,
262 265 data_shaping_R0 => data_shaping_R0,
263 266 data_shaping_R1 => data_shaping_R1,
264 267 data_shaping_R2 => data_shaping_R2,
265 sample_f0_val => sample_f0_val,
266 sample_f1_val => sample_f1_val,
267 sample_f2_val => sample_f2_val,
268 sample_f3_val => sample_f3_val,
269 sample_f0_wdata => sample_f0_data,
270 sample_f1_wdata => sample_f1_data,
271 sample_f2_wdata => sample_f2_data,
272 sample_f3_wdata => sample_f3_data,
268 sample_f0_val => sample_f_val(0),
269 sample_f1_val => sample_f_val(1),
270 sample_f2_val => sample_f_val(2),
271 sample_f3_val => sample_f_val(3),
272 sample_f0_wdata => OPEN,
273 sample_f1_wdata => OPEN,
274 sample_f2_wdata => OPEN,
275 sample_f3_wdata => OPEN,
273 276 sample_f0_time => sample_f0_time,
274 277 sample_f1_time => sample_f1_time,
275 278 sample_f2_time => sample_f2_time,
276 279 sample_f3_time => sample_f3_time
277 280 );
281 -----------------------------------------------------------------------------
282 ALL_lane: FOR J IN 0 TO 3 GENERATE
283 ALL_channel: FOR I IN 0 TO 5 GENERATE
284 sample_f_data(15 + I*16 + J*6*16 DOWNTO 14 + I*16 + J*6*16) <= STD_LOGIC_VECTOR(to_unsigned(J,2));
285 sample_f_data(13 + I*16 + J*6*16 DOWNTO 11 + I*16 + J*6*16) <= STD_LOGIC_VECTOR(to_unsigned(I,3));
278 286
287 PROCESS (clk, rstn)
288 BEGIN -- PROCESS
289 IF rstn = '0' THEN -- asynchronous reset (active low)
290 sample_f_data(10 + I*16 + J*6*16 DOWNTO 0 + I*16 + J*6*16 ) <= STD_LOGIC_VECTOR(to_unsigned(2**11/6*I,11));
291 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
292 IF sample_f_val(J) = '1' THEN
293 sample_f_data(10 + I*16 + J*6*16 DOWNTO 0 + I*16 + J*6*16) <= STD_LOGIC_VECTOR(to_unsigned(
294 to_integer(UNSIGNED(sample_f_data(10 + I*16 + J*6*16 DOWNTO 0 + I*16 + J*6*16))) + 1,
295 11));
296 END IF;
297 END IF;
298 END PROCESS;
299
300 END GENERATE ALL_channel;
301 END GENERATE ALL_lane;
302
303 PROCESS (clk, rstn)
304 BEGIN -- PROCESS
305 IF rstn = '0' THEN -- asynchronous reset (active low)
306 sample_f0_val <= '0';
307 sample_f1_val <= '0';
308 sample_f2_val <= '0';
309 sample_f3_val <= '0';
310 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
311 sample_f0_val <= sample_f_val(0);
312 sample_f1_val <= sample_f_val(1);
313 sample_f2_val <= sample_f_val(2);
314 sample_f3_val <= sample_f_val(3);
315 END IF;
316 END PROCESS;
317
318
319 sample_f0_data <= sample_f_data(1*6*16-1 DOWNTO 0*6*16);
320 sample_f1_data <= sample_f_data(2*6*16-1 DOWNTO 1*6*16);
321 sample_f2_data <= sample_f_data(3*6*16-1 DOWNTO 2*6*16);
322 sample_f3_data <= sample_f_data(4*6*16-1 DOWNTO 3*6*16);
323
324 --sample_f0_data <= X"0020" & X"0010" & X"0008" & X"0004" & X"0002" & X"0001";
325 --sample_f1_data <= X"1020" & X"1010" & X"1008" & X"1004" & X"1002" & X"1001";
326 --sample_f2_data <= X"2020" & X"2010" & X"2008" & X"2004" & X"2002" & X"2001";
327 --sample_f3_data <= X"4020" & X"4010" & X"4008" & X"4004" & X"4002" & X"4001";
279 328 -----------------------------------------------------------------------------
280 329 lpp_lfr_apbreg_1 : lpp_lfr_apbreg
281 330 GENERIC MAP (
282 331 nb_data_by_buffer_size => nb_data_by_buffer_size,
283 332 -- nb_word_by_buffer_size => nb_word_by_buffer_size, -- TODO
284 333 nb_snapshot_param_size => nb_snapshot_param_size,
285 334 delta_vector_size => delta_vector_size,
286 335 delta_vector_size_f0_2 => delta_vector_size_f0_2,
287 336 pindex => pindex,
288 337 paddr => paddr,
289 338 pmask => pmask,
290 339 pirq_ms => pirq_ms,
291 340 pirq_wfp => pirq_wfp,
292 341 top_lfr_version => top_lfr_version)
293 342 PORT MAP (
294 343 HCLK => clk,
295 344 HRESETn => rstn,
296 345 apbi => apbi,
297 346 apbo => apbo,
298 347
299 348 run_ms => OPEN,--run_ms,
300 349
301 350 ready_matrix_f0 => ready_matrix_f0,
302 351 ready_matrix_f1 => ready_matrix_f1,
303 352 ready_matrix_f2 => ready_matrix_f2,
304 353 error_buffer_full => error_buffer_full, -- TODO
305 354 error_input_fifo_write => error_input_fifo_write, -- TODO
306 355 status_ready_matrix_f0 => status_ready_matrix_f0,
307 356 status_ready_matrix_f1 => status_ready_matrix_f1,
308 357 status_ready_matrix_f2 => status_ready_matrix_f2,
309 358
310 359 matrix_time_f0 => matrix_time_f0,
311 360 matrix_time_f1 => matrix_time_f1,
312 361 matrix_time_f2 => matrix_time_f2,
313 362
314 363 addr_matrix_f0 => addr_matrix_f0,
315 364 addr_matrix_f1 => addr_matrix_f1,
316 365 addr_matrix_f2 => addr_matrix_f2,
317 366
318 367 length_matrix_f0 => length_matrix_f0,
319 368 length_matrix_f1 => length_matrix_f1,
320 369 length_matrix_f2 => length_matrix_f2,
321 370 -------------------------------------------------------------------------
322 371 --status_full => status_full, -- TODo
323 372 --status_full_ack => status_full_ack, -- TODo
324 373 --status_full_err => status_full_err, -- TODo
325 374 status_new_err => status_new_err,
326 375 data_shaping_BW => data_shaping_BW,
327 376 data_shaping_SP0 => data_shaping_SP0,
328 377 data_shaping_SP1 => data_shaping_SP1,
329 378 data_shaping_R0 => data_shaping_R0,
330 379 data_shaping_R1 => data_shaping_R1,
331 380 data_shaping_R2 => data_shaping_R2,
332 381 delta_snapshot => delta_snapshot,
333 382 delta_f0 => delta_f0,
334 383 delta_f0_2 => delta_f0_2,
335 384 delta_f1 => delta_f1,
336 385 delta_f2 => delta_f2,
337 386 nb_data_by_buffer => nb_data_by_buffer,
338 387 -- nb_word_by_buffer => nb_word_by_buffer, -- TODO
339 388 nb_snapshot_param => nb_snapshot_param,
340 389 enable_f0 => enable_f0,
341 390 enable_f1 => enable_f1,
342 391 enable_f2 => enable_f2,
343 392 enable_f3 => enable_f3,
344 393 burst_f0 => burst_f0,
345 394 burst_f1 => burst_f1,
346 395 burst_f2 => burst_f2,
347 396 run => OPEN, --run,
348 397 start_date => start_date,
349 398 -- debug_signal => debug_signal,
350 399 wfp_status_buffer_ready => wfp_status_buffer_ready,-- TODO
351 400 wfp_addr_buffer => wfp_addr_buffer,-- TODO
352 401 wfp_length_buffer => wfp_length_buffer,-- TODO
353 402
354 403 wfp_ready_buffer => wfp_ready_buffer,-- TODO
355 404 wfp_buffer_time => wfp_buffer_time,-- TODO
356 405 wfp_error_buffer_full => wfp_error_buffer_full, -- TODO
357 406 -------------------------------------------------------------------------
358 407 sample_f3_v => sample_f3_data(1*16-1 DOWNTO 0*16),
359 408 sample_f3_e1 => sample_f3_data(2*16-1 DOWNTO 1*16),
360 409 sample_f3_e2 => sample_f3_data(3*16-1 DOWNTO 2*16),
361 410 sample_f3_valid => sample_f3_val,
362 411 debug_vector => apb_reg_debug_vector
363 412 );
364 413
365 414 -----------------------------------------------------------------------------
366 415 -----------------------------------------------------------------------------
367 416 lpp_waveform_1 : lpp_waveform
368 417 GENERIC MAP (
369 418 tech => inferred,
370 419 data_size => 6*16,
371 420 nb_data_by_buffer_size => nb_data_by_buffer_size,
372 421 nb_snapshot_param_size => nb_snapshot_param_size,
373 422 delta_vector_size => delta_vector_size,
374 423 delta_vector_size_f0_2 => delta_vector_size_f0_2
375 424 )
376 425 PORT MAP (
377 426 clk => clk,
378 427 rstn => rstn,
379 428
380 429 reg_run => '1',--run,
381 430 reg_start_date => start_date,
382 431 reg_delta_snapshot => delta_snapshot,
383 432 reg_delta_f0 => delta_f0,
384 433 reg_delta_f0_2 => delta_f0_2,
385 434 reg_delta_f1 => delta_f1,
386 435 reg_delta_f2 => delta_f2,
387 436
388 437 enable_f0 => enable_f0,
389 438 enable_f1 => enable_f1,
390 439 enable_f2 => enable_f2,
391 440 enable_f3 => enable_f3,
392 441 burst_f0 => burst_f0,
393 442 burst_f1 => burst_f1,
394 443 burst_f2 => burst_f2,
395 444
396 445 nb_data_by_buffer => nb_data_by_buffer,
397 446 nb_snapshot_param => nb_snapshot_param,
398 447 status_new_err => status_new_err,
399 448
400 449 status_buffer_ready => wfp_status_buffer_ready,
401 450 addr_buffer => wfp_addr_buffer,
402 451 length_buffer => wfp_length_buffer,
403 452 ready_buffer => wfp_ready_buffer,
404 453 buffer_time => wfp_buffer_time,
405 454 error_buffer_full => wfp_error_buffer_full,
406 455
407 456 coarse_time => coarse_time,
408 457 -- fine_time => fine_time,
409 458
410 459 --f0
411 460 data_f0_in_valid => sample_f0_val,
412 461 data_f0_in => sample_f0_data,
413 462 data_f0_time => sample_f0_time,
414 463 --f1
415 464 data_f1_in_valid => sample_f1_val,
416 465 data_f1_in => sample_f1_data,
417 466 data_f1_time => sample_f1_time,
418 467 --f2
419 468 data_f2_in_valid => sample_f2_val,
420 469 data_f2_in => sample_f2_data,
421 470 data_f2_time => sample_f2_time,
422 471 --f3
423 472 data_f3_in_valid => sample_f3_val,
424 473 data_f3_in => sample_f3_data,
425 474 data_f3_time => sample_f3_time,
426 475 -- OUTPUT -- DMA interface
427 476
428 477 dma_fifo_valid_burst => dma_fifo_burst_valid(3 DOWNTO 0),
429 478 dma_fifo_data => dma_fifo_data(32*4-1 DOWNTO 0),
430 479 dma_fifo_ren => dma_fifo_ren(3 DOWNTO 0),
431 480 dma_buffer_new => dma_buffer_new(3 DOWNTO 0),
432 481 dma_buffer_addr => dma_buffer_addr(32*4-1 DOWNTO 0),
433 482 dma_buffer_length => dma_buffer_length(26*4-1 DOWNTO 0),
434 483 dma_buffer_full => dma_buffer_full(3 DOWNTO 0),
435 484 dma_buffer_full_err => dma_buffer_full_err(3 DOWNTO 0)
436 485
437 486 );
438 487
439 488 -----------------------------------------------------------------------------
440 489 -- Matrix Spectral
441 490 -----------------------------------------------------------------------------
442 491 sample_f0_wen <= NOT(sample_f0_val) & NOT(sample_f0_val) & NOT(sample_f0_val) &
443 492 NOT(sample_f0_val) & NOT(sample_f0_val);
444 493 sample_f1_wen <= NOT(sample_f1_val) & NOT(sample_f1_val) & NOT(sample_f1_val) &
445 494 NOT(sample_f1_val) & NOT(sample_f1_val);
446 495 sample_f2_wen <= NOT(sample_f2_val) & NOT(sample_f2_val) & NOT(sample_f2_val) &
447 496 NOT(sample_f2_val) & NOT(sample_f2_val);
448 497
449 498 sample_f0_wdata <= sample_f0_data((3*16)-1 DOWNTO (1*16)) & sample_f0_data((6*16)-1 DOWNTO (3*16)); -- (MSB) E2 E1 B2 B1 B0 (LSB)
450 499 sample_f1_wdata <= sample_f1_data((3*16)-1 DOWNTO (1*16)) & sample_f1_data((6*16)-1 DOWNTO (3*16));
451 500 sample_f2_wdata <= sample_f2_data((3*16)-1 DOWNTO (1*16)) & sample_f2_data((6*16)-1 DOWNTO (3*16));
452 501
453 502 -------------------------------------------------------------------------------
454 503
455 504 --ms_softandhard_rstn <= rstn AND run_ms AND run;
456 505
457 506 -----------------------------------------------------------------------------
458 507 lpp_lfr_ms_1 : lpp_lfr_ms
459 508 GENERIC MAP (
460 509 Mem_use => Mem_use)
461 510 PORT MAP (
462 511 clk => clk,
463 512 --rstn => ms_softandhard_rstn, --rstn,
464 513 rstn => rstn,
465 514
466 515 run => '1',--run_ms,
467 516
468 517 start_date => start_date,
469 518
470 519 coarse_time => coarse_time,
471 520
472 521 sample_f0_wen => sample_f0_wen,
473 522 sample_f0_wdata => sample_f0_wdata,
474 523 sample_f0_time => sample_f0_time,
475 524 sample_f1_wen => sample_f1_wen,
476 525 sample_f1_wdata => sample_f1_wdata,
477 526 sample_f1_time => sample_f1_time,
478 527 sample_f2_wen => sample_f2_wen,
479 528 sample_f2_wdata => sample_f2_wdata,
480 529 sample_f2_time => sample_f2_time,
481 530
482 531 --DMA
483 532 dma_fifo_burst_valid => dma_fifo_burst_valid(4), -- OUT
484 533 dma_fifo_data => dma_fifo_data((4+1)*32-1 DOWNTO 4*32), -- OUT
485 534 dma_fifo_ren => dma_fifo_ren(4), -- IN
486 535 dma_buffer_new => dma_buffer_new(4), -- OUT
487 536 dma_buffer_addr => dma_buffer_addr((4+1)*32-1 DOWNTO 4*32), -- OUT
488 537 dma_buffer_length => dma_buffer_length((4+1)*26-1 DOWNTO 4*26), -- OUT
489 538 dma_buffer_full => dma_buffer_full(4), -- IN
490 539 dma_buffer_full_err => dma_buffer_full_err(4), -- IN
491 540
492 541
493 542
494 543 --REG
495 544 ready_matrix_f0 => ready_matrix_f0,
496 545 ready_matrix_f1 => ready_matrix_f1,
497 546 ready_matrix_f2 => ready_matrix_f2,
498 547 error_buffer_full => error_buffer_full,
499 548 error_input_fifo_write => error_input_fifo_write,
500 549
501 550 status_ready_matrix_f0 => status_ready_matrix_f0,
502 551 status_ready_matrix_f1 => status_ready_matrix_f1,
503 552 status_ready_matrix_f2 => status_ready_matrix_f2,
504 553 addr_matrix_f0 => addr_matrix_f0,
505 554 addr_matrix_f1 => addr_matrix_f1,
506 555 addr_matrix_f2 => addr_matrix_f2,
507 556
508 557 length_matrix_f0 => length_matrix_f0,
509 558 length_matrix_f1 => length_matrix_f1,
510 559 length_matrix_f2 => length_matrix_f2,
511 560
512 561 matrix_time_f0 => matrix_time_f0,
513 562 matrix_time_f1 => matrix_time_f1,
514 563 matrix_time_f2 => matrix_time_f2,
515 564
516 565 debug_vector => debug_vector_ms);
517 566
518 567 -----------------------------------------------------------------------------
519 568 --run_dma <= run_ms OR run;
520 569
521 570 DMA_SubSystem_1 : DMA_SubSystem
522 571 GENERIC MAP (
523 572 hindex => hindex)
524 573 PORT MAP (
525 574 clk => clk,
526 575 rstn => rstn,
527 576 run => '1',--run_dma,
528 577 ahbi => ahbi,
529 578 ahbo => ahbo,
530 579
531 580 fifo_burst_valid => dma_fifo_burst_valid, --fifo_burst_valid,
532 581 fifo_data => dma_fifo_data, --fifo_data,
533 582 fifo_ren => dma_fifo_ren, --fifo_ren,
534 583
535 584 buffer_new => dma_buffer_new, --buffer_new,
536 585 buffer_addr => dma_buffer_addr, --buffer_addr,
537 586 buffer_length => dma_buffer_length, --buffer_length,
538 587 buffer_full => dma_buffer_full, --buffer_full,
539 588 buffer_full_err => dma_buffer_full_err, --buffer_full_err,
540 589 grant_error => dma_grant_error); --grant_error);
541 590
542 END beh; No newline at end of file
591 END beh;
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