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Add HeadReg for input fifo channel f1 (lpp_lfr_ms)
pellion -
r388:3dbc90b2eccb JC
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1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
3
4 ENTITY lpp_lfr_ms_reg_head IS
5
6 PORT (
7 clk : IN STD_LOGIC;
8 rstn : IN STD_LOGIC;
9
10 in_wen : IN STD_LOGIC;
11 in_data : IN STD_LOGIC_VECTOR(5*16-1 DOWNTO 0);
12 in_full : IN STD_LOGIC;
13 in_empty : IN STD_LOGIC;
14
15 out_wen : OUT STD_LOGIC;
16 out_data : OUT STD_LOGIC_VECTOR(5*16-1 DOWNTO 0);
17 out_full : OUT STD_LOGIC
18 );
19
20 END lpp_lfr_ms_reg_head;
21
22 ARCHITECTURE Beh OF lpp_lfr_ms_reg_head IS
23 TYPE fsm_state_reg_head IS (REG_EMPTY, REG_FULL);
24 SIGNAL fsm_state : fsm_state_reg_head;
25
26 SIGNAL reg_data : STD_LOGIC_VECTOR(5*16-1 DOWNTO 0);
27 SIGNAL out_wen_s : STD_LOGIC;
28 BEGIN -- Beh
29
30 PROCESS (clk, rstn)
31 BEGIN
32 IF rstn = '0' THEN
33 fsm_state <= REG_EMPTY;
34 reg_data <= (OTHERS => '0');
35 out_wen_s <= '1';
36 ELSIF clk'event AND clk = '1' THEN
37 out_wen_s <= '1';
38
39 CASE fsm_state IS
40 WHEN REG_EMPTY =>
41 reg_data <= in_data;
42 IF in_wen = '0' AND in_full = '1' THEN
43 fsm_state <= REG_FULL;
44 END IF;
45 WHEN REG_FULL =>
46 IF in_empty = '1' THEN
47 out_wen_s <= '0';
48 IF in_wen = '0' THEN
49 reg_data <= in_data;
50 ELSE
51 fsm_state <= REG_EMPTY;
52 END IF;
53 END IF;
54 WHEN OTHERS => NULL;
55 END CASE;
56
57 END IF;
58 END PROCESS;
59
60 out_full <= '1' WHEN fsm_state = REG_FULL ELSE in_full;
61
62 out_data <= reg_data WHEN fsm_state = REG_FULL ELSE in_data;
63
64 out_wen <= '0' WHEN out_wen_s = '0' ELSE
65 '1' WHEN fsm_state = REG_FULL ELSE
66 in_wen;
67
68 END Beh;
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@@ -1,439 +1,440
1 1 VHDLIB=../..
2 2 SCRIPTSDIR=$(VHDLIB)/scripts/
3 3
4 4 GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh)
5 5 TOP=TB
6 6
7 7 CMD_VLIB=vlib
8 8 CMD_VMAP=vmap
9 9 CMD_VCOM=@vcom -quiet -93 -work
10 10
11 11 ################## project specific targets ##########################
12 12
13 13 all:
14 14 @echo "make vsim"
15 15 @echo "make libs"
16 16 @echo "make clean"
17 17 @echo "make vcom_grlib vcom_lpp vcom_tb"
18 18
19 19 run:
20 20 @vsim work.TB -do run.do
21 21 # @vsim work.TB
22 22 # @vsim lpp.lpp_lfr_ms
23 23
24 24 vsim: libs vcom run
25 25
26 26 libs:
27 27 @$(CMD_VLIB) modelsim
28 28 @$(CMD_VMAP) modelsim modelsim
29 29 @$(CMD_VLIB) modelsim/techmap
30 30 @$(CMD_VMAP) techmap modelsim/techmap
31 31 @$(CMD_VLIB) modelsim/grlib
32 32 @$(CMD_VMAP) grlib modelsim/grlib
33 33 @$(CMD_VLIB) modelsim/gaisler
34 34 @$(CMD_VMAP) gaisler modelsim/gaisler
35 35 @$(CMD_VLIB) modelsim/work
36 36 @$(CMD_VMAP) work modelsim/work
37 37 @$(CMD_VLIB) modelsim/lpp
38 38 @$(CMD_VMAP) lpp modelsim/lpp
39 39 @echo "libs done"
40 40
41 41
42 42 clean:
43 43 @rm -Rf modelsim
44 44 @rm -Rf modelsim.ini
45 45 @rm -Rf *~
46 46 @rm -Rf transcript
47 47 @rm -Rf wlft*
48 48 @rm -Rf *.wlf
49 49 @rm -Rf vish_stacktrace.vstf
50 50 @rm -Rf libs.do
51 51
52 52 vcom: vcom_grlib vcom_techmap vcom_gaisler vcom_lpp vcom_tb
53 53
54 54
55 55 vcom_tb:
56 56 ## $(CMD_VCOM) lpp lpp_memory.vhd
57 57 ## $(CMD_VCOM) lpp lppFIFOxN.vhd
58 58 ## $(CMD_VCOM) lpp lpp_FIFO.vhd
59 59 ## $(CMD_VCOM) lpp lpp_lfr_ms.vhd
60 60 $(CMD_VCOM) work TB.vhd
61 61 @echo "vcom done"
62 62
63 63 vcom_grlib:
64 64 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/version.vhd
65 65 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/config_types.vhd
66 66 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/config.vhd
67 67 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/stdlib.vhd
68 68 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/stdio.vhd
69 69 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/testlib.vhd
70 70 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/ftlib/mtie_ftlib.vhd
71 71 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/util/util.vhd
72 72 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/sparc/sparc.vhd
73 73 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/sparc/sparc_disas.vhd
74 74 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/sparc/cpu_disas.vhd
75 75 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/modgen/multlib.vhd
76 76 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/modgen/leaves.vhd
77 77 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/amba.vhd
78 78 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/devices.vhd
79 79 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/defmst.vhd
80 80 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/apbctrl.vhd
81 81 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/ahbctrl.vhd
82 82 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/dma2ahb_pkg.vhd
83 83 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/dma2ahb.vhd
84 84 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/ahbmst.vhd
85 85 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/ahbmon.vhd
86 86 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/apbmon.vhd
87 87 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/ambamon.vhd
88 88 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/dma2ahb_tp.vhd
89 89 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/amba_tp.vhd
90 90 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_pkg.vhd
91 91 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahb_mst_pkg.vhd
92 92 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahb_slv_pkg.vhd
93 93 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_util.vhd
94 94 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahb_mst.vhd
95 95 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahb_slv.vhd
96 96 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahbs.vhd
97 97 $(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahb_ctrl.vhd
98 98 @echo "vcom grlib done"
99 99
100 100 vcom_gaisler:
101 101 $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/arith/arith.vhd
102 102 $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/arith/mul32.vhd
103 103 $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/arith/div32.vhd
104 104 $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/memctrl.vhd
105 105 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/sdctrl.vhd
106 106 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/sdctrl64.vhd
107 107 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/sdmctrl.vhd
108 108 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/srctrl.vhd
109 109 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ssrctrl.vhd
110 110 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsrctrlc.vhd
111 111 # # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsrctrl.vhd
112 112 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsdctrl.vhd
113 113 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsdmctrl.vhd
114 114 # # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftmctrlc.vhd
115 115 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsrctrl8.vhd
116 116 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsdmctrlx.vhd
117 117 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftmctrlcx.vhd
118 118 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftmctrl.vhd
119 119 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsdctrl64.vhd
120 120 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/grlfpu/mtie_grlfpu.vhd
121 121 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/grlfpc/mtie_grlfpc.vhd
122 122 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/grlfpcft/mtie_grlfpcft.vhd
123 123 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmuconf# ig.vhd
124 124 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmuiface.vhd
125 125 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/libmmu.vhd
126 126 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmutlbcam.vhd
127 127 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmulrue.vhd
128 128 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmulru.vhd
129 129 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmutlb.vhd
130 130 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmutw.vhd
131 131 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmu.vhd
132 132 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/leon3.vhd
133 133 # # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/libiu.vhd
134 134 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/libcache.vhd
135 135 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/tbufmem.vhd
136 136 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/dsu3x.vhd
137 137 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/dsu3.vhd
138 138 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/dsu3_2x.vhd
139 139 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/clk2xsync.vhd
140 140 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/clk2xqual.vhd
141 141 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/grfpushwx.vhd
142 142 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/libproc3.vhd
143 143 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/cachemem.vhd
144 144 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/mmu_icache.vhd
145 145 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/mmu_dcache.vhd
146 146 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/mmu_acache.vhd
147 147 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/mmu_cache.vhd
148 148 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/iu3.vhd
149 149 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/grfpwx.vhd
150 150 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/mfpwx.vhd
151 151 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/grlfpwx.vhd
152 152 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/proc3.vhd
153 153 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/leon3s2x.vhd
154 154 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/leon3s.vhd
155 155 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/leon3cg.vhd
156 156 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/grfpwxsh.vhd
157 157 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/leon3sh.vhd
158 158 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3ftv2/mtie_leon3ftv2.vhd
159 159 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/irqmp/irqmp2x.vhd
160 160 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/irqmp/irqmp.vhd
161 161 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/irqmp/irqamp.vhd
162 162 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/irqmp/irqamp2x.vhd
163 163 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/can.vhd
164 164 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/can_mod.vhd
165 165 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/can_oc.vhd
166 166 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/can_mc.vhd
167 167 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/canmux.vhd
168 168 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/can_rd.vhd
169 169 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/can_oc_core.vhd
170 170 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/grcan.vhd
171 171 $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/misc.vhd
172 172 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/rstgen.vhd
173 173 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/gptimer.vhd
174 174 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbram.vhd
175 175 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbdpram.vhd
176 176 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbtrace.vhd
177 177 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbtrace_mb.vhd
178 178 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbtrace_mmb.vhd
179 179 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grgpio.vhd
180 180 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ftahbram.vhd
181 181 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ftahbram2.vhd
182 182 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbstat.vhd
183 183 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/logan.vhd
184 184 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/apbps2.vhd
185 185 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/charrom_package.vhd
186 186 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/charrom.vhd
187 187 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/apbvga.vhd
188 188 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahb2ahb.vhd
189 189 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbbridge.vhd
190 190 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/svgactrl.vhd
191 191 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grfifo.vhd
192 192 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/gradcdac.vhd
193 193 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grsysmon.vhd
194 194 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/gracectrl.vhd
195 195 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grgpreg.vhd
196 196 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbmst2.vhd
197 197 ## $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/memscrub.vhd
198 198 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahb_mst_iface.vhd
199 199 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grgprbank.vhd
200 200 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grclkgate.vhd
201 201 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grclkgate2x.vhd
202 202 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grtimer.vhd
203 203 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grpulse.vhd
204 204 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grversion.vhd
205 205 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbfrom.vhd
206 206 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/ambatest/ahbtbp.vhd
207 207 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/ambatest/ahbtbm.vhd
208 208 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/net/net.vhd
209 209 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/uart/uart.vhd
210 210 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/uart/libdcom.vhd
211 211 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/uart/apbuart.vhd
212 212 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/uart/dcom.vhd
213 213 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/uart/dcom_uart.vhd
214 214 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/uart/ahbuart.vhd
215 215 $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/sim.vhd
216 216 $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/sram.vhd
217 217 $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/sramft.vhd
218 218 $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/sram16.vhd
219 219 $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/phy.vhd
220 220 $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/ahbrep.vhd
221 221 $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/delay_wire.vhd
222 222 $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/pwm_check.vhd
223 223 $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/ramback.vhd
224 224 $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/zbtssram.vhd
225 225 $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/slavecheck.vhd
226 226 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/jtag.vhd
227 227 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/libjtagcom.vhd
228 228 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/jtagcom.vhd
229 229 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/ahbjtag.vhd
230 230 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/ahbjtag_bsd.vhd
231 231 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/bscanctrl.vhd
232 232 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/bscanregs.vhd
233 233 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/bscanregsbd.vhd
234 234 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/jtagtst.vhd
235 235 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/ethernet_mac.vhd
236 236 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/greth.vhd
237 237 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/greth_mb.vhd
238 238 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/greth_gbit.vhd
239 239 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/greth_gbit_mb.vhd
240 240 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/grethm.vhd
241 241 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/rgmii.vhd
242 242 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/spacewire/spacewire.vhd
243 243 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/spacewire/grspw.vhd
244 244 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/spacewire/grspw2.vhd
245 245 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/spacewire/grspwm.vhd
246 246 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/spacewire/grspw2_phy.vhd
247 247 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/spacewire/grspw_phy.vhd
248 248 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/gr1553b/gr1553b_pkg.vhd
249 249 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/gr1553b/gr1553b_pads.vhd
250 250 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/gr1553b/simtrans1553.vhd
251 251 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/nand/nandpkg.vhd
252 252 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/nand/nandfctrlx.vhd
253 253 # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/nand/nandfctrl.vhd
254 254 @echo "vcom gaisler done"
255 255
256 256 vcom_techmap:
257 257 $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/gencomp/gencomp.vhd
258 258 $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/gencomp/netcomp.vhd
259 259 $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/memory_inferred.vhd
260 260 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/tap_inferred.vhd
261 261 $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/ddr_inferred.vhd
262 262 $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/mul_inferred.vhd
263 263 $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/ddr_phy_inferred.vhd
264 264 $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/ddrphy_datapath.vhd
265 265 $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/sim_pll.vhd
266 266 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/proasic3e/buffer_apa3e.vhd
267 267 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/proasic3e/clkgen_proasic3e.vhd
268 268 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/proasic3e/ddr_proasic3e.vhd
269 269 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/proasic3e/memory_apa3e.vhd
270 270 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/proasic3e/pads_apa3e.vhd
271 271 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/proasic3e/tap_proasic3e.vhd
272 272 $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/allclkgen.vhd
273 273 $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/allddr.vhd
274 274 $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/allmem.vhd
275 275 $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/allmul.vhd
276 276 $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/allpads.vhd
277 277 $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/alltap.vhd
278 278 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/clkgen.vhd
279 279 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/clkmux.vhd
280 280 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/clkand.vhd
281 281 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/ddr_ireg.vhd
282 282 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/ddr_oreg.vhd
283 283 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/ddrphy.vhd
284 284 $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram.vhd
285 285 $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram64.vhd
286 286 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram_2p.vhd
287 287 $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram_dp.vhd
288 288 $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncfifo.vhd
289 289 $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/regfile_3p.vhd
290 290 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/tap.vhd
291 291 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/techbuf.vhd
292 292 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/nandtree.vhd
293 293 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/clkpad.vhd
294 294 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/clkpad_ds.vhd
295 295 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/inpad.vhd
296 296 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/inpad_ds.vhd
297 297 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/iodpad.vhd
298 298 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/iopad.vhd
299 299 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/iopad_ds.vhd
300 300 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/lvds_combo.vhd
301 301 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/odpad.vhd
302 302 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/outpad.vhd
303 303 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/outpad_ds.vhd
304 304 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/toutpad.vhd
305 305 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/skew_outpad.vhd
306 306 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grspwc_net.vhd
307 307 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grspwc2_net.vhd
308 308 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grlfpw_net.vhd
309 309 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grlfpw4_net.vhd
310 310 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grfpw_net.vhd
311 311 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grfpw4_net.vhd
312 312 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/leon4_net.vhd
313 313 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/mul_61x61.vhd
314 314 $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/cpu_disas_net.vhd
315 315 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/ringosc.vhd
316 316 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/corepcif_net.vhd
317 317 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/pci_arb_net.vhd
318 318 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grpci2_phy_net.vhd
319 319 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/system_monitor.vhd
320 320 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grgates.vhd
321 321 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/inpad_ddr.vhd
322 322 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/outpad_ddr.vhd
323 323 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/iopad_ddr.vhd
324 324 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram128bw.vhd
325 325 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram256bw.vhd
326 326 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram128.vhd
327 327 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram156bw.vhd
328 328 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/techmult.vhd
329 329 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/spictrl_net.vhd
330 330 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/scanreg.vhd
331 331 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncrambw.vhd
332 332 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram_2pbw.vhd
333 333 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/obt1553_net.vhd
334 334 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/sdram_phy.vhd
335 335 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/from.vhd
336 336 # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/mtie_maps.vhd
337 337 @echo "vcom techmap done"
338 338
339 339 vcom_lpp:
340 340 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_amba/lpp_amba.vhd
341 341 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/iir_filter/iir_filter.vhd
342 342 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/iir_filter/RAM_CEL.vhd
343 343 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/lpp_fft/fft_components.vhd
344 344 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/lpp_fft/lpp_fft.vhd
345 345 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/lpp_fft/Linker_FFT.vhd
346 346 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/general_purpose.vhd
347 347 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/ADDRcntr.vhd
348 348 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/ALU.vhd
349 349 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Adder.vhd
350 350 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clk_Divider2.vhd
351 351 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clk_divider.vhd
352 352 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC.vhd
353 353 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_CONTROLER.vhd
354 354 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_MUX.vhd
355 355 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_MUX2.vhd
356 356 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_REG.vhd
357 357 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MUX2.vhd
358 358 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MUXN.vhd
359 359 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Multiplier.vhd
360 360 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/REG.vhd
361 361 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/SYNC_FF.vhd
362 362 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Shifter.vhd
363 363 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/TwoComplementer.vhd
364 364 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clock_Divider.vhd
365 365 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_to_level.vhd
366 366 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_detection.vhd
367 367 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_positive_detection.vhd
368 368 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/SYNC_VALID_BIT.vhd
369 369 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/RR_Arbiter_4.vhd
370 370 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/general_counter.vhd
371 371 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_ad_Conv/lpp_ad_Conv.vhd
372 372 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/dsp/iir_filter/FILTERcfg.vhd
373 373 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_amba/apb_devices_list.vhd
374 374 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_dma/lpp_dma_pkg.vhd
375 375 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/lpp_matrix.vhd
376 376 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/MatriceSpectrale.vhd
377 377 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/ALU_Driver.vhd
378 378 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/ReUse_CTRLR.vhd
379 379 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/Dispatch.vhd
380 380 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/DriveInputs.vhd
381 381 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/GetResult.vhd
382 382 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/MatriceSpectrale.vhd
383 383 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/Matrix.vhd
384 384 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/TopSpecMatrix.vhd
385 385 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/SpectralMatrix.vhd
386 386 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_Header/lpp_Header.vhd
387 387 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_Header/HeaderBuilder.vhd
388 388 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_memory/lpp_memory.vhd
389 389 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_memory/lppFIFOxN.vhd
390 390 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_memory/lpp_FIFO.vhd
391 391 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/lpp_fft/CoreFFT_simu.vhd
392 392 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_spectral_matrix/spectral_matrix_package.vhd
393 393 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_spectral_matrix/spectral_matrix_switch_f0.vhd
394 394 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_spectral_matrix/spectral_matrix_time_managment.vhd
395 395 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_spectral_matrix/MS_control.vhd
396 396 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_spectral_matrix/MS_calculation.vhd
397 397 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_amba/apb_devices_list.vhd
398 398 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_pkg.vhd
399 399 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_apbreg_simu.vhd
400 400 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_apbreg_ms_pointer.vhd
401 401 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_ms.vhd
402 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_ms_reg_head.vhd
402 403 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_ms_fsmdma.vhd
403 404 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_ms_FFT.vhd
404 405 @echo "vcom lpp done"
405 406
406 407 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_amba/apb_devices_list.vhd
407 408 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/general_purpose.vhd
408 409 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/ADDRcntr.vhd
409 410 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/ALU.vhd
410 411 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Adder.vhd
411 412 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clk_Divider2.vhd
412 413 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clk_divider.vhd
413 414 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC.vhd
414 415 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_CONTROLER.vhd
415 416 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_MUX.vhd
416 417 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_MUX2.vhd
417 418 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_REG.vhd
418 419 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MUX2.vhd
419 420 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MUXN.vhd
420 421 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Multiplier.vhd
421 422 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/REG.vhd
422 423 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/SYNC_FF.vhd
423 424 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Shifter.vhd
424 425 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/TwoComplementer.vhd
425 426 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clock_Divider.vhd
426 427 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_to_level.vhd
427 428 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_detection.vhd
428 429 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_positive_detection.vhd
429 430 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/SYNC_VALID_BIT.vhd
430 431 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/RR_Arbiter_4.vhd
431 432 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/general_counter.vhd
432 433 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lfr_time_management/lpp_lfr_time_management.vhd
433 434 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lfr_time_management/apb_lfr_time_management.vhd
434 435 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lfr_time_management/lfr_time_management.vhd
435 436 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lfr_time_management/fine_time_counter.vhd
436 437 # $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lfr_time_management/coarse_time_counter.vhd
437 438 # @echo "vcom lpp done"
438 439
439 440 #include Makefile_vcom_lpp
Show file before | Show file after | Hide comments
@@ -1,44 +1,74
1 1 onerror {resume}
2 2 quietly WaveActivateNextPane {} 0
3 add wave -noupdate -group debug -expand -group FSM_MS_DMA_state /tb/lpp_lfr_ms_1/debug_reg(0)
4 add wave -noupdate -group debug -expand -group FSM_MS_DMA_state /tb/lpp_lfr_ms_1/debug_reg(1)
5 add wave -noupdate -group debug -expand -group FSM_MS_DMA_state /tb/lpp_lfr_ms_1/debug_reg(2)
6 add wave -noupdate -group debug -expand -group status_ready_matrix /tb/lpp_lfr_ms_1/debug_reg(5)
7 add wave -noupdate -group debug -expand -group status_ready_matrix /tb/lpp_lfr_ms_1/debug_reg(4)
8 add wave -noupdate -group debug -expand -group status_ready_matrix /tb/lpp_lfr_ms_1/debug_reg(3)
9 add wave -noupdate -group debug -expand -group matrix_ready /tb/lpp_lfr_ms_1/debug_reg(8)
10 add wave -noupdate -group debug -expand -group matrix_ready /tb/lpp_lfr_ms_1/debug_reg(7)
11 add wave -noupdate -group debug -expand -group matrix_ready /tb/lpp_lfr_ms_1/debug_reg(6)
12 add wave -noupdate -group debug /tb/lpp_lfr_ms_1/debug_reg
13 add wave -noupdate -group debug /tb/lpp_lfr_apbreg_1/apbi
14 add wave -noupdate -group debug /tb/lpp_lfr_apbreg_1/apbo
15 add wave -noupdate -group debug /tb/ready_reg
16 add wave -noupdate -group Logic /tb/lpp_lfr_ms_1/debug_reg(0)
17 add wave -noupdate -group Logic /tb/lpp_lfr_ms_1/debug_reg(1)
18 add wave -noupdate -group Logic /tb/lpp_lfr_ms_1/debug_reg(2)
19 add wave -noupdate -expand /tb/lpp_lfr_apbreg_1/debug_signal
20 add wave -noupdate -expand -subitemconfig {/tb/lpp_lfr_ms_1/observation_vector_0(2) {-color Blue} /tb/lpp_lfr_ms_1/observation_vector_0(0) {-color Blue}} /tb/lpp_lfr_ms_1/observation_vector_0
3 add wave -noupdate -expand -group debug -expand -group FSM_MS_DMA_state /tb/lpp_lfr_ms_1/debug_reg(0)
4 add wave -noupdate -expand -group debug -expand -group FSM_MS_DMA_state /tb/lpp_lfr_ms_1/debug_reg(1)
5 add wave -noupdate -expand -group debug -expand -group FSM_MS_DMA_state /tb/lpp_lfr_ms_1/debug_reg(2)
6 add wave -noupdate -expand -group debug -expand -group status_ready_matrix /tb/lpp_lfr_ms_1/debug_reg(5)
7 add wave -noupdate -expand -group debug -expand -group status_ready_matrix /tb/lpp_lfr_ms_1/debug_reg(4)
8 add wave -noupdate -expand -group debug -expand -group status_ready_matrix /tb/lpp_lfr_ms_1/debug_reg(3)
9 add wave -noupdate -expand -group debug -expand -group matrix_ready /tb/lpp_lfr_ms_1/debug_reg(8)
10 add wave -noupdate -expand -group debug -expand -group matrix_ready /tb/lpp_lfr_ms_1/debug_reg(7)
11 add wave -noupdate -expand -group debug -expand -group matrix_ready /tb/lpp_lfr_ms_1/debug_reg(6)
12 add wave -noupdate -expand -group debug /tb/lpp_lfr_ms_1/debug_reg
13 add wave -noupdate -expand -group debug /tb/lpp_lfr_apbreg_1/apbi
14 add wave -noupdate -expand -group debug /tb/lpp_lfr_apbreg_1/apbo
15 add wave -noupdate -expand -group debug /tb/ready_reg
16 add wave -noupdate -expand -group Logic /tb/lpp_lfr_ms_1/debug_reg(0)
17 add wave -noupdate -expand -group Logic /tb/lpp_lfr_ms_1/debug_reg(1)
18 add wave -noupdate -expand -group Logic /tb/lpp_lfr_ms_1/debug_reg(2)
19 add wave -noupdate /tb/lpp_lfr_apbreg_1/debug_signal
20 add wave -noupdate -expand -subitemconfig {/tb/lpp_lfr_ms_1/observation_vector_0(2) {-color Blue -height 15} /tb/lpp_lfr_ms_1/observation_vector_0(0) {-color Blue -height 15}} /tb/lpp_lfr_ms_1/observation_vector_0
21 21 add wave -noupdate -expand /tb/lpp_lfr_ms_1/observation_vector_1
22 22 add wave -noupdate -divider {New Divider}
23 23 add wave -noupdate /tb/lpp_lfr_ms_1/lpp_lfr_ms_fft_1/corefft_1/counter
24 24 add wave -noupdate /tb/lpp_lfr_ms_1/lpp_lfr_ms_fft_1/corefft_1/counter_out
25 25 add wave -noupdate /tb/lpp_lfr_ms_1/lpp_lfr_ms_fft_1/corefft_1/counter_wait
26 add wave -noupdate -expand -group ERROR /tb/lpp_lfr_ms_1/error_bad_component_error
27 add wave -noupdate -expand -group ERROR /tb/lpp_lfr_ms_1/error_buffer_full
28 add wave -noupdate -expand -group ERROR /tb/lpp_lfr_ms_1/error_input_fifo_write
29 add wave -noupdate -expand -group INPUT_FIFO_F1 /tb/lpp_lfr_ms_1/lppfifoxn_f1/wen
30 add wave -noupdate -expand -group INPUT_FIFO_F1 /tb/lpp_lfr_ms_1/lppfifoxn_f1/ren
31 add wave -noupdate -expand -group INPUT_FIFO_F1 /tb/lpp_lfr_ms_1/lppfifoxn_f1/empty
32 add wave -noupdate -expand -group INPUT_FIFO_F1 /tb/lpp_lfr_ms_1/lppfifoxn_f1/full
33 add wave -noupdate -expand -group INPUT_FIFO_F1 /tb/lpp_lfr_ms_1/lppfifoxn_f1/almost_full
34 add wave -noupdate -radix hexadecimal -expand -subitemconfig {/tb/lpp_lfr_apbreg_1/reg_sp.config_active_interruption_onnewmatrix {-height 15 -radix hexadecimal} /tb/lpp_lfr_apbreg_1/reg_sp.config_active_interruption_onerror {-height 15 -radix hexadecimal} /tb/lpp_lfr_apbreg_1/reg_sp.config_ms_run {-height 15 -radix hexadecimal} /tb/lpp_lfr_apbreg_1/reg_sp.status_ready_matrix_f0_0 {-height 15 -radix hexadecimal} /tb/lpp_lfr_apbreg_1/reg_sp.status_ready_matrix_f1_0 {-height 15 -radix hexadecimal} /tb/lpp_lfr_apbreg_1/reg_sp.status_ready_matrix_f2_0 {-height 15 -radix hexadecimal} /tb/lpp_lfr_apbreg_1/reg_sp.status_ready_matrix_f0_1 {-height 15 -radix hexadecimal} /tb/lpp_lfr_apbreg_1/reg_sp.status_ready_matrix_f1_1 {-height 15 -radix hexadecimal} /tb/lpp_lfr_apbreg_1/reg_sp.status_ready_matrix_f2_1 {-height 15 -radix hexadecimal} /tb/lpp_lfr_apbreg_1/reg_sp.status_error_bad_component_error {-height 15 -radix hexadecimal} /tb/lpp_lfr_apbreg_1/reg_sp.status_error_buffer_full {-height 15 -radix hexadecimal} /tb/lpp_lfr_apbreg_1/reg_sp.status_error_input_fifo_write {-height 15 -radix hexadecimal} /tb/lpp_lfr_apbreg_1/reg_sp.addr_matrix_f0_0 {-height 15 -radix hexadecimal} /tb/lpp_lfr_apbreg_1/reg_sp.addr_matrix_f0_1 {-height 15 -radix hexadecimal} /tb/lpp_lfr_apbreg_1/reg_sp.addr_matrix_f1_0 {-height 15 -radix hexadecimal} /tb/lpp_lfr_apbreg_1/reg_sp.addr_matrix_f1_1 {-height 15 -radix hexadecimal} /tb/lpp_lfr_apbreg_1/reg_sp.addr_matrix_f2_0 {-height 15 -radix hexadecimal} /tb/lpp_lfr_apbreg_1/reg_sp.addr_matrix_f2_1 {-height 15 -radix hexadecimal} /tb/lpp_lfr_apbreg_1/reg_sp.time_matrix_f0_0 {-height 15 -radix hexadecimal} /tb/lpp_lfr_apbreg_1/reg_sp.time_matrix_f0_1 {-height 15 -radix hexadecimal} /tb/lpp_lfr_apbreg_1/reg_sp.time_matrix_f1_0 {-height 15 -radix hexadecimal} /tb/lpp_lfr_apbreg_1/reg_sp.time_matrix_f1_1 {-height 15 -radix hexadecimal} /tb/lpp_lfr_apbreg_1/reg_sp.time_matrix_f2_0 {-height 15 -radix hexadecimal} /tb/lpp_lfr_apbreg_1/reg_sp.time_matrix_f2_1 {-height 15 -radix hexadecimal}} /tb/lpp_lfr_apbreg_1/reg_sp
35 add wave -noupdate -expand -group FFT /tb/lpp_lfr_ms_1/lpp_lfr_ms_fft_1/sample_valid
36 add wave -noupdate -expand -group FFT /tb/lpp_lfr_ms_1/lpp_lfr_ms_fft_1/fft_read
37 add wave -noupdate -expand -group FFT /tb/lpp_lfr_ms_1/lpp_lfr_ms_fft_1/sample_data
38 add wave -noupdate -expand -group FFT /tb/lpp_lfr_ms_1/lpp_lfr_ms_fft_1/sample_load
39 add wave -noupdate -expand -group FFT /tb/lpp_lfr_ms_1/lpp_lfr_ms_fft_1/fft_pong
40 add wave -noupdate -expand -group FFT /tb/lpp_lfr_ms_1/lpp_lfr_ms_fft_1/fft_data_im
41 add wave -noupdate -expand -group FFT /tb/lpp_lfr_ms_1/lpp_lfr_ms_fft_1/fft_data_re
42 add wave -noupdate -expand -group FFT /tb/lpp_lfr_ms_1/lpp_lfr_ms_fft_1/fft_data_valid
43 add wave -noupdate -expand -group FFT /tb/lpp_lfr_ms_1/lpp_lfr_ms_fft_1/fft_ready
44 add wave -noupdate /tb/lpp_lfr_ms_1/state_fsm_load_fft
45 add wave -noupdate /tb/lpp_lfr_ms_1/state_fsm_select_channel
46 add wave -noupdate /tb/lpp_lfr_ms_1/lpp_lfr_ms_reg_head_1/in_wen
47 add wave -noupdate /tb/lpp_lfr_ms_1/lpp_lfr_ms_reg_head_1/in_data
48 add wave -noupdate /tb/lpp_lfr_ms_1/lpp_lfr_ms_reg_head_1/in_full
49 add wave -noupdate /tb/lpp_lfr_ms_1/lpp_lfr_ms_reg_head_1/in_empty
50 add wave -noupdate /tb/lpp_lfr_ms_1/lpp_lfr_ms_reg_head_1/fsm_state
51 add wave -noupdate /tb/lpp_lfr_ms_1/lpp_lfr_ms_reg_head_1/reg_data
52 add wave -noupdate /tb/lpp_lfr_ms_1/lpp_lfr_ms_reg_head_1/out_wen_s
53 add wave -noupdate /tb/lpp_lfr_ms_1/lpp_lfr_ms_reg_head_1/out_wen
54 add wave -noupdate /tb/lpp_lfr_ms_1/lpp_lfr_ms_reg_head_1/out_data
55 add wave -noupdate /tb/lpp_lfr_ms_1/lpp_lfr_ms_reg_head_1/out_full
26 56 TreeUpdate [SetDefaultTree]
27 WaveRestoreCursors {{Cursor 1} {20859515887 ps} 0}
28 configure wave -namecolwidth 253
57 WaveRestoreCursors {{Cursor 1} {41374417240 ps} 0} {{Cursor 2} {62390873400 ps} 0}
58 configure wave -namecolwidth 419
29 59 configure wave -valuecolwidth 112
30 60 configure wave -justifyvalue left
31 61 configure wave -signalnamewidth 0
32 62 configure wave -snapdistance 10
33 63 configure wave -datasetprefix 0
34 64 configure wave -rowmargin 4
35 65 configure wave -childrowmargin 2
36 66 configure wave -gridoffset 0
37 67 configure wave -gridperiod 1
38 68 configure wave -griddelta 40
39 69 configure wave -timeline 0
40 70 configure wave -timelineunits ps
41 71 update
42 WaveRestoreZoom {20840058904 ps} {20863099265 ps}
72 WaveRestoreZoom {62074549955 ps} {63157132736 ps}
43 73 bookmark add wave bookmark0 {{61745287067 ps} {63754655343 ps}} 0
44 74 bookmark add wave bookmark1 {{61745287067 ps} {63754655343 ps}} 0
Show file before | Show file after | Hide comments
@@ -1,1009 +1,1035
1 1 LIBRARY ieee;
2 2 USE ieee.std_logic_1164.ALL;
3 3
4 4
5 5 LIBRARY lpp;
6 6 USE lpp.lpp_memory.ALL;
7 7 USE lpp.iir_filter.ALL;
8 8 USE lpp.spectral_matrix_package.ALL;
9 9 USE lpp.lpp_dma_pkg.ALL;
10 10 USE lpp.lpp_Header.ALL;
11 11 USE lpp.lpp_matrix.ALL;
12 12 USE lpp.lpp_matrix.ALL;
13 13 USE lpp.lpp_lfr_pkg.ALL;
14 14 USE lpp.lpp_fft.ALL;
15 15 USE lpp.fft_components.ALL;
16 16
17 17 ENTITY lpp_lfr_ms IS
18 18 GENERIC (
19 19 Mem_use : INTEGER := use_RAM
20 20 );
21 21 PORT (
22 22 clk : IN STD_LOGIC;
23 23 rstn : IN STD_LOGIC;
24 24
25 25 ---------------------------------------------------------------------------
26 26 -- DATA INPUT
27 27 ---------------------------------------------------------------------------
28 28 -- TIME
29 29 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
30 30 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
31 31 --
32 32 sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
33 33 sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
34 34 --
35 35 sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
36 36 sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
37 37 --
38 38 sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
39 39 sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
40 40
41 41 ---------------------------------------------------------------------------
42 42 -- DMA
43 43 ---------------------------------------------------------------------------
44 44 dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
45 45 dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
46 46 dma_valid : OUT STD_LOGIC;
47 47 dma_valid_burst : OUT STD_LOGIC;
48 48 dma_ren : IN STD_LOGIC;
49 49 dma_done : IN STD_LOGIC;
50 50
51 51 -- Reg out
52 52 ready_matrix_f0 : OUT STD_LOGIC;
53 53 ready_matrix_f1 : OUT STD_LOGIC;
54 54 ready_matrix_f2 : OUT STD_LOGIC;
55 55 error_bad_component_error : OUT STD_LOGIC;
56 56 error_buffer_full : OUT STD_LOGIC;
57 57 error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
58 58
59 59 debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
60 60 --
61 61 observation_vector_0: OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
62 62 observation_vector_1: OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
63 63
64 64 -- Reg In
65 65 status_ready_matrix_f0 : IN STD_LOGIC;
66 66 status_ready_matrix_f1 : IN STD_LOGIC;
67 67 status_ready_matrix_f2 : IN STD_LOGIC;
68 68
69 69 config_active_interruption_onNewMatrix : IN STD_LOGIC;
70 70 config_active_interruption_onError : IN STD_LOGIC;
71 71 addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
72 72 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
73 73 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
74 74
75 75 matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
76 76 matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
77 77 matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)
78 78
79 79 );
80 80 END;
81 81
82 82 ARCHITECTURE Behavioral OF lpp_lfr_ms IS
83 83
84 84 SIGNAL sample_f0_A_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
85 85 SIGNAL sample_f0_A_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
86 86 SIGNAL sample_f0_A_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
87 87 SIGNAL sample_f0_A_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
88 88 SIGNAL sample_f0_A_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
89 89
90 90 SIGNAL sample_f0_B_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
91 91 SIGNAL sample_f0_B_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
92 92 SIGNAL sample_f0_B_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
93 93 SIGNAL sample_f0_B_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
94 94 SIGNAL sample_f0_B_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
95 95
96 96 SIGNAL sample_f1_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
97 97 SIGNAL sample_f1_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
98 98 SIGNAL sample_f1_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
99 99 SIGNAL sample_f1_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
100 100
101 101 SIGNAL sample_f1_almost_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
102 102
103 103 SIGNAL sample_f2_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
104 104 SIGNAL sample_f2_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
105 105 SIGNAL sample_f2_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
106 106 SIGNAL sample_f2_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
107 107
108 108 SIGNAL error_wen_f0 : STD_LOGIC;
109 109 SIGNAL error_wen_f1 : STD_LOGIC;
110 110 SIGNAL error_wen_f2 : STD_LOGIC;
111 111
112 112 SIGNAL one_sample_f1_full : STD_LOGIC;
113 113 SIGNAL one_sample_f1_wen : STD_LOGIC;
114 114 SIGNAL one_sample_f2_full : STD_LOGIC;
115 115 SIGNAL one_sample_f2_wen : STD_LOGIC;
116 116
117 117 -----------------------------------------------------------------------------
118 118 -- FSM / SWITCH SELECT CHANNEL
119 119 -----------------------------------------------------------------------------
120 120 TYPE fsm_select_channel IS (IDLE, SWITCH_F0_A, SWITCH_F0_B, SWITCH_F1, SWITCH_F2);
121 121 SIGNAL state_fsm_select_channel : fsm_select_channel;
122 122 SIGNAL pre_state_fsm_select_channel : fsm_select_channel;
123 123
124 124 SIGNAL sample_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
125 125 SIGNAL sample_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
126 126 SIGNAL sample_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
127 127 SIGNAL sample_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
128 128
129 129 -----------------------------------------------------------------------------
130 130 -- FSM LOAD FFT
131 131 -----------------------------------------------------------------------------
132 132 TYPE fsm_load_FFT IS (IDLE, FIFO_1, FIFO_2, FIFO_3, FIFO_4, FIFO_5);
133 133 SIGNAL state_fsm_load_FFT : fsm_load_FFT;
134 134 SIGNAL next_state_fsm_load_FFT : fsm_load_FFT;
135 135
136 136 SIGNAL sample_ren_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
137 137 SIGNAL sample_load : STD_LOGIC;
138 138 SIGNAL sample_valid : STD_LOGIC;
139 139 SIGNAL sample_valid_r : STD_LOGIC;
140 140 SIGNAL sample_data : STD_LOGIC_VECTOR(15 DOWNTO 0);
141 141
142 142
143 143 -----------------------------------------------------------------------------
144 144 -- FFT
145 145 -----------------------------------------------------------------------------
146 146 SIGNAL fft_read : STD_LOGIC;
147 147 SIGNAL fft_pong : STD_LOGIC;
148 148 SIGNAL fft_data_im : STD_LOGIC_VECTOR(15 DOWNTO 0);
149 149 SIGNAL fft_data_re : STD_LOGIC_VECTOR(15 DOWNTO 0);
150 150 SIGNAL fft_data_valid : STD_LOGIC;
151 151 SIGNAL fft_ready : STD_LOGIC;
152 152 -----------------------------------------------------------------------------
153 153 -- SIGNAL fft_linker_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0);
154 154 -----------------------------------------------------------------------------
155 155 TYPE fsm_load_MS_memory IS (IDLE, LOAD_FIFO, TRASH_FFT);
156 156 SIGNAL state_fsm_load_MS_memory : fsm_load_MS_memory;
157 157 SIGNAL current_fifo_load : STD_LOGIC_VECTOR(4 DOWNTO 0);
158 158 SIGNAL current_fifo_empty : STD_LOGIC;
159 159 SIGNAL current_fifo_locked : STD_LOGIC;
160 160 SIGNAL current_fifo_full : STD_LOGIC;
161 161 SIGNAL MEM_IN_SM_locked : STD_LOGIC_VECTOR(4 DOWNTO 0);
162 162
163 163 -----------------------------------------------------------------------------
164 164 SIGNAL MEM_IN_SM_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0);
165 165 SIGNAL MEM_IN_SM_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
166 166 SIGNAL MEM_IN_SM_wen_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
167 167 SIGNAL MEM_IN_SM_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
168 168 SIGNAL MEM_IN_SM_wData : STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0);
169 169 SIGNAL MEM_IN_SM_rData : STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0);
170 170 SIGNAL MEM_IN_SM_Full : STD_LOGIC_VECTOR(4 DOWNTO 0);
171 171 SIGNAL MEM_IN_SM_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
172 172 -----------------------------------------------------------------------------
173 173 SIGNAL SM_in_data : STD_LOGIC_VECTOR(32*2-1 DOWNTO 0);
174 174 SIGNAL SM_in_ren : STD_LOGIC_VECTOR(1 DOWNTO 0);
175 175 SIGNAL SM_in_empty : STD_LOGIC_VECTOR(1 DOWNTO 0);
176 176
177 177 SIGNAL SM_correlation_start : STD_LOGIC;
178 178 SIGNAL SM_correlation_auto : STD_LOGIC;
179 179 SIGNAL SM_correlation_done : STD_LOGIC;
180 180 SIGNAL SM_correlation_done_reg1 : STD_LOGIC;
181 181 SIGNAL SM_correlation_done_reg2 : STD_LOGIC;
182 182 SIGNAL SM_correlation_done_reg3 : STD_LOGIC;
183 183 SIGNAL SM_correlation_begin : STD_LOGIC;
184 184
185 185 SIGNAL MEM_OUT_SM_Full_s : STD_LOGIC;
186 186 SIGNAL MEM_OUT_SM_Data_in_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
187 187 SIGNAL MEM_OUT_SM_Write_s : STD_LOGIC;
188 188
189 189 SIGNAL current_matrix_write : STD_LOGIC;
190 190 SIGNAL current_matrix_wait_empty : STD_LOGIC;
191 191 -----------------------------------------------------------------------------
192 192 SIGNAL fifo_0_ready : STD_LOGIC;
193 193 SIGNAL fifo_1_ready : STD_LOGIC;
194 194 SIGNAL fifo_ongoing : STD_LOGIC;
195 195
196 196 SIGNAL FSM_DMA_fifo_ren : STD_LOGIC;
197 197 SIGNAL FSM_DMA_fifo_empty : STD_LOGIC;
198 198 SIGNAL FSM_DMA_fifo_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
199 199 SIGNAL FSM_DMA_fifo_status : STD_LOGIC_VECTOR(53 DOWNTO 0);
200 200 -----------------------------------------------------------------------------
201 201 SIGNAL MEM_OUT_SM_Write : STD_LOGIC_VECTOR(1 DOWNTO 0);
202 202 SIGNAL MEM_OUT_SM_Read : STD_LOGIC_VECTOR(1 DOWNTO 0);
203 203 SIGNAL MEM_OUT_SM_Data_in : STD_LOGIC_VECTOR(63 DOWNTO 0);
204 204 SIGNAL MEM_OUT_SM_Data_out : STD_LOGIC_VECTOR(63 DOWNTO 0);
205 205 SIGNAL MEM_OUT_SM_Full : STD_LOGIC_VECTOR(1 DOWNTO 0);
206 206 SIGNAL MEM_OUT_SM_Empty : STD_LOGIC_VECTOR(1 DOWNTO 0);
207 207
208 208 -----------------------------------------------------------------------------
209 209 -- TIME REG & INFOs
210 210 -----------------------------------------------------------------------------
211 211 SIGNAL all_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
212 212
213 213 SIGNAL f_empty : STD_LOGIC_VECTOR(3 DOWNTO 0);
214 214 SIGNAL f_empty_reg : STD_LOGIC_VECTOR(3 DOWNTO 0);
215 215 SIGNAL time_update_f : STD_LOGIC_VECTOR(3 DOWNTO 0);
216 216 SIGNAL time_reg_f : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
217 217
218 218 SIGNAL time_reg_f0_A : STD_LOGIC_VECTOR(47 DOWNTO 0);
219 219 SIGNAL time_reg_f0_B : STD_LOGIC_VECTOR(47 DOWNTO 0);
220 220 SIGNAL time_reg_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
221 221 SIGNAL time_reg_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
222 222
223 223 --SIGNAL time_update_f0_A : STD_LOGIC;
224 224 --SIGNAL time_update_f0_B : STD_LOGIC;
225 225 --SIGNAL time_update_f1 : STD_LOGIC;
226 226 --SIGNAL time_update_f2 : STD_LOGIC;
227 227 --
228 228 SIGNAL status_channel : STD_LOGIC_VECTOR(49 DOWNTO 0);
229 229 SIGNAL status_MS_input : STD_LOGIC_VECTOR(49 DOWNTO 0);
230 230 SIGNAL status_component : STD_LOGIC_VECTOR(53 DOWNTO 0);
231 231
232 232 SIGNAL status_component_fifo_0 : STD_LOGIC_VECTOR(53 DOWNTO 0);
233 233 SIGNAL status_component_fifo_1 : STD_LOGIC_VECTOR(53 DOWNTO 0);
234 234 SIGNAL status_component_fifo_0_end : STD_LOGIC;
235 235 SIGNAL status_component_fifo_1_end : STD_LOGIC;
236 236 -----------------------------------------------------------------------------
237 237 SIGNAL fft_ongoing_counter : STD_LOGIC;--_VECTOR(1 DOWNTO 0);
238 238
239 239 SIGNAL fft_ready_reg : STD_LOGIC;
240 240 SIGNAL fft_ready_rising_down : STD_LOGIC;
241 241
242 242 SIGNAL sample_load_reg : STD_LOGIC;
243 243 SIGNAL sample_load_rising_down : STD_LOGIC;
244
245 -----------------------------------------------------------------------------
246 SIGNAL sample_f1_wen_head : STD_LOGIC_VECTOR(4 DOWNTO 0);
247 SIGNAL sample_f1_wen_head_in : STD_LOGIC;
248 SIGNAL sample_f1_wen_head_out : STD_LOGIC;
249 SIGNAL sample_f1_full_head_in : STD_LOGIC;
250 SIGNAL sample_f1_full_head_out : STD_LOGIC;
251 SIGNAL sample_f1_empty_head_in : STD_LOGIC;
252
253 SIGNAL sample_f1_wdata_head : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
244 254
245 255 BEGIN
246 256
247 257
248 258 error_input_fifo_write <= error_wen_f2 & error_wen_f1 & error_wen_f0;
249 259
250 260
251 261 switch_f0_inst : spectral_matrix_switch_f0
252 262 PORT MAP (
253 263 clk => clk,
254 264 rstn => rstn,
255 265
256 266 sample_wen => sample_f0_wen,
257 267
258 268 fifo_A_empty => sample_f0_A_empty,
259 269 fifo_A_full => sample_f0_A_full,
260 270 fifo_A_wen => sample_f0_A_wen,
261 271
262 272 fifo_B_empty => sample_f0_B_empty,
263 273 fifo_B_full => sample_f0_B_full,
264 274 fifo_B_wen => sample_f0_B_wen,
265 275
266 276 error_wen => error_wen_f0); -- TODO
267 277
268 278 -----------------------------------------------------------------------------
269 279 -- FIFO IN
270 280 -----------------------------------------------------------------------------
271 281 lppFIFOxN_f0_a : lppFIFOxN
272 282 GENERIC MAP (
273 283 tech => 0,
274 284 Mem_use => Mem_use,
275 285 Data_sz => 16,
276 286 Addr_sz => 8,
277 287 FifoCnt => 5)
278 288 PORT MAP (
279 289 clk => clk,
280 290 rstn => rstn,
281 291
282 292 ReUse => (OTHERS => '0'),
283 293
284 294 wen => sample_f0_A_wen,
285 295 wdata => sample_f0_wdata,
286 296
287 297 ren => sample_f0_A_ren,
288 298 rdata => sample_f0_A_rdata,
289 299
290 300 empty => sample_f0_A_empty,
291 301 full => sample_f0_A_full,
292 302 almost_full => OPEN);
293 303
294 304 lppFIFOxN_f0_b : lppFIFOxN
295 305 GENERIC MAP (
296 306 tech => 0,
297 307 Mem_use => Mem_use,
298 308 Data_sz => 16,
299 309 Addr_sz => 8,
300 310 FifoCnt => 5)
301 311 PORT MAP (
302 312 clk => clk,
303 313 rstn => rstn,
304 314
305 315 ReUse => (OTHERS => '0'),
306 316
307 317 wen => sample_f0_B_wen,
308 318 wdata => sample_f0_wdata,
309 319 ren => sample_f0_B_ren,
310 320 rdata => sample_f0_B_rdata,
311 321 empty => sample_f0_B_empty,
312 322 full => sample_f0_B_full,
313 323 almost_full => OPEN);
314 324
315 325 -----------------------------------------------------------------------------
316 326 -- sample_f1_wen in
317 327 -- sample_f1_wdata in
318 328 -- sample_f1_full OUT
319 329
330 sample_f1_wen_head_in <= '0' WHEN sample_f1_wen = "00000" ELSE '1';
331 sample_f1_full_head_in <= '0' WHEN sample_f1_full = "00000" ELSE '1';
332 sample_f1_empty_head_in <= '1' WHEN sample_f1_empty = "11111" ELSE '0';
333
334 lpp_lfr_ms_reg_head_1:lpp_lfr_ms_reg_head
335 PORT MAP (
336 clk => clk,
337 rstn => rstn,
338 in_wen => sample_f1_wen_head_in,
339 in_data => sample_f1_wdata,
340 in_full => sample_f1_full_head_in,
341 in_empty => sample_f1_empty_head_in,
342 out_wen => sample_f1_wen_head_out,
343 out_data => sample_f1_wdata_head,
344 out_full => sample_f1_full_head_out);
320 345
346 sample_f1_wen_head <= sample_f1_wen_head_out & sample_f1_wen_head_out & sample_f1_wen_head_out & sample_f1_wen_head_out & sample_f1_wen_head_out;
321 347
322 348
323 349 lppFIFOxN_f1 : lppFIFOxN
324 350 GENERIC MAP (
325 351 tech => 0,
326 352 Mem_use => Mem_use,
327 353 Data_sz => 16,
328 354 Addr_sz => 8,
329 355 FifoCnt => 5)
330 356 PORT MAP (
331 357 clk => clk,
332 358 rstn => rstn,
333 359
334 360 ReUse => (OTHERS => '0'),
335 361
336 wen => sample_f1_wen,
337 wdata => sample_f1_wdata,
362 wen => sample_f1_wen_head,
363 wdata => sample_f1_wdata_head,
338 364 ren => sample_f1_ren,
339 365 rdata => sample_f1_rdata,
340 366 empty => sample_f1_empty,
341 367 full => sample_f1_full,
342 368 almost_full => sample_f1_almost_full);
343 369
344 370
345 371 one_sample_f1_wen <= '0' WHEN sample_f1_wen = "11111" ELSE '1';
346 372
347 373 PROCESS (clk, rstn)
348 374 BEGIN -- PROCESS
349 375 IF rstn = '0' THEN -- asynchronous reset (active low)
350 376 one_sample_f1_full <= '0';
351 377 error_wen_f1 <= '0';
352 378 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
353 IF sample_f1_full = "00000" THEN
379 IF sample_f1_full_head_out = '0' THEN
354 380 one_sample_f1_full <= '0';
355 381 ELSE
356 382 one_sample_f1_full <= '1';
357 383 END IF;
358 384 error_wen_f1 <= one_sample_f1_wen AND one_sample_f1_full;
359 385 END IF;
360 386 END PROCESS;
361 387
362 388 -----------------------------------------------------------------------------
363 389
364 390
365 391 lppFIFOxN_f2 : lppFIFOxN
366 392 GENERIC MAP (
367 393 tech => 0,
368 394 Mem_use => Mem_use,
369 395 Data_sz => 16,
370 396 Addr_sz => 8,
371 397 FifoCnt => 5)
372 398 PORT MAP (
373 399 clk => clk,
374 400 rstn => rstn,
375 401
376 402 ReUse => (OTHERS => '0'),
377 403
378 404 wen => sample_f2_wen,
379 405 wdata => sample_f2_wdata,
380 406 ren => sample_f2_ren,
381 407 rdata => sample_f2_rdata,
382 408 empty => sample_f2_empty,
383 409 full => sample_f2_full,
384 410 almost_full => OPEN);
385 411
386 412
387 413 one_sample_f2_wen <= '0' WHEN sample_f2_wen = "11111" ELSE '1';
388 414
389 415 PROCESS (clk, rstn)
390 416 BEGIN -- PROCESS
391 417 IF rstn = '0' THEN -- asynchronous reset (active low)
392 418 one_sample_f2_full <= '0';
393 419 error_wen_f2 <= '0';
394 420 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
395 421 IF sample_f2_full = "00000" THEN
396 422 one_sample_f2_full <= '0';
397 423 ELSE
398 424 one_sample_f2_full <= '1';
399 425 END IF;
400 426 error_wen_f2 <= one_sample_f2_wen AND one_sample_f2_full;
401 427 END IF;
402 428 END PROCESS;
403 429
404 430 -----------------------------------------------------------------------------
405 431 -- FSM SELECT CHANNEL
406 432 -----------------------------------------------------------------------------
407 433 PROCESS (clk, rstn)
408 434 BEGIN
409 435 IF rstn = '0' THEN
410 436 state_fsm_select_channel <= IDLE;
411 437 ELSIF clk'EVENT AND clk = '1' THEN
412 438 CASE state_fsm_select_channel IS
413 439 WHEN IDLE =>
414 440 IF sample_f1_full = "11111" THEN
415 441 state_fsm_select_channel <= SWITCH_F1;
416 442 ELSIF sample_f1_almost_full = "00000" THEN
417 443 IF sample_f0_A_full = "11111" THEN
418 444 state_fsm_select_channel <= SWITCH_F0_A;
419 445 ELSIF sample_f0_B_full = "11111" THEN
420 446 state_fsm_select_channel <= SWITCH_F0_B;
421 447 ELSIF sample_f2_full = "11111" THEN
422 448 state_fsm_select_channel <= SWITCH_F2;
423 449 END IF;
424 450 END IF;
425 451
426 452 WHEN SWITCH_F0_A =>
427 453 IF sample_f0_A_empty = "11111" THEN
428 454 state_fsm_select_channel <= IDLE;
429 455 END IF;
430 456 WHEN SWITCH_F0_B =>
431 457 IF sample_f0_B_empty = "11111" THEN
432 458 state_fsm_select_channel <= IDLE;
433 459 END IF;
434 460 WHEN SWITCH_F1 =>
435 461 IF sample_f1_empty = "11111" THEN
436 462 state_fsm_select_channel <= IDLE;
437 463 END IF;
438 464 WHEN SWITCH_F2 =>
439 465 IF sample_f2_empty = "11111" THEN
440 466 state_fsm_select_channel <= IDLE;
441 467 END IF;
442 468 WHEN OTHERS => NULL;
443 469 END CASE;
444 470
445 471 END IF;
446 472 END PROCESS;
447 473
448 474 PROCESS (clk, rstn)
449 475 BEGIN
450 476 IF rstn = '0' THEN
451 477 pre_state_fsm_select_channel <= IDLE;
452 478 ELSIF clk'EVENT AND clk = '1' THEN
453 479 pre_state_fsm_select_channel <= state_fsm_select_channel;
454 480 END IF;
455 481 END PROCESS;
456 482
457 483
458 484 -----------------------------------------------------------------------------
459 485 -- SWITCH SELECT CHANNEL
460 486 -----------------------------------------------------------------------------
461 487 sample_empty <= sample_f0_A_empty WHEN state_fsm_select_channel = SWITCH_F0_A ELSE
462 488 sample_f0_B_empty WHEN state_fsm_select_channel = SWITCH_F0_B ELSE
463 489 sample_f1_empty WHEN state_fsm_select_channel = SWITCH_F1 ELSE
464 490 sample_f2_empty WHEN state_fsm_select_channel = SWITCH_F2 ELSE
465 491 (OTHERS => '1');
466 492
467 493 sample_full <= sample_f0_A_full WHEN state_fsm_select_channel = SWITCH_F0_A ELSE
468 494 sample_f0_B_full WHEN state_fsm_select_channel = SWITCH_F0_B ELSE
469 495 sample_f1_full WHEN state_fsm_select_channel = SWITCH_F1 ELSE
470 496 sample_f2_full WHEN state_fsm_select_channel = SWITCH_F2 ELSE
471 497 (OTHERS => '0');
472 498
473 499 sample_rdata <= sample_f0_A_rdata WHEN pre_state_fsm_select_channel = SWITCH_F0_A ELSE
474 500 sample_f0_B_rdata WHEN pre_state_fsm_select_channel = SWITCH_F0_B ELSE
475 501 sample_f1_rdata WHEN pre_state_fsm_select_channel = SWITCH_F1 ELSE
476 502 sample_f2_rdata; -- WHEN state_fsm_select_channel = SWITCH_F2 ELSE
477 503
478 504
479 505 sample_f0_A_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F0_A ELSE (OTHERS => '1');
480 506 sample_f0_B_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F0_B ELSE (OTHERS => '1');
481 507 sample_f1_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F1 ELSE (OTHERS => '1');
482 508 sample_f2_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F2 ELSE (OTHERS => '1');
483 509
484 510
485 511 status_channel <= time_reg_f0_A & "00" WHEN state_fsm_select_channel = SWITCH_F0_A ELSE
486 512 time_reg_f0_B & "00" WHEN state_fsm_select_channel = SWITCH_F0_B ELSE
487 513 time_reg_f1 & "01" WHEN state_fsm_select_channel = SWITCH_F1 ELSE
488 514 time_reg_f2 & "10"; -- WHEN state_fsm_select_channel = SWITCH_F2
489 515
490 516 -----------------------------------------------------------------------------
491 517 -- FSM LOAD FFT
492 518 -----------------------------------------------------------------------------
493 519
494 520 sample_ren <= (OTHERS => '1') WHEN fft_ongoing_counter = '1' ELSE
495 521 sample_ren_s WHEN sample_load = '1' ELSE
496 522 (OTHERS => '1');
497 523
498 524 PROCESS (clk, rstn)
499 525 BEGIN
500 526 IF rstn = '0' THEN
501 527 sample_ren_s <= (OTHERS => '1');
502 528 state_fsm_load_FFT <= IDLE;
503 529 status_MS_input <= (OTHERS => '0');
504 530 --next_state_fsm_load_FFT <= IDLE;
505 531 --sample_valid <= '0';
506 532 ELSIF clk'EVENT AND clk = '1' THEN
507 533 CASE state_fsm_load_FFT IS
508 534 WHEN IDLE =>
509 535 --sample_valid <= '0';
510 536 sample_ren_s <= (OTHERS => '1');
511 537 IF sample_full = "11111" AND sample_load = '1' THEN
512 538 state_fsm_load_FFT <= FIFO_1;
513 539 status_MS_input <= status_channel;
514 540 END IF;
515 541
516 542 WHEN FIFO_1 =>
517 543 sample_ren_s <= "1111" & NOT(sample_load);
518 544 IF sample_empty(0) = '1' THEN
519 545 sample_ren_s <= (OTHERS => '1');
520 546 state_fsm_load_FFT <= FIFO_2;
521 547 END IF;
522 548
523 549 WHEN FIFO_2 =>
524 550 sample_ren_s <= "111" & NOT(sample_load) & '1';
525 551 IF sample_empty(1) = '1' THEN
526 552 sample_ren_s <= (OTHERS => '1');
527 553 state_fsm_load_FFT <= FIFO_3;
528 554 END IF;
529 555
530 556 WHEN FIFO_3 =>
531 557 sample_ren_s <= "11" & NOT(sample_load) & "11";
532 558 IF sample_empty(2) = '1' THEN
533 559 sample_ren_s <= (OTHERS => '1');
534 560 state_fsm_load_FFT <= FIFO_4;
535 561 END IF;
536 562
537 563 WHEN FIFO_4 =>
538 564 sample_ren_s <= '1' & NOT(sample_load) & "111";
539 565 IF sample_empty(3) = '1' THEN
540 566 sample_ren_s <= (OTHERS => '1');
541 567 state_fsm_load_FFT <= FIFO_5;
542 568 END IF;
543 569
544 570 WHEN FIFO_5 =>
545 571 sample_ren_s <= NOT(sample_load) & "1111";
546 572 IF sample_empty(4) = '1' THEN
547 573 sample_ren_s <= (OTHERS => '1');
548 574 state_fsm_load_FFT <= IDLE;
549 575 END IF;
550 576 WHEN OTHERS => NULL;
551 577 END CASE;
552 578 END IF;
553 579 END PROCESS;
554 580
555 581 PROCESS (clk, rstn)
556 582 BEGIN
557 583 IF rstn = '0' THEN
558 584 sample_valid_r <= '0';
559 585 next_state_fsm_load_FFT <= IDLE;
560 586 ELSIF clk'EVENT AND clk = '1' THEN
561 587 next_state_fsm_load_FFT <= state_fsm_load_FFT;
562 588 IF sample_ren_s = "11111" THEN
563 589 sample_valid_r <= '0';
564 590 ELSE
565 591 sample_valid_r <= '1';
566 592 END IF;
567 593 END IF;
568 594 END PROCESS;
569 595
570 596 sample_valid <= '0' WHEN fft_ongoing_counter = '1' ELSE sample_valid_r AND sample_load;
571 597
572 598 sample_data <= sample_rdata(16*1-1 DOWNTO 16*0) WHEN next_state_fsm_load_FFT = FIFO_1 ELSE
573 599 sample_rdata(16*2-1 DOWNTO 16*1) WHEN next_state_fsm_load_FFT = FIFO_2 ELSE
574 600 sample_rdata(16*3-1 DOWNTO 16*2) WHEN next_state_fsm_load_FFT = FIFO_3 ELSE
575 601 sample_rdata(16*4-1 DOWNTO 16*3) WHEN next_state_fsm_load_FFT = FIFO_4 ELSE
576 602 sample_rdata(16*5-1 DOWNTO 16*4); --WHEN next_state_fsm_load_FFT = FIFO_5 ELSE
577 603
578 604 -----------------------------------------------------------------------------
579 605 -- FFT
580 606 -----------------------------------------------------------------------------
581 607 lpp_lfr_ms_FFT_1 : lpp_lfr_ms_FFT
582 608 PORT MAP (
583 609 clk => clk,
584 610 rstn => rstn,
585 611 sample_valid => sample_valid,
586 612 fft_read => fft_read,
587 613 sample_data => sample_data,
588 614 sample_load => sample_load,
589 615 fft_pong => fft_pong,
590 616 fft_data_im => fft_data_im,
591 617 fft_data_re => fft_data_re,
592 618 fft_data_valid => fft_data_valid,
593 619 fft_ready => fft_ready);
594 620
595 621 observation_vector_0(11 DOWNTO 0) <= "000" & --11 10
596 622 fft_ongoing_counter & --9 8
597 623 sample_load_rising_down & --7
598 624 fft_ready_rising_down & --6
599 625 fft_ready & --5
600 626 fft_data_valid & --4
601 627 fft_pong & --3
602 628 sample_load & --2
603 629 fft_read & --1
604 630 sample_valid; --0
605 631
606 632 -----------------------------------------------------------------------------
607 633 fft_ready_rising_down <= fft_ready_reg AND NOT fft_ready;
608 634 sample_load_rising_down <= sample_load_reg AND NOT sample_load;
609 635
610 636 PROCESS (clk, rstn)
611 637 BEGIN
612 638 IF rstn = '0' THEN
613 639 fft_ready_reg <= '0';
614 640 sample_load_reg <= '0';
615 641
616 642 fft_ongoing_counter <= '0';
617 643 ELSIF clk'event AND clk = '1' THEN
618 644 fft_ready_reg <= fft_ready;
619 645 sample_load_reg <= sample_load;
620 646
621 647 IF fft_ready_rising_down = '1' AND sample_load_rising_down = '0' THEN
622 648 fft_ongoing_counter <= '0';
623 649
624 650 -- CASE fft_ongoing_counter IS
625 651 -- WHEN "01" => fft_ongoing_counter <= "00";
626 652 ---- WHEN "10" => fft_ongoing_counter <= "01";
627 653 -- WHEN OTHERS => NULL;
628 654 -- END CASE;
629 655 ELSIF fft_ready_rising_down = '0' AND sample_load_rising_down = '1' THEN
630 656 fft_ongoing_counter <= '1';
631 657 -- CASE fft_ongoing_counter IS
632 658 -- WHEN "00" => fft_ongoing_counter <= "01";
633 659 ---- WHEN "01" => fft_ongoing_counter <= "10";
634 660 -- WHEN OTHERS => NULL;
635 661 -- END CASE;
636 662 END IF;
637 663
638 664 END IF;
639 665 END PROCESS;
640 666
641 667 -----------------------------------------------------------------------------
642 668 PROCESS (clk, rstn)
643 669 BEGIN
644 670 IF rstn = '0' THEN
645 671 state_fsm_load_MS_memory <= IDLE;
646 672 current_fifo_load <= "00001";
647 673 ELSIF clk'EVENT AND clk = '1' THEN
648 674 CASE state_fsm_load_MS_memory IS
649 675 WHEN IDLE =>
650 676 IF current_fifo_empty = '1' AND fft_ready = '1' AND current_fifo_locked = '0' THEN
651 677 state_fsm_load_MS_memory <= LOAD_FIFO;
652 678 END IF;
653 679 WHEN LOAD_FIFO =>
654 680 IF current_fifo_full = '1' THEN
655 681 state_fsm_load_MS_memory <= TRASH_FFT;
656 682 END IF;
657 683 WHEN TRASH_FFT =>
658 684 IF fft_ready = '0' THEN
659 685 state_fsm_load_MS_memory <= IDLE;
660 686 current_fifo_load <= current_fifo_load(3 DOWNTO 0) & current_fifo_load(4);
661 687 END IF;
662 688 WHEN OTHERS => NULL;
663 689 END CASE;
664 690
665 691 END IF;
666 692 END PROCESS;
667 693
668 694 current_fifo_empty <= MEM_IN_SM_Empty(0) WHEN current_fifo_load(0) = '1' ELSE
669 695 MEM_IN_SM_Empty(1) WHEN current_fifo_load(1) = '1' ELSE
670 696 MEM_IN_SM_Empty(2) WHEN current_fifo_load(2) = '1' ELSE
671 697 MEM_IN_SM_Empty(3) WHEN current_fifo_load(3) = '1' ELSE
672 698 MEM_IN_SM_Empty(4); -- WHEN current_fifo_load(3) = '1' ELSE
673 699
674 700 current_fifo_full <= MEM_IN_SM_Full(0) WHEN current_fifo_load(0) = '1' ELSE
675 701 MEM_IN_SM_Full(1) WHEN current_fifo_load(1) = '1' ELSE
676 702 MEM_IN_SM_Full(2) WHEN current_fifo_load(2) = '1' ELSE
677 703 MEM_IN_SM_Full(3) WHEN current_fifo_load(3) = '1' ELSE
678 704 MEM_IN_SM_Full(4); -- WHEN current_fifo_load(3) = '1' ELSE
679 705
680 706 current_fifo_locked <= MEM_IN_SM_locked(0) WHEN current_fifo_load(0) = '1' ELSE
681 707 MEM_IN_SM_locked(1) WHEN current_fifo_load(1) = '1' ELSE
682 708 MEM_IN_SM_locked(2) WHEN current_fifo_load(2) = '1' ELSE
683 709 MEM_IN_SM_locked(3) WHEN current_fifo_load(3) = '1' ELSE
684 710 MEM_IN_SM_locked(4); -- WHEN current_fifo_load(3) = '1' ELSE
685 711
686 712 fft_read <= '0' WHEN state_fsm_load_MS_memory = IDLE ELSE '1';
687 713
688 714 all_fifo : FOR I IN 4 DOWNTO 0 GENERATE
689 715 MEM_IN_SM_wen_s(I) <= '0' WHEN fft_data_valid = '1'
690 716 AND state_fsm_load_MS_memory = LOAD_FIFO
691 717 AND current_fifo_load(I) = '1'
692 718 ELSE '1';
693 719 END GENERATE all_fifo;
694 720
695 721 PROCESS (clk, rstn)
696 722 BEGIN
697 723 IF rstn = '0' THEN
698 724 MEM_IN_SM_wen <= (OTHERS => '1');
699 725 ELSIF clk'EVENT AND clk = '1' THEN
700 726 MEM_IN_SM_wen <= MEM_IN_SM_wen_s;
701 727 END IF;
702 728 END PROCESS;
703 729
704 730 MEM_IN_SM_wData <= (fft_data_im & fft_data_re) &
705 731 (fft_data_im & fft_data_re) &
706 732 (fft_data_im & fft_data_re) &
707 733 (fft_data_im & fft_data_re) &
708 734 (fft_data_im & fft_data_re);
709 735 -----------------------------------------------------------------------------
710 736
711 737
712 738 -----------------------------------------------------------------------------
713 739 Mem_In_SpectralMatrix : lppFIFOxN
714 740 GENERIC MAP (
715 741 tech => 0,
716 742 Mem_use => Mem_use,
717 743 Data_sz => 32, --16,
718 744 Addr_sz => 7, --8
719 745 FifoCnt => 5)
720 746 PORT MAP (
721 747 clk => clk,
722 748 rstn => rstn,
723 749
724 750 ReUse => MEM_IN_SM_ReUse,
725 751
726 752 wen => MEM_IN_SM_wen,
727 753 wdata => MEM_IN_SM_wData,
728 754
729 755 ren => MEM_IN_SM_ren,
730 756 rdata => MEM_IN_SM_rData,
731 757 full => MEM_IN_SM_Full,
732 758 empty => MEM_IN_SM_Empty,
733 759 almost_full => OPEN);
734 760
735 761 -----------------------------------------------------------------------------
736 762
737 763 observation_vector_1(11 DOWNTO 0) <= '0' &
738 764 SM_correlation_done & --4
739 765 SM_correlation_auto & --3
740 766 SM_correlation_start &
741 767 SM_correlation_start & --7
742 768 status_MS_input(1 DOWNTO 0)& --6..5
743 769 MEM_IN_SM_locked(4 DOWNTO 0); --4..0
744 770
745 771 -----------------------------------------------------------------------------
746 772 MS_control_1 : MS_control
747 773 PORT MAP (
748 774 clk => clk,
749 775 rstn => rstn,
750 776
751 777 current_status_ms => status_MS_input,
752 778
753 779 fifo_in_lock => MEM_IN_SM_locked,
754 780 fifo_in_data => MEM_IN_SM_rdata,
755 781 fifo_in_full => MEM_IN_SM_Full,
756 782 fifo_in_empty => MEM_IN_SM_Empty,
757 783 fifo_in_ren => MEM_IN_SM_ren,
758 784 fifo_in_reuse => MEM_IN_SM_ReUse,
759 785
760 786 fifo_out_data => SM_in_data,
761 787 fifo_out_ren => SM_in_ren,
762 788 fifo_out_empty => SM_in_empty,
763 789
764 790 current_status_component => status_component,
765 791
766 792 correlation_start => SM_correlation_start,
767 793 correlation_auto => SM_correlation_auto,
768 794 correlation_done => SM_correlation_done);
769 795
770 796
771 797 MS_calculation_1 : MS_calculation
772 798 PORT MAP (
773 799 clk => clk,
774 800 rstn => rstn,
775 801
776 802 fifo_in_data => SM_in_data,
777 803 fifo_in_ren => SM_in_ren,
778 804 fifo_in_empty => SM_in_empty,
779 805
780 806 fifo_out_data => MEM_OUT_SM_Data_in_s, -- TODO
781 807 fifo_out_wen => MEM_OUT_SM_Write_s, -- TODO
782 808 fifo_out_full => MEM_OUT_SM_Full_s, -- TODO
783 809
784 810 correlation_start => SM_correlation_start,
785 811 correlation_auto => SM_correlation_auto,
786 812 correlation_begin => SM_correlation_begin,
787 813 correlation_done => SM_correlation_done);
788 814
789 815 -----------------------------------------------------------------------------
790 816 PROCESS (clk, rstn)
791 817 BEGIN -- PROCESS
792 818 IF rstn = '0' THEN -- asynchronous reset (active low)
793 819 current_matrix_write <= '0';
794 820 current_matrix_wait_empty <= '1';
795 821 status_component_fifo_0 <= (OTHERS => '0');
796 822 status_component_fifo_1 <= (OTHERS => '0');
797 823 status_component_fifo_0_end <= '0';
798 824 status_component_fifo_1_end <= '0';
799 825 SM_correlation_done_reg1 <= '0';
800 826 SM_correlation_done_reg2 <= '0';
801 827 SM_correlation_done_reg3 <= '0';
802 828
803 829 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
804 830 SM_correlation_done_reg1 <= SM_correlation_done;
805 831 SM_correlation_done_reg2 <= SM_correlation_done_reg1;
806 832 SM_correlation_done_reg3 <= SM_correlation_done_reg2;
807 833 status_component_fifo_0_end <= '0';
808 834 status_component_fifo_1_end <= '0';
809 835 IF SM_correlation_begin = '1' THEN
810 836 IF current_matrix_write = '0' THEN
811 837 status_component_fifo_0 <= status_component;
812 838 ELSE
813 839 status_component_fifo_1 <= status_component;
814 840 END IF;
815 841 END IF;
816 842
817 843 IF SM_correlation_done_reg3 = '1' THEN
818 844 IF current_matrix_write = '0' THEN
819 845 status_component_fifo_0_end <= '1';
820 846 ELSE
821 847 status_component_fifo_1_end <= '1';
822 848 END IF;
823 849 current_matrix_wait_empty <= '1';
824 850 current_matrix_write <= NOT current_matrix_write;
825 851 END IF;
826 852
827 853 IF current_matrix_wait_empty <= '1' THEN
828 854 IF current_matrix_write = '0' THEN
829 855 current_matrix_wait_empty <= NOT MEM_OUT_SM_Empty(0);
830 856 ELSE
831 857 current_matrix_wait_empty <= NOT MEM_OUT_SM_Empty(1);
832 858 END IF;
833 859 END IF;
834 860
835 861 END IF;
836 862 END PROCESS;
837 863
838 864 MEM_OUT_SM_Full_s <= '1' WHEN SM_correlation_done = '1' ELSE
839 865 '1' WHEN SM_correlation_done_reg1 = '1' ELSE
840 866 '1' WHEN SM_correlation_done_reg2 = '1' ELSE
841 867 '1' WHEN SM_correlation_done_reg3 = '1' ELSE
842 868 '1' WHEN current_matrix_wait_empty = '1' ELSE
843 869 MEM_OUT_SM_Full(0) WHEN current_matrix_write = '0' ELSE
844 870 MEM_OUT_SM_Full(1);
845 871
846 872 MEM_OUT_SM_Write(0) <= MEM_OUT_SM_Write_s WHEN current_matrix_write = '0' ELSE '1';
847 873 MEM_OUT_SM_Write(1) <= MEM_OUT_SM_Write_s WHEN current_matrix_write = '1' ELSE '1';
848 874
849 875 MEM_OUT_SM_Data_in <= MEM_OUT_SM_Data_in_s & MEM_OUT_SM_Data_in_s;
850 876 -----------------------------------------------------------------------------
851 877
852 878 Mem_Out_SpectralMatrix : lppFIFOxN
853 879 GENERIC MAP (
854 880 tech => 0,
855 881 Mem_use => Mem_use,
856 882 Data_sz => 32,
857 883 Addr_sz => 8,
858 884 FifoCnt => 2)
859 885 PORT MAP (
860 886 clk => clk,
861 887 rstn => rstn,
862 888
863 889 ReUse => (OTHERS => '0'),
864 890
865 891 wen => MEM_OUT_SM_Write,
866 892 wdata => MEM_OUT_SM_Data_in,
867 893
868 894 ren => MEM_OUT_SM_Read,
869 895 rdata => MEM_OUT_SM_Data_out,
870 896
871 897 full => MEM_OUT_SM_Full,
872 898 empty => MEM_OUT_SM_Empty,
873 899 almost_full => OPEN);
874 900
875 901 -----------------------------------------------------------------------------
876 902 -- MEM_OUT_SM_Read <= "00";
877 903 PROCESS (clk, rstn)
878 904 BEGIN
879 905 IF rstn = '0' THEN
880 906 fifo_0_ready <= '0';
881 907 fifo_1_ready <= '0';
882 908 fifo_ongoing <= '0';
883 909 ELSIF clk'EVENT AND clk = '1' THEN
884 910 IF fifo_0_ready = '1' AND MEM_OUT_SM_Empty(0) = '1' THEN
885 911 fifo_ongoing <= '1';
886 912 fifo_0_ready <= '0';
887 913 ELSIF status_component_fifo_0_end = '1' THEN
888 914 fifo_0_ready <= '1';
889 915 END IF;
890 916
891 917 IF fifo_1_ready = '1' AND MEM_OUT_SM_Empty(1) = '1' THEN
892 918 fifo_ongoing <= '0';
893 919 fifo_1_ready <= '0';
894 920 ELSIF status_component_fifo_1_end = '1' THEN
895 921 fifo_1_ready <= '1';
896 922 END IF;
897 923
898 924 END IF;
899 925 END PROCESS;
900 926
901 927 MEM_OUT_SM_Read(0) <= '1' WHEN fifo_ongoing = '1' ELSE
902 928 '1' WHEN fifo_0_ready = '0' ELSE
903 929 FSM_DMA_fifo_ren;
904 930
905 931 MEM_OUT_SM_Read(1) <= '1' WHEN fifo_ongoing = '0' ELSE
906 932 '1' WHEN fifo_1_ready = '0' ELSE
907 933 FSM_DMA_fifo_ren;
908 934
909 935 FSM_DMA_fifo_empty <= MEM_OUT_SM_Empty(0) WHEN fifo_ongoing = '0' AND fifo_0_ready = '1' ELSE
910 936 MEM_OUT_SM_Empty(1) WHEN fifo_ongoing = '1' AND fifo_1_ready = '1' ELSE
911 937 '1';
912 938
913 939 FSM_DMA_fifo_status <= status_component_fifo_0 WHEN fifo_ongoing = '0' ELSE
914 940 status_component_fifo_1;
915 941
916 942 FSM_DMA_fifo_data <= MEM_OUT_SM_Data_out(31 DOWNTO 0) WHEN fifo_ongoing = '0' ELSE
917 943 MEM_OUT_SM_Data_out(63 DOWNTO 32);
918 944
919 945 -----------------------------------------------------------------------------
920 946 lpp_lfr_ms_fsmdma_1 : lpp_lfr_ms_fsmdma
921 947 PORT MAP (
922 948 HCLK => clk,
923 949 HRESETn => rstn,
924 950
925 951 fifo_matrix_type => FSM_DMA_fifo_status(5 DOWNTO 4),
926 952 fifo_matrix_component => FSM_DMA_fifo_status(3 DOWNTO 0),
927 953 fifo_matrix_time => FSM_DMA_fifo_status(53 DOWNTO 6),
928 954 fifo_data => FSM_DMA_fifo_data,
929 955 fifo_empty => FSM_DMA_fifo_empty,
930 956 fifo_ren => FSM_DMA_fifo_ren,
931 957
932 958 dma_addr => dma_addr,
933 959 dma_data => dma_data,
934 960 dma_valid => dma_valid,
935 961 dma_valid_burst => dma_valid_burst,
936 962 dma_ren => dma_ren,
937 963 dma_done => dma_done,
938 964
939 965 ready_matrix_f0 => ready_matrix_f0,
940 966 ready_matrix_f1 => ready_matrix_f1,
941 967 ready_matrix_f2 => ready_matrix_f2,
942 968
943 969 error_bad_component_error => error_bad_component_error,
944 970 error_buffer_full => error_buffer_full,
945 971
946 972 debug_reg => debug_reg,
947 973 status_ready_matrix_f0 => status_ready_matrix_f0,
948 974 status_ready_matrix_f1 => status_ready_matrix_f1,
949 975 status_ready_matrix_f2 => status_ready_matrix_f2,
950 976
951 977 config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
952 978 config_active_interruption_onError => config_active_interruption_onError,
953 979
954 980 addr_matrix_f0 => addr_matrix_f0,
955 981 addr_matrix_f1 => addr_matrix_f1,
956 982 addr_matrix_f2 => addr_matrix_f2,
957 983
958 984 matrix_time_f0 => matrix_time_f0,
959 985 matrix_time_f1 => matrix_time_f1,
960 986 matrix_time_f2 => matrix_time_f2
961 987 );
962 988 -----------------------------------------------------------------------------
963 989
964 990
965 991
966 992
967 993
968 994 -----------------------------------------------------------------------------
969 995 -- TIME MANAGMENT
970 996 -----------------------------------------------------------------------------
971 997 all_time <= coarse_time & fine_time;
972 998 --
973 999 f_empty(0) <= '1' WHEN sample_f0_A_empty = "11111" ELSE '0';
974 1000 f_empty(1) <= '1' WHEN sample_f0_B_empty = "11111" ELSE '0';
975 1001 f_empty(2) <= '1' WHEN sample_f1_empty = "11111" ELSE '0';
976 1002 f_empty(3) <= '1' WHEN sample_f2_empty = "11111" ELSE '0';
977 1003
978 1004 all_time_reg: FOR I IN 0 TO 3 GENERATE
979 1005
980 1006 PROCESS (clk, rstn)
981 1007 BEGIN
982 1008 IF rstn = '0' THEN
983 1009 f_empty_reg(I) <= '1';
984 1010 ELSIF clk'event AND clk = '1' THEN
985 1011 f_empty_reg(I) <= f_empty(I);
986 1012 END IF;
987 1013 END PROCESS;
988 1014
989 1015 time_update_f(I) <= '1' WHEN f_empty(I) = '0' AND f_empty_reg(I) = '1' ELSE '0';
990 1016
991 1017 s_m_t_m_f0_A : spectral_matrix_time_managment
992 1018 PORT MAP (
993 1019 clk => clk,
994 1020 rstn => rstn,
995 1021 time_in => all_time,
996 1022 update_1 => time_update_f(I),
997 1023 time_out => time_reg_f((I+1)*48-1 DOWNTO I*48)
998 1024 );
999 1025
1000 1026 END GENERATE all_time_reg;
1001 1027
1002 1028 time_reg_f0_A <= time_reg_f((0+1)*48-1 DOWNTO 0*48);
1003 1029 time_reg_f0_B <= time_reg_f((1+1)*48-1 DOWNTO 1*48);
1004 1030 time_reg_f1 <= time_reg_f((2+1)*48-1 DOWNTO 2*48);
1005 1031 time_reg_f2 <= time_reg_f((3+1)*48-1 DOWNTO 3*48);
1006 1032
1007 1033 -----------------------------------------------------------------------------
1008 1034
1009 1035 END Behavioral;
Show file before | Show file after | Hide comments
@@ -1,416 +1,429
1 1 LIBRARY ieee;
2 2 USE ieee.std_logic_1164.ALL;
3 3
4 4 LIBRARY grlib;
5 5 USE grlib.amba.ALL;
6 6
7 7 LIBRARY lpp;
8 8 USE lpp.lpp_ad_conv.ALL;
9 9 USE lpp.iir_filter.ALL;
10 10 USE lpp.FILTERcfg.ALL;
11 11 USE lpp.lpp_memory.ALL;
12 12 LIBRARY techmap;
13 13 USE techmap.gencomp.ALL;
14 14
15 15 PACKAGE lpp_lfr_pkg IS
16 16 -----------------------------------------------------------------------------
17 17 -- TEMP
18 18 -----------------------------------------------------------------------------
19 19 COMPONENT lpp_lfr_ms_test
20 20 GENERIC (
21 21 Mem_use : INTEGER);
22 22 PORT (
23 23 clk : IN STD_LOGIC;
24 24 rstn : IN STD_LOGIC;
25 25
26 26 -- TIME
27 27 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
28 28 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
29 29 --
30 30 sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
31 31 sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
32 32 --
33 33 sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
34 34 sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
35 35 --
36 36 sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
37 37 sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
38 38
39 39
40 40
41 41 ---------------------------------------------------------------------------
42 42 error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
43 43
44 44 --
45 45 --sample_ren : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
46 46 --sample_full : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
47 47 --sample_empty : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
48 48 --sample_rdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
49 49
50 50 --status_channel : IN STD_LOGIC_VECTOR(49 DOWNTO 0);
51 51
52 52 -- IN
53 53 MEM_IN_SM_locked : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
54 54
55 55 -----------------------------------------------------------------------------
56 56
57 57 status_component : OUT STD_LOGIC_VECTOR(53 DOWNTO 0);
58 58 SM_in_data : OUT STD_LOGIC_VECTOR(32*2-1 DOWNTO 0);
59 59 SM_in_ren : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
60 60 SM_in_empty : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
61 61
62 62 SM_correlation_start : OUT STD_LOGIC;
63 63 SM_correlation_auto : OUT STD_LOGIC;
64 64 SM_correlation_done : IN STD_LOGIC
65 65 );
66 66 END COMPONENT;
67 67
68 68
69 69 -----------------------------------------------------------------------------
70 70 COMPONENT lpp_lfr_ms
71 71 GENERIC (
72 72 Mem_use : INTEGER
73 73 );
74 74 PORT (
75 75 clk : IN STD_LOGIC;
76 76 rstn : IN STD_LOGIC;
77 77
78 78 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
79 79 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
80 80
81 81 sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
82 82 sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
83 83
84 84 sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
85 85 sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
86 86
87 87 sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
88 88 sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
89 89
90 90 dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
91 91 dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
92 92 dma_valid : OUT STD_LOGIC;
93 93 dma_valid_burst : OUT STD_LOGIC;
94 94 dma_ren : IN STD_LOGIC;
95 95 dma_done : IN STD_LOGIC;
96 96
97 97 ready_matrix_f0 : OUT STD_LOGIC;
98 98 -- ready_matrix_f0_1 : OUT STD_LOGIC;
99 99 ready_matrix_f1 : OUT STD_LOGIC;
100 100 ready_matrix_f2 : OUT STD_LOGIC;
101 101 -- error_anticipating_empty_fifo : OUT STD_LOGIC;
102 102 error_bad_component_error : OUT STD_LOGIC;
103 103 error_buffer_full : OUT STD_LOGIC;
104 104 error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
105 105 debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
106 106 --
107 107 observation_vector_0: OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
108 108 observation_vector_1: OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
109 109 -------------------------------------------------------------------------
110 110 status_ready_matrix_f0 : IN STD_LOGIC;
111 111 -- status_ready_matrix_f0_1 : IN STD_LOGIC;
112 112 status_ready_matrix_f1 : IN STD_LOGIC;
113 113 status_ready_matrix_f2 : IN STD_LOGIC;
114 114 -- status_error_anticipating_empty_fifo : IN STD_LOGIC;
115 115 -- status_error_bad_component_error : IN STD_LOGIC;
116 116 config_active_interruption_onNewMatrix : IN STD_LOGIC;
117 117 config_active_interruption_onError : IN STD_LOGIC;
118 118 addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
119 119 -- addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
120 120 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
121 121 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
122 122
123 123 matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
124 124 -- matrix_time_f0_1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
125 125 matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
126 126 matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0));
127 127 END COMPONENT;
128 128
129 129 COMPONENT lpp_lfr_ms_fsmdma
130 130 PORT (
131 131 HCLK : IN STD_ULOGIC;
132 132 HRESETn : IN STD_ULOGIC;
133 133 fifo_matrix_type : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
134 134 fifo_matrix_component : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
135 135 fifo_matrix_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
136 136 fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
137 137 fifo_empty : IN STD_LOGIC;
138 138 fifo_ren : OUT STD_LOGIC;
139 139 --data_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
140 140 --fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
141 141 --fifo_empty : IN STD_LOGIC;
142 142 --fifo_ren : OUT STD_LOGIC;
143 143 --header : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
144 144 --header_val : IN STD_LOGIC;
145 145 --header_ack : OUT STD_LOGIC;
146 146 dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
147 147 dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
148 148 dma_valid : OUT STD_LOGIC;
149 149 dma_valid_burst : OUT STD_LOGIC;
150 150 dma_ren : IN STD_LOGIC;
151 151 dma_done : IN STD_LOGIC;
152 152 ready_matrix_f0 : OUT STD_LOGIC;
153 153 -- ready_matrix_f0_1 : OUT STD_LOGIC;
154 154 ready_matrix_f1 : OUT STD_LOGIC;
155 155 ready_matrix_f2 : OUT STD_LOGIC;
156 156 -- error_anticipating_empty_fifo : OUT STD_LOGIC;
157 157 error_bad_component_error : OUT STD_LOGIC;
158 158 error_buffer_full : OUT STD_LOGIC;
159 159 debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
160 160 status_ready_matrix_f0 : IN STD_LOGIC;
161 161 -- status_ready_matrix_f0_1 : IN STD_LOGIC;
162 162 status_ready_matrix_f1 : IN STD_LOGIC;
163 163 status_ready_matrix_f2 : IN STD_LOGIC;
164 164 -- status_error_anticipating_empty_fifo : IN STD_LOGIC;
165 165 -- status_error_bad_component_error : IN STD_LOGIC;
166 166 config_active_interruption_onNewMatrix : IN STD_LOGIC;
167 167 config_active_interruption_onError : IN STD_LOGIC;
168 168 addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
169 169 -- addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
170 170 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
171 171 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
172 172
173 173 matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
174 174 -- matrix_time_f0_1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
175 175 matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
176 176 matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)
177 177 );
178 178 END COMPONENT;
179 179
180 180 COMPONENT lpp_lfr_ms_FFT
181 181 PORT (
182 182 clk : IN STD_LOGIC;
183 183 rstn : IN STD_LOGIC;
184 184 sample_valid : IN STD_LOGIC;
185 185 fft_read : IN STD_LOGIC;
186 186 sample_data : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
187 187 sample_load : OUT STD_LOGIC;
188 188 fft_pong : OUT STD_LOGIC;
189 189 fft_data_im : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
190 190 fft_data_re : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
191 191 fft_data_valid : OUT STD_LOGIC;
192 192 fft_ready : OUT STD_LOGIC);
193 193 END COMPONENT;
194 194
195 195 COMPONENT lpp_lfr_filter
196 196 GENERIC (
197 197 Mem_use : INTEGER);
198 198 PORT (
199 199 sample : IN Samples(7 DOWNTO 0);
200 200 sample_val : IN STD_LOGIC;
201 201 clk : IN STD_LOGIC;
202 202 rstn : IN STD_LOGIC;
203 203 data_shaping_SP0 : IN STD_LOGIC;
204 204 data_shaping_SP1 : IN STD_LOGIC;
205 205 data_shaping_R0 : IN STD_LOGIC;
206 206 data_shaping_R1 : IN STD_LOGIC;
207 207 sample_f0_val : OUT STD_LOGIC;
208 208 sample_f1_val : OUT STD_LOGIC;
209 209 sample_f2_val : OUT STD_LOGIC;
210 210 sample_f3_val : OUT STD_LOGIC;
211 211 sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
212 212 sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
213 213 sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
214 214 sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0));
215 215 END COMPONENT;
216 216
217 217 COMPONENT lpp_lfr
218 218 GENERIC (
219 219 Mem_use : INTEGER;
220 220 nb_data_by_buffer_size : INTEGER;
221 221 nb_word_by_buffer_size : INTEGER;
222 222 nb_snapshot_param_size : INTEGER;
223 223 delta_vector_size : INTEGER;
224 224 delta_vector_size_f0_2 : INTEGER;
225 225 pindex : INTEGER;
226 226 paddr : INTEGER;
227 227 pmask : INTEGER;
228 228 pirq_ms : INTEGER;
229 229 pirq_wfp : INTEGER;
230 230 hindex : INTEGER;
231 231 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0)
232 232 );
233 233 PORT (
234 234 clk : IN STD_LOGIC;
235 235 rstn : IN STD_LOGIC;
236 236 sample_B : IN Samples(2 DOWNTO 0);
237 237 sample_E : IN Samples(4 DOWNTO 0);
238 238 sample_val : IN STD_LOGIC;
239 239 apbi : IN apb_slv_in_type;
240 240 apbo : OUT apb_slv_out_type;
241 241 ahbi : IN AHB_Mst_In_Type;
242 242 ahbo : OUT AHB_Mst_Out_Type;
243 243 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
244 244 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
245 245 data_shaping_BW : OUT STD_LOGIC;
246 246 --
247 247 observation_vector_0: OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
248 248 observation_vector_1: OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
249 249 observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
250 250 );
251 251 END COMPONENT;
252 252
253 253 -----------------------------------------------------------------------------
254 254 -- LPP_LFR with only WaveForm Picker (and without Spectral Matrix Sub System)
255 255 -----------------------------------------------------------------------------
256 256 COMPONENT lpp_lfr_WFP_nMS
257 257 GENERIC (
258 258 Mem_use : INTEGER;
259 259 nb_data_by_buffer_size : INTEGER;
260 260 nb_word_by_buffer_size : INTEGER;
261 261 nb_snapshot_param_size : INTEGER;
262 262 delta_vector_size : INTEGER;
263 263 delta_vector_size_f0_2 : INTEGER;
264 264 pindex : INTEGER;
265 265 paddr : INTEGER;
266 266 pmask : INTEGER;
267 267 pirq_ms : INTEGER;
268 268 pirq_wfp : INTEGER;
269 269 hindex : INTEGER;
270 270 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0));
271 271 PORT (
272 272 clk : IN STD_LOGIC;
273 273 rstn : IN STD_LOGIC;
274 274 sample_B : IN Samples(2 DOWNTO 0);
275 275 sample_E : IN Samples(4 DOWNTO 0);
276 276 sample_val : IN STD_LOGIC;
277 277 apbi : IN apb_slv_in_type;
278 278 apbo : OUT apb_slv_out_type;
279 279 ahbi : IN AHB_Mst_In_Type;
280 280 ahbo : OUT AHB_Mst_Out_Type;
281 281 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
282 282 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
283 283 data_shaping_BW : OUT STD_LOGIC;
284 284 observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0));
285 285 END COMPONENT;
286 286 -----------------------------------------------------------------------------
287 287 COMPONENT lpp_lfr_apbreg
288 288 GENERIC (
289 289 nb_data_by_buffer_size : INTEGER;
290 290 nb_word_by_buffer_size : INTEGER;
291 291 nb_snapshot_param_size : INTEGER;
292 292 delta_vector_size : INTEGER;
293 293 delta_vector_size_f0_2 : INTEGER;
294 294 pindex : INTEGER;
295 295 paddr : INTEGER;
296 296 pmask : INTEGER;
297 297 pirq_ms : INTEGER;
298 298 pirq_wfp : INTEGER;
299 299 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0));
300 300 PORT (
301 301 HCLK : IN STD_ULOGIC;
302 302 HRESETn : IN STD_ULOGIC;
303 303 apbi : IN apb_slv_in_type;
304 304 apbo : OUT apb_slv_out_type;
305 305 run_ms : OUT STD_LOGIC;
306 306 ready_matrix_f0 : IN STD_LOGIC;
307 307 ready_matrix_f1 : IN STD_LOGIC;
308 308 ready_matrix_f2 : IN STD_LOGIC;
309 309 error_bad_component_error : IN STD_LOGIC;
310 310 error_buffer_full : in STD_LOGIC;
311 311 error_input_fifo_write : in STD_LOGIC_VECTOR(2 DOWNTO 0);
312 312 --x debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
313 313 status_ready_matrix_f0 : OUT STD_LOGIC;
314 314 status_ready_matrix_f1 : OUT STD_LOGIC;
315 315 status_ready_matrix_f2 : OUT STD_LOGIC;
316 316 config_active_interruption_onNewMatrix : OUT STD_LOGIC;
317 317 config_active_interruption_onError : OUT STD_LOGIC;
318 318 addr_matrix_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
319 319 -- addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
320 320 addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
321 321 addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
322 322 matrix_time_f0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
323 323 -- matrix_time_f0_1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
324 324 matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
325 325 matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
326 326 status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
327 327 status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
328 328 status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
329 329 status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
330 330 data_shaping_BW : OUT STD_LOGIC;
331 331 data_shaping_SP0 : OUT STD_LOGIC;
332 332 data_shaping_SP1 : OUT STD_LOGIC;
333 333 data_shaping_R0 : OUT STD_LOGIC;
334 334 data_shaping_R1 : OUT STD_LOGIC;
335 335 delta_snapshot : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
336 336 delta_f0 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
337 337 delta_f0_2 : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
338 338 delta_f1 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
339 339 delta_f2 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
340 340 nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
341 341 nb_word_by_buffer : OUT STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
342 342 nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
343 343 enable_f0 : OUT STD_LOGIC;
344 344 enable_f1 : OUT STD_LOGIC;
345 345 enable_f2 : OUT STD_LOGIC;
346 346 enable_f3 : OUT STD_LOGIC;
347 347 burst_f0 : OUT STD_LOGIC;
348 348 burst_f1 : OUT STD_LOGIC;
349 349 burst_f2 : OUT STD_LOGIC;
350 350 run : OUT STD_LOGIC;
351 351 addr_data_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
352 352 addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
353 353 addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
354 354 addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
355 355 start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0);
356 356
357 357 debug_signal : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
358 358
359 359 );
360 360 END COMPONENT;
361 361
362 362
363 363
364 364 COMPONENT lpp_top_ms
365 365 GENERIC (
366 366 Mem_use : INTEGER;
367 367 nb_burst_available_size : INTEGER;
368 368 nb_snapshot_param_size : INTEGER;
369 369 delta_snapshot_size : INTEGER;
370 370 delta_f2_f0_size : INTEGER;
371 371 delta_f2_f1_size : INTEGER;
372 372 pindex : INTEGER;
373 373 paddr : INTEGER;
374 374 pmask : INTEGER;
375 375 pirq_ms : INTEGER;
376 376 pirq_wfp : INTEGER;
377 377 hindex_wfp : INTEGER;
378 378 hindex_ms : INTEGER);
379 379 PORT (
380 380 clk : IN STD_LOGIC;
381 381 rstn : IN STD_LOGIC;
382 382 sample_B : IN Samples14v(2 DOWNTO 0);
383 383 sample_E : IN Samples14v(4 DOWNTO 0);
384 384 sample_val : IN STD_LOGIC;
385 385 apbi : IN apb_slv_in_type;
386 386 apbo : OUT apb_slv_out_type;
387 387 ahbi_ms : IN AHB_Mst_In_Type;
388 388 ahbo_ms : OUT AHB_Mst_Out_Type;
389 389 data_shaping_BW : OUT STD_LOGIC;
390 390 matrix_time_f0_0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
391 391 matrix_time_f0_1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
392 392 matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
393 393 matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0)
394 394
395 395 );
396 396 END COMPONENT;
397 397
398 398 COMPONENT lpp_apbreg_ms_pointer
399 399 PORT (
400 400 clk : IN STD_LOGIC;
401 401 rstn : IN STD_LOGIC;
402 402 reg0_status_ready_matrix : IN STD_LOGIC;
403 403 reg0_ready_matrix : OUT STD_LOGIC;
404 404 reg0_addr_matrix : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
405 405 reg0_matrix_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
406 406 reg1_status_ready_matrix : IN STD_LOGIC;
407 407 reg1_ready_matrix : OUT STD_LOGIC;
408 408 reg1_addr_matrix : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
409 409 reg1_matrix_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
410 410 ready_matrix : IN STD_LOGIC;
411 411 status_ready_matrix : OUT STD_LOGIC;
412 412 addr_matrix : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
413 413 matrix_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0));
414 414 END COMPONENT;
415
416 COMPONENT lpp_lfr_ms_reg_head
417 PORT (
418 clk : IN STD_LOGIC;
419 rstn : IN STD_LOGIC;
420 in_wen : IN STD_LOGIC;
421 in_data : IN STD_LOGIC_VECTOR(5*16-1 DOWNTO 0);
422 in_full : IN STD_LOGIC;
423 in_empty : IN STD_LOGIC;
424 out_wen : OUT STD_LOGIC;
425 out_data : OUT STD_LOGIC_VECTOR(5*16-1 DOWNTO 0);
426 out_full : OUT STD_LOGIC);
427 END COMPONENT;
415 428
416 429 END lpp_lfr_pkg;
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@@ -1,9 +1,10
1 1 lpp_top_lfr_pkg.vhd
2 2 lpp_lfr_pkg.vhd
3 3 lpp_lfr_filter.vhd
4 4 lpp_lfr_apbreg.vhd
5 5 lpp_lfr_apbreg_ms_pointer.vhd
6 6 lpp_lfr_ms_fsmdma.vhd
7 7 lpp_lfr_ms_FFT.vhd
8 8 lpp_lfr_ms.vhd
9 lpp_lfr_ms_reg_head.vhd
9 10 lpp_lfr.vhd
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